Memory device and method of connecting transistors in a static random access memory

By designing and manufacturing SRAM-based FPGAs using logic rules and technology, and combining them with FINFETs and stacked nanosheet transistors, the integration challenges of SRAM devices with peripheral logic devices are solved, improving the overall performance in terms of power, performance, and area, and achieving robust circuit connections.

CN115274674BActive Publication Date: 2026-07-21TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
View PDF 4 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
Filing Date
2022-07-04
Publication Date
2026-07-21

AI Technical Summary

Technical Problem

Existing SRAM-based FPGA devices face challenges in terms of power, performance, and area (PPA) when integrated with configuration devices and other peripheral logic devices, and struggle to meet compatibility issues between logic rules and SRAM rules.

Method used

SRAM-based FPGAs are designed and manufactured using logical rules and technologies. By combining FinFET and stacked nanosheet transistor technologies, robust connections with configuration devices and peripheral logic devices are achieved through conductive paths and power line alignment, thus meeting the PPA target.

Benefits of technology

It improves the integration robustness of SRAM-based FPGAs with configuration devices and peripheral logic devices, enhances the overall performance in terms of power, performance and area, and achieves better circuit operating margin and connection stability.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN115274674B_ABST
    Figure CN115274674B_ABST
Patent Text Reader

Abstract

A memory device includes a first transistor including a first drain / source terminal and a second transistor including a first gate terminal. A first conductive path is electrically connected between the first drain / source terminal and the first gate terminal. The first conductive path includes a first conductive via electrically connected between the first drain / source terminal and a first track of a first conductive layer, and a second conductive via electrically connected between the first track of the first conductive layer and a first track of a second conductive layer. Embodiments of the invention also provide methods of connecting transistors in a static random access memory.
Need to check novelty before this filing date? Find Prior Art