Embedded SONOS device and preparation method thereof

Abstract

The present invention provides an embedded SONOS device and a preparation method thereof, wherein the method comprises: removing the ONO film layer of the first thickness in the selection pipe area and the device logic area; removing the ONO film layer of the second thickness in the selection pipe area and the device logic area by a wet etching process; removing the ONO film layer of the first thickness in the storage pipe area, removing the ONO film layer of the third thickness in the selection pipe area and the device logic area; forming a first gate oxide layer; forming a second gate oxide layer. The present application utilizes a wet etching process to remove the ONO film layer of the second thickness, thereby avoiding the situation where silicon nitride remains in the ONO film layer. Furthermore, the present application forms the first gate oxide layer and the second gate oxide layer respectively, and there are no other wet process steps thereafter, thereby reducing the fluctuation of the ONO film thickness caused by the wet process, reducing the divergence of the SONOS device window, and improving the performance of the device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor memory manufacturing, and in particular to an embedded SONOS device and a preparation method thereof. Background Art

[0002] As an essential storage device in computers, non-volatile memory plays an important role in storing the information being processed. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory has the characteristics of small unit size, good storage retention, low operating voltage, and compatibility with CMOS process.

[0003] In the manufacturing process of existing SONOS memory devices, the logic area of ​​the device often has a silicon nitride residue (mini-spacer) problem in the ONO film layer caused by dry etching of the ONO film layer, thereby reducing the yield of the device; in addition, in existing SONOS memory devices, a wet etching process is usually used to remove some film layers in the process between forming the ONO film layer and forming the gate structure, but the wet etching process is prone to cause fluctuations in the ONO film thickness, increasing the divergence of the SONOS device window, thereby causing a certain impact on the performance of the device. Summary of the invention

[0004] The present application provides an embedded SONOS device and a preparation method thereof, which can solve at least one of the problems of silicon nitride residue in the ONO film layer and fluctuation of the ONO film thickness due to a wet etching process in the manufacturing process of the existing SONOS memory device.

[0005] On the one hand, an embodiment of the present application provides a method for preparing an embedded SONOS device, wherein the embedded SONOS device includes: a storage region, a selection region, and a device logic region. The method for preparing the embedded SONOS device includes:

[0006] A substrate is provided, wherein a pad oxide layer is formed on the surface of the substrate, and a plurality of shallow trench isolation structures arranged at intervals are formed in the substrate to separate a storage device and a logic device in an embedded SONOS device, wherein a first well region is formed in the substrates of the storage pipe region and the selection pipe region; and a second well region located on the first well region is also formed in the substrate of the storage pipe region;

[0007] Performing an ion implantation process on the second well region of the storage pipe region and forming a tunneling storage region on the surface of the second well region of the storage pipe region;

[0008] Removing the pad oxide layers of the storage pipe area, the selection pipe area and the device logic area;

[0009] Forming an ONO film layer, wherein the ONO film layer covers the substrate of the storage pipe area, the selection pipe area and the device logic area;

[0010] Removing the ONO film layer of the first thickness in the selection pipe area and the device logic area;

[0011] Performing an ion implantation process on the substrate of the selection pipe region and the device logic region to form a third well region in the selection pipe region, and forming a fourth well region and a fifth well region in the substrate of the device logic region;

[0012] Using a wet etching process to remove the ONO film layer of the second thickness in the selection pipe area and the device logic area;

[0013] Removing the ONO film layer of the first thickness in the storage pipe area, and removing the ONO film layer of the third thickness in the selection pipe area and the device logic area to expose the substrate of the selection pipe area and the device logic area;

[0014] forming a first gate oxide layer, wherein the first gate oxide layer covers the substrate of the selection pipe region and the device logic region; and,

[0015] A second gate oxide layer is formed, wherein the second gate oxide layer covers the remaining thickness of the ONO film layer in the storage pipe region.

[0016] Optionally, in the method for preparing the embedded SONOS device, a high-temperature furnace tube oxidation process is used to form the first gate oxide layer.

[0017] Optionally, in the method for preparing the embedded SONOS device, the second gate oxide layer is formed by an in-situ water vapor generation process.

[0018] Optionally, in the method for preparing the embedded SONOS device, the ONO film layer includes a stacked bottom silicon oxide layer, a silicon nitride layer and a top silicon oxide layer.

[0019] Optionally, in the method for preparing the embedded SONOS device, removing the ONO film layer of the first thickness from the selection pipe region and the device logic region comprises:

[0020] The top silicon oxide layer of the selection pipe region and the device logic region is removed.

[0021] Optionally, in the method for preparing the embedded SONOS device, removing the ONO film layer of the second thickness from the selection pipe region and the device logic region comprises:

[0022] The silicon nitride layer in the selection pipe region and the device logic region is removed by using a hot phosphoric acid solution.

[0023] Optionally, in the method for preparing the embedded SONOS device, removing the ONO film layer of the first thickness in the storage pipe area, and removing the ONO film layer of the third thickness in the selection pipe area and the device logic area to expose the substrate of the selection pipe area and the device logic area comprises:

[0024] The top silicon oxide layer of the storage pipe area is removed by wet method, and the bottom silicon oxide layer of the selection pipe area and the device logic area is removed to expose the substrate of the selection pipe area and the device logic area.

[0025] Optionally, in the method for preparing the embedded SONOS device, the forming of the second gate oxide layer, wherein the second gate oxide layer covers the remaining thickness of the ONO film layer in the selection pipe region, comprises:

[0026] A second gate oxide layer is formed, wherein the second gate oxide layer covers the silicon nitride layer in the selection pipe region.

[0027] Optionally, in the method for preparing the embedded SONOS device, after forming a second gate oxide layer, wherein the second gate oxide layer covers the remaining thickness of the ONO film layer in the selection pipe region, the method for preparing the embedded SONOS device includes:

[0028] A plurality of gate structures are formed, and the gate structures are respectively located on the second gate oxide layer of the storage pipe region, the first gate oxide layer of the selection pipe region, and the first gate oxide layer of the device logic region.

[0029] On the other hand, an embodiment of the present application further provides an embedded SONOS device, the embedded SONOS device comprising: a storage management area, a selection management area and a device logic area, the embedded SONOS device comprising:

[0030] A substrate, wherein a plurality of shallow trench isolation structures arranged at intervals are formed in the substrate to separate the storage device and the logic device in the embedded SONOS device, wherein a first well region is formed in the substrates of the storage pipe region and the selection pipe region; a second well region located on the first well region is also formed in the substrate of the storage pipe region; a third well region is formed in the substrate of the selection pipe region; and a fourth well region and a fifth well region are formed in the substrate of the device logic region;

[0031] A tunneling storage region, wherein the tunneling storage region is located on the second well region in the substrate of the storage pipe region;

[0032] An ONO film layer of remaining thickness, wherein the ONO film layer of remaining thickness covers the substrate of the storage tube area;

[0033] A first gate oxide layer, wherein the first gate oxide layer covers the substrate of the selection pipe region and the device logic region; and

[0034] A second gate oxide layer, wherein the second gate oxide layer covers the remaining thickness of the ONO film layer in the storage pipe region.

[0035] The technical solution of this application has at least the following advantages:

[0036] The present application utilizes a wet etching process to remove the ONO film layer of the second thickness, thereby avoiding silicon nitride residue in the ONO film layer and improving the yield of the device.

[0037] Furthermore, the present application adopts different processes to form the first gate oxide layer and the second gate oxide layer respectively, and there are no other additional wet process steps between the formation of the second gate oxide layer and the subsequent formation of the gate structure, thereby reducing the fluctuation of the total thickness of the remaining thickness of the ONO film layer + the second gate oxide layer (the thickness of the ONO film) caused by the wet process, reducing the divergence of the SONOS device window, and improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 is a flow chart of a method for preparing an embedded SONOS device according to an embodiment of the present invention;

[0040] Figure 2-Figure 10 is a schematic diagram of a semiconductor structure in each process step of preparing an embedded SONOS device according to an embodiment of the present invention;

[0041] The reference numerals are described as follows:

[0042] 10-substrate, 11-shallow trench isolation structure, 12-first well region, 13-second well region, 14-tunneling storage region, 15-third well region, 16-fourth well region, 17-fifth well region, 18-source and drain region;

[0043] 20- pad oxide layer, 30- photoresist layer, 40- ONO film layer, 41- silicon nitride layer and bottom silicon oxide layer, 42- bottom silicon oxide layer, 50- photoresist layer, 60- first gate oxide layer, 70- second gate oxide layer, 80- gate structure;

[0044] SONOS-storage management area, NPASS-selection management area, HV PMOS, HV NMOS-device logic area. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0047] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0048] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0049] The present application embodiment provides a method for preparing an embedded SONOS device, wherein the embedded SONOS device includes: a storage region, a selection region, and a device logic region, please refer to Figure 1 , Figure 1 1 is a flow chart of a method for preparing an embedded SONOS device according to an embodiment of the present invention, wherein the method for preparing an embedded SONOS device comprises:

[0050] S1: providing a substrate, wherein a pad oxide layer is formed on the surface of the substrate, and a plurality of shallow trench isolation structures are formed in the substrate to separate the storage device and the logic device in the embedded SONOS device, wherein a first well region is formed in the substrates of the storage pipe region and the selection pipe region; and a second well region located on the first well region is also formed in the substrate of the storage pipe region;

[0051] S2: performing an ion implantation process on the second well region of the storage pipe region and forming a tunneling storage region on the surface of the second well region of the storage pipe region;

[0052] S3: removing the pad oxide layer of the storage pipe area, the selection pipe area and the device logic area;

[0053] S4: forming an ONO film layer, wherein the ONO film layer covers the substrate of the storage pipe area, the selection pipe area and the device logic area;

[0054] S5: removing the ONO film layer of the first thickness in the selection pipe area and the device logic area;

[0055] S6: performing an ion implantation process on the substrate of the selection pipe region and the device logic region to form a third well region in the selection pipe region, and to form a fourth well region and a fifth well region in the substrate of the device logic region;

[0056] S7: removing the ONO film layer of the second thickness in the selection pipe area and the device logic area by a wet etching process;

[0057] S8: removing the ONO film layer of the first thickness in the storage pipe area, and removing the ONO film layer of the third thickness in the selection pipe area and the device logic area to expose the substrate of the selection pipe area and the device logic area;

[0058] S9: forming a first gate oxide layer, wherein the first gate oxide layer covers the substrate of the selection pipe region and the device logic region; and,

[0059] S10: forming a second gate oxide layer, wherein the second gate oxide layer covers the remaining thickness of the ONO film layer in the storage pipe region.

[0060] For details, please refer to Figure 2-Figure 10 , Figure 2-Figure 10 It is a schematic diagram of a semiconductor structure in each process step of preparing an embedded SONOS device according to an embodiment of the present invention.

[0061] First, if Figure 2As shown, a substrate 10 is provided, and it can be seen that the embedded SONOS device includes: a storage pipe region SONOS, a selection pipe region NPASS, and a device logic region HV PMOS, HV NMOS, wherein HV PMOS is a high-voltage PMOS device region, and HV NMOS is a high-voltage NMOS device region. A pad oxide layer 20 is formed on the surface of the substrate 10, that is, a pad oxide layer 20 is formed on the substrate of the storage pipe region SONOS, the selection pipe region NPASS, and the device logic region HV PMOS, HV NMOS. Furthermore, a plurality of shallow trench isolation structures 11 are formed in the substrate 10 to separate storage devices and logic devices (the device logic area HV PMOS, HV NMOS) and other devices in the embedded SONOS device, wherein a first well region 12 is formed in the substrate 10 of the storage pipe area SONOS and the selection pipe area NPASS; a second well region 13 located on the first well region 12 is also formed in the substrate 10 of the storage pipe area SONOS; preferably, the conductivity type of the substrate 10 can be P type, and the conductivity type of the second well region 13 can be P type, which can be obtained by performing a P type ion implantation process on this area.

[0062] Then, if Figure 2 As shown, an ion implantation process is performed on the second well region 13 of the storage tube region SONOS and a tunneling storage region 14 is formed on the surface of the second well region 13 of the storage tube region SONOS. Specifically, the S2 step may include: first forming a photoresist layer 30 on the entire surface; then removing the photoresist of the storage area SONOS by a photolithography process to open a window above the pad oxide layer 20 of the storage area SONOS; then using the photoresist layer 30 as a mask, only performing a tunnel ion implantation process on the second well region 13 of the storage tube region SONOS, at this time, while injecting tunneling ions into the second well region 13, a tunneling storage region 14 can be obtained on the surface of the second well region 13 of the storage tube region SONOS; finally, removing the remaining photoresist layer 30.

[0063] Then, if Figure 3 As shown, the pad oxide layer 20 of the storage region SONOS, the selection region NPASS and the device logic regions HV PMOS and HV NMOS is removed. Specifically, in this embodiment, the pad oxide layer 20 may be removed by a wet etching process.

[0064] Further, such as Figure 4As shown, an ONO film layer 40 is formed, and the ONO film layer 40 covers the substrate 10 of the storage pipe area SONOS, the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS. Specifically, the ONO film layer 40 includes a stacked bottom silicon oxide layer, a silicon nitride layer and a top silicon oxide layer.

[0065] Then, if Figure 5 As shown, the first thickness of the ONO film layer of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS is removed. Specifically, the step S5 may include: first forming a photoresist layer 50; then removing the photoresist layer 50 of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS by a photolithography process; finally, the top silicon oxide layer in the ONO film layer 40 of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS may be removed by a dry etching process, at which time, only the silicon nitride layer and the bottom silicon oxide layer 41 are left on the substrate 10 of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS.

[0066] Further, such as Figure 5 As shown, the substrates of the selection pipe region NPASS and the device logic region are subjected to an ion implantation process to form a third well region 15 in the selection pipe region NPASS, a fourth well region 16 is formed in the substrate 10 of the device logic region HV PMOS, and a fifth well region 17 is formed in the substrate 10 of the device logic region HV NMOS. Specifically, a photoresist layer is re-coated, and a new photoresist layer is used as a mask to perform a P-type ion implantation process on the substrate of the selection pipe region NPASS to obtain the third well region 15 of the selection pipe region NPASS; an N-type ion implantation process is performed on the substrate of the high-voltage PMOS device region HV PMOS to obtain the fourth well region 16 of the high-voltage PMOS device region HV PMOS; and a P-type ion implantation process is performed on the substrate of the high-voltage NMOS device region HVNMOS to obtain the fifth well region 17 of the high-voltage NMOS device region HV NMOS. In addition, after obtaining the respective well regions, a step of removing the new photoresist layer may also be included.

[0067] Then, if Figure 6As shown, a wet etching process is used to remove the second thickness of the ONO film layer of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS. Specifically, in this embodiment, a hot phosphoric acid solution can be used to remove the silicon nitride layer of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS. At this time, only the bottom silicon oxide layer 42 remains on the surface of the substrate 10 of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS. In the present invention, a wet etching process is used to remove the second thickness of the ONO film layer, which avoids the situation in which the silicon nitride in the ONO film layer is dry-etched in the traditional process, thereby causing silicon nitride residue, and improves the yield of the device.

[0068] Further, such as Figure 7 As shown, the first thickness of the ONO film layer of the storage pipe area SONOS is removed, and the third thickness of the ONO film layer of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS is removed to expose the substrate 10 of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS. Specifically, in this embodiment, a full-wafer wet etching process can be used to remove the top silicon oxide layer of the storage pipe area SONOS, and the bottom silicon oxide layer of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS is removed. At this time, only the silicon nitride layer and the bottom silicon oxide layer 41 are left on the substrate of the storage pipe area SONOS, and the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS have been exposed from the substrate surface.

[0069] Then, if Figure 8 As shown, a first gate oxide layer 60 is formed, and the first gate oxide layer 60 covers the substrate 10 of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS. Specifically, in this embodiment, a high-temperature furnace tube oxidation process can be used to form the first gate oxide layer 60. Because the surface of the silicon nitride layer of the storage pipe area SONOS cannot be formed into an oxide layer by a high-temperature furnace tube oxidation process, the high-temperature furnace tube oxidation process can be used to form the first gate oxide layer 60 only on the substrate 10 of the selection pipe area NPASS and the device logic area HV PMOS, HV NMOS.

[0070] Finally, if Fig. 9 As shown, a second gate oxide layer 70 is formed, and the second gate oxide layer 70 covers the remaining thickness of the ONO film layer (bottom silicon oxide layer and silicon nitride layer) 41 of the storage pipe region SONOS. Specifically, the second gate oxide layer 70 can be formed by an in-situ steam generation process (ISSG).

[0071] It is worth noting that in the present embodiment, in the process of forming the second gate oxide layer 70 of the ONO film layer covering the remaining thickness of the storage pipe area SONOS by using the in-situ water vapor generation process (ISSG), the second gate oxide layer 70 (not shown) of a certain thickness will also be correspondingly formed on the first gate oxide layer 60 on the substrate 10 of the selection pipe area NPASS and the device logic areas HV PMOS and HV NMOS.

[0072] Better, such as Fig.10 As shown, after forming the second gate oxide layer 70, the preparation method of the embedded SONOS device further includes: forming a plurality of gate structures 80 and forming source and drain regions 18, wherein the gate structures 80 are respectively located on the second gate oxide layer 70 of the storage pipe region SONOS, the first gate oxide layer 60 of the selection pipe region NPASS (which can also be understood as the second gate oxide layer 70 of the selection pipe region NPASS), and the first gate oxide layer 60 of the device logic region HV PMOS, HV NMOS (which can also be understood as the second gate oxide layer 70 of the device logic region HV PMOS, HV NMOS); the source and drain regions are respectively located in the second well region 13 of the storage pipe region SONOS, the third well region 15 of the selection pipe region NPASS, the fourth well region 16 of the high-voltage PMOS device region HV PMOS, and the fifth well region 17 of the high-voltage NMOS device region HV NMOS.

[0073] The present application adopts a high-temperature furnace tube oxidation process to form the first gate oxide layer 60 and adopts an in-situ water vapor generation process to form the second gate oxide layer 70, and there are no other additional wet process steps between forming the second gate oxide layer 70 and forming the gate structure 80, thereby reducing the fluctuation of the total thickness (thickness of ONO film) of the remaining thickness of the ONO film layer 41 + the second gate oxide layer 70 caused by the wet process, reducing the divergence of the SONOS device window, and improving the performance of the device.

[0074] Based on the same inventive concept, the embodiment of the present application also provides an embedded SONOS device, such as Fig. 9 As shown, the embedded SONOS device includes: a storage management area SONOS, a selection management area NPASS and a device logic area HV PMOS, HV NMOS, and the embedded SONOS device includes:

[0075] A substrate 10, wherein a plurality of shallow trench isolation structures 11 arranged at intervals are formed in the substrate 10 to separate the storage device and the logic device in the embedded SONOS device, wherein the substrate 10 of the storage pipe area SONOS and the selection pipe area NPASS are both formed with a first well region 12; the substrate 10 of the storage pipe area SONOS is also formed with a second well region 13 located on the first well region 12; the substrate 10 of the selection pipe area NPASS is formed with a third well region 15; the substrate 10 of the device logic areas HVPMOS and HV NMOS are sequentially formed with a fourth well region 16 and a fifth well region 17;

[0076] A tunneling storage area 14, wherein the tunneling storage area 14 is located on the second well area 13 in the substrate 10 of the storage tube area SONOS;

[0077] An ONO film layer 41 of remaining thickness, wherein the ONO film layer 41 of remaining thickness covers the substrate 10 of the storage tube area SONOS, wherein the ONO film layer 41 of remaining thickness is a stacked bottom silicon oxide layer and silicon nitride layer;

[0078] A first gate oxide layer 60, wherein the first gate oxide layer 60 covers the substrate 10 of the selection pipe region NPASS and the device logic regions HV PMOS and HV NMOS; and

[0079] The second gate oxide layer 70 covers the remaining thickness of the ONO film layer 41 of the storage pipe area SONOS. Preferably, the second gate oxide layer 70 covers the first gate oxide layer 60 on the substrate 10 of the selection pipe area NPASS and the device logic areas HVPMOS and HV NMOS.

[0080] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing an embedded SONOS device, characterized in that: The embedded SONOS device comprises: a storage region, a selection region and a device logic region. The method for preparing the embedded SONOS device comprises: A substrate is provided, wherein a pad oxide layer is formed on the surface of the substrate, and a plurality of shallow trench isolation structures arranged at intervals are formed in the substrate to separate a storage device and a logic device in an embedded SONOS device, wherein a first well region is formed in the substrates of the storage pipe region and the selection pipe region; and a second well region located on the first well region is also formed in the substrate of the storage pipe region; Performing an ion implantation process on the second well region of the storage pipe region and forming a tunneling storage region on the surface of the second well region of the storage pipe region; Removing the pad oxide layers of the storage pipe area, the selection pipe area and the device logic area; Forming an ONO film layer, wherein the ONO film layer covers the substrate of the storage pipe area, the selection pipe area and the device logic area; Removing the ONO film layer of the first thickness in the selection pipe area and the device logic area; Performing an ion implantation process on the substrate of the selection pipe region and the device logic region to form a third well region in the selection pipe region, and forming a fourth well region and a fifth well region in the substrate of the device logic region; Using a wet etching process to remove the ONO film layer of the second thickness in the selection pipe area and the device logic area; Removing the ONO film layer of the first thickness in the storage pipe area, and removing the ONO film layer of the third thickness in the selection pipe area and the device logic area to expose the substrate of the selection pipe area and the device logic area; forming a first gate oxide layer, wherein the first gate oxide layer covers the substrate of the selection pipe region and the device logic region; and, A second gate oxide layer is formed, wherein the second gate oxide layer covers the remaining thickness of the ONO film layer in the storage pipe region.

2. The method for preparing an embedded SONOS device according to claim 1, characterized in that: The first gate oxide layer is formed by a high temperature furnace tube oxidation process.

3. The method for preparing an embedded SONOS device according to claim 1, characterized in that: The second gate oxide layer is formed by an in-situ water vapor generation process.

4. The method for preparing an embedded SONOS device according to claim 1, characterized in that: The ONO film layer includes a stacked bottom silicon oxide layer, a silicon nitride layer and a top silicon oxide layer.

5. The method for preparing an embedded SONOS device according to claim 4, characterized in that: The removing of the ONO film layer of the first thickness in the selection pipe area and the device logic area comprises: The top silicon oxide layer of the selection pipe region and the device logic region is removed.

6. The method for preparing an embedded SONOS device according to claim 4, characterized in that: The removing of the ONO film layer of the second thickness in the selection pipe area and the device logic area comprises: The silicon nitride layer in the selection pipe region and the device logic region is removed by using a hot phosphoric acid solution.

7. The method for preparing an embedded SONOS device according to claim 4, characterized in that: The removing of the ONO film layer of the first thickness in the storage pipe area, and removing the ONO film layer of the third thickness in the selection pipe area and the device logic area to expose the substrate of the selection pipe area and the device logic area comprises: The top silicon oxide layer of the storage pipe area is removed by wet method, and the bottom silicon oxide layer of the selection pipe area and the device logic area is removed to expose the substrate of the selection pipe area and the device logic area.

8. The method for preparing an embedded SONOS device according to claim 4, characterized in that: The forming of the second gate oxide layer, wherein the second gate oxide layer covers the remaining thickness of the ONO film layer of the selection pipe region, comprises: A second gate oxide layer is formed, wherein the second gate oxide layer covers the silicon nitride layer in the selection pipe region.

9. The method for preparing an embedded SONOS device according to claim 1, characterized in that: After forming a second gate oxide layer, wherein the second gate oxide layer covers the remaining thickness of the ONO film layer in the selection pipe region, the method for preparing the embedded SONOS device comprises: A plurality of gate structures are formed, and the gate structures are respectively located on the second gate oxide layer of the storage pipe region, the first gate oxide layer of the selection pipe region, and the first gate oxide layer of the device logic region.

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