Three-dimensional memory device with backside interconnect structure

Abstract

The present disclosure relates to three-dimensional memory devices having backside interconnect structures. Embodiments of 3D memory devices and methods of forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers over the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer over and in contact with the plurality of channel structures, a plurality of source contact over and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer over the semiconductor layer including a source line grid in plan view. The plurality of source contacts are distributed under and in contact with the source line grid. A first set of the plurality of contacts are distributed under and in contact with the source line grid.

Description

[0001] This application is a divisional application of patent application 202080001492.X, filed on July 7, 2020, entitled "Three-dimensional storage device with back-side interconnect structure".

[0002] Cross-references to related applications

[0003] This application claims the benefit of international application No. PCT / CN2020 / 084600, filed on April 14, 2020, entitled “Three-dimensional memory device with backside source contact,” and international application No. PCT / CN2020 / 084603, filed on April 14, 2020, entitled “Method for forming three-dimensional memory device with backside source contact,” the entire contents of which are incorporated herein by reference. Technical Field

[0004] Embodiments of this disclosure relate to three-dimensional (3D) storage devices and methods of manufacturing the same. Background Technology

[0005] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells is approaching its upper limit.

[0006] 3D memory architecture can address the density limitations of planar memory cells. A 3D memory architecture includes memory arrays and peripheral devices for controlling signals to and from the memory arrays. Summary of the Invention

[0007] This article discloses embodiments of 3D storage devices and methods for forming the same.

[0008] In one example, the 3D memory device includes: a substrate; a memory stack layer comprising interleaved conductive and dielectric layers above the substrate; a plurality of channel structures, each extending vertically through the memory stack layer; a semiconductor layer above and in contact with the plurality of channel structures; a plurality of source contacts above the memory stack layer and in contact with the semiconductor layer; the plurality of contacts through the semiconductor layer; and a back interconnect layer above the semiconductor layer comprising a grid of source lines in a plan view. The plurality of source contacts are distributed below and in contact with the grid of source lines. A first group of the plurality of contacts is distributed below and in contact with the grid of source lines.

[0009] In another example, the 3D memory device includes: a substrate; a memory stack layer comprising interlaced conductive and dielectric layers above the substrate; a plurality of channel structures, each extending vertically through the memory stack layer; a semiconductor layer above and in contact with the plurality of channel structures; a plurality of source contacts in contact with the semiconductor layer; and a back interconnect layer above the semiconductor layer comprising a grid of source lines in a plan view. Each of the channel structures is below and laterally aligned with a corresponding one of the source contacts. The grid of source lines is above and in contact with each of the source contacts.

[0010] In another example, a method for forming a 3D memory device is disclosed. Peripheral circuitry is formed on a first substrate. Multiple channel structures, all extending vertically through the memory stack, are formed on the front side of a second substrate. The first and second substrates are bonded face-to-face such that the channel structures are above the peripheral circuitry. The second substrate is thinned. Multiple contacts are formed through the thinned second substrate, and multiple source contacts are formed in contact with the thinned second substrate. A source line grid is formed on the back side of the thinned second substrate such that the source line grid is above and in contact with a first group of the multiple contacts and the multiple source contacts. Attached Figure Description

[0011] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0012] Figure 1 A plan view of a cross-section of an exemplary 3D storage device having a central stepped region according to some embodiments of the present disclosure is shown.

[0013] Figure 2A A plan view of a cross-section of an exemplary 3D memory device having a back-side interconnect structure according to some embodiments of the present disclosure is shown.

[0014] Figure 2B A plan view of a cross-section of another exemplary 3D storage device having a back-side interconnect structure according to some embodiments of the present disclosure is shown.

[0015] Figure 2C A plan view of a cross-section of yet another exemplary 3D storage device having a back-side interconnect structure according to some embodiments of the present disclosure is shown.

[0016] Figure 3 A side view of a cross-section of an exemplary 3D storage device having a back-side interconnect structure according to some embodiments of the present disclosure is shown.

[0017] Figure 4 A plan view of a cross-section of yet another exemplary 3D storage device having a back-side interconnect structure according to some embodiments of the present disclosure is shown.

[0018] Figure 5 A side view of a cross-section of another exemplary 3D storage device having a back-side interconnect structure according to some embodiments of the present disclosure is shown.

[0019] Figures 6A-6D A manufacturing process for forming an exemplary 3D memory device with a back-side interconnect structure is illustrated according to some embodiments of the present disclosure.

[0020] Figure 7 A flowchart is shown of a method for forming an exemplary 3D storage device having a back-side interconnect structure according to some embodiments of the present disclosure.

[0021] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0022] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other constructions and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0023] Note that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0024] Generally, terms can be understood at least in part based on their use in context. For example, at least in part based on context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Similarly, at least in part based on context, terms such as "a" or "described" can also be understood to express either a singular or a plural usage. Additionally, at least in part based on context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily clearly described.

[0025] It should be readily understood that the meanings of “above,” “above,” and “on top” in this disclosure should be interpreted in the broadest sense, such that “above” not only means “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and “above” or “on top” not only means “above” or “on top” of something but also includes “above” or “on top” of something without an intermediate feature or layer therebetween (i.e., directly on something).

[0026] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly in a similar manner.

[0027] As used herein, the term "substrate" refers to a material on which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0028] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire underlying or overlying structure, or may have a extent smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. Layers may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (VIA) contacts are formed) and one or more dielectric layers.

[0029] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for component or process operation set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may be attributed to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a given quantity value that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a given quantity value that varies, for example, within 10%–30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0030] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND memory strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral surface of the substrate.

[0031] In some 3D memory devices, peripheral circuitry and memory arrays are stacked to save wafer area and increase cell density. For example, direct bonding technology has been proposed to fabricate some 3D NAND memory devices (e.g., with 96 or more layers) by bonding peripheral devices and memory arrays on different substrates face-to-face. The memory array substrate is then thinned to allow for through-silicon vertical interconnect (VIA), also known as “TSV,” to form through-silicon vertical interconnects (VIA) with pads on the back side of the thinned substrate, leading to vertical interconnects and wire bond pads. However, a significant amount of area on the back side of the thinned substrate is wasted because only wire bond pads and TSVs are formed on the back side (i.e., the top surface of the bonded 3D memory device).

[0032] Various embodiments of this disclosure provide 3D memory devices with back-side interconnect structures to better utilize the back-side area and optimize metal wiring. Some or all of the source lines, source select gate (SSG) lines, and power lines can be moved from the front side of the memory array substrate (i.e., in the middle of the bonded 3D memory device) to the back side of the memory array substrate (i.e., on the top surface of the bonded 3D memory device) as a “back-side interconnect structure.” In some embodiments, the back-side source lines also allow source contacts to be formed on the back side of the memory array substrate, which can avoid leakage current and parasitic capacitance through the memory stack layers between the word lines and the source contacts on the front side. Various back-side interconnect structures can be arranged in different layouts (e.g., a grid (e.g., a comb-shaped grid) or parallel straight lines) to optimize metal wiring and reduce overall resistance based on different memory array structures, thereby further improving the electrical performance of the 3D memory device.

[0033] Figure 1 A plan view of a cross-section of an exemplary 3D storage device 100 having a central stepped region according to some embodiments of the present disclosure is shown. Figure 1 As shown in the plan view, the storage stack layer of the 3D storage device 100 may include two core array regions 106A and 106B having a channel structure 110 therein, and a stepped region 104 between the core array regions 106A and 106B in a first lateral direction. Note that in Figure 1 The x-axis and y-axis included in the figure represent two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. According to some embodiments, the 3D memory device 100 includes a central stepped region 104 that laterally divides the memory stack into two portions in the x-direction (e.g., the word line direction): a first core array region 106A and a second core array region 106B, each of which includes an array of channel structures 110.

[0034] According to some embodiments, the 3D memory device 100 also includes parallel insulating structures 108 (e.g., gate line gaps (GLS)) in the y-direction (e.g., bit line direction), all of which extend laterally in the x-direction to divide the array of core array regions 106A and 106B and the channel structures 110 therein into blocks 102. The 3D memory device 100 may also include parallel drain select gate (DSG) cutouts 112 (sometimes referred to as top select gate (TSG) cutouts) in the y-direction within the blocks 102 to further divide the blocks 102 into finger-like portions. It should be understood that the layout of the stepped regions and the core array regions is not limited to... Figure 1This is one example, and in other examples any other suitable layout may be included, such as having a side stepped area at the edge of the storage stack layer.

[0035] The cross-section of the 3D memory device 100 is on the front side of the 3D memory device 100 on which the channel structure 110 is formed. In some embodiments, the 3D memory device 100 is flipped over and bonded to another semiconductor device, such as a peripheral device having peripheral circuitry for facilitating the operation of the 3D memory device 100. Thus, the back side of the 3D memory device 100 can become the top surface of the bonded device that can be used for pad takeout. As described in detail below, in addition to the bonding pads, the area on the back side of the 3D memory device 100 (i.e., the top surface of the bonded device) can be used to form various back-side interconnect structures in various layouts to optimize metal wiring and reduce overall resistance, as well as reduce leakage current and parasitic capacitance on the front side of the 3D memory device 100.

[0036] Figure 2A A cross-sectional plan view of an exemplary 3D memory device 200 having a back-side interconnect structure according to some embodiments of the present disclosure is shown. The 3D memory device 200 may be an example of a 3D memory device 100 after flip-chip bonding, and Figure 2A An example of the back side of the 3D memory device 100 after flip-chip bonding is shown. Figure 2A As shown, according to some embodiments, in a plan view, the memory stack layer of the 3D memory device 200 includes two core array regions 206A and 206B having channel structures (not shown) therein, and a stepped region 204 between the core array regions 206A and 206B in the x-direction (e.g., word line direction). In some embodiments, in a plan view, the 3D memory device 200 also includes a peripheral region 208 outside the core array regions 206A or 206B of the memory stack layer. In the y-direction (e.g., bit line direction), Figure 2A The back-side interconnect structure in a block 202 of a 3D storage device 200 is shown, and the back-side interconnect structure can be repeated any suitable number of times in multiple blocks.

[0037] In some embodiments, in a plan view, the 3D storage device 200 includes a source line grid 210. For example... Figure 2AAs shown, according to some embodiments, the source line grid 210 has a comb-like shape. For example, the source line grid 210 may include axial source lines 214 that extend laterally in one of the core array regions 206A and 206B in the y-direction (e.g., bit line direction). The source line grid 210 may also include a plurality of parallel toothed source lines 212 that extend laterally in the x-direction (e.g., word line direction) from one axial source line 214 in core array region 206A through step region 204 to another core array region 206B. In some embodiments, the source line grid 210 extends, for example, across core array regions 206A and 206B and step region 204 in the x-direction, but not in the peripheral region 208.

[0038] The 3D storage device 200 may also include back-side source contacts 216 (e.g., in the form of VIA contacts) in the core array regions 206A and 206B, but not in the stepped region 204 or the peripheral region 208. For example, the back-side source contacts 216 may be uniformly distributed in the core array regions 206A or 206B. In some embodiments, the back-side source contacts 216 are distributed below and in contact with the source line grid 210. For example, the back-side source contacts 216 may be uniformly distributed below and in contact with the source line grid 210 in the core array regions 206A or 206B. In other words, in the core array regions 206A or 206B, the distance between adjacent back-side source contacts 216 is the same (e.g., in the x-direction and / or y-direction). In some embodiments, the back-side source contacts 216 are distributed below and in contact with the toothed source lines 212 of the source line grid 210, but are not distributed below or in contact with the axial source lines 214 of the source line grid 210. It should be understood that in some examples, the back-side source contacts 216 in the form of VIA contacts can be replaced by one or more source wall contacts (i.e., interconnects).

[0039] The 3D memory device 200 may also include multiple sets of contacts 218, 226, and 230, such as through-silicon contacts (TSCs). In some embodiments, contacts 218 are distributed below and contact the source line grid 210 in a portion of the stepped region 204 and the core array regions 206A and 206B. According to some embodiments, since contacts 218 may be TSCs extending through the silicon substrate, contacts 218 are distributed below and contact the peripheral portion of the source line grid 210 (including a portion in the stepped region 204) to avoid overlapping with the channel structure in the central portion of the source line grid 210 in the core array regions 206A and 206B. For example, as Figure 2A As shown, contacts 218 can be distributed and contacted below and with the axial source lines 214 and the outermost toothed source lines 212 of the source line grid 210 in the core array regions 206A and 206B. Contacts 218 can also be distributed and contacted below and with each toothed source line 212 of the source line grid 210 in the stepped region 204.

[0040] As described in detail below, each rear-side source contact 216 may be electrically connected to a common source (e.g., an array common source (ACS)) of the NAND memory strings in block 202, and a source line grid 210 is electrically connected to each rear-side source contact 216, and in turn electrically connected to the common source of the NAND memory strings in block 202. Similarly, each contact 218 may be electrically connected to peripheral circuitry of the 3D memory device 200, and a source line grid 210 is electrically connected to each contact 218, and in turn electrically connected to peripheral circuitry of the 3D memory device 200. Thus, peripheral circuitry may be electrically connected to the common source of the NAND memory strings in block 202 to control and / or sense the common source via metal wiring including the contacts 218, the source line grid 210, and the rear-side source contacts 216 on the back side of the 3D memory device 200. The layout of the contacts 218, the source line grid 210, and the back source contacts 216 (e.g., the comb shape of the source line grid 210 and the multiple distributed contacts 218 and the back source contacts 216) can reduce the total resistance of the metal wiring.

[0041] In some embodiments, the 3D storage device 200 includes another back-side interconnect structure—a power line grid 220 in a plan view. For example... Figure 2A As shown, according to some embodiments, the power line grid 220 has a comb-like shape. For example, the power line grid 220 may include axial power lines 224 extending laterally in the y-direction (e.g., bit line direction) within the peripheral region 208. The power line grid 220 may also include a plurality of parallel toothed power lines 222, each of which extends laterally in the x-direction (e.g., word line direction) from the axial power lines 224 in the peripheral region 208 through one core array region 206B and a stepped region 204 to another core array region 206A. In some embodiments, the power line grid 220 extends, for example, in the peripheral region 208, core array regions 206A and 206B, and stepped region 204, for example, from the peripheral region 208 across the core array regions 206A and 206B and the stepped region 204 in the x-direction. In some embodiments, the toothed power lines 222 intersect with the toothed source pole lines 212 in the y-direction.

[0042] In some embodiments, contacts 226 are distributed below and in contact with the power line grid 220 in the stepped region 204 and the peripheral region 208, but not in the core array regions 206A and 206B. According to some embodiments, since contacts 226 may be TSCs extending through the silicon substrate, contacts 226 are not in the core array regions 206A and 206B to avoid overlapping with the channel structures in the core array regions 206A and 206B. For example, as... Figure 2A As shown, contacts 226 may be distributed below portions of the axial power line 224 in the peripheral region 208 and the toothed power line 222 in the stepped region 204, and may contact portions of the axial power line 224 in the peripheral region 208 and the toothed power line 222 in the stepped region 204. It should be understood that in some examples, contacts 226 may be distributed in either the peripheral region 208 or the stepped region 204, but not in both. In other words, in a plan view, contacts 226 may be distributed in at least one of the stepped region 204 or the peripheral region 208 outside the memory array.

[0043] Each contact 226 can be electrically connected to a power line of the peripheral circuitry of the 3D memory device 200, and a power line grid 220 is electrically connected to each contact 226 and, in turn, to the power line of the peripheral circuitry of the 3D memory device 200. Power can be electrically connected to the power line grid 220 via bonding pads (not shown) to supply power to the 3D memory device 200 via metal wiring including the contacts 226 and the power line grid 220 on the back side of the 3D memory device 200. The bonding pads can be part of a back-side interconnect structure and can be electrically connected to the power line grid 220 via the contacts 226. For example, the layout of the contacts 226 and the power line grid 220 (e.g., a comb-like shape of the power line grid 220 and the plurality of distributed contacts 226) can reduce the total resistance of the metal wiring.

[0044] In some embodiments, the 3D memory device 200 includes another back-side interconnect structure—a plurality of SSG lines 228 in a plan view. Each SSG line 228 may extend across two core array regions 206A and 206B and a stepped region 204 in the x-direction (e.g., word line direction). In some embodiments, in a plan view, the SSG lines 228 are uniformly distributed in parallel in the y-direction (e.g., bit line direction). The SSG lines 228, tooth power lines 222, and tooth source pole lines 212 may be parallel. Figure 2A As shown, each SSG line 228 can be sandwiched between two tooth power lines 222 in the y-direction. It should be understood that in other examples, the arrangement of the SSG line 228, tooth power line 222, and tooth source pole line 212 can vary. For example, the SSG line 228, tooth power line 222, and tooth source pole line 212 can be staggered in the y-direction.

[0045] In some embodiments, in a plan view, contacts 230 are distributed below and in contact with the SSG line 228 in the core array regions 206A and 206B, but not in the stepped region 204 and the peripheral region 208. For example, as Figure 2A As shown, at least one contact 230 in core array region 206A and at least one contact 230 in core array region 206B are below and in contact with each SSG line 228. The SSG in the storage stack layer of the 3D storage device 200 can be cut in the stepped region 204, thus becoming two disconnected portions in core array regions 206A and 206B, respectively. Each contact 230 can be electrically connected to a portion of the SSG of the 3D storage device 200 in the corresponding core array region 206A or 206B. By extending in the x-direction above the stepped region 204 between the two core array regions 206A and 206B and electrically connecting to the contact 230 in each core array region 206A or 206B, the SSG line 228 can thus be electrically connected to the two disconnected portions of the SSG in core array regions 206A and 206B. In other words, the two disconnected portions of the SSG in the core array regions 206A and 206B can be "bridged" across the stepped region 204 via metal wiring, which includes SSG lines 228 and contacts 230 on the back side of the 3D memory device 200. The arrangement of contacts 230 and SSG lines 228 (e.g., multiple parallel SSG lines 228 and multiple distributed contacts 230) can reduce the total resistance of the metal wiring.

[0046] It should be understood that the back-side interconnect structure is not limited to Figure 2A As shown in the examples, and depending on the design of the 3D memory device (e.g., electrical performance specifications such as voltage and resistance), the back-side interconnect structure can include any other suitable layout. It should also be understood that, as Figure 2A As shown, additional back-side interconnect structures can be disposed on the same surface as the source line grid 210, power line grid 220, and SSG line 228. For example, bonding pads (not shown) for wire bonding can also be disposed on the back side of the 3D memory device 200, for example, in the peripheral region 208. It should also be understood that in other examples, Figure 2A One or more back-side interconnect structures shown may not be disposed on the back side of the 3D memory device; for example, they may be replaced by corresponding front-side interconnect structures disposed on the front side of the 3D memory device.

[0047] Figure 2B A cross-sectional plan view of another exemplary 3D memory device 201 with a back-side interconnect structure according to some embodiments of the present disclosure is shown. The 3D memory device 201 can be connected to... Figure 2AThe 3D storage device 200 is basically the same as that in the previous version, except that the 3D storage device 201 does not include... Figure 2A The SSG line 228 and contact 230 are in the middle. Figure 2C A cross-sectional plan view of yet another exemplary 3D memory device 203 with a back-side interconnect structure according to some embodiments of the present disclosure is shown. The 3D memory device 203 can be connected to... Figure 2A The 3D storage device 200 is basically the same as that in the previous version, except that the 3D storage device 203 does not include... Figure 2A The SSG line 228, power line grid 220, and contacts 230 and 226 are included. Furthermore, by removing the power line grid 220, the source line grid 210 in the 3D memory device 203 can have two parallel axial source lines 214 in the core array regions 206A and 206B, respectively.

[0048] Figure 3 A cross-sectional side view of an exemplary 3D memory device 300 having a back-side interconnect structure according to some embodiments of the present disclosure is shown. The 3D memory device 300 may be... Figures 2A-2C An example of 3D storage devices 200, 201 and 203. Figures 2A-2C It can be shown Figure 3 The image shows a plan view of a cross-section in plane AA of the 3D memory device 300, i.e., the back side of the 3D memory device 300. In some embodiments, the 3D memory device 300 is a bonded chip including a first semiconductor structure 302 and a second semiconductor structure 304 stacked on top of the first semiconductor structure 302. According to some embodiments, the first semiconductor structure 302 and the second semiconductor structure 304 are bonded at a bonding interface 306 therebetween. Figure 3 As shown, the first semiconductor structure 302 may include a substrate 301, which may include silicon (e.g., single-crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0049] The first semiconductor structure 302 of the 3D memory device 300 may include peripheral circuitry 308 on the substrate 301. Note that... Figure 3The x-axis, y-axis, and z-axis are included to illustrate the spatial relationships of components in the 3D memory device 300. The substrate 301 includes two lateral surfaces extending laterally in the xy-plane: a front surface on the front side of the wafer and a back surface on the back side opposite the front side of the wafer. The x and y directions are two orthogonal directions in the wafer plane: the x-direction is the word line direction, and the y-direction is the bit line direction. The z-axis is perpendicular to both the x and y axes. As used herein, when the substrate (e.g., substrate 301) of a semiconductor device (e.g., 3D memory device 300) is positioned in the lowest plane of the semiconductor device in the z-direction (a direction perpendicular to the xy-plane), whether a component (e.g., layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., layer or device) is determined relative to the substrate of the semiconductor device in the z-direction. The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0050] In some embodiments, peripheral circuitry 308 is configured to control and sense the 3D memory device 300. Peripheral circuitry 308 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for facilitating the operation of the 3D memory device 300, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuitry 308 may include transistors formed "on" substrate 301, wherein all or a portion of the transistors are formed in substrate 301 (e.g., below the top surface of substrate 301) and / or directly on substrate 301. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistor) may also be formed in substrate 301. According to some embodiments, transistors with advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, etc.) are high-speed. It should be understood that in some examples, peripheral circuitry 308 may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random access memory (SRAM)). In some embodiments, peripheral circuitry 308 includes one or more power lines to provide power (e.g., voltage) to peripheral circuitry 308.

[0051] In some embodiments, the first semiconductor structure 302 of the 3D memory device 300 further includes an interconnect layer (not shown) above the peripheral circuitry 308 for transmitting electrical signals to and from the peripheral circuitry 308. The interconnect layer may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and VIA contacts. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as mid-end process (MEOL) interconnects and back-end process (BEOL) interconnects. The interconnect layer may also include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”) in which interconnects and VIA contacts can be formed. In other words, the interconnect layer may include interconnects and VIA contacts in multiple ILD layers. The interconnects and VIA contacts in the interconnect layer may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-dielectric-constant (low-k) dielectrics, or any combination thereof.

[0052] like Figure 3 As shown, the first semiconductor structure 302 of the 3D memory device 300 may further include a bonding layer 310 at the bonding interface 306 and above the interconnect layer and peripheral circuitry 308. The bonding layer 310 may include a plurality of bonding contacts 311 and a dielectric for electrically isolating the bonding contacts 311. The bonding contacts 311 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of ​​the bonding layer 310 may be formed with a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 311 in the bonding layer 310 and the surrounding dielectric may be used for hybrid bonding.

[0053] Similarly, such as Figure 3 As shown, the second semiconductor structure 304 of the 3D memory device 300 may further include a bonding layer 312 at the bonding interface 306 and above the bonding layer 310 of the first semiconductor structure 302. The bonding layer 312 may include a plurality of bonding contacts 313 and a dielectric material for electrically isolating the bonding contacts 313. The bonding contacts 313 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of ​​the bonding layer 312 may be formed with a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 313 in the bonding layer 312 and the surrounding dielectric material may be used for mixed bonding. According to some embodiments, the bonding contacts 313 contact the bonding contacts 311 at the bonding interface 306.

[0054] As described in detail below, the second semiconductor structure 304 can be bonded face-to-face to the top of the first semiconductor structure 302 at the bonding interface 306. In some embodiments, as a result of hybrid bonding (also referred to as “metal / dielectric hybrid bonding”), the bonding interface 306 is disposed between the bonding layers 310 and 312, the hybrid bonding being a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer (e.g., solder or adhesive)) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 306 is where the bonding layers 312 and 310 meet and bond. In practice, the bonding interface 306 can be a layer of a certain thickness, the layer comprising the top surface of the bonding layer 310 of the first semiconductor structure 302 and the bottom surface of the bonding layer 312 of the second semiconductor structure 304.

[0055] In some embodiments, the second semiconductor structure 304 of the 3D memory device 300 further includes an interconnect layer (not shown) above the bonding layer 312 for transmitting electrical signals. The interconnect layer may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer may also include one or more ILD layers in which interconnect lines and VIA contacts can be formed. The interconnect lines and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0056] In some embodiments, the 3D storage device 100 is a NAND flash memory storage device, wherein storage cells are provided in the form of an array of NAND memory strings. Figure 3 As shown, the second semiconductor structure 304 of the 3D memory device 300 may include an array of channel structures 324 that serve as an array of NAND memory strings. Figure 3 As shown, each channel structure 324 may extend vertically through multiple pairs, each including a conductive layer 316 and a dielectric layer 318. The staggered conductive layers 316 and dielectric layers 318 are part of a memory stack layer 314. The number of pairs of conductive layers 316 and dielectric layers 318 in the memory stack layer 314 (e.g., 32, 64, 96, 128, 160, 192, 224, 256 or more) determines the number of memory cells in the 3D memory device 300. It should be understood that in some examples, the memory stack layer 314 may have a multi-stack architecture (not shown) comprising multiple memory stacks stacked on top of each other. The number of pairs of conductive layers 316 and dielectric layers 318 in each memory stack may be the same or different.

[0057] The memory stack 314 may include a plurality of interleaved conductive layers 316 and dielectric layers 318. The conductive layers 316 and dielectric layers 318 in the memory stack 314 may alternate in the vertical direction. In other words, except for those at the top or bottom of the memory stack 314, each conductive layer 316 may be adjacent to two dielectric layers 318 on two sides, and each dielectric layer 318 may be adjacent to two conductive layers 316 on two sides. The conductive layers 316 may include conductive materials, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer 316 may include a gate electrode (gate line) surrounded by a binder layer and a gate dielectric layer. The gate electrode of the conductive layer 316 may extend laterally as a word line, terminating in one or more stepped structures of the memory stack 314. In some embodiments, the uppermost conductive layer 316 acts as an SSG for controlling the source of a NAND memory string. The dielectric layer 318 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0058] like Figure 3 As shown, the second semiconductor structure 304 of the 3D memory device 300 may also include a first semiconductor layer 320 above the memory stack layer 314 and a second semiconductor layer 322 above and in contact with the first semiconductor layer 320. The type of dopant in each semiconductor layer 320 and 322 may vary in different examples. When semiconductor layers 320 and 322 have the same type of dopant, semiconductor layers 320 and 322 can be considered as a single semiconductor layer. It should be understood that in other examples, the number of semiconductor layers may be different and is not limited to. Figure 3 The example shown.

[0059] In some embodiments, each channel structure 324 includes a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel 328) and a composite dielectric layer (e.g., as a storage film 326). In some embodiments, the semiconductor channel 328 comprises silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the storage film 326 is a composite layer comprising a tunneling layer, a storage layer (also referred to as a "charge trapping layer"), and a barrier layer. The remaining space of the channel structure 324 may be partially or completely filled with a capping layer comprising a dielectric material such as silicon oxide and / or an air gap. The channel structure 324 may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the capping layer, semiconductor channel 328, tunneling layer, storage layer, and barrier layer of the storage film 326 are arranged radially in this order from the center of the column toward the outer surface. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the storage film 326 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0060] In some embodiments, the channel structure 324 further includes a channel plug 329 in the bottom portion of the channel structure 324 (e.g., at the lower end). As used herein, when the substrate 301 is placed in the lowest plane of the 3D memory device 300, the “upper end” of the component (e.g., the channel structure 324) is the end farther from the substrate 301 in the z-direction, and the “lower end” of the component (e.g., the channel structure 324) is the end closer to the substrate 301 in the z-direction. The channel plug 329 may comprise a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 329 acts as the drain of a NAND memory string.

[0061] like Figure 3 As shown, each channel structure 324 may extend vertically through the first semiconductor layer 320 and the interleaved conductive layers 316 and dielectric layers 318 of the memory stack layer 314. In some embodiments, the first semiconductor layer 320 surrounds a portion of the channel structure 324 and contacts a semiconductor channel 328 comprising polysilicon. In other words, according to some embodiments, the memory film 326 is broken at the portion of the channel structure 324 adjacent to the first semiconductor layer 320, thereby exposing the semiconductor channel 328 to contact the surrounding first semiconductor layer 320. In some embodiments, each channel structure 324 may also extend vertically into a second semiconductor layer 322. It should be understood that the structure of the top portion of the channel structure 324 and its relative position with respect to the semiconductor layers 320 and 322 are not limited to... Figure 3 The example in the example is shown, and it can vary in other examples.

[0062] like Figure 3 As shown, the second semiconductor structure 304 of the 3D memory device 300 may further include insulating structures 330, each extending vertically through the interlaced conductive layers 316 and dielectric layers 318 of the memory stack 314. Each insulating structure 330 may also extend laterally to divide the channel structure 324 into multiple blocks. In other words, the memory stack 314 can be divided into multiple memory blocks by the insulating structures 330, thereby dividing the array of channel structures 324 into each memory block. According to some embodiments, unlike the slotted structures in the existing 3D NAND memory devices described above that include front-side ACS contacts, the insulating structures 330 do not include any contacts (i.e., do not act as source contacts) and therefore do not introduce parasitic capacitance and leakage current with the conductive layers 316 (including word lines). In some embodiments, each insulating structure 330 includes an opening (e.g., a slot) filled with one or more dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 330 may be filled with silicon oxide.

[0063] Instead of having a front source contact, the 3D memory device 300 may include a back source contact 332 located above the memory stack layer 314 and in contact with the second semiconductor layer 322. The back source contact 332 may be... Figures 2A-2C An example of a back-side source contact 216. Source contacts 332 and the storage stack 314 (and the insulating structure 330 passing through it) may be disposed on opposite sides of the semiconductor layer 322 (the thinned substrate) and are thus considered "back-side" source contacts. In some embodiments, source contacts 332 further extend into the second semiconductor layer 322 and are electrically connected to the semiconductor channel 328 of the channel structure 324 via semiconductor layers 320 and 322. It should be understood that the depth to which source contacts 332 extend into the second semiconductor layer 322 can vary in different examples. In some embodiments where the second semiconductor layer 322 is an N-well, source contacts 332 are also referred to as back-side "N-well pick-up". Source contacts 332 may include any suitable type of contact. In some embodiments, source contacts 332 include VIA contacts (e.g., as...). Figures 2A-2C (Backside source contact 216). In some embodiments, source contact 332 includes laterally extending wall-like contacts. Source contact 332 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

[0064] like Figure 3As shown, the 3D memory device 300 may further include a BEOL back interconnect layer 333 above and in contact with the source contacts 332 for pad routing, such as transmitting electrical signals between the 3D memory device 300 and external circuitry. The back interconnect layer 333 may also include the aforementioned... Figures 2A-2C Examples of back-side interconnect structures described herein. In some embodiments, the back-side interconnect layer 333 includes one or more ILD layers 334 on the second semiconductor layer 322 and a redistribution layer 336 on the ILD layers 334. According to some embodiments, the upper end of the source contact 332 is flush with the top surface of the ILD layer 334 and the bottom surface of the redistribution layer 336, and the source contact 332 extends vertically through the ILD layer 334 into the second semiconductor layer 322. The ILD layer 334 in the back-side interconnect layer 333 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0065] The redistribution layer 336 in the back interconnect layer 333 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the redistribution layer 336 includes Al. Although in Figure 3 Not shown, but it should be understood that the redistribution layer 336 can be patterned to form various types of back-side interconnect structures described herein, such as Figure 2A The redistribution layer 336 contains source line grid 210, power line grid 220, and SSG line 228. In one example, source contacts 332 may be below and in contact with the source line grid 210 in the redistribution layer 336. In some embodiments, the back interconnect layer 333 further includes a passivation layer 338, which serves as the outermost layer for passivating and protecting the 3D memory device 300. A portion of the redistribution layer 336 may be exposed from the passivation layer 338 as bonding pads 340. In other words, the back interconnect layer 333 of the 3D memory device 300 may also include bonding pads 340 for wire bonding and / or bonding with the interposer layer. Although in Figures 2A-2C Although not shown in the diagram, in some examples, the bonding pad 340 may also be part of the back-side interconnect structure.

[0066] In some embodiments, the second semiconductor structure 304 of the 3D memory device 300 further includes contacts 342 and 344 extending through the second semiconductor layer 322. According to some embodiments, since the second semiconductor layer 322 may be a thinned substrate, contacts 342 and 344 are TSCs (Transient Current Collectors). Contact 342 may be... Figure 2A and Figure 2BAn example of contact 218 or 226 in the image. In some embodiments, contact 342 extends through the second semiconductor layer 322 and the ILD layer 334 to contact the redistribution layer 336 (e.g., including source line grid 210 and power line grid 220). For example, the source of a NAND memory string can be reached through semiconductor layers 320 and 322, source contact 332, and redistribution layer 336 (e.g., having...). Figures 2A-2C The source wire grid 210 in the middle is electrically connected to the contact 342 (e.g., as a source wire grid 210 in the middle). Figures 2A-2C (Contact 218 in the middle). In other words, contact 342 (as contact 218 or 226) can be below and in contact with source line grid 210 or power line grid 220 in redistribution layer 336, respectively. Although Figure 3 Not shown in the image, but as... Figure 2A As an example of contact 230, the 3D storage device 300 may also include a contact that extends further into the storage stack 314 to contact one of the conductive layers 316 (i.e., SSG) of the storage stack 314. Figure 2A (An example of contact 230 in the example). Contact (e.g., as...) Figure 2A The contact point 230 in the redistribution layer 336 can be below and in contact with the SSG line 228.

[0067] In some embodiments, contact 344 extends through the second semiconductor layer 322 and the ILD layer 334 to contact bonding pad 340. Both contacts 342 and 344 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least contact 344 may also include an insulator (e.g., a dielectric layer) to electrically insulate contact 344 from the second semiconductor layer 322.

[0068] In some embodiments, the 3D memory device 300 further includes peripheral contacts 346 and 348, both of which extend vertically to a second semiconductor layer 322 beyond the memory stack layer 314. Each peripheral contact 346 or 348 may have a depth greater than the depth of the memory stack layer 314 to extend vertically from the bonding layer 312 to the second semiconductor layer 322 in a peripheral region, such as corresponding to… Figures 2A-2CThe peripheral regions 208 and 204, or the core array regions 206A and 206B, are peripheral regions in which contacts 218 are disposed. In some embodiments, peripheral contacts 346 are below and in contact with contacts 342, such that source line grids 210 or power line grids 220 are electrically connected to peripheral circuitry 308 in the first semiconductor structure 302. In one example, the source of a NAND flash memory string can be electrically connected to a portion of peripheral circuitry 308 via redistribution layer 336 (e.g., including source line grids 210), contacts 342 (e.g., as contacts 218), and peripheral contacts 346 for controlling / sensing the source of the NAND flash memory string. In another example, power can be electrically connected to power lines of peripheral circuitry 308 to provide power to the 3D memory device 300 via redistribution layer 336 (e.g., including power line grids 220), contacts 342 (e.g., as contacts 226), and peripheral contacts 346. In some embodiments, peripheral contact 348 is below and in contact with contact 344, such that peripheral circuitry 308 in the first semiconductor structure 302 is electrically connected to bonding pad 340 for pad take-off at least through contact 344 and peripheral contact 348. Both peripheral contacts 346 and 348 may comprise one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0069] like Figure 3 As shown, the 3D memory device 300 also includes various local contacts (also referred to as "C1") as part of an interconnect structure, which are in direct contact with structures in the memory stack layer 314. In some embodiments, the local contacts include channel local contacts 350, each located below and in contact with the lower end of a corresponding channel structure 324. Each channel local contact 350 may be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts also include word line local contacts 352, each located below and in contact with a corresponding conductive layer 316 (including word lines) at a stepped structure of the memory stack layer 314 for word line fan-out. The local contacts (e.g., channel local contacts 350 and word line local contacts 352) may be electrically connected to the peripheral circuitry 308 of the first semiconductor structure 302 at least via bonding layers 312 and 310. Local contacts (such as channel local contact 350 and word line local contact 352) may each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0070] Figure 4A cross-sectional plan view of yet another exemplary 3D memory device 400 with a back-side interconnect structure according to some embodiments of the present disclosure is shown. The 3D memory device 400 may be an example of a 3D memory device 100 after flip-chip bonding, and Figure 4 An example of the back side of the 3D memory device 100 after flip-chip bonding is shown. Figure 4 As shown, according to some embodiments, in a plan view, the memory stack layer of the 3D memory device 400 includes two core array regions 406A and 406B having a channel structure 408 therein, and a stepped region 404 between the core array regions 406A and 406B in the x-direction (e.g., word line direction). In the y-direction (e.g., bit line direction), Figure 4 The back-side interconnect structure in a block 402 of a 3D storage device 400 is shown, and the back-side interconnect structure can be repeated any suitable number of times in multiple blocks.

[0071] In some embodiments, in a plan view, the 3D storage device 400 includes a source line grid 410. In some embodiments, the source line grid 410 is located in core array regions 406A and 406B and a stepped region 404. Figure 4 As shown, according to some embodiments, in a plan view, the source line grid 410 includes a plurality of parallel source lines 412 that extend laterally across the stepped region 404 and the core array regions 406A and 406B in the x-direction (e.g., word line direction), similar to Figures 2A-2C The source pole line 212 of the source pole line grid 210 in the image is different from the source pole line 212. Figure 2A and Figure 2B A source line grid 410 having a single-axis source line 214, in a plan view, may further include a plurality of parallel source lines 414 extending laterally in the y-direction (e.g., bit line direction). Figure 4 As shown, parallel source lines 414 can be disposed in the core array regions 406A and 406B and in the stepped region 404. It should be understood that in some examples, source lines 414 may not be disposed in the stepped region 404, but only in the core array regions 406A and 406B.

[0072] The 3D storage device 400 may also include back-side source contacts 416 (e.g., in the form of VIA contacts) in the core array regions 406A and 406B, but not in the stepped region 404. For example, the back-side source contacts 416 may be uniformly distributed in the core array regions 406A or 406B. Figure 4As shown, according to some embodiments, each channel structure 408 is below and laterally aligned with a corresponding one of the back source contacts 416. In other words, each channel structure 408 may overlap with a corresponding back source contact 416 directly on top of the channel structure 408, thereby reducing the resistance between the source of the NAND memory string and the back source contact 416. In some embodiments, since the channel structures 408 are arranged in an array of rows and columns, the back source contacts are also arranged in an array of rows and columns. In a plan view, each source line 414 or 412 may contact each of the back source contacts 416 in a row or column of the array. In some embodiments, each source line 414 extending in the y-direction may contact each of the back source contacts 416 in a column. It should be understood that in some examples, each source line 412 extending in the x-direction may contact each of the back source contacts 416 in a row. In some embodiments, in a plan view, each source line 414 or 412 contacts each of two adjacent row or column back-side source contacts 416 in the array. For example, as Figure 4 As shown, each source line 414 extending in the y-direction can contact each of the back-side source contacts 416 in two adjacent columns. Although not shown, similarly in other examples, each source line 412 extending in the x-direction can contact each of the back-side source contacts 416 in two adjacent rows.

[0073] The 3D memory device 400 may also include contacts 418, such as TSCs. In some embodiments, contacts 418 are distributed below and contact the source line grid 410 in a portion of the stepped region 404 and the core array regions 406A and 406B. According to some embodiments, since contacts 418 may be TSCs extending through the silicon substrate, contacts 418 are distributed below and contact the peripheral portion of the source line grid 410 (including the portion in the stepped region 404) to avoid overlapping with the channel structure 408 in the central portion of the source line grid 410 in the core array regions 406A and 406B. For example, as Figure 4 As shown, contacts 418 can be distributed below and in contact with the outermost source lines 412 and 414 in the core array regions 406A and 406B. Contacts 418 can also be distributed below and in contact with the source line 414 in the stepped region 404.

[0074] As described in detail below, each rear-side source contact 416 can be electrically connected to the source of the corresponding NAND memory string, and the source line grid 410 is electrically connected to each rear-side source contact 416, and in turn, electrically connected to the source of the NAND memory string. Similarly, each contact 418 can be electrically connected to the peripheral circuitry of the 3D memory device 400, and the source line grid 410 is electrically connected to each contact 418, and in turn, electrically connected to the peripheral circuitry of the 3D memory device 400. As a result, the peripheral circuitry can be electrically connected to the source of the NAND memory string to control and / or sense the source via metal wiring including the contacts 418, the source line grid 410, and the rear-side source contacts 416 on the back side of the 3D memory device 400. Figures 2A-2C Compared to the example in the previous example, the arrangement of contact 418, source line grid 410, and back source contact 416 (e.g., an array of back source contacts 416 corresponding to an array of channel structures 408), and source line 414 that contacts the back source contacts 416 in two adjacent columns in the core array regions 406A and 406B, can further reduce the total resistance of the metal wiring.

[0075] Figure 5 A side view of a cross-section of another exemplary 3D memory device 500 having a back-side interconnect structure according to some embodiments of the present disclosure is shown. The 3D memory device 500 may be... Figure 4 An example of a 3D storage device 400. A 3D storage device 500 is similar. Figure 3 The 3D memory device 300 in the middle, except for the arrangement of the source contact 502. For example... Figure 5 As shown, each channel structure 324 has a corresponding source contact 502 (e.g., Figure 4 Below and (e.g., laterally aligned with) the back-side source contact 416 (in one example), the corresponding source contact 502 contacts the semiconductor layer 322. It should be understood that, for ease of description, details of other identical structures in both 3D memory devices 500 and 300 are not repeated.

[0076] Figures 6A-6D A manufacturing process for forming an exemplary 3D memory device with a back-side interconnect structure is illustrated according to some embodiments of the present disclosure. Figure 7 A flowchart is shown of a method 700 for forming an exemplary 3D storage device having a back-side interconnect structure according to some embodiments of the present disclosure. Figures 6A-6D and Figure 7 Examples of 3D storage devices depicted include Figures 2A-2C and Figure 4 The 3D storage devices 200, 201, 203, and 400 depicted in the image will be described together. Figures 6A-6D and Figure 7 It should be understood that the operations shown in method 700 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, they may be performed simultaneously or in conjunction with... Figure 7 Some of the different sequences of operations are shown.

[0077] Reference Figure 7 Method 700 begins with operation 702, in which peripheral circuitry is formed on a first substrate. The first substrate may be a silicon substrate. Figure 6A As shown, a peripheral circuit 604 having multiple transistors is formed on a first silicon substrate 602 using a variety of processes (including but not limited to photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP)) and any other suitable process.

[0078] like Figure 7 As shown, method 700 proceeds to operation 704, wherein a plurality of channel structures extending perpendicularly through the memory stack layer are formed on the front side of the second substrate. In some embodiments, in a plan view, the memory stack layer includes two core array regions having channel structures and a stepped region between the two core array regions in a first lateral direction. Figure 6A As shown, an array of channel structures 608 extending vertically through the memory stack layers is formed on the front side of the second silicon substrate 606.

[0079] like Figure 7 As shown, method 700 proceeds to operation 706, wherein the first substrate and the second substrate are bonded face-to-face such that the channel structure is above the peripheral circuitry. Bonding may include hybrid bonding, such as 6A and... Figure 6B As shown, according to some embodiments, a second silicon substrate 606 and components formed thereon (e.g., channel structure 608) are flipped upside down and bonded (i.e., face-to-face) to an upward-facing first silicon substrate 602 and components formed thereon (e.g., peripheral circuitry 604), thereby forming a bonding interface 609 between silicon substrates 602 and 606.

[0080] like Figure 7 As shown, method 700 proceeds to operation 708, in which the second substrate is thinned. Thinning is performed from the back side of the second substrate. Figure 6B As shown, the second silicon substrate 606 is etched from the back side using CMP, polishing, dry etching, and / or wet etching. Figure 6A The second silicon substrate (606) is thinned to become a semiconductor layer 610 (i.e., a thinned second silicon substrate 606).

[0081] Method 700 proceeds to operation 710, such as... Figure 7As shown, a plurality of contacts are formed through a thinned second substrate, and a plurality of source contacts are formed in contact with the thinned second substrate. The contacts and source contacts are formed from the back side of the thinned second substrate. In some embodiments, each of the channel structures is below and laterally aligned with a corresponding one of the source contacts. In some embodiments, the source contacts are arranged in an array having rows and columns. Figure 6C As shown, a back-side source contact 612 is formed from the back side of semiconductor layer 610, and the back-side source contact 612 contacts semiconductor layer 610. In some embodiments, each channel structure 608 is below and laterally aligned with the corresponding back-side source contact 612. A plurality of TSCs 614, 616, and 618 may be formed from the back side of semiconductor layer 610 through semiconductor layer 610. In some embodiments, TSC 616 further extends into the memory stack layer to contact SSG in the memory stack layer.

[0082] like Figure 7 As shown, method 700 proceeds to operation 712, wherein a source line grid is formed on the back side of the thinned second substrate such that the source line grid is above and in contact with a first group and a plurality of source contacts among the plurality of contacts. In some embodiments, in a plan view, the source line grid comprises a plurality of parallel source lines that all extend laterally. In some embodiments, the source line grid is above and in contact with each of the source contacts. In some embodiments, in a plan view, each of the source lines is in contact with each of the source contacts in a row or column of an array. In some embodiments, in a plan view, each of the source lines is in contact with each of the source contacts in two adjacent rows or columns of an array. Figure 6D As shown, a source line grid 620 is formed on the back side of the semiconductor layer 610, such that the source line grid 620 is above and in contact with the back source contacts 612 and TSC 614. The layout of the source line grid 620, the back source contacts 612, and the TSC 614 can vary in different examples, for example, as shown. Figures 2A-2C and Figure 4 The example shown.

[0083] Method 700 proceeds to operation 714, such as... Figure 7 As shown, a plurality of SSG lines are formed on the back side of a thinned second substrate, such that the SSG lines are above and in contact with a second group of contacts. In some embodiments, in a plan view, each of the SSG lines extends across two core array regions and a stepped region in a first lateral direction, and the second group of contacts is distributed in the core array region. In some embodiments, in a plan view, the SSG lines are uniformly distributed parallel to each other in a second lateral direction perpendicular to the first lateral direction. Figure 6DAs shown, an SSG line 624 is formed on the back side of semiconductor layer 610, such that the SSG line 624 is above and in contact with TSC 616. The layout of the SSG line 624 and TSC 616 can vary in different examples, for example, as shown in... Figure 2A The example shown.

[0084] Method 700 proceeds to operation 716, such as... Figure 7 As shown, a power line grid is formed on the back side of a thinned second substrate, such that the power line grid is above and in contact with a third group of contacts. In some embodiments, in a plan view, the third group of contacts is distributed in at least one of a stepped region or a peripheral region outside the memory array. Figure 6D As shown, a power line grid 622 is formed on the back side of the semiconductor layer 610, such that the power line grid 622 is above and in contact with the TSC 618. The layout of the power line grid 622 and the TSC 618 can vary in different examples, for example, as shown in... Figure 2A and Figure 2B The example shown is illustrated. It should be understood that although operations 712, 714, and 716 are described above as three sequential operations, operations 712, 714, and 716 can be performed in the same manufacturing process. For example, one or more of the source line grid 620, power line grid 622, and SSG line 624 can be patterned and formed in the same manufacturing process.

[0085] According to one aspect of this disclosure, a 3D memory device includes: a substrate; a memory stack layer comprising interleaved conductive and dielectric layers above the substrate; a plurality of channel structures, each extending vertically through the memory stack layer; a semiconductor layer above and in contact with the plurality of channel structures; a plurality of source contacts above the memory stack layer and in contact with the semiconductor layer; the plurality of contacts extending through the semiconductor layer; and a back interconnect layer above the semiconductor layer comprising a grid of source lines in a plan view. The plurality of source contacts are distributed below and in contact with the grid of source lines. A first group of the plurality of contacts is distributed below and in contact with the grid of source lines.

[0086] In some embodiments, in a plan view, the storage stack layer includes two core array regions having a channel structure and a stepped region between the two core array regions in a first lateral direction.

[0087] In some embodiments, in a plan view, the back interconnect layer further includes a plurality of SSG lines, and a second group of the plurality of contacts is distributed below and in contact with the SSG lines.

[0088] In some embodiments, in a plan view, each of the SSG lines extends across two core array regions and a stepped region in a first lateral direction, and a second group of contacts is distributed in the core array region.

[0089] In some embodiments, each of the second group of contacts extends further into the storage stack layer to contact one of the conductive layers of the storage stack layer.

[0090] In some embodiments, in a plan view, the SSG lines are evenly distributed parallel to each other in a second lateral direction perpendicular to the first lateral direction.

[0091] In some embodiments, in a plan view, the back interconnect layer further includes a power line grid, and a third group of contacts is distributed below and in contact with the power line grid.

[0092] In some embodiments, in a plan view, the third group of contacts is distributed in at least one of the stepped or peripheral regions outside the storage array.

[0093] In some embodiments, the power cord mesh has a comb-like shape.

[0094] In some embodiments, the back interconnect layer also includes bonding pads electrically connected to the power line mesh via a third set of contacts.

[0095] In some embodiments, the source line grid has a comb-like shape.

[0096] According to another aspect of this disclosure, a 3D memory device includes: a substrate; a memory stack layer comprising interleaved conductive and dielectric layers above the substrate; a plurality of channel structures, each extending vertically through the memory stack layer; a semiconductor layer above and in contact with the plurality of channel structures; a plurality of source contacts in contact with the semiconductor layer; and a back interconnect layer above the semiconductor layer comprising a grid of source lines in a plan view. Each of the channel structures is below and laterally aligned with a corresponding one of the source contacts. The grid of source lines is above and in contact with each of the source contacts.

[0097] In some embodiments, the 3D memory device further includes a plurality of contacts that pass through the semiconductor layer and are distributed below and in contact with the source line grid.

[0098] In some embodiments, in a plan view, the storage stack layer includes one or more core array regions having a channel structure, and contacts are distributed outside the core array regions.

[0099] In some embodiments, in a plan view, the source line grid comprises a plurality of parallel source lines that all extend laterally.

[0100] In some embodiments, in a plan view, the source contacts are arranged in an array, and each of the source lines contacts each of the source contacts in a row or column of the array.

[0101] In some embodiments, in a plan view, each of the source lines contacts each of two adjacent source contacts in the array.

[0102] According to another aspect of this disclosure, a method for forming a 3D memory device is disclosed. Peripheral circuitry is formed on a first substrate. A plurality of channel structures, all extending vertically through a memory stack layer, are formed on the front side of a second substrate. The first and second substrates are bonded face-to-face such that the channel structures are above the peripheral circuitry. The second substrate is thinned. A plurality of contacts are formed through the thinned second substrate and a plurality of source contacts are formed in contact with the thinned second substrate. A source line grid is formed on the back side of the thinned second substrate such that the source line grid is above and in contact with a first group of the plurality of contacts and the plurality of source contacts.

[0103] In some embodiments, in a plan view, the storage stack layer includes two core array regions having a channel structure and a stepped region between the two core array regions in a first lateral direction.

[0104] In some embodiments, a plurality of SSG lines are formed on the back side of a thinned second substrate such that the SSG lines are above and in contact with a second set of a plurality of contacts.

[0105] In some embodiments, in a plan view, each of the SSG lines extends across two core array regions and a stepped region in a first lateral direction, and a second group of contacts is distributed in the core array region.

[0106] In some embodiments, in a plan view, the SSG lines are evenly distributed parallel to each other in a second lateral direction perpendicular to the first lateral direction.

[0107] In some embodiments, a power line grid is formed on the back side of a thinned second substrate such that the power line grid is above and in contact with a third set of contacts.

[0108] In some embodiments, in a plan view, the source line grid comprises a plurality of parallel source lines that all extend laterally.

[0109] In some embodiments, each of the channel structures is below and laterally aligned with the corresponding one of the source contacts, and the source line grid is above and in contact with each of the source contacts.

[0110] In some embodiments, in a plan view, the source contacts are arranged in an array, and each of the source lines contacts each of the source contacts in a row or column of the array.

[0111] In some embodiments, in a plan view, each of the source lines contacts each of two adjacent source contacts in the array.

[0112] The foregoing description of specific embodiments will thus reveal the general nature of this disclosure, enabling others to readily modify and / or adapt it to various applications, such as the specific embodiments, by applying knowledge of the art without departing from the general concept of this disclosure, without excessive experimentation. Therefore, based on the teachings and guidance set forth herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for descriptive rather than restrictive purposes, and that the terminology or terminology of this specification should be interpreted by those skilled in the art in light of the teachings and guidance.

[0113] Embodiments of this disclosure have been described above using functional building blocks that illustrate implementations of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternating boundaries can be defined as long as the specific functions and their relationships are properly performed.

[0114] The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of this disclosure as conceived by the inventors, and are therefore not intended to limit this disclosure and the appended claims in any way.

[0115] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: Substrate; A storage stack layer comprising, over the substrate, conductive and dielectric layers interleaved along a stacking direction; Multiple channel structures, each extending through the storage stack layer along the stacking direction; A semiconductor layer is provided above and in contact with the plurality of channel structures; the semiconductor layer includes a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer is closer to the memory stack layer than the second semiconductor layer. Multiple source contacts, which are located above the memory stack layer and in contact with the second semiconductor layer; A back interconnect layer above the second semiconductor layer, the back interconnect layer including a source line grid, the plurality of source contacts being distributed below the source line grid and in contact with the source line grid; as well as One or more dielectric layers are located between the second semiconductor layer and the source line grid, and the plurality of source contacts are connected to the second semiconductor layer through the one or more dielectric layers.

2. The semiconductor device according to claim 1, wherein, The source line grid includes axial source lines and a plurality of parallel toothed source lines, wherein the axial source lines extend along a first direction, and the plurality of parallel toothed source lines extend along a second direction perpendicular to the first direction. The axial source lines include a first axial source line extending along the first direction in one of the two core array regions of the memory stack layer.

3. The semiconductor device according to claim 2, wherein, The axial source pole line also includes a second axial source pole line extending along the first direction in another core array region of the two core array regions of the storage stack layer.

4. The semiconductor device according to claim 2, wherein, Along the second direction, the plurality of parallel tooth source pole lines extend laterally from one of the two core array regions of the storage stack layer through the stepped region of the storage stack layer to the other core array region of the two core array regions.

5. The semiconductor device according to claim 2, wherein, The source contact is located below the toothed source line of the source line grid and is in contact with the toothed source line of the source line grid.

6. The semiconductor device according to claim 1, further comprising: A first contact point passing through the semiconductor layer, the first contact point being located below and in contact with the source line grid; as well as A second contact extending along the stacking direction, the second contact being spaced apart from the storage stacking layer in a direction perpendicular to the stacking direction, the source contact being connected to the second contact via the source line grid and the first contact.

7. The semiconductor device according to claim 6, wherein, The source pole grid includes an axial source pole and multiple parallel toothed source poles. There are multiple first contacts and multiple second contacts. The multiple first contacts are located below the axial source pole and the outermost toothed source pole and are in contact with the axial source pole and the outermost toothed source pole.

8. The semiconductor device according to claim 7, wherein, The plurality of first contacts are also located below each tooth of the source line grid in the stepped region of the storage stack layer and in contact with each tooth of the source line grid in the stepped region.

9. The semiconductor device according to any one of claims 7-8, wherein, The back interconnect layer also includes a plurality of source select gate lines, wherein the plurality of source select gate lines extend parallel to each other along a second direction.

10. The semiconductor device according to claim 9, wherein, The source selection gate line is located between two adjacent source source lines in a first direction perpendicular to the second direction.

11. The semiconductor device according to claim 9, further comprising: A third contact passing through the semiconductor layer, wherein the third contact is located below and in contact with the plurality of source select gate lines; and A fourth contact extending along the stacking direction, the fourth contact being spaced apart from the storage stack layer in a direction perpendicular to the stacking direction, the source select gate line being connected to the fourth contact through the third contact.

12. The semiconductor device according to claim 1, wherein, The back interconnect layer also includes a power line grid, wherein the power line grid includes axial power lines and a plurality of parallel toothed power lines.

13. The semiconductor device according to claim 12, wherein, The source pole line grid includes an axial source pole line and a plurality of parallel tooth source pole lines, wherein the axial source pole line extends along a first direction, and the plurality of parallel tooth source pole lines extend along a second direction perpendicular to the first direction; the axial power line extends along the first direction, and the plurality of parallel tooth power lines extend along the second direction, such that the axial power line is parallel to the axial source pole line, and the plurality of parallel tooth power lines are parallel to the plurality of parallel tooth source pole lines.

14. The semiconductor device according to claim 12, wherein, The back interconnect layer also includes a plurality of source select gate lines, wherein the plurality of source select gate lines extend parallel to a second direction and are located between two adjacent toothed power lines in a first direction perpendicular to the second direction.

15. The semiconductor device according to claim 13, wherein, The source pole line and the power pole line are located parallel to each other in two different core array regions of the storage stack layer.

16. The semiconductor device of claim 12, further comprising: A fifth contact passing through the semiconductor layer, wherein the fifth contact is located below and in contact with the power line grid.

17. The semiconductor device according to claim 16, wherein, The fifth contact is located in at least one of the stepped region or peripheral region outside the memory array of the semiconductor device.

18. The semiconductor device of claim 1, further comprising peripheral circuitry formed on the substrate, wherein the storage stack layer is located between the peripheral circuitry and the first semiconductor layer.

19. The semiconductor device according to any one of claims 1-2, 4-8, 10-11, and 13-17, further comprising a gate line gap (GLS) located beneath the semiconductor layer, wherein, The gate line gap extends along the stacking direction through the interlaced conductive and dielectric layers of the memory stack.

20. The semiconductor device according to claim 19, wherein, The orthographic projection of the gate line gap on the substrate overlaps with the orthographic projection of the source contact on the substrate.

21. The semiconductor device according to claim 19, wherein, The orthographic projection of the source contact on the substrate does not overlap with the orthographic projection of the gate line gap on the substrate, but overlaps with the orthographic projection of the channel structure on the substrate.

22. The semiconductor device according to claim 21, wherein, The first source contact and the second source contact of the plurality of source contacts are respectively located on both sides of the gate line gap. The first source contact overlaps with the orthographic projection of the first channel structure of the plurality of channel structures on the substrate, and the second source contact overlaps with the orthographic projection of the second channel structure of the plurality of channel structures on the substrate.

23. The semiconductor device according to claim 1, wherein, The plurality of source contacts pass through the one or more dielectric layers and extend into the second semiconductor layer, but do not extend into the first semiconductor layer.

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