Driving substrate and preparation method thereof

Abstract

The embodiment of the present application discloses a kind of driving substrate and the preparation method of driving substrate, comprising: substrate, first oxide semiconductor layer, first insulating layer, second oxide semiconductor layer, second insulating layer, first gate, second gate and third insulating layer, first oxide semiconductor layer, first oxide semiconductor layer is set on substrate and corresponds to display area, first oxide semiconductor layer includes first active region and the first conductor part located in the two sides of first active region, first source electrode is connected to a first conductor part, first drain electrode is connected to another first conductor part, to form first thin film transistor;Second source electrode is connected to a second conductor part, second drain electrode is connected to another second conductor part, to form second thin film transistor, using the conductorization mode of ion implantation, the compression of thin film transistor device size in driving circuit area is realized, but also guarantee the reliability and current driving ability of thin film transistor device in display area simultaneously.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a driving substrate and a method for preparing the driving substrate. Background Technology

[0002] With the development of active-matrix organic light-emitting diode (OLED) panels, sub-millimeter OLED display panels, and micron-scale OLED display panels, the requirements for thin-film transistor (TFT) devices in the driving backplane of current-driven display technology are increasing. Oxide semiconductors (OSBs) are the best materials for realizing large- and medium-sized current-driven displays due to their ability to achieve large-area uniformity and lower cost. However, the current driving capability of OSB SSBs is related to the mobility of the semiconductor layer and the thickness of the gate insulating layer. To achieve narrow bezel displays, it is necessary to further improve the mobility of SSBs in the driving circuit area, thereby compressing the size of the SSBs and reducing the bezel width.

[0003] In the process of researching and practicing existing technologies, the inventors of this application discovered that existing plasma conductor technology, due to the short-channel effect caused by carrier diffusion, greatly limits the development of small-sized thin-film transistors in the driving circuit region. Summary of the Invention

[0004] This application provides a driving substrate and a method for fabricating the driving substrate. By employing ion implantation for conductor formation and combining it with a hybrid structure thin-film transistor device, the size of the thin-film transistor device in the driving circuit area is compressed, while ensuring the reliability and current driving capability of the thin-film transistor device in the in-plane display area.

[0005] This application provides a method for preparing a driving substrate, comprising the following steps:

[0006] A substrate is provided, the substrate including a display area and a driving circuit area disposed on at least one side of the display area;

[0007] A first oxide semiconductor layer is formed in the region of the substrate corresponding to the display area. The first oxide semiconductor layer includes a first active region and first doped regions located on both sides of the first active region.

[0008] A first insulating layer is formed on the substrate, the first insulating layer covering the first oxide semiconductor layer;

[0009] A second oxide semiconductor layer is formed in the region of the first insulating layer corresponding to the driving circuit region. The second oxide semiconductor layer includes a second active region and second doped regions located on both sides of the second active region.

[0010] A second insulating layer is formed on the first insulating layer, and the second insulating layer covers the second oxide semiconductor layer;

[0011] A first gate and a second gate are formed on the second insulating layer, wherein the first gate corresponds to the first active region and the second gate corresponds to the second active region;

[0012] Using the first gate and the second gate as masks, the first doped region and the second doped region are simultaneously subjected to conductor treatment to form a first conductor portion located on both sides of the first active region and a second conductor portion located on both sides of the second active region;

[0013] A third insulating layer is formed on the second insulating layer, the third insulating layer covering the first gate and the second gate;

[0014] A first source, a first drain, a second source, and a second drain are formed on the third insulating layer. The first source is connected to a first conductor portion, and the first drain is connected to another first conductor portion to form a first thin-film transistor. The second source is connected to a second conductor portion, and the second drain is connected to two other second conductor portions to form a second thin-film transistor.

[0015] Optionally, in some embodiments of this application, using the first gate and the second gate as masks, the first doped region and the second doped region are simultaneously subjected to conductor-enhancing treatment, including the following steps:

[0016] Using the first gate and the second gate as masks, an ion implantation process is employed to simultaneously perform ion doping on the first doped region and the second doped region at the same energy level.

[0017] Optionally, in some embodiments of this application, the density of N-type doped particles in the first conductor portion is less than the density of N-type doped particles in the second conductor portion.

[0018] Optionally, in some embodiments of this application, after forming a third insulating layer on the second insulating layer, and before forming a first source, a first drain, a second source, and a second drain on the third insulating layer, the fabrication method further includes the step of:

[0019] Simultaneously, the first insulating layer, the second insulating layer, and the third insulating layer are patterned to form a first via and a second via. The first via penetrates the first insulating layer, the second insulating layer, and the third insulating layer to expose the first conductor portion, and the second via penetrates the second insulating layer and the third insulating layer to expose the second conductor portion.

[0020] Optionally, in some embodiments of this application, before forming a first oxide semiconductor layer on the substrate in the region corresponding to the display area, the fabrication method further includes the following steps:

[0021] A light-shielding layer is formed on the substrate;

[0022] A buffer layer is formed on the substrate, and the buffer layer covers the light-shielding layer.

[0023] Optionally, in some embodiments of this application, the first insulating layer, the second insulating layer, and the third insulating layer are patterned simultaneously, and a third via is also formed; the third via penetrates the buffer layer, the first insulating layer, the second insulating layer, and the third insulating layer, and exposes the light-shielding layer; the epitaxial portion of the first source electrode is connected to the light-shielding layer through the third via.

[0024] Optionally, in some embodiments of this application, the preparation method further includes the following steps:

[0025] A protective layer is formed on the third insulating layer, the protective layer covering the first source, the first drain, the second source, and the second drain.

[0026] Optionally, in some embodiments of this application, the step of forming a second oxide semiconductor layer in the region of the first insulating layer corresponding to the driving circuit region includes:

[0027] At a set temperature, a second oxide semiconductor material layer is deposited on the first insulating layer to form a crystallized second oxide semiconductor material layer;

[0028] The patterned crystallized second oxide semiconductor layer is formed to create the second oxide semiconductor layer;

[0029] or

[0030] The second oxide semiconductor material layer is deposited on the first insulating layer at room temperature;

[0031] The second oxide semiconductor material layer is crystallized at a set temperature;

[0032] The patterned crystallized second oxide semiconductor layer forms the second oxide semiconductor layer.

[0033] Accordingly, embodiments of this application also provide a driving substrate, including:

[0034] A substrate, the substrate including a display area and a driving circuit area disposed on at least one side of the display area;

[0035] A first oxide semiconductor layer is disposed on the substrate and corresponds to the display area. The first oxide semiconductor layer includes a first active region and first conductor portions located on both sides of the first active region.

[0036] A first insulating layer is disposed on the substrate and covers the first oxide semiconductor layer;

[0037] A second oxide semiconductor layer is disposed on the first insulating layer and corresponds to the driving circuit region. The second oxide semiconductor layer includes a second active region and second conductor portions located on both sides of the second active region.

[0038] A second insulating layer is disposed on the first insulating layer and covers the second oxide semiconductor layer;

[0039] A first gate and a second gate are disposed on the same layer of the second insulating layer. The first gate overlaps with the first active region, and the second gate overlaps with the second active region.

[0040] A third insulating layer is disposed on the second insulating layer and covers the first gate and the second gate;

[0041] A first source, a first drain, a second source, and a second drain are disposed in the same layer and on the third insulating layer; the first source is connected to a first conductor portion, and the first drain is connected to another first conductor portion to form a first thin-film transistor; the second source is connected to a second conductor portion, and the second drain is connected to two other second conductor portions to form a second thin-film transistor.

[0042] Optionally, in some embodiments of this application, the first conductor portion includes a first oxide body and a first N-type dopant particle doped in the first oxide body, and the second conductor portion includes a second oxide body and a second N-type dopant particle doped in the second oxide body; the number of second N-type dopant particles per unit area is greater than the number of first N-type dopant particles.

[0043] Optionally, in some embodiments of this application, the first oxide semiconductor layer is an amorphous structure, and the second oxide semiconductor layer is a crystalline structure.

[0044] The embodiments of this application employ ion implantation for conductor formation, combined with hybrid structure thin-film transistor devices, to achieve compression of the size of thin-film transistor devices in the driving circuit area, while simultaneously ensuring the reliability and current driving capability of the thin-film transistor devices in the in-plane display area. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the driving substrate structure provided in Embodiment 1 of this application;

[0047] Figure 2 This is a schematic diagram of the driving substrate fabrication method provided in Embodiment 2 of this application;

[0048] Figure 3 This is a schematic diagram of step B1 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0049] Figure 4 This is a schematic diagram of step C11 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0050] Figure 5 This is a schematic diagram of step C12 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0051] Figure 6 This is a schematic diagram of step B2 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0052] Figure 7 This is a schematic diagram of step B3 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0053] Figure 8 This is a schematic diagram of step B4 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0054] Figure 9 This is a schematic diagram of step C411 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0055] Figure 10 This is a schematic diagram of step C412 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0056] Figure 11 This is a schematic diagram of step C421 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0057] Figure 12 This is a schematic diagram of step C422 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0058] Figure 13 This is a schematic diagram of step C423 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0059] Figure 14 This is a schematic diagram of step B5 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0060] Figure 15 This is a schematic diagram of step B6 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0061] Figure 16 This is a schematic diagram of step B7 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0062] Figure 17 This is a schematic diagram of step B8 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0063] Figure 18 This is a schematic diagram of step C81 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0064] Figure 19 This is a schematic diagram of step C82 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0065] Figure 20 This is a schematic diagram of step B9 in the driving substrate fabrication method provided in Embodiment 2 of this application;

[0066] Figure 21 This is a schematic diagram of step B10 in the driving substrate fabrication method provided in Embodiment 2 of this application.

[0067] Explanation of reference numerals in the attached drawings: driving substrate 100, substrate 10, display area AA, driving circuit area NA, first oxide semiconductor layer 11, first active area 11a, first doped area 11b, first insulating layer 12, second oxide semiconductor layer 13, second active area 13a, second doped area 13b, second insulating layer 21, first gate 14a, second gate 14b, first conductor portion 11c, second conductor portion 13c, third insulating layer 15, first source 16a, first drain 16b, second source 16c, second drain 16d, first thin film transistor T1, second thin film transistor T2, N-type doped particle 101, first via 17a, second via 17b, third via 17c, light-shielding layer 18, buffer layer 19, protective layer 20. Detailed Implementation

[0068] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0069] This application provides a driving substrate and a method for fabricating the driving substrate, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0070] Example 1

[0071] Please see Figure 1This embodiment provides a driving substrate 100, including: a substrate 10, a first oxide semiconductor layer 11, a first insulating layer 12, a second oxide semiconductor layer 13, a second insulating layer 21, a first gate 14a, a second gate 14b, and a third insulating layer 15. The substrate 10 includes a display area AA and a driving circuit area NA disposed on at least one side of the display area AA. The first oxide semiconductor layer 11 is disposed on the substrate 10 and corresponds to the display area AA, and includes a first active area 11a and first conductor portions 11c located on both sides of the first active area 11a. The first insulating layer 12 is disposed on the substrate 10 and covers the first oxide semiconductor layer 11. The second oxide semiconductor layer 13 is disposed on the first insulating layer 12 and corresponds to the driving circuit area NA, and includes a second active area 13a and second conductor portions 13c located on both sides of the second active area 13a. The second insulating layer 21 is disposed on the first insulating layer 12 and covers the second oxide semiconductor layer 13. A first gate 14a and a second gate 14b are disposed on the second insulating layer 21 in the same layer. The first gate 14a overlaps with the first active region 11a, and the second gate 14b overlaps with the second active region 13a. A third insulating layer 15 is disposed on the second insulating layer 21 and covers the first gate 14a and the second gate 14b. A first source 16a, a first drain 16b, a second source 16c, and a second drain 16d are disposed in the same layer and on the third insulating layer 15. The first source 16a is connected to a first conductor portion 11c, and the first drain 16b is connected to another first conductor portion 11c to form a first thin-film transistor T1. The second source 16c is connected to a second conductor portion 13c, and the second drain 16d is connected to two other second conductor portions 13c to form a second thin-film transistor T2.

[0072] It is understood that in this embodiment, the conductor-enhancing method of ion implantation is used in combination with hybrid structure thin-film transistor devices to achieve the compression of the size of the thin-film transistor device in the NA region of the driving circuit, while ensuring the reliability and current driving capability of the thin-film transistor device in the AA region of the in-plane display area.

[0073] In this embodiment, the first conductor portion 11c includes a first oxide body and a first N-type dopant particle 101 doped within the first oxide body, and the second conductor portion 13c includes a second oxide body and a second N-type dopant particle 101 doped within the second oxide body; the number of second N-type dopant particles 101 per unit area is greater than the number of first N-type dopant particles 101.

[0074] It is understood that a first conductor portion 11c with good conductivity is formed by doping a specific element or particle in the first doping region 11b; and a second conductor portion 13c with good conductivity is formed by doping a specific element or particle in the second doping region 13b, wherein the number of second N-type doped particles 101 per unit area is greater than the number of first N-type doped particles 101. On the one hand, the conductivity of the second conductor portion 13c can be better than that of the first conductor portion 11c, which can improve the working performance of the second oxide semiconductor layer 13; on the other hand, it can also save on mask and ion implantation processes.

[0075] Optionally, in some embodiments of this application, the first oxide semiconductor layer 11 is an amorphous structure, and the second oxide semiconductor layer 13 is a crystalline structure.

[0076] Understandably, after the second oxide semiconductor layer 13 undergoes crystallization treatment, its mobility is further improved, making it more suitable for products with higher mobility requirements for the drive circuit region NA.

[0077] In this application, the driving substrate 100 further includes a light-shielding layer 18 and a buffer layer 19. The light-shielding layer 18 is disposed on the substrate 10 and has a double-layer structure. The first layer is made of a material including molybdenum, titanium, tungsten, chromium, or nickel, or an alloy of the above metals, and has a thickness of 50 angstroms to 500 angstroms, for example, 50 angstroms, 225 angstroms, or 500 angstroms. The second layer is made of a material including copper, aluminum, or an alloy of the above metals, and has a thickness of 2000 angstroms to 5000 angstroms, for example, 2000 angstroms, 3500 angstroms, or 5000 angstroms. The buffer layer 19 covers the light-shielding layer 18. It is understood that the buffer layer 19 can be a single-layer structure or a multi-layer structure. The material of the buffer layer 19 includes silicon nitride, silicon oxide, or silicon oxynitride.

[0078] In this application, the driving substrate 100 further includes a protective layer 20. The protective layer 20 is disposed on the third insulating layer 15 and covers the first source 16a, the first drain 16b, the second source 16c, and the second drain 16d. It should be noted that the protective layer 20 can drive the substrate 100. The material of the buffer layer 19 includes silicon nitride, silicon oxide, or silicon oxynitride.

[0079] In this application, the driving substrate 100 further includes a third via 17c, which penetrates the buffer layer 19, the first insulating layer 12, the second insulating layer 21, and the third insulating layer 15, and exposes the light-shielding layer 18. The epitaxial portion of the first source electrode 16a is connected to the light-shielding layer 18 through the third via 17c. It is understood that connecting the epitaxial portion of the first source electrode 16a to the light-shielding layer 18 through the third via 17c can effectively improve the space utilization of the driving substrate 100. The light-shielding layer 18 can also connect traces, including power lines.

[0080] Example 2

[0081] This application provides a method for fabricating an array substrate as described in Embodiment 1.

[0082] Please see Figure 2 The method for preparing the driving substrate 100 includes the following steps:

[0083] Step B1, a substrate 10 is provided, the substrate 10 including a display area AA and a driving circuit area NA disposed on at least one side of the display area AA;

[0084] Step B2: A first oxide semiconductor layer 11 is formed in the region of the substrate 10 corresponding to the display region AA. The first oxide semiconductor layer 11 includes a first active region 11a and a first doped region 11b located on both sides of the first active region 11a.

[0085] Step B3: A first insulating layer 12 is formed on the substrate 10, and the first insulating layer 12 covers the first oxide semiconductor layer 11.

[0086] Step B4 forms a second oxide semiconductor layer 13 in the region of the first insulating layer 12 corresponding to the driving circuit region NA. The second oxide semiconductor layer 13 includes a second active region 13a and second doped regions 13b located on both sides of the second active region 13a.

[0087] Step B5: A second insulating layer 21 is formed on the first insulating layer 12, and the second insulating layer 21 covers the second oxide semiconductor layer 13.

[0088] Step B6: A first gate 14a and a second gate 14b are formed on the second insulating layer 21. The first gate 14a corresponds to the first active region 11a, and the second gate 14b corresponds to the second active region 13a.

[0089] Step B7: Using the first gate 14a and the second gate 14b as masks, the first doped region 11b and the second doped region 13b are simultaneously conductiveized to form the first conductive portion 11c located on both sides of the first active region 11a and the second conductive portion 13c located on both sides of the second active region 13a.

[0090] Step B8: A third insulating layer 15 is formed on the second insulating layer 21, and the third insulating layer 15 covers the first gate 14a and the second gate 14b.

[0091] In step B9, a first source 16a, a first drain 16b, a second source 16c, and a second drain 16d are formed on the third insulating layer 15. The first source 16a is connected to a first conductor portion 11c, and the first drain 16b is connected to another first conductor portion 11c to form a first thin-film transistor T1. The second source 16c is connected to a second conductor portion 13c, and the second drain 16d is connected to two other second conductor portions 13c to form a second thin-film transistor T2.

[0092] It is understood that in this embodiment, the conductor-enhancing method of ion implantation is used in combination with hybrid structure thin-film transistor devices to achieve the compression of the size of the thin-film transistor device in the NA region of the driving circuit, while ensuring the reliability and current driving capability of the thin-film transistor device in the AA region of the in-plane display area.

[0093] The fabrication method of the driving substrate 100 will be described in detail below:

[0094] Please see Figure 3 In step B1, a substrate 10 is provided, the substrate 10 including a display area AA and a driving circuit area NA disposed on at least one side of the display area AA.

[0095] In this embodiment, after step B1 and before step B2, the method for fabricating the driving substrate 100 further includes the following steps:

[0096] Please see Figure 4 In step C11, a light-shielding layer 18 is formed on the substrate 10. The light-shielding layer 18 has a double-layer structure. The first layer is made of a material including molybdenum, titanium, tungsten, chromium, or nickel, or an alloy of the above metals, and has a thickness of 50 angstroms to 500 angstroms, for example, 50 angstroms, 225 angstroms, or 500 angstroms. The second layer is made of a material including copper, aluminum, or an alloy of the above metals, and has a thickness of 2000 angstroms to 5000 angstroms, for example, 2000 angstroms, 3500 angstroms, or 5000 angstroms. Then, proceed to step C12.

[0097] Please see Figure 5 In step C12, a buffer layer 19 is formed on the substrate 10, and the buffer layer 19 covers the light-shielding layer 18. It is understood that the buffer layer 19 can be a single-layer structure or a multi-layer structure. The material of the buffer layer 19 includes silicon nitride, silicon oxide, or silicon oxynitride. Then proceed to step B2.

[0098] Please see Figure 6In step B2, a first oxide semiconductor layer 11 is formed in the region of the substrate 10 corresponding to the display region AA. The first oxide semiconductor layer 11 includes a first active region 11a and first doped regions 11b located on both sides of the first active region 11a. It is understood that the material of the first oxide semiconductor layer 11 includes a thickness of 100 angstroms to 1000 angstroms, for example, 100 angstroms, 500 angstroms, or 1000 angstroms. Then, proceed to step B3.

[0099] Please see Figure 7 In step B3, a first insulating layer 12 is formed on the substrate 10, the first insulating layer 12 covering the first oxide semiconductor layer 11. It is understood that the material of the first insulating layer 12 includes at least one selected from silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, magnesium oxide, titanium oxide, and organic photoresist, and its thickness is 300 angstroms to 2000 angstroms, for example, 300 angstroms, 1150 angstroms, or 2000 angstroms. Then, proceed to step B4.

[0100] Please see Figure 8 In step B4, a second oxide semiconductor layer 13 is formed in the region of the first insulating layer 12 corresponding to the driving circuit region NA. The second oxide semiconductor layer 13 includes a second active region 13a and second doped regions 13b located on both sides of the second active region 13a. It should be noted that the mobility of the second oxide semiconductor layer 13 is greater than that of the first oxide semiconductor layer 11. The material of the second oxide semiconductor layer 13 includes indium gallium zinc tin oxide or indium gallium zinc oxide, and its thickness is 100 angstroms to 1000 angstroms, for example, 100 angstroms, 550 angstroms, or 1000 angstroms.

[0101] It should be noted that, in some embodiments, the step of forming the second oxide semiconductor layer 13 in the region of the first insulating layer 12 corresponding to the driving circuit region NA further includes:

[0102] Please see Figure 9 In step C411, a second oxide semiconductor material layer is deposited on the first insulating layer 12 at a set temperature to form a crystallized second oxide semiconductor material layer. It should be noted that the set temperature ranges from 100 degrees Celsius to 350 degrees Celsius, for example, 100 degrees Celsius, 225 degrees Celsius, or 350 degrees Celsius. Simultaneously, to improve crystallization, the oxygen content within the equipment can be increased, ranging from 5% to 80%, for example, 5%, 42%, or 80%. Then, the process proceeds to step BC412.

[0103] Please see Figure 10 In step C412, the patterned crystallized second oxide semiconductor layer 13 is formed to create the second oxide semiconductor layer.

[0104] or

[0105] Please see Figure 11 In step C421, a second oxide semiconductor material layer is deposited on the first insulating layer 12 at room temperature. Then proceed to step C422.

[0106] Please see Figure 12 In step C422, the second oxide semiconductor material layer is crystallized at a set temperature. It should be noted that the set temperature ranges from 150 degrees Celsius to 400 degrees Celsius, for example, 150 degrees Celsius, 275 degrees Celsius, or 400 degrees Celsius. This step can be performed under nitrogen, oxygen, or a vacuum. Then, proceed to step C423.

[0107] Please see Figure 13 In step C423, the patterned crystallized second oxide semiconductor layer 13 is formed to create the second oxide semiconductor layer.

[0108] It should be noted that the external shape of the crystallization and patterning of the second oxide semiconductor layer 13 does not change significantly in steps B4, C411, C412, C421, C422 and C423.

[0109] Understandably, after the second oxide semiconductor layer 13 undergoes crystallization treatment, its mobility is further improved, making it more suitable for products with higher mobility requirements for the drive circuit region NA.

[0110] Then proceed to step B5.

[0111] Please see Figure 14 In step B5, a second insulating layer 21 is formed on the first insulating layer 12, and the second insulating layer 21 covers the second oxide semiconductor layer 13. It is understood that the material of the second insulating layer 21 includes at least one selected from silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, magnesium oxide, titanium oxide, and organic photoresist, and its thickness is 500 angstroms to 2000 angstroms, for example, 500 angstroms, 1250 angstroms, or 2000 angstroms. Then, proceed to step B6.

[0112] Please see Figure 15In step B6, a first gate 14a and a second gate 14b are formed on the second insulating layer 21. The first gate 14a corresponds to the first active region 11a, and the second gate 14b corresponds to the second active region 13a. It is understood that the first gate 14a and the second gate 14b are disposed on the same layer, meaning that the first gate 14a and the second gate 14b can be patterned from the same metal layer. Both the first gate 14a and the second gate 14b can adopt a double-layer structure. The first layer of the first gate 14a is made of a material including molybdenum, titanium, tungsten, chromium, or nickel, or an alloy of the above metals, with a thickness of 50 angstroms to 500 angstroms, for example, 50 angstroms, 225 angstroms, or 500 angstroms. The second layer is made of a material including copper, aluminum, or an alloy of the above metals, with a thickness of 2000 angstroms to 5000 angstroms, for example, 2000 angstroms, 3500 angstroms, or 5000 angstroms. The first layer of the second gate 14b is made of a material selected from molybdenum, titanium, tungsten, chromium, or nickel, or an alloy of the aforementioned metals, with a thickness of 50 angstroms to 500 angstroms, for example, 50 angstroms, 225 angstroms, or 500 angstroms; the second layer is made of a material selected from copper, aluminum, or an alloy of the aforementioned metals, with a thickness of 2000 angstroms to 5000 angstroms, for example, 2000 angstroms, 3500 angstroms, or 5000 angstroms. The first and second layers are stacked, with the first layer disposed on the second insulating layer. Then proceed to step B7.

[0113] Please see Figure 16 In step B7, using the first gate 14a and the second gate 14b as masks, the first doped region 11b and the second doped region 13b are simultaneously subjected to a conductor-enhancing process to form a first conductor portion 11c located on both sides of the first active region 11a and a second conductor portion 13c located on both sides of the second active region 13a. It is understood that the conductor-enhancing process of the first doped region 11b and the second doped region 13b includes ion implantation. A first conductor portion 11c with good conductivity is formed by doping the first doped region 11b with specific elements or particles; a second conductor portion 13c with good conductivity is formed by doping the second doped region 13b with specific elements or particles. It should be noted that the formation of the first conductor portion 11c and the second conductor portion 13c is performed simultaneously. The doped element or particle is an N-type dopant particle 101, including but not limited to hydrogen, helium, boron, aluminum, nitrogen, fluorine, phosphorus, argon, or sulfur.

[0114] In this embodiment, using the first gate 14a and the second gate 14b as masks, an ion implantation process is employed to simultaneously perform ion doping on the first doped region 11b and the second doped region 13b at the same energy. It is understood that, at the same energy, the N-type doped particles 101 can reach the same distance on the driving substrate 100. In this embodiment, at the same energy, the N-type doped particles 101 can at least simultaneously penetrate the first insulating layer 12 and the second insulating layer 21, reaching the first oxide semiconductor layer 11 and the second oxide semiconductor layer 13, respectively. Since the energy required to penetrate the first semi-oxide conductor layer and the second oxide semiconductor layer is much higher than the initial energy of the N-type doped particles 101, the possibility of breakdown in the first semi-oxide conductor layer and the second oxide semiconductor layer is not considered here. It should be noted that, due to losses incurred by the N-type doped particles 101 during their journey to the first doped region 11b and the second doped region 13b, the N-type doped particles 101 need to pass through the first insulating layer 12 and the second insulating layer 21 to reach the first doped region 11b, while they only need to pass through the second insulating layer 21 to reach the second doped region 13b. Therefore, in the final result, the first conductor portion 11c formed in the first doped region 11b and the second conductor portion 13c formed in the second doped region 13b have a lower density of N-type doped particles 101 than that in the second conductor portion 13c. It can be understood that the first and second N-type doped particles are the same type of N-type doped particle 101.

[0115] It is understandable that by designing to simultaneously perform ion doping treatment on the first doped region 11b and the second doped region 13b at the same energy, on the one hand, the conductivity of the second conductor portion 13c can be made better than that of the first conductor portion 11c, which can improve the working performance of the second oxide semiconductor layer 13, and on the other hand, it can also save on mask and ion implantation processes.

[0116] Then proceed to step B8.

[0117] Please see Figure 17 In step B8, a third insulating layer 15 is formed on the second insulating layer 21, the third insulating layer 15 covering the first gate 14a and the second gate 14b. It is understood that the material of the third insulating layer 15 includes at least one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, magnesium oxide, titanium oxide, and organic photoresist, and its thickness is from 500 angstroms to 2000 angstroms, for example 500 angstroms, 1250 angstroms, or 2000 angstroms.

[0118] It should be noted that after the formation of the third insulating layer 15 on the second insulating layer 21 in step B8, and before the formation of the first source 16a, the first drain 16b, the second source 16c, and the second drain 16d on the third insulating layer 15 in step B9, the method for fabricating the driving substrate 100 further includes the following steps:

[0119] Please see Figure 18 In step C81, the first insulating layer 12, the second insulating layer 21, and the third insulating layer 15 are simultaneously patterned to form a first via 17a and a second via 17b. The first via 17a penetrates the first insulating layer 12, the second insulating layer 21, and the third insulating layer 15, exposing the first conductor portion 11c. The second via 17b penetrates the second insulating layer 21 and the third insulating layer 15, exposing the second conductor portion 13c. In some embodiments, the exposed area of ​​the first conductor portion 11c is smaller than the exposed area of ​​the second conductor portion 13c. It is understood that having a smaller exposed area of ​​the first conductor portion 11c than the exposed area of ​​the second conductor portion 13c can increase the contact area between the second source 16c and the second drain 16d and the second conductor portion 13c, thereby improving the conductivity of the second thin-film transistor T2 and enhancing its operating performance.

[0120] In this embodiment, step C81 further includes:

[0121] Please see Figure 19 In step C82, the first insulating layer 12, the second insulating layer 21, and the third insulating layer 15 are patterned simultaneously, and a third via 17c is also formed. The third via 17c penetrates the buffer layer 19, the first insulating layer 12, the second insulating layer 21, and the third insulating layer 15, and exposes the light-shielding layer 18. The epitaxial portion of the first source electrode 16a is connected to the light-shielding layer 18 through the third via 17c. It can be understood that connecting the epitaxial portion of the first source electrode 16a to the light-shielding layer 18 through the third via 17c can effectively improve the space utilization of the driving substrate 100. The light-shielding layer 18 can also connect traces, including power lines.

[0122] Then proceed to step B9.

[0123] Please see Figure 20In step B9, a first source 16a, a first drain 16b, a second source 16c, and a second drain 16d are formed on the third insulating layer 15. The first source 16a is connected to a first conductor portion 11c, and the first drain 16b is connected to another first conductor portion 11c to form a first thin-film transistor T1. The second source 16c is connected to a second conductor portion 13c, and the second drain 16d is connected to two other second conductor portions 13c to form a second thin-film transistor T2. The first source 16a, the first drain 16b, the second source 16c, and the second drain 16d are formed by patterning the same metal layer. The metal layer comprises a two-layer structure. The first layer is disposed on the third insulating layer 15 and is made of one of molybdenum, titanium, tungsten, chromium, or nickel, or an alloy of the aforementioned metals. It may also be a conductive oxide material, including indium tin oxide, indium zinc oxide, or aluminum zinc oxide, and has a thickness of 2000 angstroms to 5000 angstroms, for example, 2000 angstroms, 3500 angstroms, or 5000 angstroms. The second layer is disposed on the first layer and is made of one of copper or aluminum, or an alloy of the aforementioned metals, and has a thickness of 2000 angstroms to 10000 angstroms, for example, 2000 angstroms, 6000 angstroms, or 10000 angstroms.

[0124] In some embodiments of this application, the method for fabricating the driving substrate 100 further includes the following steps:

[0125] Please see Figure 1 and Figure 21 In step B10, a protective layer 20 is formed on the third insulating layer 15, covering the first source 16a, the first drain 16b, the second source 16c, and the second drain 16d. It should be noted that the protective layer 20 can drive the substrate 100. The material of the buffer layer 19 includes silicon nitride, silicon oxide, or silicon oxynitride.

[0126] Thus, the drive substrate 100 is fabricated.

[0127] The foregoing has provided a detailed description of a driving substrate and a method for preparing the driving substrate according to the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for fabricating a driving substrate, characterized in that, Includes the following steps: A substrate is provided, the substrate including a display area and a driving circuit area disposed on at least one side of the display area; A first oxide semiconductor layer is formed in the region of the substrate corresponding to the display area. The first oxide semiconductor layer includes a first active region and first doped regions located on both sides of the first active region. A first insulating layer is formed on the substrate, the first insulating layer covering the first oxide semiconductor layer; A second oxide semiconductor layer is formed in the region of the first insulating layer corresponding to the driving circuit region. The second oxide semiconductor layer includes a second active region and second doped regions located on both sides of the second active region. A second insulating layer is formed on the first insulating layer, and the second insulating layer covers the second oxide semiconductor layer; A first gate and a second gate are formed on the second insulating layer, wherein the first gate corresponds to the first active region and the second gate corresponds to the second active region; Using the first gate and the second gate as masks, an ion implantation process is employed to simultaneously conduct the first doped region and the second doped region at the same energy level. N-type doped particles can penetrate at least the first insulating layer and the second insulating layer simultaneously to form a first conductor portion located on both sides of the first active region and a second conductor portion located on both sides of the second active region. The density of N-type doped particles in the first conductor portion is less than the density of N-type doped particles in the second conductor portion, and the conductivity of the second conductor portion is better than that of the first conductor portion. A third insulating layer is formed on the second insulating layer, the third insulating layer covering the first gate and the second gate; Simultaneously, the first insulating layer, the second insulating layer, and the third insulating layer are patterned to form a first via and a second via. The first via penetrates the first insulating layer, the second insulating layer, and the third insulating layer to expose the first conductor portion, and the second via penetrates the second insulating layer and the third insulating layer to expose the second conductor portion. A first source, a first drain, a second source, and a second drain are formed on the third insulating layer. The first source is connected to a first conductor portion through a first via, and the first drain is connected to another first conductor portion through another first via to form a first thin-film transistor. The second source is connected to a second conductor portion through a second via, and the second drain is connected to two other second conductor portions through another second via to form a second thin-film transistor.

2. The method for preparing the driving substrate according to claim 1, characterized in that, Before forming a first oxide semiconductor layer in the region of the substrate corresponding to the display area, the fabrication method further includes the following steps: A light-shielding layer is formed on the substrate; A buffer layer is formed on the substrate, and the buffer layer covers the light-shielding layer.

3. The method for preparing the driving substrate according to claim 2, characterized in that, Simultaneously, the first insulating layer, the second insulating layer, and the third insulating layer are patterned, and a third via is also formed; the third via penetrates the buffer layer, the first insulating layer, the second insulating layer, and the third insulating layer, and exposes the light-shielding layer; the epitaxial portion of the first source electrode is connected to the light-shielding layer through the third via.

4. The method for preparing the driving substrate according to claim 1, characterized in that, The preparation method further includes the following steps: A protective layer is formed on the third insulating layer, the protective layer covering the first source, the first drain, the second source, and the second drain.

5. The method for preparing the driving substrate according to claim 1, characterized in that, The step of forming a second oxide semiconductor layer in the region of the first insulating layer corresponding to the driving circuit region includes: A second oxide semiconductor material layer is deposited on the first insulating layer at a set temperature to form a crystallized second oxide semiconductor material layer; A patterned crystallized second oxide semiconductor material layer is formed to create the second oxide semiconductor layer; or The second oxide semiconductor material layer is deposited on the first insulating layer at room temperature; The second oxide semiconductor material layer is crystallized at a set temperature; A patterned crystallized second oxide semiconductor material layer is formed to create the second oxide semiconductor layer.

6. A driving substrate, characterized in that, include: A substrate, the substrate including a display area and a driving circuit area disposed on at least one side of the display area; A first oxide semiconductor layer is disposed on the substrate and corresponds to the display area. The first oxide semiconductor layer includes a first active region and first conductor portions located on both sides of the first active region. A first insulating layer is disposed on the substrate and covers the first oxide semiconductor layer; The second oxide semiconductor layer is disposed on the first insulating layer and corresponds to the driving circuit region. The second oxide semiconductor layer includes a second active region and a second conductor portion located on both sides of the second active region. The second conductor portion and the first conductor portion are formed simultaneously by ion implantation. The N-type dopant density of the first conductor portion is less than that of the second conductor portion. The conductivity of the second conductor portion is better than that of the first conductor portion. A second insulating layer is disposed on the first insulating layer and covers the second oxide semiconductor layer; A first gate and a second gate are disposed on the same layer of the second insulating layer. The first gate overlaps with the first active region, and the second gate overlaps with the second active region. A third insulating layer is disposed on the second insulating layer and covers the first gate and the second gate. The first insulating layer, the second insulating layer and the third insulating layer are simultaneously patterned to form a first via and a second via. The first via penetrates the first insulating layer, the second insulating layer and the third insulating layer to expose the first conductor portion, and the second via penetrates the second insulating layer and the third insulating layer to expose the second conductor portion. A first source, a first drain, a second source, and a second drain are disposed in the same layer and on the third insulating layer; the first source is connected to a first conductor portion through a first via, and the first drain is connected to another first conductor portion through another first via to form a first thin-film transistor. The second source is connected to a second conductor portion through a second via, and the second drain is connected to two other second conductor portions through another second via to form a second thin-film transistor.

7. The driving substrate according to claim 6, characterized in that, The first conductor portion includes a first oxide body and a first N-type doped particle doped within the first oxide body, and the second conductor portion includes a second oxide body and a second N-type doped particle doped within the second oxide body; the number of second N-type doped particles per unit area is greater than the number of first N-type doped particles.

8. The driving substrate according to claim 6, characterized in that, The first oxide semiconductor layer has an amorphous structure, while the second oxide semiconductor layer has a crystalline structure.

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