Array substrate and manufacturing method thereof

Abstract

This invention discloses an array substrate and its fabrication method. The array substrate includes a substrate layer and a thin-film transistor structure layer disposed on the substrate layer. The substrate layer includes a first substrate layer; a first barrier layer disposed on the first substrate layer; a metal layer disposed on the first barrier layer, the metal layer including a plurality of spaced-apart light-shielding blocks; and a second substrate layer disposed on the metal layer and covering the plurality of spaced-apart light-shielding blocks. By providing a metal layer on the first barrier layer and patterning it as light-shielding blocks, this application achieves a light-shielding effect. Simultaneously, the spaced-apart light-shielding blocks increase surface roughness, enhancing the adhesion of the first barrier layer to the second substrate layer, making the second substrate layer less prone to detachment or cracking. The multiple bumps formed by the downward protrusion of the second substrate layer can disperse bending stress, improving the flexibility of the array substrate.

Description

Technical Field

[0001] This invention relates to the field of display panels, and in particular to an array substrate and its fabrication method. Background Technology

[0002] Flexible folding technology has attracted much attention in recent years, but it also places higher demands on the flexibility of flexible substrates.

[0003] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an array substrate included in a flexible display panel in the prior art. The array substrate includes a substrate layer 10 and a thin-film transistor structure layer 20. The substrate layer 10 includes a substrate 110, a first isolation layer 120, a first substrate layer 130, a first barrier layer 140, a second isolation layer 122, a second substrate layer 160, and a second barrier layer 170. The thin-film transistor structure layer 20 includes a buffer layer 210, a light-shielding layer 180, an active layer 220, a gate insulating layer 230, a gate layer 240, an interlayer dielectric layer 250, a contact hole 251, a buffer hole 190, a source-drain layer 260, a passivation layer 270, a wiring layer 280, a planarization layer 290, a pixel electrode layer 310, and a pixel definition layer 320. The source-drain layer 260 is connected to the light-shielding layer 180 through the buffer hole 190.

[0004] Faced with increasingly complex product design and performance requirements, conventional array substrate designs cannot effectively disperse bending stress and are difficult to meet the requirements of flexible substrates. In addition, the complex manufacturing process of array substrates is the reason for their high price. Finding ways to save on manufacturing costs is particularly important in the highly competitive panel industry. Summary of the Invention

[0005] The embodiments of the present invention provide an array substrate and a method for preparing the same, in order to solve the problems in the prior art where the array substrate cannot effectively disperse bending stress and the array substrate process is complex, resulting in high cost.

[0006] To address the aforementioned technical problems, embodiments of the present invention disclose the following technical solutions:

[0007] On one hand, an array substrate is provided, including a substrate layer and a thin-film transistor structure layer disposed on the substrate layer; the substrate layer includes a first substrate layer; a first barrier layer disposed on the first substrate layer; a metal layer disposed on the first barrier layer, the metal layer including a plurality of spaced-apart light-shielding blocks; and a second substrate layer disposed on the metal layer and covering the plurality of spaced-apart light-shielding blocks.

[0008] In addition to one or more of the features disclosed above, or as an alternative, the cross-sectional shape of the light-shielding block is square, trapezoidal, or conical.

[0009] In addition to one or more of the features disclosed above, or as an alternative, the material of the light-shielding block is a titanium alloy, a titanium-molybdenum alloy, or an iron alloy, and the thickness of the light-shielding block is less than 3000 angstroms.

[0010] In addition to one or more of the features disclosed above, or alternatively, the second substrate layer forms a plurality of bumps facing the first substrate layer in the portion between the light-shielding blocks.

[0011] In addition to one or more of the features disclosed above, or as an alternative, the light-shielding block is disposed corresponding to a thin-film transistor device, the projection of the thin-film transistor device on the first substrate falling into the projection of the light-shielding block on the first substrate.

[0012] In addition to one or more of the features disclosed above, or alternatively, the substrate layer further includes: a substrate; a first isolation layer disposed on the substrate; wherein the first substrate layer is disposed on the first isolation layer.

[0013] In addition to one or more of the features disclosed above, or as an alternative, the first barrier layer is an inorganic insulating layer, wherein the plurality of spaced-apart light-shielding blocks are disposed on the inorganic insulating layer, and the plurality of protrusions are in contact with the inorganic insulating layer.

[0014] In addition to one or more of the features disclosed above, or alternatively, the substrate layer further includes a second barrier layer disposed on the second substrate layer; wherein the second barrier layer includes: a first silicon oxide layer disposed on the second substrate layer; a silicon nitride layer disposed on the first silicon oxide layer; a second silicon oxide layer disposed on the silicon nitride layer; wherein the thin film transistor structure layer is disposed on the second silicon oxide layer.

[0015] In addition to one or more of the features disclosed above, or as an alternative, the thin-film transistor structure layer includes: an active layer disposed on the substrate layer; a gate insulating layer disposed on the active layer; a gate layer disposed on the gate insulating layer; an interlayer dielectric layer disposed on the gate layer; a contact hole extending from the side of the interlayer dielectric layer away from the substrate layer to the surface of the active layer away from the substrate layer; and a source-drain layer disposed on the interlayer dielectric layer, the source-drain layer being connected to the active layer through the contact hole to form the thin-film transistor device.

[0016] On the other hand, a fabrication method is provided for fabricating the array substrate of the present invention. The fabrication method includes the following steps: fabricating a substrate layer; fabricating a thin-film transistor structure layer on the substrate layer; the step of fabricating the substrate layer specifically includes the following steps: fabricating a first substrate layer; fabricating a first barrier layer on the first substrate layer; fabricating a metal layer on the first barrier layer, and patterning the metal layer to form a plurality of spaced light-shielding blocks; fabricating a second substrate layer on the metal layer, wherein the second substrate layer covers the plurality of spaced light-shielding blocks.

[0017] One of the above technical solutions has the following advantages or beneficial effects: By setting a metal layer on the first barrier layer and patterning it into light-shielding blocks, the present application can achieve a light-shielding effect; at the same time, the spaced light-shielding blocks can improve the surface roughness, increase the adhesion of the first barrier layer to the second substrate layer, and make the second substrate layer less likely to fall off or crack; the multiple bumps formed by the downward protrusion of the second substrate layer can disperse bending stress and improve the flexibility of the array substrate.

[0018] Furthermore, the light-shielding block can replace the light-shielding layer in the prior art, thus eliminating the step of preparing the light-shielding layer, saving the cost of the light-shielding layer, and consequently eliminating the need to prepare the buffer hole, saving the photomask for preparing the buffer hole, further reducing costs. Attached Figure Description

[0019] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0020] Figure 1 This is a schematic diagram of the structure of an array substrate provided in the prior art;

[0021] Figure 2 This is a schematic diagram of the structure of the array substrate provided in an embodiment of the present invention;

[0022] Figure 3 A flowchart illustrating the method for fabricating an array substrate according to an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of step 14 of the array substrate fabrication method provided in an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of step 15 of the array substrate fabrication method provided in an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of step 16 of the array substrate fabrication method provided in an embodiment of the present invention;

[0026] Figure 7A schematic diagram of step 17 of the array substrate fabrication method provided in an embodiment of the present invention;

[0027] Figure 8 This is a schematic diagram of step 21 of the method for fabricating an array substrate according to an embodiment of the present invention;

[0028] Figure 9 This is a schematic diagram of step 22 of the method for fabricating an array substrate according to an embodiment of the present invention;

[0029] Figure 10 This is a schematic diagram of step 23 of the method for fabricating an array substrate according to an embodiment of the present invention.

[0030] Figure 11 This is a schematic diagram of step 24 of the array substrate fabrication method provided in an embodiment of the present invention.

[0031] Figure label:

[0032] Array substrate-100; Substrate layer-10;

[0033] Thin-film transistor structure layer-20; Substrate-110;

[0034] First isolation layer - 120; First substrate layer - 130;

[0035] First barrier layer - 140; Metal layer - 150;

[0036] Light-shielding block - 151; Second substrate layer - 160;

[0037] Second barrier layer - 170; First silicon oxide layer - 171;

[0038] Silicon nitride layer - 172; Second silicon oxide layer - 173;

[0039] Buffer layer - 210; Active layer - 220;

[0040] Gate insulating layer -230; Gate layer -240;

[0041] Interlayer dielectric layer - 250; Source / drain layer - 260;

[0042] Contact hole-251; Wiring layer-270;

[0043] Passivation layer - 280; Planarization layer - 290;

[0044] Pixel electrode layer - 310; Pixel definition layer - 320;

[0045] Light-shielding layer - 180; Buffer hole - 190;

[0046] Second isolation layer -122. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. In the description of the present invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0048] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of an array substrate 100 provided in this embodiment. The array substrate 100 includes a substrate layer 10 and a thin film transistor structure layer 20.

[0049] The substrate layer 10 includes a substrate 110, a first isolation layer 120, a first substrate layer 130, a first barrier layer 140, a metal layer 150, a second substrate layer 160, and a second barrier layer 170.

[0050] The substrate 110 is a base component used to support the array structure. The array substrate 100 is fabricated using the substrate 110 as a support, and the substrate film layer is subsequently peeled off from the substrate 110. In this embodiment, the substrate 110 can be made of glass.

[0051] The first isolation layer 120 is disposed on the substrate 110, and the first isolation layer 120 can be made of α-Si. On the one hand, the first isolation layer 120 can improve the surface roughness, which is beneficial to the adhesion of the first substrate layer 130. On the other hand, laser lift-off technology can be used to vaporize the α-Si, which facilitates the separation of the first substrate layer 130 from the substrate 110.

[0052] The first substrate layer 130 is disposed on the first isolation layer 120, and the first substrate layer 130 may be made of an organic material. The organic material may be any one or a combination of polyimide, polyethylene, polypropylene, polystyrene, polyethylene terephthalate and polyethylene naphthalate.

[0053] A first barrier layer 140 is disposed on a first substrate layer 130. The first barrier layer 140 may be made of an inorganic material, such as one or more combinations of aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium oxide, zirconium oxide, and zinc oxide. The thickness of the first barrier layer 140 is between 5 micrometers and 10 micrometers. The first barrier layer 140 can be used to block water and oxygen, preventing the thin-film transistor devices in the array substrate 100 from failing.

[0054] A metal layer 150 is disposed on the first barrier layer 140, and the metal layer 150 includes a plurality of spaced-apart light-shielding blocks 151. The first barrier layer 140 is an inorganic insulating layer, and the plurality of spaced-apart light-shielding blocks 151 are disposed on the inorganic insulating layer. By disposing of the metal layer 150 on the first barrier layer 140 and patterning it into light-shielding blocks 151, a light-shielding effect can be achieved; furthermore, when a bending force is applied, the stress is mainly applied between the light-shielding blocks 151, which can effectively reduce the damage to the thin-film transistor devices and light-emitting devices on the array substrate caused by bending, thereby improving product performance.

[0055] The cross-sectional shape of the light-shielding block 151 can be square, trapezoidal, or conical. Different shapes can be adjusted according to the manufacturing process precision. The spacing between the light-shielding blocks 151 can also be different, and this embodiment does not limit this. The material of the light-shielding block 151 is titanium alloy, titanium-molybdenum alloy, or iron alloy. The thickness of the light-shielding block 151 is less than 3000 angstroms.

[0056] The second substrate layer 160 is disposed on the metal layer 150 and covers the light-shielding blocks 151. A plurality of bumps facing the first substrate layer 130 are formed in the portion of the second substrate layer 160 between the light-shielding blocks 151, and these bumps contact the inorganic insulating layer. The spaced-apart light-shielding blocks 151 improve surface roughness, increasing the adhesion of the first barrier layer 140 to the second substrate layer 160, making the second substrate layer 160 less prone to detachment or cracking. The multiple bumps formed by the downward protrusion of the second substrate layer 160 can disperse bending stress and improve the flexibility of the array substrate.

[0057] The second substrate layer 160 can be made of organic materials. The organic materials can be any one or a combination of polyimide, polyethylene, polypropylene, polystyrene, polyethylene terephthalate, and polyethylene naphthalate. The reason for fabricating the first substrate layer 130 and the second substrate layer 160 is that using two organic layers as substrates can improve yield. Furthermore, a single organic substrate tends to contain more particles, dust, and other impurities; fabricating two organic substrates can reduce the problem of these impurities.

[0058] In other embodiments, an inorganic insulating layer (not shown) may be provided between the first substrate layer 130 and the second substrate layer 160, wherein a plurality of light-shielding blocks 151 are disposed on the inorganic insulating layer at intervals, and a plurality of protrusions are in contact with the inorganic insulating layer.

[0059] The second barrier layer 170 is disposed on the second substrate layer 160. The second barrier layer 170 includes a first silicon oxide layer 171, a silicon nitride layer 172, and a second silicon oxide layer 173. The first silicon oxide layer 171 is disposed on the second substrate layer 160; the silicon nitride layer 172 is disposed on the first silicon oxide layer 171; and the second silicon oxide layer 173 is disposed on the silicon nitride layer 172.

[0060] The thin-film transistor structure layer 20 includes a buffer layer 210, an active layer 220, a gate insulating layer 230, a gate layer 240, an interlayer dielectric layer 250, a source-drain layer 260, a wiring layer 280, a passivation layer 270, a planarization layer 290, a contact hole 251, a pixel electrode layer 310, and a pixel definition layer 320.

[0061] A buffer layer 210 is disposed on the substrate layer 10. The buffer layer 210 serves to block water and oxygen on the light-shielding layer 180. In this embodiment, the second barrier layer 170 is already made of a water and oxygen barrier material, so the buffer layer 210 is not required, thereby saving costs and simplifying the manufacturing process.

[0062] An active layer 220 is disposed on a buffer layer 210; a gate insulating layer 230 is disposed on the active layer 220, and the gate insulating layer 230 includes an inorganic layer such as silicon oxide or silicon nitride, and may include a single layer or multiple layers. A gate layer 240 is disposed on the gate insulating layer 230; an interlayer dielectric layer 250 is disposed on the gate layer 240, and the interlayer dielectric layer 250 may include inorganic or organic materials. Inorganic materials may include at least one selected from silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. Organic materials may include at least one selected from acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, and perylene resins.

[0063] A source / drain layer 260 is disposed on the interlayer dielectric layer 250. The material of the source / drain layer 260 can be any one or more of silver, molybdenum, aluminum, and copper. A contact hole 251 extends from the side of the interlayer dielectric layer 250 away from the substrate layer 10 to the surface of the active layer 220 away from the substrate layer 10. The source / drain layer 260 is connected to the active layer 220 through the contact hole 251 to form a thin-film transistor device. A light-shielding block 151 is disposed corresponding to the thin-film transistor device. The projection of the thin-film transistor device on the first substrate layer 130 falls into the projection of the light-shielding block 151 on the first substrate layer 130. The light-shielding block 151 is used to block ambient light from the bottom of the array substrate from the thin-film transistor device.

[0064] A passivation layer 270 is disposed on the source / drain layer 260, a wiring layer 280 is disposed on the passivation layer 270, and a planarization layer 290 is disposed on the wiring layer 280. The planarization layer 290 may include organic materials such as acrylic, polyimide (PI) or benzocyclobutene (BCB), and the planarization layer 290 has a planarization function.

[0065] The pixel electrode layer 310 is disposed on the planarization layer 290, and the pixel definition layer 320 is disposed on the pixel electrode layer 310. The configuration of the pixel electrode layer 310 and the pixel definition layer 320 is a technical means well known to those skilled in the art, and will not be described in detail here.

[0066] This invention also provides a preparation method for preparing the array substrate 100 involved in this invention. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a flowchart of a method for fabricating the array substrate 100, which includes steps 1-2.

[0067] Step 1: Prepare substrate layer 10.

[0068] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure in step 1 of the preparation method.

[0069] Specifically, step 1 includes steps 11-17:

[0070] Step 11: Provide a substrate 110.

[0071] The substrate 110 is a base component used to support the array structure. The array substrate 100 is fabricated using the substrate 110 as a support, and the substrate film layer is subsequently peeled off from the substrate 110. In this embodiment, the substrate 110 can be made of glass.

[0072] Step 12: Prepare the first isolation layer 120 on the substrate 110.

[0073] The first isolation layer 120 can be made of α-Si. On the one hand, the first isolation layer 120 can improve the surface roughness, which is beneficial to the adhesion of the first substrate layer 130. On the other hand, laser stripping technology can be used to vaporize α-Si, which facilitates the separation of the first substrate layer 130 from the substrate 110.

[0074] Step 13: Prepare the first substrate layer 130 on the first isolation layer 120.

[0075] The first substrate layer 130 can be made of an organic material. The organic material can be any one or a combination of polyimide, polyethylene, polypropylene, polystyrene, polyethylene terephthalate, and polyethylene naphthalate.

[0076] Step 14: Prepare a first barrier layer 140 on the first substrate layer 130.

[0077] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of step 14 in the preparation method.

[0078] Specifically, a first barrier layer 140 is deposited on the first substrate layer 130. The thickness of the first barrier layer 140 is between 5 micrometers and 10 micrometers. The first barrier layer 140 can be made of inorganic materials, such as one or more combinations of alumina, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium oxide, zirconium oxide, and zinc oxide. The thickness of the first barrier layer 140 is between 5 micrometers and 10 micrometers. The first barrier layer 140 can be used to block water and oxygen, preventing the thin-film transistor devices in the array substrate 100 from failing.

[0079] Step 15: Prepare a metal layer 150 on the first barrier layer 140, and pattern the metal layer 150 to form a plurality of spaced light-shielding blocks 151.

[0080] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of step 15 in the preparation method.

[0081] Specifically, the metal layer 150 is patterned using a photolithography process, and the cross-sectional shape of the light-shielding block 151 can be square, trapezoidal, or conical. Different shapes can be adjusted according to the process precision. The spacing between the light-shielding blocks 151 can also be different, and this embodiment does not limit this. The material of the light-shielding block 151 is titanium alloy, titanium-molybdenum alloy, or iron alloy. The thickness of the light-shielding block 151 is less than 3000 angstroms.

[0082] The light-shielding block 151 can replace the light-shielding layer 180 in the prior art. Therefore, the step of preparing the light-shielding layer 180 can be eliminated, saving the cost of the light-shielding layer 180. Consequently, there is no need to prepare the buffer hole 190, saving the photomask that prepares the buffer hole 190, further saving costs.

[0083] Step 16: Prepare a second substrate layer 160 on the metal layer 150, and cover the light-shielding block 151 with the second substrate layer 160.

[0084] Please see Figure 6 , Figure 6 This is a schematic diagram of step 16 of the preparation method.

[0085] Specifically, a second substrate layer 160 is coated on the metal layer 150. The portion of the second substrate layer 160 between the light-shielding blocks 151 protrudes downwards to form multiple bumps. The spaced-apart light-shielding blocks 151 improve surface roughness, increasing the adhesion of the first barrier layer 140 to the second substrate layer 160, making the second substrate layer 160 less prone to detachment or cracking. The multiple bumps formed by the downward protrusion of the second substrate layer 160 can disperse bending stress and improve the flexibility of the array substrate.

[0086] Step 17: Prepare a second barrier layer 170 on the second substrate layer 160.

[0087] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of step 17 in the preparation method.

[0088] Specifically, a second barrier layer 170 is deposited on the second substrate layer 160. The second barrier layer 170 includes a multilayer film. The specific steps include: preparing a first silicon oxide layer 171 on the second substrate layer 160; preparing a silicon nitride layer 172 on the first silicon oxide layer 171; and preparing a second silicon oxide layer 173 on the silicon nitride layer 172.

[0089] Step 2: Fabricate a thin-film transistor structure layer 20 on the substrate layer 10.

[0090] Specifically, step 2 includes steps 21-24.

[0091] Step 21: Prepare a buffer layer 210 on the substrate layer 10.

[0092] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of step 21 of the preparation method.

[0093] Specifically, a buffer layer 210 is deposited on the second barrier layer 170. The material of the buffer layer 210 is silicon nitride, silicon oxide, or silicon oxynitride, and the thickness of the buffer layer 210 can be between 1000 angstroms and 5000 angstroms.

[0094] The buffer layer 210 serves to block water and oxygen on the light-shielding layer 180. In this embodiment, the second barrier layer 170 is already made of a water- and oxygen-blocking material, so the buffer layer 210 is not required, thereby saving costs and simplifying the manufacturing process.

[0095] Step 22: Prepare an active layer 220 on the buffer layer 210, prepare a gate insulating layer 230 on the active layer 220, and prepare a gate layer 240 on the gate insulating layer 230.

[0096] Please see Figure 9 , Figure 9 This is a schematic diagram of step 22 of the preparation method.

[0097] Specifically, an active layer 220 is deposited on the buffer layer 210. The material of the active layer 220 can be any one of indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium zinc tin oxide (IGZTO), indium tin oxide (ITO), indium zinc oxide (IZO), indium aluminum zinc oxide (IAZO), indium gallium tin oxide (IGTO), or antimony tin oxide (ATO). These materials have excellent conductivity and transparency, and are relatively thin, so they do not affect the overall thickness of the display panel. They also reduce harmful electronic radiation and ultraviolet and infrared light. The thickness of the active layer 220 is between 100 angstroms and 1000 angstroms.

[0098] A gate insulating layer 230 is deposited on the active layer 220. The gate insulating layer 230 is made of an inorganic layer of silicon oxide or silicon nitride and may consist of a single layer or multiple layers. The thickness of the gate insulating layer 230 is between 1000 angstroms and 3000 angstroms.

[0099] A gate layer 240 is deposited on the gate insulating layer 230. The gate layer 240 can be a single layer of molybdenum, aluminum, copper, or titanium, or it can be a stack of molybdenum / aluminum / molybdenum, aluminum / molybdenum, aluminum / copper, or molybdenum-titanium alloy / copper. The thickness of the gate layer 240 is between 500 angstroms and 10,000 angstroms.

[0100] Plasma is used to process the portion of the active layer 220 that is not covered by the gate insulating layer 230 to form an N+ conductor region for subsequent connection with the source and drain. The portion covered by the gate insulating layer 230 is not processed and serves as the channel of the thin-film transistor device.

[0101] Step 23: Prepare an interlayer dielectric layer 250 on the gate layer 240, prepare a contact hole 251, and prepare a source / drain layer 260 on the interlayer dielectric layer 250.

[0102] Please see Figure 10 , Figure 10 This is a schematic diagram of step 23 of the fabrication method. Specifically, an interlayer dielectric layer 250 is deposited on the gate layer 240 as a dielectric layer. The interlayer dielectric layer 250 may include inorganic or organic materials. Inorganic materials may include at least one selected from silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride. Organic materials may include at least one selected from acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, and perylene resins. The thickness of the deposited interlayer insulating layer is between 3000 angstroms and 10000 angstroms.

[0103] The source / drain layer 260 can be made of any one or more of silver, molybdenum, aluminum, and copper. The thickness of the source / drain layer 260 is between 2,000 angstroms and 10,000 angstroms.

[0104] Contact holes 251 extend from the side of the interlayer dielectric layer 250 away from the substrate layer 10 to the surface of the active layer 220 away from the substrate layer 10. Source / drain layers 260 are connected to the active layer 220 through contact holes 251 to form a thin-film transistor device. A light-shielding block 151 is disposed corresponding to the thin-film transistor device, and the projection of the thin-film transistor device on the first substrate layer 130 falls within the projection of the light-shielding block 151 on the first substrate layer 130. The light-shielding block 151 is used to block ambient light from the bottom of the array substrate from reaching the thin-film transistor device.

[0105] Step 24: Prepare a passivation layer 270 on the source / drain layer 260, prepare a wiring layer 280 on the passivation layer 270, prepare a planarization layer 290 on the wiring layer 280, prepare a pixel electrode layer 310 on the planarization layer 290, and prepare a pixel definition layer 320 on the pixel electrode layer 310.

[0106] Please see Figure 11 , Figure 11 This is a schematic diagram of step 24 of the preparation method.

[0107] Specifically, a passivation layer 270 is deposited on the source / drain layer 260. The material of the passivation layer 270 is silicon oxide, and the thickness ranges from 1000 to 5000 angstroms.

[0108] The thickness of wiring layer 280 ranges from 500 to 1000 angstroms.

[0109] Planarization layer 290 may include organic materials such as acrylic, polyimide (PI), or benzocyclobutene (BCB), and planarization layer 290 has a planarization effect. The thickness of planarization layer 290 ranges from 1000 to 40000 angstroms.

[0110] A pixel electrode layer 310 is deposited on the planarization layer 290. The pixel electrode layer 310 is a stack of highly reflective metallic materials, such as an ITO / silver (Ag) / ITO stack, an IZO / Ag / IZO stack, an ITO / aluminum (Al) / ITO stack, or an IZO / Al / IZO stack. The pixel electrode layer 310 is also connected to the source / drain layer 260.

[0111] The pixel definition layer 320 can be a photoresist layer of different composition. The thickness of the pixel definition layer 320 is between 10,000 angstroms and 20,000 angstroms.

[0112] This application provides an exemplary description of the fabrication of the array substrate 100. It is understood that the array substrate 100 may also include other devices. These other devices and their assembly are well-known techniques to those skilled in the art and will not be described in detail here.

[0113] The above provides a detailed description of an array substrate and its fabrication method provided by the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An array substrate, characterized in that, include: A substrate layer and a thin-film transistor structure layer disposed on the substrate layer, the thin-film transistor structure layer including a plurality of spaced-apart thin-film transistor devices; the substrate layer includes: Base; A first isolation layer is disposed on the substrate; A first substrate layer is disposed on the first isolation layer; A first barrier layer is disposed on the first substrate layer; A metal layer is disposed on the first barrier layer, the metal layer comprising a plurality of light-shielding blocks spaced apart, each light-shielding block corresponding to a thin-film transistor device; A second substrate layer is disposed on the metal layer and covers a plurality of spaced-apart light-shielding blocks; A second barrier layer is disposed on the second substrate layer, wherein the thin-film transistor structure layer is disposed on the second barrier layer.

2. The array substrate as described in claim 1, characterized in that, The second substrate layer has a plurality of bumps formed in the portion between the light-shielding blocks facing the first substrate layer.

3. The array substrate as described in claim 2, characterized in that, The light-shielding block is positioned corresponding to the thin-film transistor device, and the projection of the thin-film transistor device on the first substrate falls into the projection of the light-shielding block on the first substrate layer.

4. The array substrate as described in claim 1, characterized in that, The cross-sectional shape of the light-shielding block is square, trapezoidal, or conical.

5. The array substrate as described in claim 1, characterized in that, The material of the light-shielding block is titanium alloy, titanium-molybdenum alloy, or iron alloy, and the thickness of the light-shielding block is less than 3000 angstroms.

6. The array substrate as described in claim 2, characterized in that, The first barrier layer is an inorganic insulating layer, wherein the plurality of spaced-apart light-shielding blocks are disposed on the inorganic insulating layer, and the plurality of protrusions are in contact with the inorganic insulating layer.

7. The array substrate as claimed in claim 1, characterized in that, The second barrier layer includes: A first silicon oxide layer is disposed on the second substrate layer; A silicon nitride layer is disposed on the first silicon oxide layer; A second silicon oxide layer is disposed on the silicon nitride layer; The thin-film transistor structure layer is disposed on the second silicon oxide layer.

8. The array substrate as described in claim 3, characterized in that, The thin-film transistor structure layer includes: An active layer is disposed on the substrate layer; A gate insulating layer is disposed on the active layer; A gate layer is disposed on the gate insulating layer; An interlayer dielectric layer is disposed on the gate layer; A contact hole extending from the side of the interlayer dielectric layer away from the substrate layer to the surface of the active layer away from the substrate layer; A source-drain layer is disposed on the interlayer dielectric layer, and the source-drain layer is connected to the active layer through the contact hole to form the thin-film transistor device.

9. A method for preparing an array substrate as described in claim 1, characterized in that, The preparation method includes the following steps: Fabrication of substrate layer; A thin-film transistor structure layer is fabricated on the substrate layer; The step of preparing the substrate layer specifically includes the following steps: A substrate, a first isolation layer, and a first substrate layer are stacked together; A first barrier layer is prepared on the first substrate layer; A metal layer is prepared on the first barrier layer, and the metal layer is patterned to form a plurality of spaced light-shielding blocks; A second substrate layer is prepared on the metal layer, and the second substrate layer covers a plurality of spaced-apart light-shielding blocks; A second isolation layer is prepared on a second substrate layer, wherein the thin-film transistor structure layer is disposed on the second isolation layer.

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