Display panel, manufacturing method and display device

Abstract

The application discloses a display panel, a manufacturing method and a display device. The display panel comprises a substrate, at least two grooves are arranged on the substrate, at least two power lines are arranged on the substrate at intervals, the power line comprises a first part arranged in the groove and a second part arranged on the first part, and a functional structure layer is arranged on the substrate. The application increases the first part, which is equivalent to increasing the thickness of the power line, reducing the resistance, thereby reducing the total resistance of the panel power line, improving the IR Drop problem, and further achieving the purpose of improving the brightness non-uniformity of the panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel, a manufacturing method, and a display device. Background Technology

[0002] In recent years, the display industry has experienced rapid development, especially in my country, where it has undergone tremendous changes. Competition in the display industry has become increasingly fierce, with product cycles constantly shortening, particularly between LCD (Liquid Crystal Display) and OLED (Organic Electroluminescence Display). With the maturation of OLED processes and materials, and improvements in yield rates, LCD has gradually lost its market advantage in small-sized displays, especially in the mobile phone market, where OLED has gradually replaced LCD. Many new display technologies have also emerged in recent years, such as QLED displays, E-ink, flexible LCDs, PE displays, Mini LED, and Micro LED. However, these new technologies still face challenges related to cost, lifespan, and reliability, preventing them from achieving the mass production feasibility of LCDs and OLEDs. Micro LED, with its advantages of wide color gamut, high contrast, fast response speed, high resolution, and long lifespan, has been heavily promoted by many companies and is considered the most promising next-generation display technology.

[0003] Several Micro LED demos have been released, but many problems still exist. These include uneven brightness, reliability issues, low transfer yield, poor TFT uniformity, color crosstalk, color mixing, and poor contrast. Among these, IRDrop caused by RC loading can lead to uneven brightness in Micro LED panels. Summary of the Invention

[0004] This application provides a display panel, a manufacturing method, and a display device. By adding a first part, the thickness of the power line is increased, the resistance is reduced, thereby reducing the total resistance of the panel power line, improving the IR drop problem, and thus achieving the purpose of improving the uneven brightness of the panel.

[0005] In a first aspect, embodiments of this application provide a display panel, including:

[0006] A substrate having at least two trenches;

[0007] At least two power lines are spaced apart on the substrate, and the power lines include a first portion disposed in the trench and a second portion disposed on the first portion;

[0008] A functional structure layer is disposed on the substrate.

[0009] In some embodiments, the display area of ​​the display panel includes a light-emitting area and a light-shielding area, the substrate extends from the light-emitting area to the light-shielding area, and the at least two power lines are located in the light-shielding area.

[0010] In some embodiments, the functional structure layer includes:

[0011] A thin-film transistor structure layer is disposed on the substrate, and the thin-film transistor structure layer is located in the light-shielding area;

[0012] A light-emitting device layer is disposed on the substrate, and the light-emitting device layer is located in the light-emitting area.

[0013] In some embodiments, the light-emitting device layer includes:

[0014] A buffer layer is disposed on the substrate;

[0015] An interlayer dielectric layer is disposed on the buffer layer;

[0016] A metal layer is disposed on the interlayer dielectric layer;

[0017] A passivation layer covering the interlayer dielectric layer and the metal layer;

[0018] A planarization layer is disposed on the passivation layer, the planarization layer having a first via, and the first via penetrating the passivation layer to expose a portion of the metal layer;

[0019] An electrode layer is disposed on the planar layer, and the electrode layer is deposited in the first via and contacts the metal layer.

[0020] In some embodiments, the electrode layer includes:

[0021] A metal electrode layer is disposed on the planarization layer, and the metal electrode layer is deposited in the first via and in contact with the metal layer;

[0022] An ITO electrode layer covers the metal electrode layer.

[0023] In some embodiments, the thin-film transistor structure layer includes:

[0024] A light-shielding layer is disposed on the substrate;

[0025] The buffer layer extends from the light-emitting area to the light-shielding area, and the buffer layer covers the light-shielding layer;

[0026] An active layer is disposed on the buffer layer;

[0027] A gate insulating layer is disposed on the active layer;

[0028] A gate layer is disposed on the gate insulating layer;

[0029] The interlayer dielectric layer extends from the light-emitting region to the light-shielding region, and covers the buffer layer, the active layer, the gate insulating layer, and the gate layer. The interlayer dielectric layer is provided with a second via and a third via. The second via exposes a portion of the active layer, and the third via penetrates the buffer layer to expose a portion of the light-shielding layer.

[0030] The metal layer extends from the light-emitting area to the light-shielding area, and the metal layer is deposited in the second via and contacts the active layer, while the metal layer is deposited in the third via and contacts the light-shielding layer.

[0031] The passivation layer extends from the light-emitting area to the light-shielding area;

[0032] The planar layer extends from the light-emitting area to the light-shielding area;

[0033] A light-shielding passivation layer is disposed on the planarization layer, and the light-shielding passivation layer is located in the light-shielding area;

[0034] A black matrix layer is disposed on the light-shielding passivation layer, and the black matrix layer is located in the light-shielding area.

[0035] In some embodiments, the thickness of the first portion is greater than the thickness of the second portion, and the thickness direction is the stacking direction from the substrate to the functional structure layer.

[0036] In some embodiments, the first portion is set to copper.

[0037] Secondly, this application provides a method for manufacturing a display panel, including:

[0038] A substrate is provided, on which at least two grooves are etched;

[0039] A copper film is deposited on the side of the substrate where the trench is provided until the trench is filled;

[0040] The side of the substrate where the copper film is deposited is ground until the copper film in the trench is retained to obtain the first portion;

[0041] A metal layer is deposited on one side of the substrate where the first portion is located, and then etched to obtain a second portion, the second portion being disposed opposite to the first portion;

[0042] A functional structure layer is prepared on the side of the substrate where the first portion is located.

[0043] Thirdly, this application provides a display device, the display device including the display panel described in any one of the above claims.

[0044] The display panel, manufacturing method, and display device provided in this application embodiment have a portion of the power lines deposited in trenches on the substrate. Compared to the case where only the power lines are deposited on the substrate surface, i.e., the power lines only include a second part, this embodiment adds a first part, which is equivalent to increasing the thickness of the power lines, reducing the resistance, thereby reducing the total resistance of the panel power lines, improving the IR drop problem, and thus achieving the purpose of improving the uneven brightness of the panel. Attached Figure Description

[0045] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0046] Figure 1 This is a schematic cross-sectional view of the display panel structure in one embodiment of this application;

[0047] Figure 2 This is a flowchart illustrating the fabrication process of the display panel in one embodiment of this application.

[0048] Icon labels:

[0049] 1. Substrate; 11. Trench; 2. Power line; 21. First part; 22. Second part; 3. Functional structure layer; 31. Light-emitting device layer; 311. Buffer layer; 312. Interlayer dielectric layer; 313. Metal layer; 314. Passivation layer; 315. Planarization layer; 316. Electrode layer; 3161. Metal electrode layer; 3162. ITO electrode layer; 32. Thin film transistor structure layer; 321. Light-shielding layer; 322. Active layer; 323. Gate insulating layer; 324. Gate layer; 325. Light-shielding passivation layer; 326. Black matrix layer. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0051] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0052] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0053] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0054] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0055] Please see Figure 1 and Figure 2 This application provides a display panel, which includes a substrate 1, power lines 2, and a functional structure layer 3. The power lines 2 and the functional structure layer 3 are both disposed on the substrate 1. The substrate 1 has trenches 11. The power lines 2 include at least two power lines 2, a VDD power line and a VSS power line. Different power lines 2 are arranged at intervals. Each power line 2 is partially deposited in the trenches 11, and the power lines 2 are not connected to each other. Therefore, the trenches 11 on the substrate 1 correspond one-to-one with the power lines 2.

[0056] In addition, each power line 2 includes a first part 21 and a second part 22. The first part 21 is deposited in the corresponding trench 11, and the second part 22 is deposited on the first part 21. That is, the first part 21 and the second part 22 are connected, and the first part 21 is made of copper.

[0057] The electrical parameters of the display panel, such as current and resistance, are determined based on the display requirements (e.g., panel clarity, uniformity, etc.), thereby determining the minimum contact area between the first part 21 and the second part 22. While ensuring the contact area between the first part 21 and the second part 22 meets the required minimum area, the bottom surface of the second part 22 can be larger than the top surface of the first part 21, or the bottom surface of the second part 22 can be smaller than the top surface of the first part 21. This embodiment does not impose specific limitations, but the bottom surface of the second part 22 contacts the top surface of the first part 21. For example, the width of the second part 22 can be slightly smaller than the linewidth of the VDD and VSS Power lines in the first part 21 Pixel by 3-5µm.

[0058] In this embodiment, a portion of the power line 2 is deposited in a trench 11 on the substrate 1. Compared to the case where the power line 2 is deposited only on the surface of the substrate 1, i.e. the power line 2 only includes the second part 22, this embodiment adds a first part 21, which is equivalent to increasing the thickness of the power line 2, reducing the resistance, thereby reducing the total resistance of the panel power line 2, improving the IR drop problem, and thus achieving the purpose of improving the uneven brightness of the panel.

[0059] In one embodiment, the display panel includes a display area and a non-display area surrounding the display area. In this embodiment, the area includes a light-emitting area and a light-shielding area. The light-emitting area is equipped with LED beads, so all power lines 2 are located in the light-emitting area. The light-shielding area is a black matrix (BM) area, used to shield the traces of components such as thin-film transistors. Furthermore, all components in the light-shielding and light-emitting areas of the substrate 1 are mounted on the substrate 1. Therefore, the substrate 1 extends from the light-emitting area to the light-shielding area. The substrate 1 can be made of common transparent materials such as glass, quartz, sapphire, or resin. This embodiment does not impose a specific limitation.

[0060] In one embodiment, the functional structure layer 3 includes a thin-film transistor structure layer 32 and a light-emitting device layer 31. Both the thin-film transistor structure layer 32 and the light-emitting device layer 31 are disposed on the substrate 1 and on the same side of the substrate 1. The difference is that the thin-film transistor structure layer 32 is located in the light-shielding area and mainly consists of structures such as thin-film transistors in the pixel driving circuit. The light-emitting device layer 31 is located in the light-emitting area and is connected to the LED beads.

[0061] In one embodiment, the light-emitting device layer 31 includes a buffer layer 311, an interlayer dielectric layer 312, a metal layer 313, a passivation layer 314, a planarization layer 315, and an electrode layer 316 stacked sequentially, and the components included in the light-emitting device layer 31 are all located in the light-emitting area.

[0062] A buffer layer 311 is disposed on one side of the substrate 1, an inter-layer dielectric layer 312 (ILD) is disposed on the side of the buffer layer 311 away from the substrate 1, and a metal layer 313 is disposed on the side of the inter-layer dielectric layer 312 away from the substrate 1. The power supply is part of the metal layer 313. When fabricating a display panel, a metal layer is deposited on the inter-layer dielectric layer 312, followed by reverse etching to obtain the power lines 2 of the light-emitting area. Therefore, the metal layer 313 only occupies a portion of the inter-layer dielectric layer 312. When a passivation layer 314 (PV) is deposited on the side of the inter-layer dielectric layer 312 away from the substrate 1, the passivation layer 314 simultaneously covers both the inter-layer dielectric layer 312 and the metal layer 313.

[0063] A planarization layer 315 (PLN) is disposed on the passivation layer 314, and an electrode layer 316 is disposed on the planarization layer 315. Since the electrode layer 316 needs to be electrically connected to the metal layer 313, the planarization layer 315 is provided with a first via, and the first via penetrates the passivation layer 314 to expose a portion of the metal layer 313 that needs to be electrically connected. Then, the electrode layer 316 is deposited in the first via to achieve contact between the electrode layer 316 and the metal layer 313.

[0064] In one embodiment, electrode layer 316 includes a metal electrode layer 3161 and an ITO (Indium Tin Oxides) electrode layer 316. The metal electrode layer 3161 is deposited in a first via and contacts the metal layer 313. The ITO electrode layer 3162 covers the metal electrode layer 3161, and finally, the ITO electrode layer 3162 is electrically connected to the electrodes of the LED chip. The ITO electrode layer 3162 can enhance conductivity and transparency.

[0065] In one embodiment, the thin-film transistor structure layer 32 includes a light-shielding layer 321, a buffer layer 311, an active layer 322, a gate insulating layer 323, a gate layer 324, an interlayer dielectric layer 312, a metal layer 313, a passivation layer 314, a planarization layer 315, a light-shielding passivation layer 325, and a black matrix layer 326.

[0066] A light-shielding layer 321 (LightShield, LS) is fabricated on substrate 1 through exposure and etching processes. The light-shielding layer 321 occupies only a portion of substrate 1. Therefore, a buffer layer 311 is deposited on both substrate 1 and the light-shielding layer 321, covering both. It should be noted that the buffer layer 311 extends from the light-emitting area to the light-shielding area; that is, the buffer layers 311 in different areas are fabricated using the same process and are integrally formed.

[0067] The active layer 322 is disposed on the buffer layer 311, and the active layer 322 occupies only a portion of the buffer layer 311. The gate insulating layer 323 (GI) is disposed on the active layer 322, and the coating area of ​​the gate insulating layer 323 does not exceed the active layer 322; that is, there is no gate insulating layer 323 on the buffer layer 311. The gate layer 324 (GE) is disposed on the gate insulating layer 323; similarly, the coating area of ​​the gate layer 324 does not exceed the gate insulating layer 323; that is, there is no gate insulating layer 323 on either the gate insulating layer 323 or the buffer layer 311. Furthermore, a light-shielding layer 321 is disposed opposite to the active layer 322, shielding the active layer 322. In addition, the active layer 322 includes a channel region (not shown in the figure) and conductor regions (not shown in the figure) disposed on both sides of the channel region. The channel region is disposed opposite to the gate layer 324, and the light-shielding layer 321 is disposed opposite to the channel region. The range of the light-shielding layer 321 is larger than that of the channel region, so as to block the channel region and prevent light from entering.

[0068] Therefore, when depositing the inter-layer dielectric (ILD) 312 on the gate layer 324, the ILD 312 covers the buffer layer 311, the active layer 322, the gate insulating layer 323, and the gate layer 324. It should be noted that the ILD 312 extends from the light-emitting region to the light-shielding region; that is, the ILD 312 in different regions is fabricated using the same process and is integrally formed. To enable the gate to be electrically connected to other electronic components, and to facilitate contact between the light-shielding layer 321 and other electronic components for subsequent driving, the ILD 312 is provided with a second via and a third via. The second via exposes a portion of the active layer 322, and the third via penetrates the buffer layer to expose a portion of the light-shielding layer 321.

[0069] A metal layer 313 is disposed on the interlayer dielectric layer 312. The metal layer 313 includes source and drain electrodes (SD). Both the source and drain electrodes in the metal layer 313 are deposited in the second vias and contact the active layer 322. However, it should be noted that the source and drain electrodes are deposited in different second vias and connected to the conductor regions on both sides of the channel region of the active layer 322. In addition, the source electrode in the metal layer 313 is also deposited in the third via and contacts the light-shielding layer 321. Furthermore, the metal layer 313 extends from the light-emitting region to the light-shielding region, that is, the metal layer 313 in different regions is fabricated by the same process and integrally formed. The metal layer 313 includes the source and drain electrodes in the light-shielding region and the power lines 2 in the light-emitting region.

[0070] Similarly, the passivation layer 314 and the planarization layer 315 also extend from the light-emitting area to the light-shielding area. That is, the passivation layer 314 and the planarization layer 315 in different areas are prepared by the same process and integrally formed. The passivation layer 314 is disposed on the interlayer dielectric layer 312 and the metal layer 313, and the planarization layer 315 is disposed on the passivation layer 314.

[0071] In addition, a light-shielding passivation layer 325 is disposed on the planarization layer 315 in the light-shielding area, and a black matrix layer 326 is disposed on the light-shielding passivation layer 325. Both the light-shielding passivation layer 325 and the black matrix layer 326 are located only in the light-shielding area.

[0072] In one embodiment, the thickness of the first portion 21 of the power line 2 is greater than the thickness of the second portion 22, and the thickness direction is the stacking direction from the substrate 1 to the functional structure layer 3. For example, the depth of the trench 11 is set to 5-100um. Increasing the thickness of the first portion 21 reduces the resistance, thereby reducing the total resistance of the panel power line, improving the IR drop problem, and thus achieving the purpose of improving the uneven brightness of the panel.

[0073] In this embodiment, simply adding conventional processes to increase the first part 21 without reducing the PPI of the Micro LED panel can effectively improve the panel IR Drop problem and enhance the display quality of the Micro LED display panel.

[0074] Please see Figures 1 to 2 This application provides a method for manufacturing a display panel, the method comprising:

[0075] A substrate 1 is provided, on which at least two grooves 11 are etched;

[0076] A copper film is deposited on the side of the substrate 1 where the trench 11 is provided until the trench 11 is filled;

[0077] The side of the substrate 1 where the copper film is deposited is ground until the copper film in the trench 11 is retained to obtain the first part 21;

[0078] A metal layer 313 is deposited on one side of the substrate 1 where the first portion 21 is provided, and then etched to obtain a second portion 22, the second portion 22 being disposed opposite to the first portion 21;

[0079] A functional structure layer 3 is prepared on the side of the substrate 1 where the first portion 21 is provided.

[0080] Specifically, trenches 11 for the VDD and VSS Power auxiliary lines (i.e., the first part 21 of power lines 2) are laser-etched onto substrate 1. The positions of the trenches 11 correspond one-to-one with the positions of the VDD and VSS Power lines (i.e., the second part 22 of power lines 2) in the Pixel. The trenches 11 are 5-100µm deep and 3-5µm wider than the VDD and VSS Power lines in the Pixel. A copper film is deposited by electroplating until the trenches 11 are filled. The film surface is then ground to remove all the metal from the surface of substrate 1, leaving only the metal in the trenches 11 to form the VDD and VSS Power auxiliary line pattern (i.e., the first part 21 of power lines 2). Afterwards, normal backplane fabrication and subsequent processes are performed to fabricate the functional structure layer 3. The functional structure layer 3 is fabricated sequentially according to the structure described in the above embodiment; its significance will not be elaborated further in this embodiment.

[0081] In this embodiment, simply adding conventional processes to increase the first part 21 without reducing the PPI of the Micro LED panel can effectively improve the panel IR Drop problem and enhance the display quality of the Micro LED display panel.

[0082] This application provides a display device, which includes the display panel described in any of the above embodiments.

[0083] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0084] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The above provides a detailed description of a display panel, manufacturing method, and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display panel, characterized in that, include: A substrate, wherein the substrate is a glass substrate and has at least two trenches, the trenches being located within the substrate and the depth of the trenches being 5µm to 100µm; At least two power lines are spaced apart on the substrate. Each power line includes a first portion and a second portion. The first portion fills the trench, and the second portion covers the first portion and extends to contact the surface of the substrate outside the trench. The first portion includes copper. A functional structure layer is disposed on the substrate and includes a light-shielding layer and a thin-film transistor structure layer; The light-shielding layer is located on the surface of the substrate outside the trench and is disposed in the same layer as the second portion; the thin-film transistor structure layer is located on the side of the light-shielding layer away from the substrate and overlaps with the light-shielding layer; Wherein, the thickness of the first part is greater than the thickness of the second part, and the thickness direction is the stacking direction from the substrate to the functional structure layer.

2. The display panel as described in claim 1, characterized in that, The display panel includes a light-emitting area and a light-shielding area, the substrate extends from the light-emitting area to the light-shielding area, and the at least two power lines are located in the light-emitting area.

3. The display panel as described in claim 2, characterized in that, The thin-film transistor structure layer is located in the light-shielding area; The functional structure layer further includes a light-emitting device layer, which is disposed on the substrate and located in the light-emitting area.

4. The display panel as described in claim 3, characterized in that, The light-emitting device layer includes: A buffer layer is disposed on the substrate; An interlayer dielectric layer is disposed on the buffer layer; A metal layer is disposed on the interlayer dielectric layer; A passivation layer covering the interlayer dielectric layer and the metal layer; A planarization layer is disposed on the passivation layer, the planarization layer having a first via, and the first via penetrating the passivation layer to expose a portion of the metal layer; An electrode layer is disposed on the planar layer, and the electrode layer is deposited in the first via and contacts the metal layer.

5. The display panel as described in claim 4, characterized in that, The electrode layer includes: A metal electrode layer is disposed on the planarization layer, and the metal electrode layer is deposited in the first via and in contact with the metal layer; An ITO electrode layer covers the metal electrode layer.

6. The display panel as described in claim 4, characterized in that, The thin-film transistor structure layer includes: The buffer layer extends from the light-emitting area to the light-shielding area, and the buffer layer covers the light-shielding layer; An active layer is disposed on the buffer layer; A gate insulating layer is disposed on the active layer; A gate layer is disposed on the gate insulating layer; The interlayer dielectric layer extends from the light-emitting region to the light-shielding region, and covers the buffer layer, the active layer, the gate insulating layer, and the gate layer. The interlayer dielectric layer is provided with a second via and a third via. The second via exposes a portion of the active layer, and the third via penetrates the buffer layer to expose a portion of the light-shielding layer. The metal layer extends from the light-emitting area to the light-shielding area, and the metal layer is deposited in the second via and contacts the active layer, while the metal layer is deposited in the third via and contacts the light-shielding layer. The passivation layer extends from the light-emitting area to the light-shielding area; The planar layer extends from the light-emitting area to the light-shielding area; A light-shielding passivation layer is disposed on the planarization layer, and the light-shielding passivation layer is located in the light-shielding area; A black matrix layer is disposed on the light-shielding passivation layer, and the black matrix layer is located in the light-shielding area.

7. A method for manufacturing a display panel, characterized in that, include: A glass substrate is provided, and at least two grooves are etched on the glass substrate, the depth of the grooves being 5um to 100um; A copper film is deposited on the side of the glass substrate where the trench is located until the trench is filled; The side of the glass substrate where the copper film is deposited is ground until the copper film in the trench is retained, thus obtaining a first portion that fills the trench; A metal layer is deposited on one side of the glass substrate where the first portion is provided, and then etched to obtain a second portion, the second portion covering the first portion and extending to contact the surface of the glass substrate outside the trench; A functional structure layer is prepared on one side of the glass substrate where the first portion is provided. The functional structure layer includes a light-shielding layer and a thin-film transistor structure layer. The light-shielding layer is located on the surface of the glass substrate outside the trench and is disposed in the same layer as the second portion; the thin-film transistor structure layer is located on the side of the light-shielding layer away from the substrate and overlaps with the light-shielding layer; The thickness of the first part is greater than the thickness of the second part, and the thickness direction is the stacking direction from the glass substrate to the functional structure layer.

8. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-6.

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