Storage array structure, memory and memory operation method

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a storage array structure, a memory and a memory operation method, the structure comprising: a plurality of magnetic storage units, the magnetic storage unit comprising: a first transistor with a first source-drain electrode and a second source-drain electrode, a second transistor with a third source-drain electrode and a fourth source-drain electrode, the second source-drain electrode and the third source-drain electrode being connected to a signal line, the gate of the first transistor being connected to a first word line, and the gate of the second transistor being connected to a second word line; one end of a first magnetic tunnel junction and one end of a second magnetic tunnel junction are both electrically connected to the fourth source-drain electrode through a transmission line, the other end of the first magnetic tunnel junction and the other end of the second magnetic tunnel junction are both in contact with a spin-orbit coupling layer, the spin-orbit coupling layer is electrically connected to the first source-drain electrode and a bit line, wherein the diameter of the first magnetic tunnel junction is greater than the diameter of the second magnetic tunnel junction, and the spin-orbit coupling layer is a rectangular structure with consistent line width, so as to improve the storage density of SOT-MRAM.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and in particular to a memory array structure, a memory, and a memory operation method. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a novel type of solid-state non-volatile memory with high-speed read and write capabilities, formed using the properties of a magnetic tunnel junction (MTJ). MRAM stores data using magnetic field polarization rather than electric charge. The MTJ consists of a free layer, a tunneling layer, and a fixed layer. The magnetic field polarization direction of the free layer can change, while the magnetization direction of the fixed layer remains constant. When the magnetization directions of the free and fixed layers are the same, the MTJ exhibits low resistance; conversely, it exhibits high resistance. By detecting the resistance of the MTJ, the stored data ("0" or "1") can be determined.

[0003] Traditional spin-transfer torque magnetic random access memory (STT-MRAM) utilizes the spin angular momentum transfer of electrons, where a flow of spin-polarized electrons transfers its angular momentum to the magnetic material in the free layer. With the discovery of the spin-orbit moment effect, a new type of magnetic random access memory (SOT-MRAM) was proposed. SOT-MRAM, based on a spin-orbit coupling layer, uses charge-induced spin current to generate spin-transfer torque, thereby controlling the magnetic memory cells. SOT-MRAM is a next-generation magnetic memory, offering faster read / write speeds and lower power consumption compared to traditional STT-MRAM.

[0004] However, SOT-MRAM increases the area of ​​magnetic storage cells by introducing a spin-orbit coupling layer, but each magnetic storage cell can only store one data bit and requires at least three ports for read and write operations, resulting in a low storage density of magnetic storage cells. Summary of the Invention

[0005] This disclosure provides a storage array structure, a memory, and a memory operation method to improve the storage density of SOT-MRAM.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a memory array structure, including: a plurality of magnetic memory cells, each magnetic memory cell including: a first transistor and a second transistor, the first transistor having a first source-drain and a second source-drain, the second transistor having a third source-drain and a fourth source-drain, and the second source-drain and the third source-drain being connected to a signal line, the gate of the first transistor being connected to a first word line, and the gate of the second transistor being connected to a second word line; a first magnetic tunnel junction and a second magnetic tunnel junction, one end of the first magnetic tunnel junction and one end of the second magnetic tunnel junction being electrically connected to the fourth source-drain through a transmission line, the other end of the first magnetic tunnel junction and the other end of the second magnetic tunnel junction being in contact with a spin-orbit coupling layer, the spin-orbit coupling layer being located on the side of the first magnetic tunnel junction and the second magnetic tunnel junction away from the transmission line, the spin-orbit coupling layer being electrically connected to the first source-drain and the bit line, wherein the diameter of the first magnetic tunnel junction is larger than the diameter of the second magnetic tunnel junction, and the spin-orbit coupling layer is a rectangular structure with a uniform linewidth.

[0007] In some embodiments, along the direction away from the spin-orbit coupling layer, the first magnetic tunnel junction sequentially includes a first free layer, a first tunneling layer, and a first fixed layer, with the first free layer located on the surface of the spin-orbit coupling layer; the second magnetic tunnel junction sequentially includes a second free layer, a second tunneling layer, and a second fixed layer, with the second free layer located on the surface of the spin-orbit coupling layer, wherein the magnetization direction in the first fixed layer is the same as the magnetization direction in the second fixed layer.

[0008] In some embodiments, the contact point between the spin-orbit coupling layer and the first free layer is located between the first connection point and the second connection point, and the contact point between the spin-orbit coupling layer and the second free layer is located between the first connection point and the second connection point; the first connection point is the connection point between the first source / drain electrode and the spin-orbit coupling layer, and the second connection point is the connection point between the bit line and the spin-orbit coupling layer.

[0009] In some embodiments, a first transistor and a second transistor are formed on a substrate, and the gate of the first transistor is located within the substrate, and the gate of the second transistor is located within the substrate.

[0010] In some embodiments, the diameter of the first magnetic tunnel junction is 50%-70% of the diameter of the second magnetic tunnel junction.

[0011] In some embodiments, along a first direction, the gates of the first transistors in a plurality of magnetic memory cells are connected to the same first word line, and the gates of the second transistors in a plurality of magnetic memory cells are connected to the same second word line; along a second direction, a plurality of magnetic memory cells are connected to the same signal line; along a third direction, a plurality of magnetic memory cells are connected to the same bit line, wherein the first direction and the third direction are not parallel to each other.

[0012] In some embodiments, multiple magnetic storage cells are arranged in a parallelogram array.

[0013] In some embodiments, one side of the parallelogram is disposed in a first direction, and the other side of the parallelogram is disposed in a fourth direction, wherein the fourth direction is the extension direction of the spin-orbit coupling layer.

[0014] In some embodiments, the second direction is the same as the first direction.

[0015] In some embodiments, the second direction is perpendicular to the fourth direction.

[0016] In some embodiments, the second direction is the same as the fourth direction.

[0017] In some embodiments, the third direction is the same as the fourth direction.

[0018] In some embodiments, the third direction is the same as the second direction.

[0019] In some embodiments, multiple magnetic storage cells are arranged in a rectangular array.

[0020] In some embodiments, the signal lines of all magnetic storage cells are connected together.

[0021] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory, the array structure of which is based on the memory array structure in the above embodiments.

[0022] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory operation method, including a writing step and a reading step, applied to the memory in the above embodiments.

[0023] In some embodiments, the writing step includes: acquiring a first word line, a second word line, a signal line, and a bit line corresponding to the target magnetic memory cell; applying a conduction voltage to the corresponding first word line to turn on a first transistor; passing a first forward current through the signal line and the bit line, the magnitude of the first forward current being greater than a first preset value, so that both the first magnetic tunnel junction and the second magnetic tunnel junction are in a first state; or, passing a first reverse current through the signal line and the bit line, the magnitude of the first reverse current being greater than a first preset value, so that both the first magnetic tunnel junction and the second magnetic tunnel junction are in a second state, wherein the current direction of the first forward current is opposite to the current direction of the first reverse current.

[0024] In some embodiments, the writing step further includes: if both the first magnetic tunnel junction and the second magnetic tunnel junction are in a first state, then changing the first forward current to a second reverse current, wherein the direction of the second reverse current is opposite to that of the first forward current, and the magnitude of the second reverse current is greater than a second preset value and less than a first preset value, so that the first magnetic tunnel junction remains in the first state and the second magnetic tunnel junction is in the second state; if both the first magnetic tunnel junction and the second magnetic tunnel junction are in the second state, then changing the first reverse current to a second forward current, wherein the direction of the second forward current is opposite to that of the first reverse current, and the magnitude of the second forward current is greater than a second preset value and less than a first preset value, so that the first magnetic tunnel junction remains in the second state and the second magnetic tunnel junction is in the first state.

[0025] In some embodiments, the reading step includes: acquiring a first word line, a second word line, a signal line, and a bit line corresponding to the target magnetic memory cell; applying a conduction voltage in the corresponding second word line to turn on the second transistor; determining the resistance value R of the target magnetic memory cell based on the magnitude of the current in the signal line and the bit line, and reading the stored data.

[0026] In some embodiments, the resistance R of the target magnetic storage cell is determined based on the magnitude of the current in the signal line and bit line, and the stored data is read, including: if the resistance R of the target magnetic storage cell is R1, then the stored data in the target storage cell is "11"; if the resistance R of the target magnetic storage cell is R2, then the stored data in the target storage cell is "10"; if the resistance R of the target magnetic storage cell is R3, then the stored data in the target storage cell is "01"; if the resistance R of the target magnetic storage cell is R4, then the stored data in the target storage cell is "00"; wherein, the first bit of the stored data represents the stored data of the first magnetic tunnel junction, and the second bit of the stored data represents the stored data of the second magnetic tunnel junction.

[0027] The technical solution provided in this disclosure has at least the following advantages: By connecting the second source and drain of the first transistor and the third source and drain of the second transistor to the same signal line, the first transistor and the second transistor can share a source or drain, reducing the area of ​​the first transistor and the second transistor, which is beneficial to improving the space utilization of the magnetic memory cell, thereby increasing the integration density of the magnetic memory cell. Furthermore, the sharing of the signal line between the first transistor and the second transistor can reduce the number of control terminals on the signal line. The first source and drain of the first transistor are connected to the bit line through a spin-orbit coupling layer, and both the first magnetic tunnel junction and the second magnetic tunnel junction are in contact with the spin-orbit coupling layer. Since the diameter of the first magnetic tunnel junction is larger than the diameter of the second magnetic tunnel junction, the driving current of the first magnetic tunnel junction is greater than the driving current of the second magnetic tunnel junction. Therefore, the signal line can be controlled by turning on the first transistor. By controlling the direction and magnitude of the current within the bit line, the first and second magnetic tunnel junctions can be written to respectively, thus achieving two storage bits and four forms of stored data. The fourth source and drain of the second transistor are connected to the bit line in parallel with the first and second magnetic tunnel junctions through a transmission line. By controlling the conduction of the second transistor and based on the magnitude of the current in the signal line and bit line, the resistance of the first and second magnetic tunnel junctions after parallel connection can be determined, thereby determining the resistance state of the first and second magnetic tunnel junctions and enabling the reading of data stored in the magnetic memory cell. In addition, the spin-orbit coupling layer is a rectangular structure with a uniform linewidth, which facilitates the fabrication of the spin-orbit coupling layer in the magnetic memory cell. It eliminates the need for corresponding spin-orbit coupling layer designs for magnetic tunnel junctions of different diameters, improving the efficiency of the magnetic memory cell structure fabrication process. Attached Figure Description

[0028] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a magnetic storage cell provided in one embodiment of the present disclosure;

[0030] Figures 2 to 8 This is a top view of various storage array structures provided in one embodiment of the present disclosure. Detailed Implementation

[0031] As can be seen from the background technology, SOT-MRAM increases the area of ​​magnetic storage cells by introducing a spin-orbit coupling layer. However, each magnetic storage cell can only store one bit, and at least three ports are required for read and write operations, resulting in a low storage density of magnetic storage cells.

[0032] Analysis revealed that the spin-orbit coupling layer of SOT-MRAM allows for separate read and write paths. Therefore, each magnetic storage cell requires two transistors to control the read and write operations respectively. This means SOT-MRAM typically uses a 2T-1R cell structure, while STT-MRAM usually uses a 1T-1R cell structure. This results in a larger device cell area for SOT-MRAM compared to STT-MRAM, leading to a decrease in SOT-MRAM integration density. Furthermore, each SOT-MRAM magnetic storage cell can only store one bit and requires three ports for control. For example, during writing, the write transistor needs to be turned on, and the direction and magnitude of the current in the source and bit lines need to be controlled to reverse the magnetization direction of the magnetic tunnel junction. This further contributes to the lower storage density of the SOT-MRAM structure.

[0033] One embodiment of this disclosure provides a storage array structure to improve the storage density of SOT-MRAM.

[0034] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0035] Figure 1 This is a schematic diagram of the structure of a magnetic storage cell provided in one embodiment of the present disclosure. Figures 2 to 8 This is a top view of various memory array structures provided in one embodiment of the present disclosure. The memory array structures provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0036] refer to Figure 1The memory array structure includes: multiple magnetic memory cells, each magnetic memory cell 10 including: a substrate 100 and a first transistor T1 and a second transistor T2 formed on the substrate 100. The first transistor T1 has a first source-drain 101 and a second source-drain 102, the second transistor T2 has a third source-drain 103 and a fourth source-drain 104, and the second source-drain 102 and the third source-drain 103 are connected to a signal line 113. The gate of the first transistor T1 is connected to a first word line 111, and the gate of the second transistor T2 is connected to a second word line 112; a first magnetic tunnel junction 200 and a second magnetic tunnel junction 300. One end of the first magnetic tunnel junction 200 and one end of the second magnetic tunnel junction 300 are electrically connected to the fourth source / drain 104 via the transmission line 105. The other ends of the first magnetic tunnel junction 200 and the second magnetic tunnel junction 300 are in contact with the spin-orbit coupling layer 115. The spin-orbit coupling layer 115 is located on the side of the first magnetic tunnel junction 200 and the second magnetic tunnel junction 300 away from the transmission line 105. The spin-orbit coupling layer 115 is electrically connected to the first source / drain 101 and the bit line 114. The diameter of the first magnetic tunnel junction 200 is larger than the diameter of the second magnetic tunnel junction 300. The spin-orbit coupling layer 115 is a rectangular structure with a uniform linewidth.

[0037] By connecting the second source / drain 102 of the first transistor T1 and the third source / drain 103 of the second transistor T2 to the signal line 113, the first transistor T1 and the second transistor T2 can share a source or drain, reducing the area of ​​the first transistor T1 and the second transistor T2. This is beneficial for improving the space utilization of the magnetic memory cell, thereby increasing the integration density of the magnetic memory cell. Furthermore, sharing the signal line 113 between the first transistor T1 and the second transistor T2 can reduce the number of control terminals on the signal line. The first source / drain 101 of the first transistor T1 is connected to the bit line 114 through the spin-orbit coupling layer 115, and both the first magnetic tunnel junction 200 and the second magnetic tunnel junction 300 are in contact with the spin-orbit coupling layer 115. Since the diameter of the first magnetic tunnel junction 200 is larger than the diameter of the second magnetic tunnel junction 300, the driving current of the first magnetic tunnel junction 200 is greater than the driving current of the second magnetic tunnel junction 300. Therefore, the conduction of the first transistor T1 can control the current in the signal line 113 and the bit line 114. The direction and magnitude of the current flow enable writing to the first magnetic tunnel junction 200 and the second magnetic tunnel junction 300 respectively, thus achieving two storage bits, i.e., four forms of stored data. The fourth source-drain 104 of the second transistor T2 connects the first magnetic tunnel junction 200 and the second magnetic tunnel junction 300 in parallel through the transmission line 105 and then connects to the bit line 114. By controlling the conduction of the second transistor T2, the resistance of the first magnetic tunnel junction 200 and the second magnetic tunnel junction 300 after parallel connection can be determined based on the magnitude of the current in the signal line 113 and the bit line 114, thereby determining the resistance state of the first magnetic tunnel junction 200 and the second magnetic tunnel junction 300, so as to realize the reading of the stored data in the magnetic storage cell 10. In addition, the spin-orbit coupling layer 115 is a rectangular structure with a uniform line width, which facilitates the fabrication of the spin-orbit coupling layer 115 in the magnetic storage cell 10. It eliminates the need for corresponding spin-orbit coupling layer 115 designs for magnetic tunnel junctions of different diameters, thereby improving the efficiency of the fabrication process of the magnetic storage cell 10 structure.

[0038] In this embodiment, the first transistor T1 and the second transistor T2 are formed on the substrate 100, and the gate of the first transistor T1 is located inside the substrate 100, and the gate of the second transistor T2 is located inside the substrate 100, that is, the gates of the first transistor T1 and the second transistor T2 are buried gate structures; in other embodiments, the first transistor and the second transistor may be planar gate structures.

[0039] It should be noted that, for clarity of the accompanying drawings, in this embodiment, the gate of the first transistor T1 is connected to the first word line 101, and the gate of the second transistor T2 is connected to the second word line 102. Furthermore, based on the buried gate structure of the first and second transistors, the first and second word lines can be buried word line structures. The buried gate and buried word line structures can increase the area of ​​the transistor channel region, thereby improving the transistor's current control capability and thus improving the performance of the semiconductor structure. Simultaneously, the buried gate and buried word line structures can improve the space utilization of the semiconductor structure, thereby further increasing the integration density of the memory array structure.

[0040] It should be noted that in this embodiment, the second source-drain 103 is the source of the first transistor T1, and the third source-drain 103 is the source of the second transistor T2. That is, the first transistor T1 and the second transistor T2 share a common source, which is used to connect the signal line 113, which is the source line of the magnetic storage cell 10. The first source-drain 101 is the drain of the first transistor T1 and is connected to the spin-orbit coupling layer 115, and the fourth source-drain 104 is the drain of the second transistor T2 and is connected to the transmission line 105. The specific connection methods of the "source" and "drain" defined above do not constitute a limitation on the embodiments of this application. In other embodiments, the connection methods of "drain" replacing "source" and "source" replacing "drain" can be used.

[0041] For the first magnetic tunnel junction 200 and the second magnetic tunnel junction 300, along the direction away from the spin-orbit coupling layer 115, the first magnetic tunnel junction 200 sequentially includes a first free layer 201, a first tunneling layer 202, and a first fixed layer 203, with the first free layer 201 located on the surface of the spin-orbit coupling layer 115; the second magnetic tunnel junction 300 sequentially includes a second free layer 301, a second tunneling layer 302, and a second fixed layer 303, with the second free layer 301 located on the surface of the spin-orbit coupling layer 115. The magnetization direction within the first fixed layer 203 is the same as the magnetization direction within the second fixed layer 303. By setting the magnetization direction within the first fixed layer 203 and the second fixed layer 303 to be the same, both the first magnetic tunnel junction 200 and the second magnetic tunnel junction 300 can be in a high-resistance state or both in a low-resistance state under a high driving current in a fixed direction, thus facilitating the writing of data "00" or "11".

[0042] In some embodiments, the magnetization direction within the first fixed layer may be different from the magnetization direction within the second fixed layer.

[0043] In this embodiment, the diameter of the second magnetic tunnel junction is 50% to 70% of the diameter of the first magnetic tunnel junction. Specifically, the diameter of the second magnetic tunnel junction can be 50%, 60%, or 70% of the diameter of the first magnetic tunnel junction. It is understood that the greater the difference in diameter between the first and second magnetic tunnel junctions, the greater the difference in drive current between them, requiring an increased drive current to power the first magnetic tunnel junction and increasing current consumption during writing, thus affecting the lifespan of the magnetic storage cell. Conversely, the smaller the difference in diameter between the first and second magnetic tunnel junctions, the smaller the difference in drive current between them, which is not conducive to writing to the second magnetic tunnel junction with its smaller drive current. Therefore, the ratio of the diameters of the first and second magnetic tunnel junctions needs to be adjusted within a certain range to ensure that the corresponding drive current can be used to write to different magnetic tunnel junctions without excessively burdening the drive current.

[0044] In some embodiments, the magnetization directions of the first magnetic tunnel junction 200 and the second magnetic tunnel junction 300 are both perpendicular to the surface of the spin-orbit coupling layer 115; in other embodiments, the magnetization directions of the first magnetic tunnel junction 200 and the second magnetic tunnel junction 300 are both parallel to the surface of the spin-orbit coupling layer 115. When the magnetization direction of the magnetic tunnel junction is perpendicular to the surface of the spin-orbit coupling layer, the magnetization direction in the free layer can be converted to a direction perpendicular to and towards the surface of the spin-orbit coupling layer, or a direction perpendicular to and away from the surface of the spin-orbit coupling layer; the magnetization direction in the fixed layer can be fixed to a direction perpendicular to and away from the surface of the spin-orbit coupling layer, or a direction perpendicular to and towards the surface of the spin-orbit coupling layer. When the free layer undergoes a magnetization direction change due to the spin-orbit interaction in the spin-orbit coupling layer, if the magnetization direction in the free layer changes to be the same as the magnetization direction of the fixed layer, the magnetic tunnel junction exhibits a low-resistance state; if the magnetization direction in the free layer changes to be opposite to the magnetization direction of the fixed layer, the magnetic tunnel junction exhibits a high-resistance state. Furthermore, the magnetization direction of the magnetic tunnel junction can also be parallel to the surface of the spin-orbit coupling layer. That is, the magnetization direction within the fixed layer of the magnetic tunnel junction is parallel to the surface of the spin-orbit coupling layer, and the magnetic field within the free layer can be the same as or opposite to the magnetization direction of the fixed layer. The corresponding magnetization directions of the free and fixed layers determine the magnitude of the resistive state of the magnetic tunnel junction. It is understood that the magnetization direction of the magnetic tunnel junction can be selected and determined according to actual conditions, and this embodiment does not excessively limit the magnetization direction of the magnetic tunnel junction.

[0045] It should be noted that in this embodiment, the magnetization direction in the first fixing layer 203 is the same as the magnetization direction in the second fixing layer 303; in other embodiments, the magnetization direction in the first fixing layer 203 may be different from the magnetization direction in the second fixing layer 303.

[0046] For the first free layer 201, the second free layer 301, the first fixed layer 203, and the second fixed layer 303, each of the first free layer 201, the second free layer 301, the first fixed layer 203, and the second fixed layer 303 includes any one of cobalt iron boron, cobalt, or nickel iron.

[0047] Both the first tunneling layer 202 and the second tunneling layer 302 are made of magnesium oxide.

[0048] For the spin-orbit coupling layer 115, the material of the spin-orbit coupling layer 115 can be any one of platinum, tantalum, tungsten, iridium, hafnium, ruthenium, thallium, bismuth, gold, titanium and osmium.

[0049] It should be noted that, in this embodiment, the first free layer in the first magnetic tunnel junction and the second free layer in the second magnetic tunnel junction are made of the same material, the first tunneling layer in the first magnetic tunnel junction and the second tunneling layer in the second magnetic tunnel junction are made of the same material, and the first fixed layer in the first magnetic tunnel junction and the second fixed layer in the second magnetic tunnel junction are made of the same material; in other embodiments, the materials of the first free layer in the first magnetic tunnel junction and the second free layer in the second magnetic tunnel junction may be different, the materials of the first tunneling layer in the first magnetic tunnel junction and the second tunneling layer in the second magnetic tunnel junction may be different, and the materials of the first fixed layer in the first magnetic tunnel junction and the second fixed layer in the second magnetic tunnel junction may be different.

[0050] Furthermore, the contact point between the spin-orbit coupling layer and the first free layer is located between the first connection point and the second connection point, and the contact point between the spin-orbit coupling layer and the second free layer is also located between the first connection point and the second connection point. The first connection point is the connection point between the first source / drain electrode and the spin-orbit coupling layer, and the second connection point is the connection point between the potential line and the spin-orbit coupling layer. It can be understood that the spin-orbit coupling layer utilizes the spin Hall effect or anti-spin current effect to convert the current flowing in the spin-orbit coupling layer with strong spin-orbit coupling into a spin current. This spin current diffuses into the free layer, applying a torque to the magnetic moment of the free layer, causing it to flip. When the current flowing through the spin-orbit coupling layer can completely flow through the surface where the free layer contacts the spin-orbit coupling layer, the diffusion effect of the spin current into the free layer is better, thus making it easier for the magnetic field in the free layer to flip.

[0051] refer to Figure 2In some embodiments, along the first direction X, the gates of the first transistors T1 in the plurality of magnetic storage cells 10 are connected to the same first word line 111, and the gates of the second transistors T2 in the plurality of magnetic storage cells 10 are connected to the same second word line 112; along the second direction Y, the plurality of magnetic storage cells 10 are connected to the same signal line 113; and along the third direction Z, the plurality of magnetic storage cells 10 are connected to the same bit line 114, wherein the first direction X and the third direction Z are not parallel to each other. By having the plurality of magnetic storage cells 10 share the first word line 111 and the second word line 112 along the first direction X; share the signal line 113 along the second direction Y; and share the bit line 114 along the third direction Z, the control terminals of the first word line 111, the second word line 112, the signal line 113, and the bit line 114 can be reduced, thereby improving the control capability of the storage array.

[0052] Continue to refer to Figure 2 In some embodiments, the magnetic storage cells 10 can be arranged in a parallelogram array. This parallelogram arrangement makes the magnetic storage cells more regular, facilitating the fabrication of the semiconductor structure and enabling the realization of a hexagonal close-packed configuration.

[0053] refer to Figure 3 In some embodiments, one side of the parallelogram can be set in the first direction X, and the other side of the parallelogram can be set in the fourth direction W. The second direction Y is the same as the first direction X, that is, the extension directions of the first word line 111, the second word line 112 and the signal line 113 are the same. The fourth direction W is the extension direction of the spin-orbit coupling layer 115.

[0054] Further reference Figure 3 In some embodiments, the extension direction of the third direction Z, i.e., the bit line 114, may be the same as the fourth direction W; see reference. Figure 4 In other embodiments, the direction of extension of the third direction Z, i.e., the position line 114, may be different from the fourth direction W.

[0055] refer to Figures 5 to 7 In some embodiments, the second direction Y can be perpendicular to the fourth direction W, that is, the extension direction of the signal line 113 is perpendicular to the extension direction of the spin-orbit coupling layer 115. Further, referring to... Figure 5 In some embodiments, the extension direction of the third direction Z, i.e., the bit line 114, may be the same as the fourth direction W; see reference. Figure 6 In other embodiments, the extension direction of the third direction W, i.e., the bit line 114, may be the same as the second direction Y; see reference. Figure 7 In some other embodiments, the direction of extension of the third direction W, i.e., the position line 114, may be different from either the fourth direction W or the second direction Y.

[0056] refer to Figure 8 In some embodiments, the plurality of magnetic storage cells 10 may be arranged in a rectangular array. Furthermore, the second direction Y may be the same as the fourth direction W, and the third direction Z may be the same as the fourth direction W.

[0057] It is understood that, based on the different arrangements of magnetic storage cells in the above embodiments, and the different extension methods of the first word line, second word line, signal line, and bit line, during the writing process of the target magnetic tunnel junction, by selecting the first word line corresponding to the target magnetic tunnel junction, the first transistor in all magnetic storage cells of the magnetic storage cell corresponding to the target magnetic tunnel junction in the first direction can be turned on. Furthermore, by controlling the magnitude and direction of the current in the signal line and bit line corresponding to the storage cell where the target magnetic tunnel junction is located, the writing of the target magnetic tunnel junction can be achieved. During the reading process of the target magnetic tunnel junction, by selecting the second word line corresponding to the target magnetic tunnel junction, the second transistor in all storage cells of the magnetic storage cell corresponding to the target magnetic tunnel junction in the first direction can be turned on. Furthermore, by judging the resistance of the target magnetic tunnel junction based on the current in the signal line and bit line corresponding to the storage cell where the target magnetic tunnel junction is located, the stored data in the target magnetic tunnel junction can be determined. It is not difficult to see that when both the first word line and the second word line have different extension directions from the bit line, the target magnetic memory cell can be located by the first word line and the corresponding bit line or the second word line and the corresponding bit line. Thus, the first transistor controls the writing to the magnetic tunnel junction, and the second transistor controls the reading to the magnetic tunnel junction.

[0058] It should be noted that the extension directions of the first word line and the second word line, the second direction (signal line), and the third direction (bit line) provided in this embodiment can be arbitrarily combined without conflict to obtain new embodiments of the extension directions of the first word line and the second word line, the signal line, and the bit line. This allows for adjustment of the extension direction of the control terminal during the fabrication process of the memory array structure according to actual needs, to coordinate with the arrangement of memory cells to form the densest stacking, thereby increasing the integration density of the memory array structure and improving the control capability of the memory array structure.

[0059] Continue to refer to Figure 8In some embodiments, the signal lines 113 of all magnetic storage cells 10 can be connected. By connecting the signal lines 113 of all magnetic storage cells 10, the number of control terminals of a large number of signal lines 113 in the storage array structure can be reduced, while the control capability of the storage array structure can be improved and the manufacturing process of the storage array structure can be simplified. When all signal lines of the magnetic storage cells are connected, during the writing process of the target magnetic tunnel junction, by applying a conduction voltage to the first word line corresponding to the target magnetic tunnel junction, the first transistor in the column of magnetic storage cells containing the target magnetic tunnel junction is turned on, further selecting the signal lines. All magnetic storage cells in the column containing the target magnetic tunnel junction are in a state ready to be written. The magnetic storage cell containing the target magnetic tunnel junction can be located through the corresponding bit line. Then, based on the magnitude and direction of the current in the signal lines and bit lines, the writing of the target magnetic tunnel junction is achieved. During the reading process of the target magnetic tunnel junction, by applying a conduction voltage to the second word line corresponding to the target magnetic tunnel junction, the second transistor in the column of magnetic storage cells containing the target magnetic tunnel junction is turned on, further selecting the signal lines. All magnetic storage cells in the column containing the target magnetic tunnel junction are in a state ready to be read. The magnetic storage cell containing the target magnetic tunnel junction can be located through the corresponding bit line. Then, based on the current in the signal lines and bit lines, the resistance of the target magnetic tunnel junction is determined, and the data stored in the target magnetic tunnel junction can be determined.

[0060] The memory array structure provided in this disclosure allows the first and second transistors to share a common source or drain by connecting the second source and drain of the first transistor and the third source and drain of the second transistor to a signal line. This reduces the area of ​​the first and second transistors, improving the space utilization of the magnetic memory cells and thus increasing their integration density. Furthermore, sharing a signal line between the first and second transistors reduces the number of control terminals on the signal line. The first source and drain of the first transistor are connected to the bit line through a spin-orbit coupling layer, and both the first and second magnetic tunnel junctions are in contact with the spin-orbit coupling layer. Since the diameter of the first magnetic tunnel junction is larger than that of the second magnetic tunnel junction, the driving current of the first magnetic tunnel junction is greater than that of the second magnetic tunnel junction. Therefore, the conduction of the first transistor can control the signal line and the bit line. The direction and magnitude of the current within the transistor allow for writing to the first and second magnetic tunnel junctions, enabling two storage bits and four data storage formats. The fourth source and drain of the second transistor connect the first and second magnetic tunnel junctions in parallel via a transmission line to the bit line. By controlling the conduction of the second transistor and the magnitude of the current in the signal and bit lines, the resistance of the parallel connection between the first and second magnetic tunnel junctions can be determined, thus determining their resistance state and enabling data retrieval from the magnetic storage cell. Furthermore, the spin-orbit coupling layer is a rectangular structure with a uniform linewidth, facilitating its fabrication in the magnetic storage cell. This eliminates the need for specific spin-orbit coupling layer designs for magnetic tunnel junctions of different diameters, improving the efficiency of the magnetic storage cell fabrication process.

[0061] Another embodiment of this disclosure provides a memory whose array structure is based on the memory array structure provided in the above embodiments, so as to improve the storage density of SOT-MRAM.

[0062] Specifically, memory can be a storage cell or device based on a semiconductor device or component. For example, a memory device can be volatile memory, such as dynamic random access memory (DRAM), or it can be non-volatile memory, such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0063] Another embodiment of this disclosure provides a memory operation method, including a write step and a read step, applied to the memory in the above embodiments.

[0064] In some embodiments, the writing step includes: acquiring a first word line, a second word line, a signal line, and a bit line corresponding to the target magnetic memory cell; applying a conduction voltage to the corresponding first word line to turn on a first transistor; passing a first forward current through the signal line and the bit line, the magnitude of the first forward current being greater than a first preset value, so that both the first magnetic tunnel junction and the second magnetic tunnel junction are in a first state; or, passing a first reverse current through the signal line and the bit line, the magnitude of the first reverse current being greater than a first preset value, so that both the first magnetic tunnel junction and the second magnetic tunnel junction are in a second state, wherein the current direction of the first forward current is opposite to the current direction of the first reverse current.

[0065] Specifically, for example, when the initial states of the first magnetic tunnel junction and the second magnetic tunnel junction are not considered, the first preset value is the driving current value of the first magnetic tunnel junction. When the magnitude of the first forward current is greater than the first preset value, the first forward current can cause both the first magnetic tunnel junction and the second magnetic tunnel junction to change to the first state, i.e., the low-resistance state. At this time, the magnetic storage cell is written with "00" (the first bit of the stored data represents the stored data of the first magnetic tunnel junction, and the second bit of the stored data represents the stored data of the second magnetic tunnel junction). The first reverse current is opposite to the direction of the first forward current. When the magnitude of the first reverse current is greater than the first preset value, the first reverse current can cause both the first magnetic tunnel junction and the second magnetic tunnel junction to change to the second state, i.e., the high-resistance state. The magnetic storage cell is written with "11".

[0066] Furthermore, the writing step also includes: if both the first magnetic tunnel junction and the second magnetic tunnel junction are in the first state, then the first forward current is changed to a second reverse current, the second reverse current is opposite in direction to the first forward current, and the magnitude of the second reverse current is greater than a second preset value and less than the first preset value, so that the first magnetic tunnel junction remains in the first state and the second magnetic tunnel junction is in the second state; if both the first magnetic tunnel junction and the second magnetic tunnel junction are in the second state, then the first reverse current is changed to a second forward current, the second forward current is opposite in direction to the first reverse current, and the magnitude of the second forward current is greater than a second preset value and less than the first preset value, so that the first magnetic tunnel junction remains in the second state and the second magnetic tunnel junction is in the first state.

[0067] Specifically, for example, the second preset value is the driving current value of the second magnetic tunnel junction. If both the first and second magnetic tunnel junctions are in the first state (low resistance state), the magnetic storage unit stores data "00". After changing the first forward current to the second reverse current, the direction of the second reverse current is opposite to that of the first forward current. The magnitude of the second reverse current is greater than the second preset value and less than the first preset value. Therefore, the second reverse current can only make the second magnetic tunnel junction change to the high resistance state, and the stored data changes to "01". If both the first and second magnetic tunnel junctions are in the second state (high resistance state), the magnetic storage unit stores data "11". After changing the first reverse current to the second forward current, the direction of the second forward current is opposite to that of the first reverse current. The magnitude of the second forward current is greater than the second preset value and less than the first preset value. Therefore, the second forward current can only make the second magnetic tunnel junction change to the low resistance state, and the stored data changes to "10".

[0068] Based on the writing steps in the above embodiments, the step of writing the stored data in the magnetic storage unit to "00" is defined as step A; the step of writing the stored data in the magnetic storage unit to "11" is defined as step B; the step of writing the stored data in the magnetic storage unit from "00" to "01" is defined as step C; and the step of writing the stored data in the magnetic storage unit from "11" to "10" is defined as step D. Combining the initial state and the corresponding final state of the magnetic storage unit, the following operation table can be formed:

[0069]

[0070] Understandably, when the initial state and the final state are the same, no operation is required; when "00" needs to be written, the initial state does not need to be considered, and step A can be performed directly; or when "11" needs to be written, the initial state does not need to be considered, and step B can be performed directly; when the initial state to the final state cannot be directly completed through one of steps A, B, C, or D, two steps are required. For example, when the initial state is "00" and the final state is "10", step B needs to be performed first to make the first magnetic tunnel junction change to a high-resistance state. At this time, since the driving current of the second magnetic tunnel junction is less than that of the first magnetic tunnel junction, the second magnetic tunnel junction will also change to a high-resistance state, and the corresponding stored data will change to "11". Corresponding to the above four steps, the operation that changes from "11" to "10" can be found to be step D. Then step D is performed to change the stored data from "00" to "10" through two steps.

[0071] It should be noted that, for ease of explanation, in the above embodiments, the first forward current causes both the first magnetic tunnel junction and the second magnetic tunnel junction to be in a first state (low resistance state); the first reverse current causes both the first magnetic tunnel junction and the second magnetic tunnel junction to be in a second state (high resistance state). This does not constitute a limitation of the corresponding resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction by the first forward current, nor does it constitute a limitation of the corresponding resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction by the first reverse current. In other embodiments, based on the operating method provided in the above embodiments, the first forward current can be used to convert both the first magnetic tunnel junction and the second magnetic tunnel junction to a high resistance state; the first reverse current can be used to convert both the first magnetic tunnel junction and the second magnetic tunnel junction to a low resistance state. The corresponding second forward current and second reverse current are adaptively adjusted to obtain new embodiments.

[0072] In some embodiments, the reading step includes: acquiring a first word line, a second word line, a signal line, and a bit line corresponding to the target magnetic memory cell; applying a conduction voltage in the corresponding second word line to turn on the second transistor; determining the resistance value R of the target magnetic memory cell based on the magnitude of the current in the signal line and the bit line, and reading the stored data.

[0073] Specifically, based on the current magnitude in the signal line and bit line, the resistance value R of the target magnetic storage cell is determined, and the stored data is read, including: if the resistance value R of the target magnetic storage cell is R1, then the stored data in the target storage cell is "11"; if the resistance value R of the target magnetic storage cell is R2, then the stored data in the target storage cell is "10"; if the resistance value R of the target magnetic storage cell is R3, then the stored data in the target storage cell is "01"; if the resistance value R of the target magnetic storage cell is R4, then the stored data in the target storage cell is "00"; wherein, the first bit of the stored data represents the stored data of the first magnetic tunnel junction, and the second bit of the stored data represents the stored data of the second magnetic tunnel junction.

[0074] For example, assume the high-resistance resistance of the first magnetic tunnel junction is 20 ohms and the low-resistance resistance is 2 ohms; assume the high-resistance resistance of the second magnetic tunnel junction is 10 ohms and the low-resistance current is 1 ohm. The corresponding relationship between the stored data and the parallel resistance of the first and second magnetic tunnel junctions is as follows: when the stored data is "11", R1 = 6.67 ohms; when the stored data is "10", R2 = 0.95 ohms; when the stored data is "01", R3 = 1.67 ohms; and when the stored data is "00", R4 = 0.667 ohms.

[0075] As can be seen from the above, based on the resistance state and corresponding resistance of the first magnetic tunnel junction and the resistance state and corresponding resistance of the second magnetic tunnel junction, the resistance value of the parallel resistance of the first magnetic tunnel junction and the second magnetic tunnel junction can be obtained. Then, based on the resistance value of the parallel resistance, the stored data in the magnetic storage cell can be determined.

[0076] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A storage array structure, characterized in that, include: Multiple magnetic storage cells, each of the magnetic storage cells comprising: A first transistor and a second transistor, the first transistor having a first source-drain and a second source-drain, the second transistor having a third source-drain and a fourth source-drain, and the second source-drain and the third source-drain being connected to a signal line, the gate of the first transistor being connected to a first word line, and the gate of the second transistor being connected to a second word line; A first magnetic tunnel junction and a second magnetic tunnel junction, one end of the first magnetic tunnel junction and one end of the second magnetic tunnel junction are electrically connected to the fourth source and drain via a transmission line. The other ends of the first magnetic tunnel junction and the second magnetic tunnel junction are in contact with a spin-orbit coupling layer. The spin-orbit coupling layer is located on the side of the first magnetic tunnel junction and the second magnetic tunnel junction away from the transmission line. The spin-orbit coupling layer is electrically connected to the first source and drain and the bit line. The diameter of the first magnetic tunnel junction is larger than the diameter of the second magnetic tunnel junction. The spin-orbit coupling layer is a rectangular structure with a uniform linewidth.

2. The storage array structure according to claim 1, characterized in that, Along a direction away from the spin-orbit coupling layer, the first magnetic tunnel junction sequentially includes a first free layer, a first tunneling layer, and a first fixed layer, with the first free layer located on the surface of the spin-orbit coupling layer; the second magnetic tunnel junction sequentially includes a second free layer, a second tunneling layer, and a second fixed layer, with the second free layer located on the surface of the spin-orbit coupling layer, wherein the magnetization direction in the first fixed layer is the same as the magnetization direction in the second fixed layer.

3. The storage array structure according to claim 2, characterized in that, The contact point between the spin-orbit coupling layer and the first free layer is located between the first connection point and the second connection point, and the contact point between the spin-orbit coupling layer and the second free layer is located between the first connection point and the second connection point; the first connection point is the connection point between the first source / drain electrode and the spin-orbit coupling layer, and the second connection point is the connection point between the bit line and the spin-orbit coupling layer.

4. The storage array structure according to claim 1, characterized in that, The first transistor and the second transistor are formed on a substrate, and the gate of the first transistor is located within the substrate, and the gate of the second transistor is located within the substrate.

5. The storage array structure according to claim 1, characterized in that, The diameter of the second magnetic tunnel junction is 50% to 70% of the diameter of the first magnetic tunnel junction.

6. The storage array structure according to claim 1, characterized in that, include: Along the first direction, the gates of the first transistors in the plurality of magnetic memory cells are connected to the same first word line, and the gates of the second transistors in the plurality of magnetic memory cells are connected to the same second word line; Along the second direction, multiple magnetic storage cells are connected to the same signal line; Along a third direction, a plurality of magnetic storage cells are connected to the same bit line, wherein the first direction is not parallel to the third direction.

7. The storage array structure according to claim 6, characterized in that, The multiple magnetic storage cells are arranged in a parallelogram array.

8. The storage array structure according to claim 7, characterized in that, One side of the parallelogram is disposed in the first direction, and the other side of the parallelogram is disposed in the fourth direction, wherein the fourth direction is the extension direction of the spin-orbit coupling layer.

9. The storage array structure according to claim 8, characterized in that, The second direction is the same as the first direction.

10. The storage array structure according to claim 8, characterized in that, The second direction is perpendicular to the fourth direction.

11. The storage array structure according to claim 8, characterized in that, The second direction is the same as the fourth direction.

12. The storage array structure according to any one of claims 9 to 11, characterized in that, The third direction is the same as the fourth direction.

13. The storage array structure according to claim 10 or 11, characterized in that, The third direction is the same as the second direction.

14. The storage array structure according to claim 6, characterized in that, The multiple magnetic storage units are arranged in a rectangular array.

15. The storage array structure according to claim 1, characterized in that, The signal lines of all the magnetic storage cells are connected.

16. A memory, wherein the array structure of the memory is configured based on the memory array structure according to any one of claims 1 to 15.

17. A memory operation method, comprising a write step and a read step, applied to the memory of claim 16.

18. The memory operation method according to claim 17, characterized in that, The writing step includes: Obtain the first word line, the second word line, the signal line, and the bit line corresponding to the target magnetic storage cell; A conduction voltage is applied to the corresponding first word line to turn on the first transistor; A first positive current is passed through the signal line and the bit line, the magnitude of the first positive current being greater than a first preset value, so that both the first magnetic tunnel junction and the second magnetic tunnel junction are in a first state; Alternatively, a first reverse current is introduced into the signal line and the bit line, the magnitude of the first reverse current being greater than the first preset value, so that both the first magnetic tunnel junction and the second magnetic tunnel junction are in the second state, wherein the current direction of the first forward current is opposite to the current direction of the first reverse current.

19. The memory operation method according to claim 18, characterized in that, The writing step further includes: If both the first magnetic tunnel junction and the second magnetic tunnel junction are in the first state, the first forward current is changed to the second reverse current. The second reverse current is opposite in direction to the first forward current. The magnitude of the second reverse current is greater than a second preset value and less than the first preset value, so that the first magnetic tunnel junction remains in the first state and the second magnetic tunnel junction is in the second state. If both the first magnetic tunnel junction and the second magnetic tunnel junction are in the second state, the first reverse current is changed to a second forward current. The direction of the second forward current is opposite to that of the first reverse current. The magnitude of the second forward current is greater than the second preset value and less than the first preset value, so that the first magnetic tunnel junction remains in the second state and the second magnetic tunnel junction is in the first state.

20. The memory operation method according to claim 17, characterized in that, The reading step includes: Obtain the first word line, the second word line, the signal line, and the bit line corresponding to the target magnetic storage cell; A conduction voltage is applied to the corresponding second word line to turn on the second transistor; Based on the magnitude of the current in the signal line and the bit line, the resistance R of the target magnetic storage cell is determined, and the stored data is read.

21. The memory operation method according to claim 20, characterized in that, The step of determining the resistance R of the target magnetic storage cell based on the current magnitude in the signal line and the bit line, and then reading the stored data, includes: If the resistance of the target magnetic storage cell is R=R1, then the stored data in the target magnetic storage cell is "11". If the resistance of the target magnetic storage cell is R=R2, then the stored data in the target magnetic storage cell is "10"; If the resistance of the target magnetic storage cell is R=R3, then the stored data in the target magnetic storage cell is "01"; If the resistance of the target magnetic storage cell is R=R4, then the stored data in the target magnetic storage cell is "00". Wherein, the first bit of the stored data represents the stored data of the first magnetic tunnel junction, and the second bit of the stored data represents the stored data of the second magnetic tunnel junction.

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