Enhanced radio frequency device based on p-gan cap layer and fin structure and method of manufacturing the same
By employing a P-GaN cap layer and Fin structure in RF devices, combined with a high-aluminum composition barrier layer and a floating T-type gate electrode, the problems of device size and etching damage were solved, resulting in higher gate control capability and output power, and improved channel electronic performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2022-07-01
- Publication Date
- 2026-07-03
AI Technical Summary
The large size of existing RF devices, both horizontally and vertically, leads to increased channel resistance, increased gate-to-channel distance, decreased gate control capability, and reduced transconductance. At the same time, etching the P-GaN cap layer is prone to damage and defects, Mg doping is not easily activated, and the manufacturing process is difficult.
A P-GaN cap layer and Fin structure are adopted, and the barrier layer is made of a high aluminum composition material. After etching, a floating T-type gate electrode and Fin structure are formed, which reduces the distance between the gate and the channel, increases the gate control capability, and reduces etching damage by regrowing the P-GaN cap layer.
It improves the device's operating frequency and output power, reduces etching damage, improves interface states, enhances the gate's control over the channel, and increases transconductance and breakdown voltage.
Smart Images
Figure CN115274851B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device technology, specifically relating to an enhancement-enhanced radio frequency device based on a P-GaN cap layer and Fin structure and its fabrication method. Background Technology
[0002] Third-generation semiconductor materials possess high critical breakdown field strength, high carrier mobility, wide bandgap, and high saturation carrier velocity, making them widely used in the fabrication of high-frequency, high-temperature, and high-power devices. GaN devices are primarily used in optoelectronics, power electronics, and microwave radio frequency (RF) fields. In optoelectronics, they are mainly used in LEDs, lasers, and detectors; in power electronics, they are mainly used in smart grids, high-speed rail, new energy vehicles, and consumer electronics; and in microwave RF, they are mainly used in 5G communications, satellite communications, and radar early warning systems.
[0003] With the advent of the 5G era, the demands and requirements for the radio frequency (RF) front-end in wireless communication systems are becoming increasingly stringent. Key components of the RF front-end, such as amplifiers, low-noise operational amplifiers, RF switches, and duplexers, are operating at increasingly higher RF power. To enable RF devices to achieve higher operating frequencies, output power, and stability, more precise manufacturing processes are required, and material selection must meet the performance requirements of the RF devices. Due to the need to reduce parasitic effects and on-resistance, the size of RF devices is generally very small. This requires not only reducing the lateral aspect ratio but also further reducing the longitudinal aspect ratio. The longitudinal aspect ratio primarily involves reducing the thickness of the barrier layer, thereby decreasing the gate-to-channel distance, enhancing gate control capability, and increasing transconductance.
[0004] However, this RF device is designed for high-power enhancement, resulting in a relatively large size both laterally and vertically. This presents several drawbacks for RF devices. The larger lateral size increases channel resistance, while the larger vertical size, especially in the barrier and cap layers, increases the gate-to-channel distance, reducing gate control capability and transconductance, which will impact the device's operating frequency. Furthermore, there is the issue of etching the P-GaN cap layer. Because the gate P-GaN cap layer is very short, most of the cap layer material needs to be etched. Etching causes significant damage and defects, leading to interface deterioration and current collapse, which affects electron concentration within the channel, reducing its concentration and even mobility. Finally, there is the problem of high-concentration Mg doping. Mg doping readily forms complexes with H, becoming neutral and difficult to activate. Therefore, high-concentration Mg doping is difficult to achieve, making the manufacturing process challenging. Summary of the Invention
[0005] To address the aforementioned problems in the prior art, this invention provides an enhanced radio frequency device based on a P-GaN cap layer and a Fin structure, and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:
[0006] One aspect of the present invention provides an enhanced radio frequency device based on a P-GaN cap layer and a Fin structure, comprising a substrate, an AlN nucleation layer, a GaN buffer layer, a GaN channel layer, and a barrier layer stacked sequentially from bottom to top, wherein...
[0007] The upper surface of the barrier layer includes a source electrode and a drain electrode on both sides, and the lower surfaces of the source electrode and the drain electrode are in contact with the upper surface of the GaN buffer layer, respectively.
[0008] The upper surface of the barrier layer and the upper surfaces of the source electrode and the drain electrode include a SiN passivation layer. A gate foot region groove is formed on the SiN passivation layer, penetrating the front and back of the SiN passivation layer and extending to the upper surface of the barrier layer. A P-GaN cap layer is provided on the gate foot region groove and the upper surface of the SiN passivation layer.
[0009] The P-GaN cap layer is provided with a Fin structure, which includes a plurality of parallel grooves that extend downward into the GaN buffer layer.
[0010] A floating T-shaped gate electrode is formed inside the groove of the gate foot area and on the upper surface of the Fin structure; a metal interconnect layer is respectively provided above the source electrode and the drain electrode, and the lower end of the metal interconnect layer is in contact with the source electrode and the drain electrode.
[0011] In one embodiment of the present invention, an electrically isolated mesa is provided on the outer side of the source electrode and the drain electrode, and the electrically isolated mesa extends downward to the GaN buffer layer.
[0012] In one embodiment of the present invention, the plurality of grooves of the Fin structure are parallel to each other and perpendicular to the groove of the gate foot region, and one side of each groove extends to the inner surface of the source electrode and the other side extends to the inner surface of the drain electrode.
[0013] In one embodiment of the present invention, the width of each groove of the Fin structure is 1.5um to 2.5um, and the depth is the sum of the thicknesses of the GaN buffer layer, the GaN channel layer, the barrier layer, the SiN passivation layer, and the P-GaN cap layer after etching.
[0014] In one embodiment of the present invention, the barrier layer is made of a high-aluminum material with an aluminum content of 0.8 to 1%.
[0015] In one embodiment of the present invention, the floating T-shaped gate electrode includes a vertical portion and a horizontal portion suspended above the vertical portion. The vertical portion fills the groove of the gate foot region and the tooth groove of the Fin structure along the front-back extension direction of the groove of the gate foot region.
[0016] Another aspect of the present invention provides a method for fabricating an enhancement-mode radio frequency device based on a P-GaN cap layer and a Fin structure, used to fabricate the enhancement-mode radio frequency device based on a P-GaN cap layer and a Fin structure as described in any of the above embodiments, the fabrication method comprising:
[0017] S1: Obtain an epitaxial substrate consisting of a substrate, an AlN nucleation layer, a GaN buffer layer, a GaN channel layer, and a barrier layer, from bottom to top.
[0018] S2: Source electrodes and drain electrodes are fabricated on both sides of the upper surface of the barrier layer;
[0019] S3: Photolithography and etching of the active region's electrical isolation mesa on both sides of the source electrode and the drain electrode, the electrical isolation mesa extending downward into the interior of the GaN buffer layer;
[0020] S4: A SiN passivation layer is deposited on the upper surface of the barrier layer and on the upper surfaces of the source and drain electrodes;
[0021] S5: A gate foot region groove is formed on the SiN passivation layer, and a P-GaN cap layer is deposited on the upper surface of the SiN passivation layer and in the gate foot region groove;
[0022] S6: Etching a Fin structure onto the P-GaN cap layer;
[0023] S7: A floating T-shaped gate electrode is formed inside the groove in the gate foot area and on the upper surface of the Fin structure;
[0024] S8: Metal interconnect holes are etched above the source electrode and the drain electrode, and a metal interconnect layer is formed in the metal interconnect opening area.
[0025] In one embodiment of the present invention, S5 includes:
[0026] S5.1: Photolithographically pattern the gate pin area on the SiN passivation layer;
[0027] S5.2: The SiN passivation layer material in the gate foot area pattern region is removed by etching using the ICP process to form a gate foot area groove that runs through the front and back of the SiN passivation layer, and the gate foot area groove extends downward to the upper surface of the barrier layer.
[0028] In one embodiment of the present invention, S6 includes:
[0029] S6.1: Photolithography is performed on the P-GaN cap layer to form multiple comb groove patterns of the Fin structure. The multiple comb groove patterns are parallel to each other and are all perpendicular to the groove of the gate foot region.
[0030] S6.2: The P-GaN cap layer in the Fin structure groove pattern region is removed by chlorine-based etching using ICP etching, and the SiN passivation layer in the Fin structure groove pattern region is removed by fluorine-based etching. Finally, the barrier layer, GaN channel layer and GaN buffer layer in the Fin structure groove pattern region are removed by chlorine-based etching. The GaN buffer layer is etched downwards to remove 20nm to 30nm, thereby forming multiple parallel grooves that extend downwards into the interior of the GaN buffer layer.
[0031] In one embodiment of the present invention, S7 includes:
[0032] S7.1: Photolithographically etch the region of the floating T-shaped gate electrode on the P-GaN cap layer;
[0033] S7.2: The floating T-shaped gate electrode is formed by depositing metal using electron beam evaporation.
[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0035] 1. The enhancement-mode radio frequency device based on P-GaN cap layer and Fin structure of the present invention uses AlN, a material with high aluminum content, as the barrier layer. When its thickness is 3nm to 5nm, the two-dimensional electron gas concentration can reach 10. 13 cm -3 Secondly, the thinner barrier layer shortens the distance from the gate to the GaN channel layer, thereby increasing gate control capability; the main doping concentration of the P-GaN cap layer in this invention is 10. 15 cm -3 The thickness is 5–10 nm. On the one hand, this reduces the technical problems associated with heavy Mg doping. On the other hand, the reduction in the P-GaN cap layer also reduces the distance between the gate and the channel.
[0036] 2. The enhancement-mode RF device based on a P-GaN cap layer and a Fin structure of the present invention incorporates a Fin structure on the P-GaN cap layer and the SiN passivation layer, with etching depth extending into the GaN buffer layer. On one hand, the introduction of the side gate releases some stress in the barrier layer, reducing piezoelectric polarization and further depleting the two-dimensional electron gas under the gate, resulting in a positive threshold voltage. Simultaneously, it avoids the problem of excessive consumption of the two-dimensional electron gas in the channel, which could lead to significant output current attenuation. On the other hand, the three-dimensional gate structure increases the gate's control over the channel, improving transconductance. Furthermore, the side gate modulates the electric field near the drain gate corner, thereby increasing the device's breakdown voltage.
[0037] 3. The enhancement-mode RF device based on the P-GaN cap layer and Fin structure of the present invention utilizes the regrown P-GaN cap layer. When the epitaxial substrate contains a P-GaN cap layer, it is necessary to remove the P-GaN cap layer outside the gate pin region on the barrier layer surface using inductively coupled plasma etching (ICP). This method will cause severe damage to the barrier layer surface. Secondly, in the present invention, the barrier layer is relatively thin, and the allowable error during etching is very small, which can easily cause the RF characteristics of the device to deteriorate. Therefore, the present invention first passivates, then etches the gate pin region, and finally deposits the P-GaN cap layer and gate metal.
[0038] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0039] Figure 1 This is a schematic diagram of an enhanced radio frequency device based on a P-GaN cap layer and Fin structure provided in an embodiment of the present invention;
[0040] Figure 2 This is a top view schematic diagram of an enhanced radio frequency device based on a P-GaN cap layer and Fin structure provided in an embodiment of the present invention;
[0041] Figure 3a It is along Figure 1 A schematic diagram of the cross-section taken by line AA in the diagram;
[0042] Figure 3b It is along Figure 1 A schematic diagram of the cross-section taken by the BB line in the diagram;
[0043] Figure 4 This is a flowchart illustrating a method for fabricating an enhanced radio frequency device based on a P-GaN cap layer and Fin structure, as provided in an embodiment of the present invention.
[0044] Figures 5a to 5j This is a schematic diagram illustrating the fabrication process of an enhanced radio frequency device based on a P-GaN cap layer and Fin structure, provided by an embodiment of the present invention. Detailed Implementation
[0045] To further illustrate the technical means and advantages of this invention in achieving its intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a detailed explanation of the enhanced radio frequency device based on a P-GaN cap layer and Fin structure and its fabrication method according to this invention.
[0046] The foregoing and other technical contents, features, and advantages of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and advantages adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.
[0047] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.
[0048] Example 1
[0049] This embodiment provides an enhanced radio frequency device based on a P-GaN cap layer and a Fin structure. Please refer to [link to relevant documentation]. Figures 1 to 4 The enhancement device of this embodiment includes a substrate 1, an AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 4, and a barrier layer 5 stacked sequentially from bottom to top. A source electrode 9 and a drain electrode 10 are provided on both sides of the upper surface of the barrier layer 5, and the lower surfaces of the source electrode 9 and the drain electrode 10 are in contact with the upper surface of the GaN buffer layer 3, respectively. A SiN passivation layer 8 is provided on the upper surface of the barrier layer 5 and the upper surfaces of the source electrode 9 and the drain electrode 10. An upper passivation layer is formed on the SiN passivation layer 8, penetrating from front to back and extending to the upper surface of the barrier layer 5. A gate foot region groove 14 is formed on the surface. A P-GaN cap layer 6 is provided inside the gate foot region groove 14 and on the upper surface of the SiN passivation layer 8. A Fin structure 7 is provided on the P-GaN cap layer 6. The Fin structure 7 includes multiple parallel grooves 7-1 that extend downward into the GaN buffer layer 3. A floating T-shaped gate electrode 11 is formed inside the gate foot region groove 14 and on the upper surface of the Fin structure 7. A metal interconnect layer 13 is provided above the source electrode 9 and the drain electrode 10, respectively. The lower end of the metal interconnect layer 13 is in contact with the source electrode 9 or the drain electrode 10.
[0050] In this embodiment, substrate 1 is a SiC substrate. The barrier layer 5 is made of a high-aluminum composition material with an aluminum content of 0.8-1, such as scandium aluminum nitrogen (ScAlN), indium aluminum nitrogen (InAlN), and aluminum nitrogen (AlN). This invention takes AlN material as an example, and its thickness is 3 nm.
[0051] In this embodiment, an electrical isolation mesa 15 is included on the outer side of the source electrode 9 and the drain electrode 10, and the electrical isolation mesa 15 extends downward to the GaN buffer layer 3.
[0052] Furthermore, the grooves 7-1 of the Fin structure 7 are parallel to each other and perpendicular to the gate foot region groove 14, and one side of each groove 7-1 extends to the inner surface of the source electrode 9, and the other side extends to the inner surface of the drain electrode 10. The width of each groove 7-1 of the Fin structure 7 is 1.5um to 2.5um, the length is the distance between the source electrode 9 and the drain electrode 10, and the depth is the sum of the thicknesses of the etched and removed GaN buffer layer 3, GaN channel layer 4, barrier layer 5, SiN passivation layer 8, and P-GaN cap layer 6.
[0053] Furthermore, the floating T-shaped gate electrode 11 includes a vertical portion and a horizontal portion suspended above the vertical portion. The vertical portion fills the gate foot region groove 14 and the tooth groove 7-1 of the Fin structure 7 along the extending direction of the gate foot region groove 14. In this embodiment, the doping concentration of the P-GaN cap layer is 10. 15 cm -3 The thickness is 5-10 nm.
[0054] This invention provides a Fin structure, such as the fin structure of a semiconductor device like a FinFET (Fin Field-Effect Transistor). The transistor's shape resembles a fish fin, and the length of the fin along the source and drain directions constitutes the channel length. Because the P-GaN cap layer 6 in this embodiment is relatively thin, the HEMT device cannot achieve enhancement mode. Therefore, based on this device structure, a Fin structure 7 is etched, extending to the interior of the GaN buffer layer 3. On one hand, the introduction of the side gate releases some stress in the barrier layer 5, reducing piezoelectric polarization and further depleting the concentration of the two-dimensional electron gas under the gate, resulting in a positive threshold voltage. Simultaneously, it avoids the problem of excessive consumption of the two-dimensional electron gas in the channel, leading to a significant decrease in output current. On the other hand, the three-dimensional gate structure increases the gate's control over the channel, improving transconductance. Furthermore, the side gate modulates the electric field near the drain gate corner, thereby increasing the device's breakdown voltage.
[0055] In this embodiment, the enhanced radio frequency device based on the P-GaN cap layer and Fin structure uses a high-aluminum material as the barrier layer 5. When its thickness is 3nm to 5nm, the two-dimensional electron gas concentration can reach 10. 13 cm -3 Secondly, the thinner barrier layer shortens the distance from the gate to the GaN channel layer, thereby increasing gate control capability; the main doping concentration of the P-GaN cap layer in this invention is 10. 15 cm -3The thickness is 5–10 nm. On the one hand, this reduces the technical problems associated with heavy Mg doping. On the other hand, the reduction in the P-GaN cap layer also reduces the distance between the gate and the channel. Furthermore, the use of metal-organic chemical vapor deposition (MOCVD) to grow the P-GaN cap layer material reduces the damage to the device surface barrier layer caused by etching, improves the interface states, and reduces the impact on the two-dimensional electron gas in the channel.
[0056] Example 2
[0057] Based on the above embodiments, this embodiment provides a method for fabricating an enhanced radio frequency device based on a P-GaN cap layer and a Fin structure. Please refer to [link to relevant documentation]. Figure 4 and Figures 5a to 5j The preparation method of this embodiment includes:
[0058] S1: Obtain an epitaxial substrate consisting of, from bottom to top, substrate 1, AlN nucleation layer 2, GaN buffer layer 3, GaN channel layer 4, and barrier layer 5, such as Figure 5a As shown.
[0059] In this embodiment, an epitaxial substrate with a pre-formed substrate 1, AlN nucleation layer 2, GaN buffer layer 3, GaN channel layer 4, and barrier layer 5 is selected. In this embodiment, the thicknesses of substrate 1, AlN nucleation layer 2, and GaN buffer layer 3 are all 0.5 μm to 3 μm, and substrate 1 is a SiC substrate. The thickness of GaN channel layer 4 is 100 nm. The barrier layer 5 is made of AlN material and has a thickness of 3 nm to 5 nm.
[0060] S2: Source electrode 9 and drain electrode 10 are fabricated on both sides of the upper surface of barrier layer 5, as follows: Figure 5b As shown.
[0061] Specifically, the epitaxial substrate is placed on a hot plate for baking; a release agent is applied and spun onto the barrier layer 5, and the epitaxial substrate sample is placed on a hot plate for baking; a photoresist is applied and spun onto the release agent, and the epitaxial substrate sample is placed on a hot plate for baking; the coated and spun epitaxial substrate sample is placed in a photolithography machine to expose the coated surface, and the exposed epitaxial substrate sample is placed in a developing solution to remove the photoresist and release agent. After rinsing with ultrapure water and blowing with nitrogen, photolithographic patterns of the source electrode region and the drain electrode region are formed.
[0062] Subsequently, metal is evaporated on the barrier layer 5 within the photolithographic pattern of the source electrode region and the photolithographic pattern of the drain electrode region, as well as on the photoresist outside the source electrode and drain electrode regions, to form the source electrode 9 and the drain electrode 10.
[0063] Specifically, the sample, including the photolithographic patterns of the source and drain electrodes, is placed in a plasma resist remover for bottom film treatment; the sample is then placed in an electron beam evaporation stage, and the vacuum level in the reaction chamber of the electron beam evaporation stage reaches 2 × 10⁻⁶. -6 After Torr, ohmic metal is evaporated on the barrier layer 5 in the source and drain electrode regions and on the photoresist outside the source and drain electrode regions to form source electrode 9 and drain electrode 10. The ohmic metal is a metal stack structure composed of four metal layers Ti, Al, Ni and Au from bottom to top. Then, the sample after ohmic metal evaporation is stripped to remove the ohmic metal, photoresist and release adhesive outside the source and drain electrode regions. The sample is then rinsed with ultrapure water and dried with nitrogen. The sample after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing to form ohmic contact between source electrode 9 and drain electrode 10 and GaN channel layer 4, and then annealing is performed.
[0064] S3: Photolithographically etch and etch the electrically isolated mesa 15 of the active region on both sides of the source electrode 9 and the drain electrode 10. The electrically isolated mesa 15 extends downward into the interior of the GaN buffer layer 3, such as... Figure 5c As shown.
[0065] In this embodiment, step S3 specifically includes:
[0066] S3.1: Photolithographically etched electrical isolation regions on both sides of the source electrode 9 and the drain electrode 10.
[0067] Specifically, the epitaxial substrate sample is baked on a hot plate; photoresist is applied and spun off, and the sample is baked on a hot plate; the sample is placed in a photolithography machine to expose the photoresist in the electrically isolated areas on both sides of the source electrode 9 and the drain electrode 10; the exposed sample is then placed in a developing solution to remove the photoresist in the electrically isolated areas, and then rinsed with ultrapure water and dried with nitrogen.
[0068] S3.2: Etch the electrically isolated mesa 15 on both sides of the source electrode 9 and the drain electrode 10.
[0069] Specifically, the barrier layer 5, GaN channel layer 4 and GaN buffer layer 3 of the electrically isolated region are sequentially etched using inductively coupled plasma (ICP) technology, and electrically isolated mesa 15 extending to the GaN buffer layer 3 are formed on both sides of the source electrode 9 and the drain electrode 10, thereby achieving mesa isolation of the active region.
[0070] S4: A SiN passivation layer 8 is deposited on the upper surface of the barrier layer 5 and on the upper surfaces of the source electrode 9 and the drain electrode 10, such as... Figure 5d As shown.
[0071] Specifically, a SiN passivation layer 8 with a thickness of 50 nm is grown on the source electrode 9, drain electrode 10 and the upper surface of barrier layer 5 using plasma-enhanced chemical vapor deposition (PECVD).
[0072] S5: A gate foot region groove 14 is formed on the SiN passivation layer 8, and a P-GaN cap layer 6 is deposited on the upper surface of the SiN passivation layer 8 and in the gate foot region groove 14.
[0073] In this embodiment, step S5 includes:
[0074] S5.1: Photolithographic patterning of the gate pin area on SiN passivation layer 8.
[0075] Specifically, the sample is baked on a hot plate; photoresist is applied and spun off, and the sample is baked on a hot plate; the sample is placed in a photolithography machine to expose the photoresist in the gate pin area between the source electrode 9 and the drain electrode 10; the exposed sample is placed in a developing solution to remove the photoresist in the gate pin area, and then rinsed with ultrapure water and dried with nitrogen.
[0076] S5.2: Etch the SiN passivation layer 8 on the SiN passivation layer 8 to remove the SiN passivation layer 8 within the gate pin area pattern to form a gate pin area groove 14.
[0077] The cleaned sample is then etched using an ICP process to remove the SiN passivation layer 8 material from the gate pin area pattern, forming a gate pin area groove 14, as shown. Figure 5e As shown. The groove 14 extends downward to the upper surface of the barrier layer 5, with an etching depth of 50 nm. After etching, the sample is sequentially placed in acetone solution, stripping solution, acetone solution and isopropanol solution for cleaning.
[0078] S5.3: A P-GaN cap layer 6 is deposited on the upper surface of the SiN passivation layer 8 and within the gate pin region groove 14, as shown below. Figure 5f As shown.
[0079] Specifically, a 5 nm thick P-GaN cap layer 6 is grown in the groove 14 of the gate foot region using a metal-organic chemical vapor deposition (MOCVD) process.
[0080] S6: Fin structure 7 is formed by etching on the P-GaN cap layer 6, such as Figure 5g As shown, Figure 5g It is a top view that can display Fin structure 7.
[0081] In this embodiment, step S6 includes:
[0082] S6.1: Photolithography is performed on the P-GaN cap layer 6 to form the comb pattern of the Fin structure 7.
[0083] Specifically, the sample processed in the previous step is placed on a hot plate for baking; photoresist is applied and spun off, and the sample is placed on a hot plate for baking; the sample is placed in a photolithography machine to expose the photoresist of Fin structure 7; the exposed sample is placed in a developing solution to remove the photoresist in the Fin groove, and then rinsed with ultrapure water and dried with nitrogen.
[0084] S6.2: Etching is performed on the P-GaN cap layer 6 to form the Fin structure 7.
[0085] The P-GaN cap layer 6 of the Fin structure 7 is removed using ICP etching with chlorine-based etching. Then, the SiN passivation layer 8 is removed using fluorine-based etching. Finally, the barrier layer 5, GaN channel layer 4, and the interior of the GaN buffer layer 3 are removed using chlorine-based etching, with the GaN buffer layer 3 being etched downwards by 20nm to 30nm. The SiN passivation layer 8 is etched to a depth of 50nm. The P-GaN cap layer 6, barrier layer 5, GaN channel layer 4, and GaN buffer layer 3 undergo a second etching process. The first chlorine-based etching depth is 5nm, and the second chlorine-based etching depth is 3nm. Each groove 7-1 in the Fin structure 7 has a width of 2µm, a length equal to the distance between the source electrode 9 and the drain electrode 10, and a depth equal to the sum of the thicknesses of the removed GaN buffer layer 3, GaN channel layer 4, barrier layer 5, SiN passivation layer 8, and P-GaN cap layer 6.
[0086] S7: A floating T-shaped gate electrode 11 is formed inside the groove 14 in the gate foot region and on the upper surface of the Fin structure 7, such as Figure 5h As shown.
[0087] In this embodiment, step S7 includes:
[0088] S7.1: The region of the floating T-shaped gate electrode is photolithographically etched on the P-GaN cap layer 6.
[0089] Specifically, the sample processed in the previous step is placed on a hot plate for baking; a first layer of photoresist is applied to the sample until the first photoresist completely covers the upper surface of the Fin structure 7; a second layer of photoresist is then applied to the sample so that the second layer of photoresist completely covers the first layer of photoresist; the sample after photoresist application is subjected to a second exposure; the exposed sample is placed in a developing solution to remove the photoresist in the T-gate region, and then rinsed with ultrapure water and dried with nitrogen.
[0090] S7.2: Using electron beam evaporation, metal is deposited to form a floating T-shaped gate electrode 11.
[0091] Specifically, the sample with photolithographic patterns on the gate electrode region is placed in a plasma resist remover for underfilm treatment; the cleaned sample is then placed in an electron beam evaporation stage, and the vacuum level in the reaction chamber of the electron beam evaporation stage reaches 2×10⁻⁶.-6 After Torr, gate metal is evaporated on the photoresist within and outside the gate electrode region. The gate metal is a metal stack structure consisting of two layers of metal, Ni and Au, arranged sequentially from bottom to top. Next, the sample after the gate metal evaporation is completed is stripped to remove the gate metal, photoresist, and stripping adhesive outside the gate electrode region. The sample is then rinsed with ultrapure water and dried with nitrogen to form gate electrode 11.
[0092] S8: Metal interconnect vias 12 are etched above the source electrode 9 and the drain electrode 10, and a metal interconnect layer 13 is formed in the metal interconnect opening area 12.
[0093] Specifically, the sample processed in the previous step is baked on a hot plate; photoresist is applied and spun off, and the sample is baked on a hot plate again; the sample is placed in a photolithography machine to expose the photoresist in the metal interconnect layer opening area; the exposed sample is placed in a developer to remove the photoresist in the interconnect opening area, and then rinsed with ultrapure water and dried with nitrogen; first, the P-GaN cap layer 6 is removed using ICP etching with chlorine-based etching to a depth of 5nm; then, the SiN passivation layer 8 is removed using ICP etching with fluorine-based etching, removing the 50nm thick SiN passivation layer 8 in the interconnect opening area, as shown below. Figure 5i As shown.
[0094] Next, the sample with completed metal interconnect via etching is placed on a hot plate for baking; release adhesive is applied and spun onto the source electrode 9 and drain electrode 10 of the metal interconnect via region 13 and the unetched P-GaN cap layer 6, and the sample is placed on a hot plate for baking; photoresist is applied and spun onto the release adhesive, and the sample is placed on a hot plate for baking; the sample with completed coating and spun is placed in a photolithography machine to expose the photoresist in the metal interconnect region, and then the exposed sample is placed in a developer to remove the photoresist and release adhesive in the metal interconnect region, and then rinsed with ultrapure water and dried with nitrogen; the metal interconnect layer 13 is evaporated on the electrodes and P-GaN cap layer 6 in the metal interconnect region and on the photoresist outside the metal interconnect region.
[0095] The sample with metal interconnect regions was placed in a plasma stripper for bottom film treatment; the sample was then placed in an electron beam evaporation stage, and the vacuum level in the reaction chamber of the electron beam evaporation stage was increased to 2 × 10⁻⁶. -6 Following the Torr process, interconnect metal is evaporated onto the electrodes and P-GaN cap layer 6 within the metal interconnect region, as well as onto the photoresist outside the metal interconnect region, forming a metal interconnect layer 13. This metal interconnect layer 13 is a metal stack structure consisting of two layers, Ti and Au, arranged sequentially from bottom to top, to lead out the electrodes. The sample after interconnect metal evaporation is then stripped to remove the metal, photoresist, and release adhesive outside the metal interconnect layer 13. The sample is then rinsed with ultrapure water and dried with nitrogen gas to complete the device fabrication. Figure 5j As shown. At this point, the process flow for the enhanced RF device based on the P-GaN cap layer and Fin structure in this embodiment has been completed.
[0096] The enhancement-mode RF device based on P-GaN cap layer and Fin structure prepared by the method of the present invention can achieve enhancement mode, and the device has a large transconductance and improved interface states, which reduces the impact on channel carrier concentration and mobility, thereby resulting in a larger output current, weakened current collapse effect, and better RF characteristics of the device.
[0097] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. An enhanced radio frequency device based on a P-GaN cap layer and a Fin structure, characterized in that, The structure includes, from bottom to top, a substrate (1), an AlN nucleation layer (2), a GaN buffer layer (3), a GaN channel layer (4), a barrier layer (5), and a P-GaN cap layer (6), which are stacked sequentially. The upper surface of the barrier layer (5) includes a source electrode (9) and a drain electrode (10) on both sides, and the lower surfaces of the source electrode (9) and the drain electrode (10) are in contact with the upper surface of the GaN buffer layer (3), respectively. The upper surface of the barrier layer (5) and the upper surfaces of the source electrode (9) and the drain electrode (10) include a SiN passivation layer (8), and a gate foot region groove (14) is formed on the SiN passivation layer (8) that penetrates the front and back of the SiN passivation layer (8) and extends to the upper surface of the barrier layer (5). The P-GaN cap layer (6) includes a first part and a second part. The first part is disposed inside the gate foot region groove (14) and is in contact with the upper surface of the barrier layer (5). The second part is disposed on the upper surface of the SiN passivation layer (8). The orthographic projection of the second part on the substrate (1) coincides with the orthographic projection of the SiN passivation layer (8) on the substrate (1). The P-GaN cap layer (6) is provided with a Fin structure (7), and the Fin structure (7) includes a plurality of parallel grooves (7-1) extending downward into the GaN buffer layer (3); A floating T-shaped gate electrode (11) is formed inside the groove (14) of the gate foot area and on the upper surface of the Fin structure (7); A metal interconnect layer (13) is provided above the source electrode (9) and the drain electrode (10), respectively, and the lower end of the metal interconnect layer (13) is in contact with the source electrode (9) or the drain electrode (10).
2. The enhanced RF device based on a P-GaN cap layer and Fin structure according to claim 1, characterized in that, An electrically isolated mesa (15) is provided on the outer side of the source electrode (9) and the drain electrode (10), respectively, and the electrically isolated mesa (15) extends downward to the GaN buffer layer (3).
3. The enhanced radio frequency device based on a P-GaN cap layer and Fin structure according to claim 1, characterized in that, The multiple grooves (7-1) of the Fin structure (7) are parallel to each other and perpendicular to the groove (14) of the gate foot area. One side of each groove (7-1) extends to the inner surface of the source electrode (9) and the other side extends to the inner surface of the drain electrode (10).
4. The enhanced radio frequency device based on a P-GaN cap layer and Fin structure according to claim 1, characterized in that, The width of each groove (7-1) of the Fin structure (7) is 1.5um to 2.5um, and the depth is the sum of the thicknesses of the GaN buffer layer (3), the GaN channel layer (4), the barrier layer (5), the SiN passivation layer (8), and the P-GaN cap layer (6) after etching.
5. The enhanced RF device based on a P-GaN cap layer and Fin structure according to claim 1, characterized in that, The barrier layer (5) is made of a high-aluminum material with an aluminum content of 0.8-1%.
6. The enhanced radio frequency device based on a P-GaN cap layer and Fin structure according to claim 1, characterized in that, The floating T-shaped gate electrode (11) includes a vertical part and a horizontal part suspended above the vertical part. The vertical part fills the groove (14) of the gate foot area and the tooth groove (7-1) of the Fin structure (7) along the front and rear extension direction of the groove (14).
7. A method for fabricating an enhancement-mode radio frequency device based on a P-GaN cap layer and a Fin structure, characterized in that, The method for fabricating an enhanced radio frequency device based on a P-GaN cap layer and a Fin structure as described in any one of claims 1 to 6 comprises: S1: Obtain an epitaxial substrate consisting of a substrate, an AlN nucleation layer, a GaN buffer layer, a GaN channel layer, and a barrier layer, from bottom to top. S2: Source electrodes and drain electrodes are fabricated on both sides of the upper surface of the barrier layer; S3: Photolithography and etching of the active region's electrical isolation mesa on both sides of the source electrode and the drain electrode, the electrical isolation mesa extending downward into the interior of the GaN buffer layer; S4: A SiN passivation layer is deposited on the upper surface of the barrier layer and on the upper surfaces of the source electrode and the drain electrode; S5: A gate foot region groove is formed on the SiN passivation layer, and a P-GaN cap layer is deposited on the upper surface of the SiN passivation layer and in the gate foot region groove; S6: A Fin structure is formed by etching on the P-GaN cap layer; the P-GaN cap layer (6) includes a first part and a second part, the first part is disposed inside the gate foot region groove (14) and is in contact with the upper surface of the barrier layer (5); the second part is disposed on the upper surface of the SiN passivation layer (8), and the orthographic projection of the second part on the substrate (1) coincides with the orthographic projection of the SiN passivation layer (8) on the substrate (1); S7: A floating T-shaped gate electrode is formed inside the groove in the gate foot area and on the upper surface of the Fin structure; S8: Metal interconnect holes are etched above the source electrode and the drain electrode, and a metal interconnect layer is formed in the metal interconnect opening area.
8. The method for fabricating an enhanced radio frequency device based on a P-GaN cap layer and Fin structure according to claim 7, characterized in that, S5 includes: S5.1: Photolithographically pattern the gate pin area on the SiN passivation layer; S5.2: The SiN passivation layer material in the gate foot area pattern region is removed by etching using the ICP process to form a gate foot area groove that runs through the front and back of the SiN passivation layer, and the gate foot area groove extends downward to the upper surface of the barrier layer.
9. The method for fabricating an enhanced radio frequency device based on a P-GaN cap layer and Fin structure according to claim 7, characterized in that, S6 includes: S6.1: Photolithography is performed on the P-GaN cap layer to form multiple comb groove patterns of the Fin structure. The multiple comb groove patterns are parallel to each other and are all perpendicular to the groove of the gate foot region. S6.2: The P-GaN cap layer in the Fin structure groove pattern region is removed by chlorine-based etching using ICP etching, and the SiN passivation layer in the Fin structure groove pattern region is removed by fluorine-based etching. Finally, the barrier layer, GaN channel layer and part of the GaN buffer layer in the Fin structure groove pattern region are removed by chlorine-based etching. The GaN buffer layer is etched downwards by 20nm~30nm to form multiple parallel grooves that extend downwards into the interior of the GaN buffer layer.
10. The method for fabricating an enhanced radio frequency device based on a P-GaN cap layer and Fin structure according to any one of claims 7 to 9, characterized in that, S7 includes: S7.1: Photolithographically etch the region of the floating T-shaped gate electrode on the P-GaN cap layer; S7.2: The floating T-shaped gate electrode is formed by depositing metal using electron beam evaporation.