Voltage equalization control circuit for flying capacitor

Abstract

This application relates to the field of power electronics technology, and in particular to a voltage equalization control circuit for flying capacitors, comprising: an N-level circuit, a clamping circuit, and a subsequent circuit; the N-level circuit is coupled to the clamping circuit, and both the N-level circuit and the clamping circuit are coupled to the subsequent circuit; the clamping circuit and the subsequent circuit are jointly configured to stabilize the voltages across each stage of the flying capacitors in the N-level circuit; wherein, the number of levels in the multi-level circuit is N, where N is a natural number greater than or equal to 3, and the number of stages of the flying capacitors is (N-2). Achieving voltage equalization of the flying capacitors through the combined action of the subsequent circuit and the clamping circuit, and improving the reliability of the entire system circuit, is a pressing technical problem that needs to be solved in the application of multi-level circuit topologies in the system circuits.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a voltage equalization control circuit for a flying capacitor. Background Technology

[0002] Multilevel topologies can significantly reduce the volt-second product on inductors, thereby reducing inductor size. Therefore, multilevel topologies are widely used in power supply circuits. However, in the application of multilevel topologies, it is necessary to control the voltage equalization of the flying capacitors. If the voltage equalization effect of the flying capacitors is not well controlled, it will increase the stress on the power transistors in the multilevel circuit, leading to damage and failure of the power transistors, and consequently reducing the reliability of the system circuit in which the multilevel topology is used.

[0003] Therefore, existing technologies typically control the voltage equalization effect of the flying capacitor by adjusting the duty cycle of different units or by using carrier phase shift angle. However, this significantly increases the complexity of the control circuit and reduces the reliability of the system. This problem is even more pronounced in multi-level topologies with a higher number of voltage levels; that is, the more voltage levels a multi-level circuit has, the more complex the control circuit for equalizing the voltage of the flying capacitor becomes, and the lower the overall system reliability.

[0004] How to reduce the complexity of the control circuit and improve the reliability of the entire system circuit is an urgent technical problem that multilevel circuit topologies need to solve in the system circuits in which they are applied. Summary of the Invention

[0005] Therefore, it is necessary to provide a voltage equalization control circuit for a flying capacitor to address the above-mentioned technical problems, thereby solving the technical problems of high complexity of control circuits and low reliability of system circuits used in multi-level circuits in the prior art.

[0006] This application provides a voltage equalization control circuit for a flying capacitor, including: an N-level circuit, a clamping circuit, and a subsequent circuit.

[0007] The N-level circuit is coupled to the clamping circuit, and both the N-level circuit and the clamping circuit are coupled to the subsequent circuit.

[0008] The clamping circuit and the subsequent circuit are configured together to maintain the voltage across each flying capacitor in the N-level circuit at a desired value.

[0009] In the multi-level circuit, the number of levels is N, where N is a natural number greater than or equal to 3, and the number of flying capacitors is (N-2).

[0010] In one embodiment, the clamping circuit is used to control the voltage of each flying capacitor to a corresponding value related to the input voltage of the subsequent circuit, so that the voltage across each flying capacitor is maintained at the desired value.

[0011] In one embodiment, when the flying capacitor has a stage number of 1, the N-level circuit is a 3-level circuit. The clamping circuit includes a first clamping power transistor and a second clamping power transistor, which are connected in series. The connection node of the first clamping power transistor and the second clamping power transistor connected in series is electrically connected to the subsequent circuit. The first terminal of the first clamping power transistor is electrically connected to the first terminal of the flying capacitor, and the second terminal of the second clamping power transistor is electrically connected to the second terminal of the flying capacitor.

[0012] The clamping circuit and the subsequent circuit are configured together to maintain the voltage across the flying capacitor at a desired value.

[0013] In one embodiment, the turn-on timing of the first clamping power transistor is consistent with the turn-on timing of the second-stage power transistor connected to the second clamping power transistor in the 3-level circuit, and the turn-on timing of the second clamping power transistor is consistent with the turn-on timing of the second-stage power transistor connected to the first clamping power transistor in the 3-level circuit.

[0014] In the 3-level circuit, the two power transistors connected in parallel with the flying capacitor are the first-stage power transistors, and the other two power transistors are the second-stage power transistors.

[0015] In one embodiment, when the flying capacitor has a stage number of 1, the N-level circuit is a 3-level circuit, and the clamping circuit includes a third clamping power transistor. One end of the third clamping power transistor is electrically connected to the first end of the flying capacitor, and the other end of the third clamping power transistor is electrically connected to the subsequent circuit.

[0016] The third clamping power transistor and the subsequent circuitry are configured together to maintain the voltage across the flying capacitor at a desired value.

[0017] In one embodiment, the turn-on timing of the third clamping power transistor is consistent with the turn-on timing of the second-stage power transistor in the 3-level circuit that is not connected to the third clamping power transistor;

[0018] In the 3-level circuit, the two power transistors connected in parallel with the flying capacitor are the first-stage power transistors, and the other two power transistors are the second-stage power transistors.

[0019] In one embodiment, when the flying capacitor has a stage number of 1, the N-level circuit is a 3-level circuit, and the clamping circuit includes a fourth clamping power transistor. One end of the fourth clamping power transistor is electrically connected to the second end of the flying capacitor, and the other end of the fourth clamping power transistor is electrically connected to the subsequent circuit.

[0020] The fourth clamping power transistor and the subsequent circuit are configured together to maintain equal voltage across the flying capacitor.

[0021] In one embodiment, the turn-on timing of the fourth power transistor is consistent with the turn-on timing of the second-stage power transistor in the 3-level circuit that is not connected to the fourth clamping power transistor;

[0022] In the 3-level circuit, the two power transistors connected in parallel with the flying capacitor are the first-stage power transistors, and the other two power transistors are the second-stage power transistors.

[0023] In one embodiment, when the number of stages of the flying capacitor is greater than or equal to 2, the flying capacitor with a number of stages greater than or equal to 2 is divided into multiple first equivalent capacitors, and the first equivalent capacitors of the same stage are connected in series sequentially.

[0024] The number of first equivalent capacitors in each stage is the same as the number of stages of the flying capacitors.

[0025] In one embodiment, the clamping circuit includes a multi-stage clamping power transistor group, each clamping power transistor group consisting of two clamping power transistors connected in series, and each clamping power transistor group being connected in parallel across the flying capacitor and the plurality of first equivalent capacitors.

[0026] Furthermore, the intra-group connection node of each clamped power transistor group is electrically connected to the connection node of the first equivalent capacitor connected in series with the next stage.

[0027] Each of the clamped power transistor groups connected in parallel with the plurality of first equivalent capacitors of the final stage is electrically connected to the subsequent stage circuit.

[0028] In one embodiment, the turn-on timing of the first clamping power transistor in the (N-2)th stage clamping power transistor group is consistent with the turn-on timing of the (N-1)th stage power transistor connected to the second clamping power transistor in the N-level circuit;

[0029] The turn-on timing of the second clamping power transistor in the clamping power transistor group of the (N-2)th stage is consistent with the turn-on timing of the (N-1)th stage power transistor in the N-level circuit that is connected to the first clamping power transistor.

[0030] The number of stages of the clamping power transistor group is consistent with the number of stages of the flying capacitor or the first equivalent capacitor connected in parallel; in the N-level circuit, the number of stages of the power transistor is consistent with the number of stages of the flying capacitor or the first equivalent capacitor connected in parallel, and the remaining two power transistors are the (N-1)th stage power transistors.

[0031] In one embodiment, the clamping circuit includes multiple clamping power transistors, with the first terminal of each clamping power transistor electrically connected to the first terminal of the flying capacitor or the first equivalent capacitor, and the second terminal of each clamping power transistor electrically connected to the connection node of the first equivalent capacitor connected in series in the next stage.

[0032] The second terminal of each clamping power transistor, which is connected to the plurality of first equivalent capacitors in the final stage, is electrically connected to the subsequent stage circuit.

[0033] In one embodiment, the turn-on timing of the clamping power of the (N-2)th stage is consistent with the turn-on timing of the power transistor of the (N-1)th stage that is not connected to it in the N-level circuit;

[0034] The clamping power transistor has the same number of stages as the flying capacitor or the first equivalent capacitor connected to its first terminal. In the N-level circuit, the power transistor has the same number of stages as the flying capacitor or the first equivalent capacitor connected in parallel. The other two power transistors are the (N-1)th stage power transistors.

[0035] In one embodiment, the clamping circuit includes multiple clamping power transistors, with the first terminal of each clamping power transistor electrically connected to the second terminal of the flying capacitor or the first equivalent capacitor, and the second terminal of each clamping power transistor electrically connected to the connection node of the first equivalent capacitor connected in series in the next stage.

[0036] The second terminal of each clamping power transistor, which is connected to the plurality of first equivalent capacitors in the final stage, is electrically connected to the subsequent stage circuit.

[0037] In one embodiment, the turn-on timing of the clamping power of the (N-2)th stage is consistent with the turn-on timing of the power transistor of the (N-1)th stage that is not connected to it in the N-level circuit;

[0038] The clamping power transistor has the same number of stages as the flying capacitor or the first equivalent capacitor connected to its first terminal. In the N-level circuit, the power transistor has the same number of stages as the flying capacitor or the first equivalent capacitor connected in parallel. The other two power transistors are the (N-1)th stage power transistors.

[0039] In one embodiment, the downstream circuitry includes an isolation module and multiple input capacitors;

[0040] The multiple input capacitors connected in series are coupled to the isolation module;

[0041] The isolation module is configured to maintain the voltage across the plurality of input capacitors at a desired value;

[0042] The number of input capacitors is (N-1).

[0043] In one embodiment, the isolation module includes multiple power stage circuits;

[0044] The multiple power stage circuits are electrically connected to the two ends of each input capacitor, and the output terminals of the multiple power stage circuits are connected in parallel to maintain the voltage across the input capacitor at the desired value.

[0045] In one embodiment, the power stage circuit includes an inverter circuit, a transformer circuit, and a rectifier circuit;

[0046] The input terminal of the inverter circuit is coupled to the input capacitor, the output terminal of the inverter circuit is coupled to the input terminal of the transformer circuit, and the output terminal of the transformer circuit is coupled to the input terminal of the rectifier circuit.

[0047] In one embodiment, the plurality of said transformer circuits are configured as a single magnetically integrated transformer circuit.

[0048] In one embodiment, the isolation module includes an LLC circuit, a transformer circuit, and a rectifier circuit;

[0049] The input terminal of the LLC circuit is coupled to the input capacitor, the output terminal of the LLC circuit is coupled to the input terminal of the transformer circuit, and the output terminal of the transformer circuit is coupled to the input terminal of the rectifier circuit.

[0050] In one embodiment, the circuit includes two voltage equalization control circuits for the flying capacitors described in the above embodiments; the two voltage equalization control circuits for the flying capacitors are connected in series.

[0051] Compared to related technologies, the voltage equalization control circuit for the flying capacitor provided in this application achieves the voltage equalization effect of the flying capacitor through the combined action of the subsequent circuit and the clamping circuit, thereby improving the reliability of the entire system circuit. This is a technical problem that the multi-level circuit topology urgently needs to solve in the applied system circuit.

[0052] Therefore, the present invention effectively overcomes the various shortcomings of the prior art and thus has high industrial application value.

[0053] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1a This is a circuit diagram of a three-level flying capacitor in the prior art;

[0056] Figure 1b This is a circuit diagram of a five-level flying capacitor in the prior art;

[0057] Figure 2 The driving waveform diagram for the three-level flying capacitor;

[0058] Figure 3 This is a schematic block diagram of Embodiment 1 of the voltage equalization control circuit for the flying capacitor of this application;

[0059] Figure 3a for Figure 3 Working status diagram during the time interval 0-t1;

[0060] Figure 3b for Figure 3 Working status diagram during the time interval t1-t2;

[0061] Figure 3c for Figure 3 Working status diagram during the time interval t2-t3;

[0062] Figure 3d for Figure 3 Working status diagram during the t3-t4 time interval;

[0063] Figure 4 This is a schematic block diagram of Embodiment 2 of the voltage equalization control circuit for the flying capacitor in this application;

[0064] Figure 4a for Figure 4 Working status diagram during the time interval 0-t1;

[0065] Figure 4b for Figure 4 Working status diagram during the time interval t1-t2;

[0066] Figure 4c for Figure 4Working status diagram during the time interval t2-t3;

[0067] Figure 4d for Figure 4 Working status diagram during the t3-t4 time interval;

[0068] Figure 5 This is a schematic block diagram of Embodiment 3 of the voltage equalization control circuit for the flying capacitor in this application;

[0069] Figure 5a for Figure 5 Working status diagram during the time interval 0-t1;

[0070] Figure 5b for Figure 5 Working status diagram during the time interval t1-t2;

[0071] Figure 5c for Figure 5 Working status diagram during the time interval t2-t3;

[0072] Figure 5d for Figure 5 Working status diagram during the t3-t4 time interval;

[0073] Figure 6 This is a schematic block diagram of Embodiment 4 of the voltage equalization control circuit for the flying capacitor in this application;

[0074] Figure 7 This is a schematic block diagram of Embodiment 5 of the voltage equalization control circuit for the flying capacitor in this application;

[0075] Figure 8 This is a schematic block diagram of Embodiment 6 of the voltage equalization control circuit for the flying capacitor of this application;

[0076] Figure 9 This is a schematic block diagram of Embodiment 7 of the voltage equalization control circuit for the flying capacitor of this application;

[0077] Figure 10 This is a schematic block diagram of Embodiment 8 of the voltage equalization control circuit for the flying capacitor of this application;

[0078] Figure 11 This is a schematic block diagram of Embodiment 9 of the voltage equalization control circuit for the flying capacitor of this application. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0080] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0081] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0082] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0083] Figure 1a Figure 1 shows the circuit diagram of a three-level flying capacitor in the prior art. To make the flying capacitor C... fly The voltage on is 1 / 2V DC And maintain the flying capacitance C within one modulation cycle. fly The voltage on it is 1 / 2V DC Nearby, it is necessary to control the complementary driving states of the driving signals of power transistors S1 and S4, and the complementary driving states of the driving signals of power transistors S2 and S3, and to control the phase difference between the driving signals of power transistors S1 and S2 to be 180°. Figure 2 The diagram shows the driving waveforms of the three-level flying capacitor, where... Figure 2 In this case, the modulation signal Vs is less than 0.5. For example... Figure 2 As shown, in the 0-t1 segment: power transistors S2 and S4 are on, while power transistors S1 and S3 are off; in the t1-t2 segment: power transistors S3 and S4 are on, while power transistors S1 and S2 are off; in the t2-t3 segment: power transistors S1 and S3 are on, while power transistors S2 and S4 are off; in the t3-t4 segment: power transistors S3 and S4 are on, while power transistors S1 and S2 are off.

[0084] Figure 2This demonstrates the on / off state of the power transistors in a three-level circuit when the modulation signal Vs is less than 0.5, and the on / off state of each power transistor and their conduction sequence when the modulation signal Vs is greater than 0.5. Figure 2 The differences shown in the text will not be elaborated here.

[0085] In the prior art, the control circuit adjusts the duty cycle of different units or the carrier phase shift angle according to... Figure 2 The drive waveform in the image controls each power transistor, such as... Figure 1a The three-level flying capacitor circuit shown can maintain the flying capacitor C fly The voltage across the terminals is maintained at 1 / 2V. DC Nearby, it can reduce the volt-second of inductor L to a quarter of its original value and also halve the voltage stress on the power transistor. However, the technical problem is that the control circuit controls the voltage of the flying capacitor by adjusting the duty cycle of different units or the carrier phase shift angle, which is complex and difficult to control.

[0086] In multilevel circuits, the more levels there are, the more complex the control circuit required to maintain the voltage equalization of the flying capacitors in each level, and the greater the control difficulty. Figure 1b The circuit diagram of a five-level flying capacitor in the prior art is shown below. Taking a five-level flying capacitor as an example, its circuit topology is as follows: Figure 1b As shown, the flying capacitor C is controlled by the control circuit. fly1 ~C fly3 The voltages on each side are 1 / 4V. DC 2 / 4V DC 3 / 4V DC And cause the flying capacitor C fly1 ~C fly3 The voltage on it was maintained at 1 / 4V. DC 2 / 4V DC 3 / 4V DC Nearby. Similarly, the control schemes used in existing technologies are still based on adjusting the duty cycle of different units or the carrier phase shift angle to make the flying capacitor C... fly1 ~C fly3 While maintaining the expected value, the five-level flying capacitor circuit also suffers from the technical problems of complex control circuitry and high control difficulty. Compared with the three-level flying capacitor circuit, the five-level flying capacitor circuit has greater control complexity and greater control difficulty. The increased control difficulty reduces the reliability of the system, thus limiting its application in power supply circuits with more level circuit topologies, and consequently limiting the power density and efficiency of the power supply circuit.

[0087] Example 1:

[0088] Figure 3 This is a schematic block diagram of Embodiment 1 of the voltage equalization control circuit for the flying capacitor of this application, as shown below. Figure 3 As shown, in this embodiment, the voltage equalization control circuit of the flying capacitor includes an N-level circuit, a clamping circuit, and a subsequent circuit. In this embodiment, the N-level circuit is a 3-level circuit, such as... Figure 3 As shown, the 3-level circuit includes four power transistors connected in series. The four power transistors are S, S, and S, respectively. 2a S 1a S 1b S 2b In a 3-level circuit, the flying capacitor has only one stage, meaning there is only one stage of flying capacitor C in a 3-level circuit. flya To make the flying capacitor C flya The voltage across the terminals is maintained near a desired value. In this embodiment, the desired value is either the voltage value of input capacitor C1 or the voltage value of input capacitor C2, since the voltage values ​​of input capacitor C1 and input capacitor C2 are equal. In this embodiment, the clamping circuit includes two clamping power transistors S connected in series. 21 and S 22 Two clamping power transistors S connected in series 21 and S 22 Parallel connection in flying capacitor C flya Both ends, and the first clamping power transistor S 21 Second clamping power transistor S 22 The common node connected in series is called the first node. The first node is electrically connected to the subsequent circuit, which includes an isolation module, input capacitor C1, and input capacitor C2. Input capacitors C1 and C2 are connected in series, and the common node of the series connection of input capacitors C1 and C2 is called the second node. The first node and the second node are electrically connected. The isolation module includes two parallel power stage circuits, which include an inverter circuit, a transformer circuit, and a rectifier circuit. The output terminal of the inverter circuit INV. is coupled to the input terminal of the transformer circuit, and the output terminal of the transformer circuit is coupled to the input terminal of the rectifier circuit RECT. The output terminals of both rectifier circuits RECT are connected in parallel with output capacitors. Specifically, the input terminal of the first inverter circuit INV. is connected in parallel across the input capacitor C1, and the input terminal of the second inverter circuit INV. is connected in parallel across the input capacitor C2.

[0089] In this embodiment, the input terminals of the subsequent circuit are connected in series (i.e., input capacitor C1 and input capacitor C2 are connected in series), and the output terminals are connected in parallel (the isolation module includes two parallel power stage circuits). Since the circuit with series input and parallel output can naturally equalize voltage, that is, the voltage across input capacitor C1 and input capacitor C2 remains stable, and the average voltage across input capacitor C1 and input capacitor C2 is equal.

[0090] like Figure 3a As shown, prior art knows that in the 0-t1 segment: power transistor S 1a and power transistor S 2b On, power transistor S 2a and power transistor S 1b Disconnected. Due to the first clamping power transistor S 21 On-time and power transistor S 2b The conduction timing is consistent, and the second clamping power transistor S... 22 On-time and power transistor S 2a Since the conduction timing is consistent, therefore, in the 0-t1 segment: the first clamping power transistor S... 21 Turn on, second clamping power transistor S 22 Disconnect; flying capacitor C flya This is equivalent to being connected in parallel across the input capacitor C2; therefore, the flying capacitor C... flya The voltage across the two ends is the same as the voltage across the input capacitor C2.

[0091] like Figure 3b As shown, segment t1-t2: power transistor S 1b and power transistor S 2b On, power transistor S 1a and power transistor S 2a Disconnect. Flying capacitor C flya During the time period t1-t2, no circuit was connected, due to the flying capacitor C flya Energy is stored during the time interval 0-t1; therefore, the flying capacitor C flya During the time period t1-t2, the voltage across its terminals remains at a value similar to that of the input capacitor C2.

[0092] like Figure 3c As shown, in segment t2-t3: power transistor S 1a and power transistor S 3a On, power transistor S 2a and power transistor S 4a Disconnected. Due to the first clamping power transistor S 21 On-time and power transistor S 2b The conduction timing is consistent, and the second clamping power transistor S... 22 On-time and power transistor S 2a The conduction timing is consistent; therefore, the first clamping power transistor S... 21 Disconnect, second clamping power transistor S 22 On; flying capacitor C flya This is equivalent to being connected in parallel across the input capacitor C1, and the flying capacitor C flya The voltage across the two ends is the same as the voltage across the input capacitor C1.

[0093] like Figure 3dAs shown, in segment t3-t4: power transistor S 3a and power transistor S 4a On, power transistor S 1a and power transistor S 2a Disconnect. Flying capacitor C flya During the time period t3-t4, no circuit was connected, due to the flying capacitor C flya Energy is stored during the time interval t2-t3; therefore, the flying capacitor C flya During the time period t3-t4, the voltage across its terminals remains at a value similar to that of the input capacitor C1.

[0094] In summary, the flying capacitor C flya Within the aforementioned cycle, the flying capacitor C flya The voltage across the terminals is maintained at a value close to that of the input capacitor C2. Compared to existing technologies, this embodiment employs a combination of a downstream circuit and a clamping circuit to achieve the crossing of the capacitor C2. flya The voltage equalization function reduces the complexity of the control circuit and improves the reliability of the power supply circuit in which the three-level circuit is applied.

[0095] Example 2:

[0096] Figure 4 This is a schematic block diagram of a second embodiment of the voltage equalization control circuit for the flying capacitor in this application, as shown below. Figure 4 As shown, in this embodiment, the voltage equalization control circuit of the flying capacitor includes an N-level circuit, a clamping circuit, and a subsequent circuit. In this embodiment, the N-level circuit is a 3-level circuit, such as... Figure 4 As shown, the 3-level circuit includes four power transistors connected in series. The four power transistors are S, S, and S, respectively. 2a S 1a S 1b S 2b In a 3-level circuit, the flying capacitor has only one stage, meaning there is only one stage of flying capacitor C in a 3-level circuit. flya To maintain the flying capacitor C flya The voltage across the terminals is maintained near a desired value. In this embodiment, the desired value is either the voltage value of input capacitor C1 or the voltage value of input capacitor C2, since the voltage values ​​of input capacitor C1 and input capacitor C2 are equal. In this embodiment, the clamping circuit includes one clamping power transistor S. 21 Clamping power transistor S 21 The first terminal and the flying capacitor C flya The first terminal is electrically connected, clamping the power transistor S. 21 The other end is electrically connected to the subsequent circuit.

[0097] Clamping power transistor S 21Together with the subsequent circuitry, they are configured to enable the flying capacitor C. flya The voltage across the terminals is maintained at a desired value, which in this embodiment is the voltage value of the input capacitor C2.

[0098] The subsequent circuit includes an isolation module and input capacitors C1 and C2. The structure of the subsequent circuit is exactly the same as that of the subsequent module in Example 1, and will not be described again here. Similarly, the common node of the series connection between input capacitors C1 and C2 is called the second node, clamping the power transistor S. 21 The second end is electrically connected to the second node.

[0099] In this embodiment, since the structure of the subsequent circuit is the same as that in Embodiment 1, the input terminals of the subsequent circuit are also connected in series (input capacitor C1 and input capacitor C2 are connected in series), and the output terminals are also connected in parallel (the isolation module includes two parallel power stage circuits). Similarly, the circuit with the input series and output parallel connection can naturally equalize the voltage, that is, the voltage across input capacitor C1 and input capacitor C2 remains stable, and the average voltage across input capacitor C1 and input capacitor C2 is equal.

[0100] like Figure 4a As shown, in the 0-t1 segment: power transistor S 1a and power transistor S 2b On, power transistor S 2a and power transistor S 1b Disconnected due to clamping power transistor S 21 On-time and power transistor S 2b The conduction timing is consistent; therefore, the clamping power transistor S... 21 On; flying capacitor C flya This is equivalent to being connected in parallel across the input capacitor C2, and the flying capacitor C flya The voltage across the two ends is the same as the voltage across the input capacitor C2.

[0101] like Figure 4b As shown, segment t1-t2: power transistor S 1b and power transistor S 2b On, power transistor S 1a and power transistor S 2a Disconnect; flying capacitor C flya During the time period t1-t2, no circuit was connected, due to the flying capacitor C flya Energy is stored during the time interval 0-t1; therefore, the flying capacitor C flya During the time period t1-t2, the voltage across its terminals remains near the voltage value of the input capacitor C2.

[0102] like Figure 4c As shown, in segment t2-t3: power transistor S2a and power transistor S 1b On, power transistor S 1a and power transistor S 2b Disconnect; flying capacitor C flya It is connected in series with input capacitors C1 and C2, due to the flying capacitor C fly Energy is stored during the time interval 0-t1; therefore, the flying capacitor C fly During the time period t2-t3, the voltage change across its terminals is very small, remaining near the voltage value of the input capacitor C2.

[0103] like Figure 4d As shown, in segment t3-t4: power transistor S 1b and power transistor S 2b On, power transistor S 1a and power transistor S 2a Disconnect. Flying capacitor C flya During the time period t3-t4, no circuit was connected; therefore, the flying capacitor C... fly During the time period t3-t4, the voltage change across its terminals is small, remaining near the voltage value of the input capacitor C2.

[0104] In summary, the flying capacitor C flya Within the aforementioned period, there exists at any given moment when the flying capacitor C... flya The capacitor connected in parallel across the input capacitor C2, due to the flying capacitor C flya It is an energy storage element with a small voltage change across its terminals, maintaining the voltage across the input capacitor C2 close to its value. In this embodiment, compared to existing technologies, a downstream circuit and a clamping circuit work together to achieve the flying capacitor C... flya The voltage equalization function reduces the complexity of the control circuit and improves the reliability of the power supply circuit in which the three-level circuit is applied.

[0105] Example 3:

[0106] Figure 5 This is a schematic block diagram of the third embodiment of the voltage equalization control circuit for the flying capacitor in this application, as shown below. Figure 5 As shown, the clamping circuit includes one clamping power transistor S. 22 The difference between this embodiment and Embodiment 2 is that the clamping power transistor S... 22 The first terminal and the flying capacitor C flya The second terminal is electrically connected. In this embodiment, the subsequent circuit is the same as in Embodiment 2. Similarly, the common node of the input capacitor C1 and the input capacitor C2 connected in series is called the second node, and the clamping power transistor S... 22 The second end is electrically connected to the second node.

[0107] like Figure 5aAs shown, in the 0-t1 segment: power transistor S 1a and power transistor S 2b On, power transistor S 2a and power transistor S 1b Disconnect; flying capacitor C flya Connected in series with inductor L, for flying capacitor C flya Charging is performed, and the flying capacitor C is used for charging. flya The voltage values ​​at both ends do not change much, remaining near the voltage value at the last moment of the previous cycle, that is, near the voltage value of the input capacitor C1.

[0108] like Figure 5b As shown, segment t1-t2: power transistor S 1b and power transistor S 2b On, power transistor S 1a and power transistor S 2a Disconnect; flying capacitor C flya During the time period t1-t2, no circuit was connected; therefore, the flying capacitor C... flya The voltage across the terminals remains constant.

[0109] like Figure 5c As shown, in segment t2-t3: power transistor S 2a and power transistor S 1b On, power transistor S 1a and power transistor S 2b Disconnected due to clamping power transistor S 22 On-time and power transistor S 2a The conduction timing is consistent; therefore, the clamping power transistor S... 22 On; flying capacitor C flya This is equivalent to being connected in parallel across the input capacitor C1, and the flying capacitor C flya The voltage across the two ends is the same as the voltage across the input capacitor C1.

[0110] like Figure 5d As shown, in segment t3-t4: power transistor S 1b and power transistor S 2b On, power transistor S 1a and power transistor S 2a Disconnect. Flying capacitor C flya During the time period t3-t4, no circuit was connected, due to the flying capacitor C fly Energy is stored during the time interval t2-t3; therefore, the flying capacitor C flya During the time period t3-t4, the voltage change across its terminals is very small, remaining near the voltage value of the input capacitor C1.

[0111] In summary, the flying capacitor C flya Within a single cycle, there exists at any given moment that the capacitor C is flying across. flyaThe capacitor connected in parallel across the input capacitor C1, due to the flying capacitor C flya It is an energy storage element with a small voltage change across its terminals, maintaining the voltage across the input capacitor C1. Compared to existing technologies, this embodiment employs a combination of a downstream circuit and a clamping circuit to achieve the flying capacitor C1. flya The voltage equalization function reduces the complexity of the control circuit and improves the reliability of the power supply circuit in which the three-level circuit is applied.

[0112] Example 4:

[0113] Figure 6 This is a schematic block diagram of Embodiment 4 of the voltage equalization control circuit for the flying capacitor in this application, as shown below. Figure 6 As shown, in this embodiment, the voltage equalization control circuit of the flying capacitor includes an N-level circuit, a clamping circuit, and a subsequent circuit. In this embodiment, the N-level circuit is a 4-level circuit. Figure 6 As shown, the 4-level circuit includes six power transistors connected in series. The six power transistors are, in order, S... 3a S 2a S 1a S 1b S 2b S 3b In a 4-level circuit, the number of flying capacitor stages is 2, meaning there are two stages of flying capacitors in a 4-level circuit. The first stage flying capacitor C... 11 The second-stage flying capacitor is divided into two equivalent capacitances, C and C respectively. 21 and C 22 And the equivalent capacitance C 21 and C 22 Series connection, equivalent capacitance C 21 and equivalent capacitance C 22 The common node in the series is called the second node.

[0114] To maintain a stable voltage across the two flying capacitors, in this embodiment, the clamping circuit includes a clamping power transistor S. 21 S 22 S 31 S 32 S 33 S 34 Clamping power transistor S 21 and power transistor S 22 These transistors are connected in series to form a power transistor group, called the first-stage clamping power transistor group. The first-stage clamping power transistor group is connected in parallel to the first-stage flying capacitor C. 11 At both ends, of which, the clamping power transistor S 21 and clamping power transistor S 22 The common node in the series connection is called the first node; clamping power transistor S 31and clamping power transistor S 32 These transistors are connected in series to form a clamping power transistor group, referred to as the first clamping power transistor group in the second-stage clamping power transistor group. The first clamping power transistor group in the second-stage clamping power transistor group is connected in parallel to the equivalent capacitance C. 21 At both ends, of which, the clamping power transistor S 31 and clamping power transistor S 32 The common node in the series connection is called the third node; similarly, the clamping power transistor S... 33 and clamping power transistor S 34 They are connected in series to form a power transistor group, which is called the second clamping power transistor group in the second-stage clamping power transistor group. The second clamping power transistor group in the second-stage clamping power transistor group is connected in parallel to the equivalent capacitance C. 22 At both ends, of which, the clamping power transistor S 31 and clamping power transistor S 32 The common node connected in series is called the fourth node. The subsequent circuit includes three input capacitors, C1, C2, and C3. The common node where input capacitors C1 and C2 are connected in series is called the fifth node, and the common node where input capacitors C2 and C3 are connected in series is called the sixth node. Among them, the first and second nodes are electrically connected, the third and fifth nodes are electrically connected, and the fourth and sixth nodes are electrically connected.

[0115] The subsequent circuit also includes an isolation module, which includes three power stage circuits. The three power stage circuits are connected in parallel across the input capacitors C1, C2, and C3, respectively. The power stage circuits include an inverter circuit, a transformer circuit, and a rectifier circuit. The input terminal of the inverter circuit is coupled to the input capacitor, the output terminal of the inverter circuit is coupled to the input terminal of the transformer circuit, and the output terminal of the transformer circuit is coupled to the input terminal of the rectifier circuit.

[0116] Similar to Example 1, since the input terminals of the subsequent circuit are connected in series and the output terminals are connected in parallel, the subsequent circuit can naturally equalize the voltage. That is, the voltages across input capacitors C1, C2, and C3 are all maintained at the desired values. The first clamping power transistor S in the first-stage clamping power transistor group... 21 The conduction timing of the second-stage power transistor S 2b The conduction timing is consistent, and the second clamping power transistor S in the first-stage clamping power transistor group is... 22 The conduction timing of the second-stage power transistor S 2a The conduction timing is consistent; the first clamping power transistor S in the first group of clamping power transistors in the second-stage clamping power transistor group. 31 The conduction timing and the third-stage power transistor S 3bThe conduction timing is consistent, and the second clamping power transistor S in the first clamping power transistor group of the second-stage clamping power transistor group is... 32 The conduction timing and the third-stage power transistor S 3a The conduction timing is consistent; the first clamping power transistor S in the second clamping power transistor group of the second-stage clamping power transistor group. 33 The conduction timing and the third-stage power transistor S 3b The conduction timing is consistent, and the second clamping power transistor S in the second clamping power transistor group of the second-stage clamping power transistor group is... 34 The conduction timing and the third-stage power transistor S 3a The conduction timing is consistent. Based on the above control state, the power transistor in the clamping circuit is turned on or off, causing the equivalent capacitance C to... 21 It is connected in parallel across either input capacitor C1 or input capacitor C2, such that the equivalent capacitance C 22 It is connected in parallel across the input capacitor C2 or C3, thereby making the equivalent capacitance C 21 and equivalent capacitance C 22 The voltage across the terminals is maintained at the desired value, and the first-stage flying capacitor C is kept at the desired value. 11 Parallel connection to the equivalent capacitance C 21 or equivalent capacitance C 22 The two ends of the capacitor cause the first-stage flying capacitor C to... 11 Maintaining the voltage across the terminals at the desired value reduces the complexity of the control circuit and improves the reliability of the voltage equalization control circuit for the flying capacitor.

[0117] Additionally, in this embodiment, the clamping circuit may also include only S. 21 S 31 S 33 Or the clamping circuit only includes S 22 S 32 S 34 There are two other scenarios, which are similar to those in this embodiment and will not be described again here.

[0118] Example 5:

[0119] Figure 7 This is a schematic block diagram of Embodiment 5 of the voltage equalization control circuit for the flying capacitor in this application, as shown below. Figure 7 As shown, in this embodiment, the voltage equalization control circuit of the flying capacitor includes an N-level circuit, a clamping circuit, and a subsequent circuit. In this embodiment, the multi-level circuit is a 5-level circuit. Figure 7 As shown, the 5-level circuit includes eight power transistors connected in series. The eight power transistors are, in order, S... 4a S 3a S 2a S 1a S 1b S2b

[0120] S 3b S 4b In a 5-level circuit, the number of flying capacitor stages is 3, meaning there are three flying capacitor stages in a 5-level circuit. The first flying capacitor is C. 11 The second-stage flying capacitor is divided into two equivalent capacitances, C and C respectively. 21 and C 22 The third-stage flying capacitor is divided into three equivalent capacitances, which are C3, C4, C5, C6, C7, C8, C9, C10, C11, C21, C12, C1331 C 32 and C 31 .

[0121] In this embodiment, the clamping circuit includes a clamping power transistor S. 21 S 22 S 31 S 32 S 33 S 34 S 41 S 42 S 43 S 44 S 45 S 46 Clamping power transistor S 21 and clamping power transistor S 22 These transistors are connected in series to form a clamping power transistor group, called the first-stage clamping power transistor group. The first-stage clamping power transistor group is connected in parallel to the first-stage flying capacitor C. 11 Both ends; clamping power transistor S 31 and clamping power transistor S 32 These transistors are connected in series to form a clamping power transistor group, referred to as the first clamping power transistor group in the second-stage clamping power transistor group. The first clamping power transistor group in the second-stage clamping power transistor group is connected in parallel to the equivalent capacitance C. 21 Both ends; similarly, clamping power transistor S 33 and clamping power transistor S 34 These transistors are connected in series to form a power transistor group, called the second clamping power transistor group in the second-stage clamping power transistor group. The second clamping power transistor group in the second-stage clamping power transistor group is connected in parallel to the equivalent capacitance C. 22 Both ends; clamping power transistor S 41 and clamping power transistor S 42 These transistors are connected in series to form a power transistor group, called the first clamping power transistor group in the third-stage clamping power transistor group. The first clamping power transistor group in the third-stage clamping power transistor group is connected in parallel to the equivalent capacitance C. 31 Both ends; clamping power transistor S 43 and clamping power transistor S 44These transistors are connected in series to form a power transistor group, known as the second clamping power transistor group in the third-stage clamping power transistor group. The second clamping power transistor group in the third-stage clamping power transistor group is connected in parallel to the equivalent capacitance C. 32 Both ends; clamping power transistor S 45 and clamping power transistor S 46 These transistors are connected in series to form a power transistor group, called the third clamping power transistor group in the third-stage clamping power transistor group. The third clamping power transistor group in the third-stage clamping power transistor group is connected in parallel to the equivalent capacitance C. 33 The two ends.

[0122] The subsequent circuit includes four input capacitors, C1, C2, C3, and C4. It also includes an isolation module comprising four power stage circuits connected in parallel across the input capacitors C1, C2, C3, and C4. Each power stage circuit includes an inverter circuit, a transformer circuit, and a rectifier circuit. The inverter circuit's input is coupled to the input capacitors, its output is coupled to the transformer circuit's input, and the transformer circuit's output is coupled to the rectifier circuit's input. Similar to Example 1, because the subsequent circuit has series-connected inputs and parallel-connected outputs, it can naturally equalize voltages, meaning the voltages across input capacitors C1, C2, C3, and C4 are maintained at the desired values. The first clamping power transistor S in the first-stage clamping power transistor group... 21 The conduction timing of the second-stage power transistor S 2b The conduction timing is consistent, and the second clamping power transistor S in the first-stage clamping power transistor group is... 22 The conduction timing of the second-stage power transistor S 2a The conduction timing is consistent; the first clamping power transistor S in the first group of clamping power transistors in the second-stage clamping power transistor group. 31 The conduction timing and the third-stage power transistor S 3b The conduction timing is consistent, and the second clamping power transistor S in the first clamping power transistor group of the second-stage clamping power transistor group is... 32 The conduction timing and the third-stage power transistor S 3a The conduction timing is consistent; the first clamping power transistor S in the second clamping power transistor group of the second-stage clamping power transistor group. 33 The conduction timing and the third-stage power transistor S 3b The conduction timing is consistent, and the second clamping power transistor S in the second clamping power transistor group of the second-stage clamping power transistor group is... 34 The conduction timing and the third-stage power transistor S 3a The conduction timing is consistent.

[0123] The first clamping power transistor S in the first group of the third-level clamping power transistor group41 The conduction timing and the fourth stage power transistor S 4b The conduction timing is consistent, and the second clamping power transistor S in the first group of the third-stage clamping power transistor group is... 42 The conduction timing and the fourth stage power transistor S 4a The conduction timing is consistent; the first clamping power transistor S in the second group of clamping power transistors in the third-stage clamping power transistor group. 43 The conduction timing and the fourth stage power transistor S 4b The conduction timing is consistent, and the second clamping power transistor S in the second group of the third-stage clamping power transistor group is... 44 The conduction timing and the fourth stage power transistor S 4a The conduction timing is consistent; the first clamping power transistor S in the third clamping power transistor group of the third-stage clamping power transistor group. 45 The conduction timing and the fourth stage power transistor S 4b The conduction timing is consistent, and the second clamping power transistor S in the third clamping power transistor group of the third-stage clamping power transistor group is... 46 The conduction timing and the fourth stage power transistor S 4a The conduction timing is consistent. Based on the above control state, the conduction or disconnection of each clamping power transistor in the clamping circuit is controlled, causing the equivalent capacitance C to... 31 It is connected in parallel across the input capacitor C1 or C2, making the equivalent capacitance C 32 It is connected in parallel across the input capacitor C2 or C3, making the equivalent capacitance C 33 It is connected in parallel across the input capacitor C3 or C4, thereby making the equivalent capacitance C 31 Equivalent capacitance C 32 and equivalent capacitance C 33 The voltage across the terminals is maintained at the desired value;

[0124] And make the equivalent capacitance C 21 Parallel connection to the equivalent capacitance C 31 or equivalent capacitance C 32 The two ends of the capacitor make the equivalent capacitance C 22 Parallel connection to the equivalent capacitance C 32 or equivalent capacitance C 33 The two ends of the capacitor cause the equivalent capacitance C to be... 21 Second stage flying capacitor C 22 The voltage across the terminals is maintained at the desired value;

[0125] And the first-stage flying capacitor C 11 Parallel connection to the equivalent capacitance C 21 or equivalent capacitance C 22 The two ends of the capacitor cause the first-stage flying capacitor C to... 11Maintaining the voltage across the terminals at the desired value reduces the complexity of the control circuit and improves the reliability of the voltage equalization control circuit for the flying capacitor.

[0126] Alternatively, the clamping circuit can also consist of only the power transistor S. 21 S 31 S 33 S 41 S 43 S 45 Or the clamping circuit only includes the power transistor S. 22 S 32 S 34 S 42 S 44 S 46 There are two other scenarios, which are similar to those in this embodiment and will not be described again here.

[0127] Example 6:

[0128] Figure 8 This is a schematic block diagram of Embodiment 6 of the voltage equalization control circuit for the flying capacitor of this application, as shown below. Figure 8 As shown, the difference between this embodiment and Embodiment 1 is the transformer module in the subsequent circuit.

[0129] In this embodiment, the two transformer circuits in the subsequent circuit reuse a single magnetic core. That is, the magnetic cores of the two transformers in the subsequent circuit are integrated into a single magnetic core. Since transformers are generally large, the solution in this embodiment can minimize the system volume and increase the power density.

[0130] Example 7:

[0131] Figure 9 This is a schematic block diagram of Embodiment 7 of the voltage equalization control circuit for the flying capacitor of this application, as shown below. Figure 9 As shown, the difference between this embodiment and Embodiment 1 is the subsequent circuit.

[0132] The subsequent circuit includes an isolation module and input capacitors C1 and C2 connected in series. The isolation module includes a resonant circuit, a transformer circuit, and a rectifier circuit. The resonant circuit can be an LLC circuit. In this embodiment, a half-bridge LLC circuit is used as an example.

[0133] Specifically, unlike Embodiment 1, the two inverter circuits in Embodiment 1 are replaced by a half-bridge LLC circuit. The half-bridge LLC circuit includes power transistors S1 and S2, an inductor Lr, and a capacitor Cr. Power transistors S1 and S2 are connected in series and in parallel across the input capacitors C1 and C2, which are connected in series. The first terminal of the inductor Lr is electrically connected to the common node of the series-connected power transistors S1 and S2. The second terminal of the inductor Lr is connected to the first terminal of the primary winding of the transformer. The second terminal of the primary winding of the transformer is connected to the first terminal of the capacitor Cr. The second terminal of the capacitor Cr is electrically connected to the common node of the series-connected output capacitors C1 and C2. The driving states of power transistors S1 and S2 are complementary.

[0134] In a half-bridge LLC circuit, when power transistor S1 is on and power transistor S2 is off, the input capacitor C1, inductor Lr, capacitor Cr, and the primary winding of the transformer are connected in series. Correspondingly, the secondary winding of the transformer is coupled to the output capacitor C. Since the impedances of inductor Lr and capacitor Cr are sufficiently small, the input capacitor C1 is effectively connected in parallel with the voltage across the primary winding of the output capacitor C. Similarly, when power transistor S1 is off and power transistor S2 is on, the input capacitor C2, inductor Lr, capacitor Cr, and the primary winding of the transformer are connected in series. Correspondingly, the secondary winding of the transformer is coupled to the output capacitor C. Since the impedances of inductor Lr and capacitor Cr are sufficiently small, the input capacitor C1 is effectively connected in parallel with the voltage across the primary winding of the output capacitor C. When the subsequent circuit is a half-bridge LLC circuit, within one cycle, it is equivalent to the input capacitors C1 and C2 being alternately connected in parallel across the output capacitor C. Since the average voltage across the input capacitors C1 and C2 is equal, the subsequent circuit can achieve voltage equalization. Furthermore, by controlling the on / off state of the power transistor in the clamping circuit, the on / off sequence of the power transistor is consistent with that in Embodiment 1 above, and will not be repeated here. This allows the flying capacitor to be connected in parallel across either the input capacitor C1 or C2, thereby maintaining the voltage across the flying capacitor at the desired value, reducing the complexity of the control circuit and improving the reliability of the voltage equalization control circuit for the flying capacitor.

[0135] Example 8:

[0136] Figure 10 This is a schematic block diagram of Embodiment 8 of the voltage equalization control circuit for the flying capacitor of this application, as shown below. Figure 10As shown, in this embodiment, the voltage equalization control circuits of the two flying capacitors of Embodiment 1 are connected in series to form a new voltage equalization control circuit for the flying capacitor. This voltage equalization control circuit for the flying capacitor is also a 5-level circuit. Compared with Embodiment 5, the voltage equalization control circuit for the flying capacitor in this embodiment can also solve the voltage equalization problem of multi-level circuits. In this embodiment, the number of power transistors used in the clamping circuit is small, which greatly reduces the complexity of the control circuit and improves the reliability of the voltage equalization control circuit for the flying capacitor.

[0137] Example 9:

[0138] Figure 11 This is a schematic block diagram of Embodiment 9 of the voltage equalization control circuit for the flying capacitor of this application, as shown below. Figure 11 As shown, in this embodiment, the difference from embodiment 8 is that the transformer circuit adopts magnetic integration, integrating the magnetic cores of the four transformers in the subsequent circuit into one magnetic core. Since the transformer is generally large in size, the solution of this embodiment can minimize the system volume and increase the power density.

[0139] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

[0140] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0141] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A flying capacitor voltage equalization control circuit, comprising: include: N-level circuit, clamping circuit and subsequent circuit; The N-level circuit is coupled to the clamping circuit, and both the N-level circuit and the clamping circuit are coupled to the subsequent circuit. The clamping circuit and the subsequent circuit are configured together to maintain the voltage across each flying capacitor in the N-level circuit at a desired value. The clamping circuit includes a first clamping power transistor and a second clamping power transistor, which are connected in series. The connection node of the first clamping power transistor and the second clamping power transistor connected in series is electrically connected to the subsequent circuit. The first end of the first clamping power transistor is electrically connected to the first end of the flying capacitor, and the second end of the second clamping power transistor is electrically connected to the second end of the flying capacitor. When the number of stages of the flying capacitor is 1, the N-level circuit is a 3-level circuit. The turn-on timing of the first clamping power transistor is consistent with the turn-on timing of the second stage power transistor connected to the second clamping power transistor in the 3-level circuit. The turn-on timing of the second clamping power transistor is consistent with the turn-on timing of the second stage power transistor connected to the first clamping power transistor in the 3-level circuit. In the 3-level circuit, the two power transistors connected in parallel with the flying capacitor are the first-stage power transistors, and the other two power transistors are the second-stage power transistors. In the N-level circuit, the number of levels is N, where N is a natural number greater than or equal to 3, and the number of flying capacitors is (N-2); the input terminals of the subsequent circuit are connected in series, and the output terminals are connected in parallel.

2. The flying capacitor voltage equalization control circuit according to claim 1, wherein The clamping circuit is used to control the voltage of each flying capacitor to a corresponding value related to the input voltage of the subsequent circuit, so that the voltage across each flying capacitor is maintained at the desired value.

3. The voltage equalization control circuit for the flying capacitor according to claim 2, characterized in that, When the flying capacitor has a stage number of 1, the N-level circuit is a 3-level circuit. The clamping circuit includes a third clamping power transistor. One end of the third clamping power transistor is electrically connected to the first end of the flying capacitor, and the other end of the third clamping power transistor is electrically connected to the subsequent stage circuit. The third clamping power transistor and the subsequent circuitry are configured together to maintain the voltage across the flying capacitor at a desired value.

4. The flying capacitor voltage equalization control circuit according to claim 3, wherein The turn-on timing of the third clamping power transistor is consistent with the turn-on timing of the second-stage power transistor in the 3-level circuit that is not connected to the third clamping power transistor. In the 3-level circuit, the two power transistors connected in parallel with the flying capacitor are the first-stage power transistors, and the other two power transistors are the second-stage power transistors.

5. The voltage equalization control circuit for the flying capacitor according to claim 2, characterized in that, When the flying capacitor has a stage number of 1, the N-level circuit is a 3-level circuit. The clamping circuit includes a fourth clamping power transistor. One end of the fourth clamping power transistor is electrically connected to the second end of the flying capacitor, and the other end of the fourth clamping power transistor is electrically connected to the subsequent circuit. The fourth clamping power transistor and the subsequent circuit are configured together to maintain the voltage across the flying capacitor at a desired equal value.

6. The flying capacitor voltage equalization control circuit of claim 5, wherein, The conduction timing of the fourth clamping power transistor is consistent with the conduction timing of the second-stage power transistor in the 3-level circuit that is not connected to the fourth clamping power transistor. In the 3-level circuit, the two power transistors connected in parallel with the flying capacitor are the first-stage power transistors, and the other two power transistors are the second-stage power transistors.

7. The voltage equalization control circuit for the flying capacitor according to claim 2, characterized in that, When the number of stages of the flying capacitor is greater than or equal to 2, the flying capacitor with a number of stages greater than or equal to 2 is divided into multiple first equivalent capacitors, and the first equivalent capacitors of the same stage are connected in series in sequence. The number of first equivalent capacitors in each stage is the same as the number of stages of the flying capacitors.

8. The voltage equalization control circuit for the flying capacitor according to claim 7, characterized in that, The clamping circuit includes a multi-stage clamping power transistor group, each clamping power transistor group consists of two clamping power transistors connected in series, and each clamping power transistor group is connected in parallel across the flying capacitor and the multiple first equivalent capacitors. Furthermore, the intra-group connection node of each clamped power transistor group is electrically connected to the connection node of the first equivalent capacitor connected in series with the next stage. Each of the clamped power transistor groups connected in parallel with the plurality of first equivalent capacitors of the final stage is electrically connected to the subsequent stage circuit.

9. The voltage equalization control circuit for the flying capacitor according to claim 8, characterized in that, The turn-on timing of the first clamping power transistor in the clamping power transistor group of the (N-2)th stage is consistent with the turn-on timing of the (N-1)th stage power transistor connected to the second clamping power transistor in the N-level circuit; The turn-on timing of the second clamping power transistor in the clamping power transistor group of the (N-2)th stage is consistent with the turn-on timing of the (N-1)th stage power transistor connected to the first clamping power transistor in the N-level circuit. The number of stages of the clamping power transistor group is consistent with the number of stages of the flying capacitor or the first equivalent capacitor connected in parallel; in the N-level circuit, the number of stages of the power transistor is consistent with the number of stages of the flying capacitor or the first equivalent capacitor connected in parallel, and the remaining two power transistors are the (N-1)th stage power transistors.

10. The voltage equalization control circuit for the flying capacitor according to claim 7, characterized in that, The clamping circuit includes multiple clamping power transistors. The first end of each clamping power transistor is electrically connected to the first end of the flying capacitor or the first equivalent capacitor. The second end of each clamping power transistor is electrically connected to the connection node of the first equivalent capacitor connected in series in the next stage. The second terminal of each clamping power transistor, which is connected to the plurality of first equivalent capacitors in the final stage, is electrically connected to the subsequent stage circuit.

11. The voltage equalization control circuit for the flying capacitor according to claim 10, characterized in that, The turn-on timing of the clamping power in stage (N-2) is consistent with the turn-on timing of the power transistor in stage (N-1) that is not connected to it in the N-level circuit; The clamping power transistor has the same number of stages as the flying capacitor or the first equivalent capacitor connected to its first terminal. In the N-level circuit, the power transistor has the same number of stages as the flying capacitor or the first equivalent capacitor connected in parallel. The other two power transistors are the (N-1)th stage power transistors.

12. The voltage equalization control circuit for the flying capacitor according to claim 7, characterized in that, The clamping circuit includes multiple clamping power transistors. The first end of each clamping power transistor is electrically connected to the second end of the flying capacitor or the first equivalent capacitor. The second end of each clamping power transistor is electrically connected to the connection node of the first equivalent capacitor connected in series in the next stage. The second terminal of each clamping power transistor, which is connected to the plurality of first equivalent capacitors in the final stage, is electrically connected to the subsequent stage circuit.

13. The voltage equalization control circuit for the flying capacitor according to claim 12, characterized in that, The turn-on timing of the clamping power in stage (N-2) is consistent with the turn-on timing of the power transistor in stage (N-1) that is not connected to it in the N-level circuit; The clamping power transistor has the same number of stages as the flying capacitor or the first equivalent capacitor connected to its first terminal. In the N-level circuit, the power transistor has the same number of stages as the flying capacitor or the first equivalent capacitor connected in parallel. The other two power transistors are the (N-1)th stage power transistors.

14. The flying capacitor voltage sharing control circuit of claim 1, wherein, The subsequent circuitry includes an isolation module and multiple input capacitors; The multiple input capacitors connected in series are coupled to the isolation module; The isolation module is configured to maintain the voltage across the plurality of input capacitors at a desired value; The number of input capacitors is (N-1).

15. The flying capacitor voltage equalization control circuit of claim 14, wherein, The isolation module includes multiple power stage circuits; The multiple power stage circuits are electrically connected to the two ends of each input capacitor, and the output terminals of the multiple power stage circuits are connected in parallel to maintain the voltage across the input capacitor at the desired value.

16. The flying capacitor voltage sharing control circuit of claim 15, wherein, The power stage circuit includes an inverter circuit, a transformer circuit, and a rectifier circuit; The input terminal of the inverter circuit is coupled to the input capacitor, the output terminal of the inverter circuit is coupled to the input terminal of the transformer circuit, and the output terminal of the transformer circuit is coupled to the input terminal of the rectifier circuit.

17. The voltage equalization control circuit for the flying capacitor according to claim 16, characterized in that, The multiple transformer circuits are configured as a single magnetically integrated transformer circuit.

18. The voltage equalization control circuit for the flying capacitor according to claim 14, characterized in that, The isolation module includes an LLC circuit, a transformer circuit, and a rectifier circuit; The input terminal of the LLC circuit is coupled to the input capacitor, the output terminal of the LLC circuit is coupled to the input terminal of the transformer circuit, and the output terminal of the transformer circuit is coupled to the input terminal of the rectifier circuit.

19. A voltage equalization control circuit for a flying capacitor, characterized in that, Includes a voltage equalization control circuit for two flying capacitors as described in any one of claims 1-18; The voltage equalization control circuits of the two flying capacitors are connected in series.

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