A high-voltage power supply circuit and a high-voltage power supply device

Abstract

The application discloses a high-voltage power supply circuit and a high-voltage power supply device. In the circuit, the non-inverting input terminal of a first operational amplifier is connected to the ground, the inverting input terminals are respectively connected to a signal generator and the output terminal of a second operational amplifier, and the output terminal is connected to the gate of a third MOS tube; the drain of the third MOS tube is connected to the source of a first MOS tube; the gate of the first MOS tube is connected to the input voltage terminal and the second output terminal of a PWM control chip, and the drain is connected to the drain of a second MOS tube; the gate of the second MOS tube is connected to the first output terminal of the PWM control chip and the ground, and the drain is connected to the third terminal of a transformer and the ground; the first terminal of the transformer is connected between the drain of the first MOS tube and the drain of the second MOS tube, and the second terminal and the fourth terminal are respectively connected to the input terminal of a voltage doubling circuit; the non-inverting input terminal of the second operational amplifier is connected to the ground, and the second resistor is connected between the inverting input terminal and the output terminal; and the PWM control chip can output a preset square wave signal.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a high-voltage power supply circuit and a high-voltage power supply device. Background Technology

[0002] With the development of transistors, various semiconductor devices, including optocouplers and various optical isolation devices, are being used extensively, making integrated circuits increasingly widely used in various fields. During integrated circuit manufacturing, ensuring the reliability of various components requires testing to guarantee their normal performance. When testing optical isolation devices, such as MOSFETs or half-bridge driver chips, a high-voltage floating power supply is needed on the high side of the chip's output drive. Similarly, a high-voltage power supply is required when testing the breakdown voltage of the collector and emitter stages at the output of an optocoupler. Summary of the Invention

[0003] The inventors have discovered that ordinary high-voltage power supplies have limited output voltage range, poor current load capacity, and insufficient output accuracy. Furthermore, they rarely meet the switching requirements between constant voltage and pulse voltage modes. In view of these problems, this invention is proposed to provide a high-voltage power supply circuit and device that overcomes or at least partially solves these problems.

[0004] In a first aspect, embodiments of the present invention provide a high-voltage power supply circuit, comprising: a signal generator, a first operational amplifier, a first MOSFET, a second MOSFET, a third MOSFET, a transformer, a voltage multiplier circuit, a second operational amplifier, a first capacitor, a first resistor, a second resistor, and a PWM control chip;

[0005] The non-inverting input of the first operational amplifier is grounded, the inverting input of the first operational amplifier is connected to the output of the signal generator and the output of the second operational amplifier, and the output of the first operational amplifier is connected to the gate of the third MOS transistor.

[0006] The source of the third MOS transistor is connected to the input voltage terminal, and the drain of the third MOS transistor is connected to the source of the first MOS transistor.

[0007] The gate of the first MOSFET is connected to the input voltage terminal and the second output terminal of the PWM control chip, and the drain of the first MOSFET is connected to the drain of the second MOSFET.

[0008] The gate of the second MOSFET is connected to the first output terminal of the PWM control chip and grounded, and the drain of the second MOSFET is connected to the third terminal of the transformer and grounded.

[0009] The first terminal of the transformer is connected between the drain of the first MOSFET and the drain of the second MOSFET, and the second and fourth terminals of the transformer are respectively connected to the input terminals of the voltage multiplier circuit.

[0010] The output terminal of the voltage multiplier circuit is connected to the non-inverting input terminal of the second operational amplifier through a first capacitor, and is connected to the inverting input terminal of the second operational amplifier through a first resistor;

[0011] The non-inverting input of the second operational amplifier is grounded, and a second resistor is connected between the inverting input and the output of the second operational amplifier; the resistance of the first resistor is greater than the resistance of the second resistor.

[0012] The signal generator can output a preset constant voltage signal or a pulse voltage signal;

[0013] The PWM control chip can output a preset square wave signal.

[0014] In one or more alternative embodiments, a third resistor is connected between the inverting input of the first operational amplifier and the signal generator, and a fourth resistor is connected between the inverting input of the first operational amplifier and the output of the second operational amplifier.

[0015] In one or more optional embodiments, the voltage multiplier circuit includes a first diode, a second diode, a second capacitor, and a third capacitor;

[0016] The first diode and the second diode are connected in reverse parallel. The second capacitor is connected to the third terminal of the transformer and the common terminal of the first diode and the second diode. The third capacitor is connected between the anode of the first diode and the cathode of the second diode.

[0017] In one or more alternative embodiments, a third diode is connected between the inverting input and output of the first operational amplifier.

[0018] In one or more alternative embodiments, a second capacitor and a fifth resistor are connected between the inverting input and output of the first operational amplifier.

[0019] In one or more optional embodiments, the high-voltage power supply circuit further includes: a fourth MOSFET, a sixth resistor, and a seventh resistor;

[0020] The gate of the fourth MOS transistor is connected to the second output terminal of the PWM control chip via the sixth resistor. The source of the fourth MOS transistor is grounded, and the source and gate of the fourth MOS transistor are connected via the seventh resistor. The drain of the fourth MOS transistor is connected to the gate of the first MOS transistor.

[0021] In one or more optional embodiments, the high-voltage power supply circuit further includes: an eighth resistor disposed between the gate of the first MOS transistor and the input voltage terminal;

[0022] A ninth resistor is disposed between the gate of the first MOS transistor and the drain of the fourth MOS transistor.

[0023] The tenth resistor is disposed between the gate of the second MOS transistor and the input voltage terminal;

[0024] The eleventh resistor is located between the gate of the second MOS transistor and the first input terminal of the PWM control chip.

[0025] In one or more optional embodiments, the high-voltage power supply circuit further includes: a twelfth resistor disposed between the gate and drain of the third MOS transistor and a thirteenth resistor disposed between the gate of the third MOS transistor and the first operational amplifier.

[0026] In one or more optional embodiments, the high-voltage power supply circuit further includes a resistor matrix disposed between the voltage output terminal and the output terminal of the voltage multiplier circuit.

[0027] The ninth resistor is disposed between the gate of the first MOS transistor and the drain of the fourth MOS transistor.

[0028] Secondly, embodiments of the present invention provide a high-voltage power supply device, comprising: the high-voltage power supply circuit described in any of the above claims.

[0029] The beneficial effects of the above-described technical solutions provided in the embodiments of the present invention include at least the following:

[0030] The high-voltage power supply circuit provided in this embodiment of the invention utilizes the virtual ground characteristic of the operational amplifier input terminal to form a Kirchhoff circuit. According to Kirchhoff's Current Law (KCL), the sum of the currents at the inverting input terminal of the operational amplifier is zero, thereby enabling the voltage at the output terminal of the operational amplifier to be adjusted according to the output voltage of the signal generator. Then, based on the first and second resistors connected to the second operational amplifier, an inverting proportional operation is performed to determine the voltage at the inverting input terminal of the second operational amplifier, i.e., the preset output voltage. Since the gate of the third MOSFET is connected to the output terminal of the first operational amplifier, a closed loop is formed between the output terminal and the inverting input terminal of the second operational amplifier. The variable resistance region of the third MOSFET is automatically adjusted by the first operational amplifier to ensure the stability of the closed loop. Furthermore, the source voltage of the first MOSFET is adjusted by the third MOSFET, achieving automatic adjustment of the loop voltage and improving the circuit's adjustment accuracy. A PWM control chip is used in conjunction with a push-pull circuit composed of the first and second MOSFETs to drive the transformer, and a voltage multiplier circuit is used to boost the supply voltage to the preset output voltage. Based on actual voltage requirements, the constant voltage mode and pulse voltage mode can be switched by controlling the signal generator. The high voltage range of the output is controllable, which improves the current load capacity, the output accuracy is higher, and the overall circuit structure is simple and easy to operate.

[0031] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0032] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0033] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0034] Figure 1 This is a schematic diagram of the high-voltage power supply circuit provided in an embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram of a partial circuit structure of a high-voltage power supply including a PWM control chip, provided in an embodiment of the present invention.

[0036] Figure 3 A schematic diagram of the functional modules of the half-bridge driver chip IR2110 provided in an embodiment of the present invention;

[0037] Figure 4 for Figure 3 The diagram shows the circuit structure for testing the time parameters of the IR2110 chip.

[0038] Figure 5 for Figure 3 The waveform diagram of the switching time of the IR2110 chip is shown. Detailed Implementation

[0039] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0040] To illustrate the technical solution described in this invention, specific embodiments are described below.

[0041] This invention provides a high-voltage power supply circuit, with reference to... Figure 1 As shown, it includes: a signal generator, a first operational amplifier U1, a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, a transformer T1, a voltage multiplier circuit, a second operational amplifier U2, a first capacitor C1, a first resistor R1, a second resistor R2, and a PWM control chip U3;

[0042] The non-inverting input of the first operational amplifier U1 is grounded, the inverting input of the first operational amplifier U1 is connected to the output of the signal generator and the second operational amplifier U2 respectively, and the output of the first operational amplifier U1 is connected to the gate of the third MOS transistor Q3.

[0043] The source of the third MOSFET Q3 is connected to the input voltage terminal, and the drain of the third MOSFET Q3 is connected to the source of the first MOSFET Q1.

[0044] The gate of the first MOSFET Q1 is connected to the input voltage terminal and the second output terminal DV2 of the PWM control chip U3, and the drain of the first MOSFET Q1 is connected to the drain of the second MOSFET Q2.

[0045] The gate of the second MOSFET Q2 is connected to the first output terminal DV1 of the PWM control chip U3 and grounded, and the drain of the second MOSFET Q2 is connected to the third terminal of the transformer T1 and grounded.

[0046] The first terminal of the transformer T1 is connected between the drain of the first MOS transistor Q1 and the drain of the second MOS transistor Q2, and the second and fourth terminals of the transformer T1 are respectively connected to the input terminals of the voltage multiplier circuit.

[0047] The output terminal of the voltage multiplier circuit is connected to the non-inverting input terminal of the second operational amplifier U2 through the first capacitor C1, and is connected to the inverting input terminal of the second operational amplifier U2 through the first resistor R1;

[0048] The non-inverting input terminal of the second operational amplifier U2 is grounded, and a second resistor R2 is connected between the inverting input terminal and the output terminal of the second operational amplifier U2; the resistance value of the first resistor R1 is greater than the resistance value of the second resistor R2.

[0049] The signal generator can output a preset constant voltage signal or a pulse voltage signal;

[0050] The PWM control chip U3 can output a preset square wave signal.

[0051] In this embodiment of the invention, the signal generator can be implemented using a digital-to-analog converter (DA) chip. By controlling the input digital signal, the DA chip outputs a preset constant voltage signal or a pulse voltage signal. The pulse voltage signal can be a stepped increasing signal or a stepped decreasing signal. By changing the input digital signal according to a preset period, the desired pulse voltage signal can be obtained. For example, by inputting a digital signal that changes with a period of 1ms, an output pulse voltage signal with a period of 1ms can be obtained. Alternatively, by inputting a constant digital signal, the output will be a continuous DC level, i.e., the preset constant voltage signal.

[0052] In this embodiment of the invention, a push-pull circuit is formed by the first MOSFET Q1 and the second MOSFET Q2. To prevent the first MOSFET Q1 and the second MOSFET Q2 from conducting simultaneously, the square wave signal output by the PWM control chip U3 needs to have a dead time and a reasonable duty cycle. Based on this, the specific model and specifications of the PWM control chip U3 can be selected according to the actual circuit requirements; for example, it can be an SG3525 chip. (Refer to...) Figure 2 As shown, the model and specifications of the components in the circuit can be set according to the SG3525 datasheet to enable the SG3525 chip's first output terminal DV1 and second output terminal DV2 to output square wave signals with appropriate duty cycles and dead times. Specifically, the values ​​of R16, R17, C7, and C8 can be selected according to the duty cycle requirements, and the desired square wave waveform can be obtained by selecting R18, C9, C10, and C11 and adjusting the resistance value of potentiometer RV2. At the same time, the frequency can be adjusted by adjusting the resistance value of potentiometer RV1.

[0053] In this embodiment of the invention, a square wave signal with a suitable duty cycle and dead time is output through the first output terminal DV1 and the second output terminal DV2 of the PWM control chip U3. The first MOSFET Q1 and the second MOSFET Q2 cause the primary coil of the transformer T1 to generate a corresponding square wave. Then, the secondary coil of the transformer T1 will generate a proportionally amplified square wave. The voltage output by the transformer T1 is then amplified by the voltage multiplier circuit to obtain the output voltage of the high-voltage power supply circuit.

[0054] In this embodiment of the invention, the transformer T1 can be selected according to actual needs, for example, a transformer with a transformer ratio of 500 or 1000 can be selected.

[0055] In one specific embodiment, refer to Figure 1 As shown, the voltage multiplier circuit can be a half-bridge voltage multiplier circuit, which includes a first diode D1, a second diode D2, a second capacitor C2, and a third capacitor C3.

[0056] The first diode D1 and the second diode D2 are connected in reverse parallel. The second capacitor C2 is connected to the third terminal of the transformer T1 and the common terminal of the first diode D1 and the second diode D2. The third capacitor C3 is connected between the anode of the first diode D1 and the cathode of the second diode D2. In this embodiment of the invention, through... Figure 1 The half-bridge voltage multiplier circuit shown can amplify the output voltage of transformer T1 by two times to obtain the output voltage HVOUT+. Those skilled in the art can also choose other methods to implement this voltage multiplier circuit according to actual circuit requirements, and can also change the type and specifications of the first diode D1, the second diode D2, the second capacitor C2, and the third capacitor C3. Figure 1 The amplification factor of the half-bridge voltage multiplier circuit shown can be described in detail in the relevant technical descriptions, and will not be repeated here.

[0057] Reference Figure 1 As shown, the high-voltage current circuit also includes a resistor matrix disposed between the voltage output terminal and the output terminal of the voltage multiplier circuit. This resistor matrix is ​​a current-limiting resistor matrix. By setting the current-limiting resistor matrix, a preset output voltage HVSOUT is obtained. By setting the resistor matrix, the current is limited to prevent short circuits and protect the high-voltage power supply and the device under test.

[0058] The resistor matrix described in this embodiment of the invention can be formed by connecting a series of relay switches and resistors in series and parallel. By controlling the on and off of different relay switches, the resistance value connected to the high-voltage power supply circuit can be controlled. The specific resistor matrix and the control method of its relay switches can be implemented according to the detailed description of related technologies, and will not be repeated here.

[0059] In this embodiment of the invention, reference is made to Figure 1 As shown, the first MOSFET Q1 is a PNP type MOSFET, and the second MOSFET Q2 is an NPN type MOSFET. The voltage input terminal continuously provides voltage to the gate of the first MOSFET Q1. To turn on the first MOSFET Q1, its gate needs to be at a low level. Since the first output terminal DV1 and the second output terminal DV2 of the SG3525 chip are non-inverting terminals, in order to control the first MOSFET Q1 and the second MOSFET Q2, an inverting circuit can also be connected to the second output terminal DV2. The inverting circuit inverts the output waveform of the second output terminal DV2, so that when the second output terminal DV2 is at a high level, the first MOSFET Q1 is turned on, and when the first output terminal DV1 is at a high level, the second MOSFET is turned on.

[0060] In one specific embodiment, refer to Figure 2 As shown, the inverting circuit includes: a fourth MOSFET Q4, a sixth resistor R6, and a seventh resistor R7;

[0061] The gate of the fourth MOS transistor Q4 is connected to the sixth resistor R6 between the gate and the second output terminal DV2 of the PWM control chip. The source of the fourth MOS transistor Q4 is grounded, and the source and gate of the fourth MOS transistor Q4 are connected to the seventh resistor R7. The drain of the fourth MOS transistor Q4 is connected to the gate of the first MOS transistor Q1.

[0062] In this embodiment of the invention, the fourth MOSFET Q4 can be a BS107A type MOSFET. Of course, those skilled in the art can also select other suitable MOSFETs based on the teachings of related technologies. In this embodiment of the invention, no specific limitation is made.

[0063] In one specific embodiment, refer to Figure 1 As shown, a third resistor R3 is connected between the inverting input terminal of the first operational amplifier U1 and the signal generator, and a fourth resistor R4 is connected between the inverting input terminal of the first operational amplifier U1 and the output terminal of the second operational amplifier U2.

[0064] In this embodiment of the invention, a Kirchhoff circuit is constructed based on the virtual ground characteristic of the operational amplifier input. The inverting input of the operational amplifier, i.e., node TP1, is at zero potential. According to Kirchhoff's Current Law (KCL), the sum of the currents in the third resistor R3 and the fourth resistor R4 is zero. Therefore, referring to... Figure 1 As shown, DA+ / R3 = -UTP4 / R4, as Figure 1As shown, since both the third resistor R3 and the fourth resistor R4 are 10KΩ precision resistors, the voltage at point TP4 is equal to -DV+, meaning the voltage at the output of the second operational amplifier U2 is -DA+. (Refer to...) Figure 1 As shown, the resistance of the first resistor R1 is much greater than the resistance of the second resistor R2. The second operational amplifier U2, together with the connected first resistor R1 and second resistor R2, forms an inverting attenuation circuit. According to Kirchhoff's law, HVOUT+ / R1 = DA+ / R2, therefore HVOUT+ = 200 * DA+. Thus, it can be seen that when DA+ is a constant value, HVOUT+ is also a constant value; when DA+ is a pulse voltage signal, HVOUT+ is also a pulse signal. In this embodiment of the invention, to ensure the reliability of the circuit, the width of the pulse voltage signal output by the signal generator, i.e., the DA+ pulse signal, can be set to be greater than 10µs.

[0065] In one specific embodiment, refer to Figure 1 As shown, an energy storage capacitor C5 is connected in parallel between the inverting input terminal and the output terminal of the second operational amplifier U2 to achieve the function of stabilizing the circuit.

[0066] In one specific embodiment, refer to Figure 1 As shown, the high-voltage power supply circuit further includes: a twelfth resistor R12 disposed between the gate and drain of the third MOS transistor Q3 and a thirteenth resistor R13 disposed between the gate of the third MOS transistor Q3 and the first operational amplifier U1.

[0067] In this embodiment of the invention, the third MOSFET Q3 is connected via the twelfth resistor R12 and the thirteenth resistor R13 to provide a bias voltage for Q3, ensuring its normal operation. Since the gate of the third MOSFET is connected to the output of the first operational amplifier U1 via the thirteenth resistor R13, the output of the second operational amplifier U2 and its inverting input are connected. The second operational amplifier U2, as the main operational amplifier of the high-voltage power supply circuit, forms a closed-loop circuit. The first operational amplifier U1 automatically adjusts the variable resistance region of the third MOSFET, ensuring the stability of the closed-loop circuit. Because the resistance values ​​of the first resistor R1 and the second resistor R2 are fixed, the attenuation factor of the inverting attenuation circuit formed by the second operational amplifier U2, the first resistor R1, and the second resistor R2 is fixed. Therefore, the source voltage (i.e., the voltage of the first MOSFET) is adjusted via the third MOSFET. Figure 1 The voltage at node TP3 in the middle section is used to realize the automatic adjustment of the loop voltage, which improves the adjustment accuracy of the circuit.

[0068] In one specific embodiment, refer to Figure 1As shown, a third diode D3 is also connected between the inverting input and output terminals of the first operational amplifier. By using the unidirectional conduction characteristic of the third diode D3, the output is ensured not to be biased towards the negative power supply, thus preventing the circuit output voltage from being too high.

[0069] In one specific embodiment, refer to Figure 1 As shown, a fourth capacitor C4 and a fifth resistor R5 are connected between the inverting input and output terminals of the first operational amplifier.

[0070] In one specific embodiment, refer to Figure 1 As shown, the high-voltage power supply circuit also includes an eighth resistor R8 disposed between the gate of the first MOS transistor and the input voltage terminal;

[0071] The ninth resistor R9 is set between the gate of the first MOS transistor and the drain of the fourth MOS transistor.

[0072] The tenth resistor R10 is disposed between the gate of the second MOS transistor and the input voltage terminal;

[0073] The eleventh resistor R11 is located between the gate of the second MOS transistor and the first input terminal of the PWM control chip.

[0074] In this embodiment of the invention, voltage division is achieved by setting voltage dividing resistors at the gates of the first MOS transistor and the second MOS transistor, thereby ensuring the stability of the circuit.

[0075] In one specific embodiment, refer to Figure 1 As shown, a bypass capacitor C6 is also connected between the voltage input terminal and the ground terminal to filter the circuit and reduce noise in the circuit; an electrolytic capacitor E1 is also connected between the voltage input terminal and the common terminal of the eighth resistor and the ground terminal to store energy in the circuit.

[0076] In one specific embodiment, refer to Figure 1 As shown, a resistor R14 is connected between the gate and source of the first MOSFET; a resistor R15 is also connected between the gate and source of the second MOSFET to achieve the function of stabilizing the circuit.

[0077] The high-voltage power supply circuit provided by this invention will be illustrated through a specific application below:

[0078] Reference Figure 3 The diagram shows the functional modules of the IR2110 half-bridge driver chip. Figure 4The diagram shows the time parameter testing circuit for the half-bridge driver chip IR2110. A high-voltage power supply provided in this embodiment is connected to the VS terminal of this time parameter testing circuit. A floating power supply is connected to the Vb terminal of the circuit, and excitation signal sources are connected to the HIN and LIN terminals to provide excitation signals. The output waveforms at the HO and LO terminals are measured. (Refer to...) Figure 5 The diagram shows a waveform representation of the measured switching time. By comparing the waveform of the excitation signal with the output waveform of the timing parameter test circuit, the turn-on time (ton), rise time (tr), turn-off time (toff), and fall time (tf) of the IR2110 chip can be obtained. Figure 5 As can be seen from the output waveform, the stability of the high-voltage power supply circuit provided in this embodiment of the invention meets the testing requirements of the actual device under test.

[0079] The high-voltage power supply circuit provided in this embodiment of the invention utilizes the virtual ground characteristic of the operational amplifier input terminal to form a Kirchhoff circuit. According to Kirchhoff's Current Law (KCL), the current at the inverting input terminal of the operational amplifier, i.e., node TP1, is zero. Therefore, the voltage at the output terminal of operational amplifier U4 can be adjusted according to the output voltage of the signal generator. Then, based on the first and second resistors connected to the second operational amplifier, an inverting proportional operation is performed to determine the voltage at the inverting input terminal of the second operational amplifier, i.e., the preset output voltage. Since the gate of the third MOSFET is connected to the output terminal of the first operational amplifier, a closed-loop circuit is formed between the output terminal and the inverting input terminal of the second operational amplifier. The first operational amplifier automatically adjusts the variable resistance region of the third MOSFET to ensure the stability of the closed-loop circuit. Furthermore, the source voltage of the first MOSFET is adjusted through the third MOSFET, achieving automatic adjustment of the loop voltage and improving the circuit's adjustment accuracy. A PWM control chip, in conjunction with a push-pull circuit composed of the first and second MOSFETs, drives the transformer, and a voltage multiplier circuit boosts the supply voltage to the preset output voltage. Based on actual voltage requirements, the constant voltage mode and pulse voltage mode can be switched by controlling the signal generator. The high voltage range of the output is controllable, which improves the current load capacity, the output accuracy is higher, and the overall circuit structure is simple and easy to operate.

[0080] In this embodiment of the invention, the specific specifications and models of the electrical components used are only one specific implementation method. Those skilled in the art can select appropriate electrical components to obtain the high-voltage power supply circuit of the present invention based on the description of the prior art. In this embodiment of the invention, the specific models of the electrical components used in the circuit are not specifically limited.

[0081] Example 2

[0082] Based on the same inventive concept, this embodiment of the invention also provides a high-voltage power supply device, including: the high-voltage power supply circuit described in embodiment 1 above.

[0083] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims and their equivalents, the invention is also intended to include these modifications and variations.

[0084] Unless otherwise specifically stated, terms such as processing, calculation, operation, determination, display, etc., may refer to the actions and / or processes of one or more processing or computing systems or similar devices that represent the manipulation and conversion of data representing physical (e.g., electronic) quantities within the registers or memory of the processing system into other data similarly representing physical quantities within the memory, registers, or other such information storage, transmission, or display devices of the processing system. Information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0085] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to the specific order or hierarchy described.

[0086] In the detailed description above, various features are combined together in a single embodiment to simplify this disclosure. This approach to disclosure should not be construed as reflecting an intention that embodiments of the claimed subject matter require more features than are explicitly stated in each claim. Rather, as reflected in the appended claims, the invention is presented with fewer features than all of the features in a single disclosed embodiment. Therefore, the appended claims are hereby explicitly incorporated into the detailed description, with each claim representing a separate preferred embodiment of the invention.

[0087] Those skilled in the art will also understand that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments herein can be implemented as electronic hardware, computer software, or a combination thereof. To clearly illustrate the interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps described above are generally described in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in alternative ways for each specific application; however, such implementation decisions should not be construed as departing from the scope of this disclosure.

[0088] The steps of the methods or algorithms described in conjunction with the embodiments herein can be directly embodied in hardware, software modules executed by a processor, or a combination thereof. The software modules can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium well known in the art. An exemplary storage medium is connected to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a user terminal. Alternatively, the processor and storage medium can exist as discrete components in the user terminal.

[0089] For software implementation, the techniques described in this application can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described in this application. This software code can be stored in memory units and executed by a processor. The memory units can be implemented within the processor or outside the processor; in the latter case, they are communicatively coupled to the processor via various means, as is well known in the art.

[0090] The foregoing description includes examples of one or more embodiments. It is certainly impossible to describe all possible combinations of components or methods in order to describe the above embodiments, but those skilled in the art will recognize that further combinations and arrangements of the various embodiments are possible. Therefore, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of the appended claims. Furthermore, the term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as interpreted when used as a conjunction in the claims. Additionally, the use of any term "or" in the specification of the claims is intended to mean "non-exclusive or."

Claims

1. A high-voltage power supply circuit, characterized in that, include: The signal generator, first operational amplifier, first MOSFET, second MOSFET, third MOSFET, transformer, voltage multiplier circuit, second operational amplifier, first capacitor, first resistor, second resistor, and PWM control chip; The non-inverting input of the first operational amplifier is grounded, the inverting input of the first operational amplifier is connected to the output of the signal generator and the output of the second operational amplifier, and the output of the first operational amplifier is connected to the gate of the third MOS transistor. The source of the third MOS transistor is connected to the input voltage terminal, and the drain of the third MOS transistor is connected to the source of the first MOS transistor. The gate of the first MOSFET is connected to the input voltage terminal and the second output terminal of the PWM control chip, and the drain of the first MOSFET is connected to the drain of the second MOSFET. The gate of the second MOSFET is connected to the first output terminal of the PWM control chip and grounded, and the drain of the second MOSFET is connected to the third terminal of the transformer and grounded. The first terminal of the transformer is connected between the drain of the first MOSFET and the drain of the second MOSFET, and the second and fourth terminals of the transformer are respectively connected to the input terminals of the voltage multiplier circuit. The output terminal of the voltage multiplier circuit is connected to the non-inverting input terminal of the second operational amplifier through a first capacitor, and is connected to the inverting input terminal of the second operational amplifier through a first resistor; The non-inverting input of the second operational amplifier is grounded, and a second resistor is connected between the inverting input and the output of the second operational amplifier; the resistance of the first resistor is greater than the resistance of the second resistor. The signal generator can output a preset constant voltage signal or a pulse voltage signal; The PWM control chip can output a preset square wave signal.

2. The circuit as described in claim 1, characterized in that, A third resistor is connected between the inverting input terminal of the first operational amplifier and the signal generator, and a fourth resistor is connected between the inverting input terminal of the first operational amplifier and the output terminal of the second operational amplifier.

3. The circuit as described in claim 1, characterized in that, The voltage multiplier circuit includes a first diode, a second diode, a second capacitor, and a third capacitor; The first diode and the second diode are connected in reverse parallel. The second capacitor is connected to the third terminal of the transformer and the common terminal of the first diode and the second diode. The third capacitor is connected between the anode of the first diode and the cathode of the second diode.

4. The circuit as described in claim 1, characterized in that, A third diode is connected between the inverting input and output of the first operational amplifier.

5. The circuit as described in claim 1, characterized in that, A fourth capacitor and a fifth resistor are connected between the inverting input and output of the first operational amplifier.

6. The circuit as described in claim 1, characterized in that, Also includes: The fourth MOSFET, the sixth resistor, and the seventh resistor; The gate of the fourth MOS transistor is connected to the second output terminal of the PWM control chip via the sixth resistor. The source of the fourth MOS transistor is grounded, and the source and gate of the fourth MOS transistor are connected via the seventh resistor. The drain of the fourth MOS transistor is connected to the gate of the first MOS transistor.

7. The circuit as described in claim 1, characterized in that, Also includes: An eighth resistor is disposed between the gate of the first MOS transistor and the input voltage terminal; A ninth resistor is disposed between the gate of the first MOS transistor and the drain of the fourth MOS transistor. The tenth resistor is disposed between the gate of the second MOS transistor and the input voltage terminal; The eleventh resistor is located between the gate of the second MOS transistor and the first input terminal of the PWM control chip.

8. The circuit as described in claim 1, characterized in that, Also includes: The twelfth resistor is disposed between the gate and drain of the third MOS transistor, and the thirteenth resistor is disposed between the gate of the third MOS transistor and the first operational amplifier.

9. The circuit as described in any one of claims 1-8, characterized in that, Also includes: A resistor matrix is ​​configured between the voltage output terminal and the output terminal of the voltage multiplier circuit.

10. A high-voltage power supply device, characterized in that, include: The high-voltage power supply circuit according to any one of claims 1-9.

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