A reference clock signal generating device

Abstract

This invention provides a reference clock signal generator, comprising a reference signal source, an analog phase-locked loop (PLL), an auxiliary PLL, a first multiplexer switch, a first voltage-controlled oscillator (VCO), and a microcontroller. First, the auxiliary PLL controls the high-frequency oscillator to output the required frequency based on the reference signal and feedback signal. Once the auxiliary PLL has completed signal locking, the switch is switched to allow the analog PLL to control the high-frequency oscillator to output the final clock reference signal based on the reference signal and feedback signal. This invention uses a passive analog PLL to control the high-frequency oscillator's clock signal output, thereby overcoming the noise floor limitations of digital PLL chips and significantly reducing the phase noise of the clock reference signal.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to a reference clock signal generating device. Background Technology

[0002] With the development of technologies such as digital communication, radar, information warfare, and electronic countermeasures, the demand for signal sources with higher performance indicators is increasing. Among these, phase noise is a very critical indicator, often becoming a limiting factor for improving system performance. Therefore, reducing the phase noise of signal sources has become a very important direction in signal source design.

[0003] There are three ways to implement a signal source. Regardless of which method is used, the phase noise of the reference source plays a decisive role in the phase noise of the frequency source. Therefore, a low-phase-noise clock reference is a prerequisite for a signal source to achieve low phase noise.

[0004] By employing phase-locked loop (PLL) frequency synthesis, without considering the inherent noise floor of the PLL chip, the near-end phase noise of the clock reference is determined by the near-end phase noise of the low-frequency crystal oscillator, while the far-end phase noise of the clock reference is consistent with the far-end phase noise of the high-frequency crystal oscillator. This achieves the splicing of near-end and far-end phase noise, thereby improving the phase noise of the clock reference.

[0005] However, with technological advancements, the requirements for phase noise of clock references are becoming increasingly stringent. At this point, the noise floor of digital phase-locked loop (PLL) chips can no longer be ignored, especially the noise floor near the PLL's end, which has become a key factor limiting the phase noise of the clock reference. Therefore, how to overcome the limitations of digital PLL chip noise floor to reduce the phase noise of the clock reference has become an urgent problem to be solved. Summary of the Invention

[0006] The present invention provides a reference clock signal generating device to solve the above-mentioned technical problems, which can get rid of the limitation of the noise floor of digital phase-locked loop chips and reduce the phase noise of the clock reference.

[0007] This invention provides a reference clock signal generating device, including a reference signal source, an analog phase-locked loop, an auxiliary phase-locked loop, a first multiplexer, a first voltage-controlled oscillator, and a microcontroller;

[0008] The reference signal source is used to transmit the reference signal to the analog phase-locked loop and the auxiliary phase-locked loop respectively through the first signal distributor;

[0009] The output terminal of the simulated phase-locked loop and the output terminal of the auxiliary phase-locked loop are respectively connected to the first input terminal and the second input terminal of the first multiplexer switch;

[0010] The auxiliary phase-locked loop is used to generate an initial control voltage based on the reference signal and the first feedback signal output by the first voltage-controlled oscillator, and transmits the initial control voltage to the voltage control terminal of the first voltage-controlled oscillator through the first multiplexer switch.

[0011] The microcontroller is used to perform signal lock detection on the output signal of the auxiliary phase-locked loop. When the signal lock is detected and determined to be completed by the auxiliary phase-locked loop, the microcontroller controls the first multiplexer switch to switch to the analog phase-locked loop. The microcontroller is also used to configure the parameters of the auxiliary phase-locked loop.

[0012] The analog phase-locked loop is used to output a control signal through an analog phase detector based on the reference signal and the second feedback signal output by the first voltage-controlled oscillator, and transmit the control signal to the voltage control terminal of the first voltage-controlled oscillator through the first multiplexer, so that the first voltage-controlled oscillator outputs a clock signal based on the control signal.

[0013] Furthermore, the reference signal source includes a first reference source circuit, a second reference source circuit, and a second multiplexer switch; the output terminals of the first reference source circuit and the second reference source circuit are respectively connected to the first input terminal and the second input terminal of the second multiplexer switch, and the output terminal of the second multiplexer switch is connected to the output terminal of the reference signal source through a reference signal output circuit;

[0014] The first reference source circuit is used to filter the received external reference signal and then transmit it to the reference signal output circuit through the second multiplexer switch;

[0015] The second reference source circuit is used to generate an internal reference signal through a second voltage-controlled oscillator, and transmit the internal reference signal to the reference signal output circuit through the second multiplexer switch; wherein, the control voltage of the second voltage-controlled oscillator is obtained by filtering the voltage signal output by the DAC;

[0016] The microcontroller is also used to switch the second multiplexer switch based on the magnitude of the external reference signal transmitted by the first reference source circuit.

[0017] Furthermore, the microcontroller is also used to perform signal lock detection on the output signal of the analog phase-locked loop. When it is detected and determined that the analog phase-locked loop has lost signal lock, it controls the first multiplexer switch to switch to the auxiliary phase-locked loop.

[0018] Furthermore, the output terminal of the first voltage-controlled oscillator is connected to a second signal distributor; wherein, the first voltage-controlled oscillator outputs the first feedback signal through the first output terminal of the second signal distributor, the first voltage-controlled oscillator outputs the second feedback signal through the second output terminal of the second signal distributor, and the first voltage-controlled oscillator outputs the clock signal through the third output terminal of the second signal distributor.

[0019] Furthermore, the third output terminal of the second signal distributor is connected to a power divider, which is used to divide the clock signal output by the first voltage-controlled oscillator through the third output terminal of the second signal distributor into multiple paths.

[0020] Furthermore, the first signal distributor is a power divider or a coupler, and the second signal distributor is a power divider or a coupler.

[0021] Furthermore, the first reference source circuit is specifically used to sequentially filter, amplify, and filter the received external reference signal, and then transmit it to the reference signal output circuit through the second multiplexer switch.

[0022] Furthermore, the reference signal output circuit includes a first filter, a first amplifier, a frequency multiplier, a second filter, and a second amplifier connected in series.

[0023] Furthermore, the frequency multiplier is an adjustable frequency multiplier, and the frequency modulation factor of the adjustable frequency multiplier is determined based on the ratio of the frequency of the input reference signal of the adjustable frequency multiplier to the preset output frequency.

[0024] Furthermore, the first voltage-controlled oscillator is a temperature-controlled crystal oscillator or a surface acoustic wave oscillator.

[0025] The reference clock signal generating device provided by the present invention first uses an auxiliary phase-locked loop to control a high-frequency oscillator to output the required frequency based on a reference signal and a feedback signal. When the auxiliary phase-locked loop is detected to have completed signal locking, the switch is switched to use an analog phase-locked loop to control the high-frequency oscillator to output the final clock reference signal based on the reference signal and the feedback signal.

[0026] This invention uses a passive analog phase-locked loop to control the output clock signal of a high-frequency oscillator, thereby overcoming the limitation of the noise floor of digital phase-locked loop chips and greatly reducing the phase noise of the clock reference signal. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 This is one of the structural schematic diagrams of the reference clock signal generating device provided in the embodiments of the present invention;

[0029] Figure 2 This is a second schematic diagram of the structure of the reference clock signal generating device provided in the embodiment of the present invention;

[0030] Figure 3 This is the third schematic diagram of the reference clock signal generating device provided in the embodiment of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0032] like Figure 1 As shown, an embodiment of the present invention provides a reference clock signal generating device, including a reference signal source, an analog phase-locked loop, an auxiliary phase-locked loop, a first multiplexer, a first voltage-controlled oscillator, and a microcontroller;

[0033] The reference signal source is used to transmit the reference signal to the analog phase-locked loop and the auxiliary phase-locked loop respectively through the first signal distributor;

[0034] The output terminal of the simulated phase-locked loop and the output terminal of the auxiliary phase-locked loop are respectively connected to the first input terminal and the second input terminal of the first multiplexer switch;

[0035] The auxiliary phase-locked loop is used to generate an initial control voltage based on the reference signal and the first feedback signal output by the first voltage-controlled oscillator, and transmits the initial control voltage to the voltage control terminal of the first voltage-controlled oscillator through the first multiplexer switch.

[0036] The microcontroller is used to perform signal lock detection on the output signal of the auxiliary phase-locked loop. When the signal lock is detected and determined to be completed by the auxiliary phase-locked loop, the microcontroller controls the first multiplexer switch to switch to the analog phase-locked loop. The microcontroller is also used to configure the parameters of the auxiliary phase-locked loop.

[0037] The analog phase-locked loop is used to output a control signal through an analog phase detector based on the reference signal and the second feedback signal output by the first voltage-controlled oscillator, and transmit the control signal to the voltage control terminal of the first voltage-controlled oscillator through the first multiplexer, so that the first voltage-controlled oscillator outputs a clock signal based on the control signal.

[0038] Furthermore, the first voltage-controlled oscillator is a temperature-controlled crystal oscillator or a surface acoustic wave oscillator.

[0039] In this embodiment of the invention, the reference signal is split into two paths by a first signal distributor. One path is input to the analog phase-locked loop (PLL) as a reference signal, and the other path is input to the auxiliary PLL as a reference signal. The outputs of the analog PLL and the auxiliary PLL are respectively connected to a first multiplexer switch, which selects one of the two input signals for output by switching.

[0040] It should be noted that, during operation, the circuit of this invention first utilizes the digital phase detector of the auxiliary phase-locked loop (PLL) to output a corresponding control voltage based on the frequency difference between the reference signal and the feedback signal. After passing through the corresponding loop filter, this voltage is output to the voltage-controlled terminal of the high-frequency oscillator (first voltage-controlled oscillator), enabling the high-frequency oscillator to output the required frequency. When the microcontroller detects that the auxiliary PLL has completed signal locking, it switches to the analog PLL and simultaneously disconnects the auxiliary PLL to prevent interference with the analog PLL. After frequency discrimination and phase locking by the digital phase detector, the reference signal and the high-frequency oscillator frequency are now the same. The analog phase detector of the analog PLL outputs a corresponding control signal based on the phase difference between the reference signal and the feedback signal. After passing through the corresponding loop filter, this control signal is output to the voltage-controlled terminal of the high-frequency oscillator, enabling the high-frequency oscillator to output the required frequency. The microcontroller detects the analog PLL lock signal, indicating that the clock reference has been locked and normal operation is possible. The high-frequency oscillator output provides the clock reference signal for the signal source.

[0041] This invention uses a passive analog phase-locked loop to control the output clock signal of a high-frequency oscillator, thereby overcoming the limitation of the noise floor of digital phase-locked loop chips and greatly reducing the phase noise of the clock reference signal.

[0042] Please see Figure 2In this embodiment of the invention, the reference signal source further includes a first reference source circuit, a second reference source circuit, and a second multiplexer; the output terminal of the first reference source circuit and the output terminal of the second reference source circuit are respectively connected to the first input terminal and the second input terminal of the second multiplexer, and the output terminal of the second multiplexer is connected to the output terminal of the reference signal source through a reference signal output circuit;

[0043] The first reference source circuit is used to filter the received external reference signal and then transmit it to the reference signal output circuit through the second multiplexer switch;

[0044] The second reference source circuit is used to generate an internal reference signal through a second voltage-controlled oscillator and transmit the internal reference signal to the reference signal output circuit through the second multiplexer switch; wherein, the control voltage of the second voltage-controlled oscillator is obtained by filtering the voltage signal output by the DAC; further, the reference signal output circuit is connected in series with a first filter, a first amplifier, a frequency multiplier, a second filter, and a second amplifier.

[0045] The microcontroller is also used to switch the second multiplexer switch based on the magnitude of the external reference signal transmitted by the first reference source circuit.

[0046] In this embodiment, the reference signal source includes a first reference source circuit and a second reference source circuit. The first reference source circuit is used to transmit an external reference signal, and the second reference source circuit is used to transmit an internal reference signal. The outputs of the first and second reference source circuits are respectively connected to a second multiplexer switch. The second multiplexer switch selects one of the two input signals for output by switching the input signal. During operation, the microcontroller can monitor the output of the external reference signal and switch the switch according to the magnitude of the external reference signal. For example, if the microcontroller does not detect an external reference signal output from the first reference source circuit after filtering the external reference signal, it switches to the second reference source circuit, which generates the internal reference signal using a low-frequency oscillator. The internal reference signal is generated using an ultra-low phase noise low-frequency oscillator, and the power supply needs to be filtered. The control voltage is controlled by a DAC, and the DAC output needs to be specially filtered to prevent the oscillator from being affected by DAC noise.

[0047] In this embodiment of the invention, the microcontroller is further configured to perform signal lock detection on the output signal of the analog phase-locked loop, and when it is detected and determined that the analog phase-locked loop has lost signal lock, control the first multiplexer switch to switch to the auxiliary phase-locked loop.

[0048] In this embodiment of the invention, after the circuit is working normally, when the simulated phase-locked loop is detected to be out of lock, the switch is switched to the auxiliary phase-locked loop to re-lock the signal, and then switched back to the simulated phase-locked loop to continue working.

[0049] In this embodiment of the invention, the output terminal of the first voltage-controlled oscillator is further connected to a second signal distributor; wherein, the first voltage-controlled oscillator outputs the first feedback signal through the first output terminal of the second signal distributor, the first voltage-controlled oscillator outputs the second feedback signal through the second output terminal of the second signal distributor, and the first voltage-controlled oscillator outputs the clock signal through the third output terminal of the second signal distributor.

[0050] It should be noted that the first voltage-controlled oscillator can distribute the output signal through the second signal distributor. The second signal distributor can be divided into three paths: the first path is used to output the first feedback signal to the auxiliary phase-locked loop, the second path is used to output the second feedback signal to the analog phase-locked loop, and the third path is used to output the final clock signal.

[0051] In this embodiment of the invention, the third output terminal of the second signal distributor is further connected to a power divider, which is used to divide the clock signal output by the first voltage-controlled oscillator through the third output terminal of the second signal distributor into multiple paths.

[0052] It should be noted that the clock signal output by the high-frequency oscillator can be further divided into multiple paths by a power divider. Each clock signal is amplified and filtered before being output to provide a clock reference signal for the signal source.

[0053] In this embodiment of the invention, the first signal distributor is a power divider or a coupler, and the second signal distributor is a power divider or a coupler.

[0054] It should be noted that, for the first signal distributor and the second signal distributor in the embodiments of the present invention, a power divider or a coupler can be selected to distribute and output the signal.

[0055] In this embodiment of the invention, the first reference source circuit is specifically used to filter, amplify and filter the received external reference signal in sequence, and then transmit it to the reference signal output circuit through the second multiplexer switch.

[0056] It should be noted that the first reference source circuit can filter, amplify, and then output the received external reference signal through the second multiplexer to further reduce the noise of the external reference signal.

[0057] In this embodiment of the invention, the frequency multiplier is further described as an adjustable frequency multiplier, and the frequency modulation factor of the adjustable frequency multiplier is determined based on the ratio of the frequency of the input reference signal of the adjustable frequency multiplier to a preset output frequency.

[0058] It should be noted that, in this embodiment of the invention, the reference signal after the switch is filtered, then amplified, and then enters the frequency multiplier; the multiplier is adjustable, and the frequency multiplier can be determined according to the ratio of the reference frequency to the output frequency; after frequency multiplication, it is filtered, amplified, and then output.

[0059] The main key features of the reference clock signal generator in this embodiment of the invention are as follows:

[0060] 1. The analog phase-locked loop (PLL) scheme is adopted. The analog phase detector in the analog PLL does not have internal frequency dividers, charge pumps, or other circuits. Therefore, it is not affected by the noise floor of components such as digital phase detectors, frequency dividers, and charge pumps contained in ordinary PLL chips. Furthermore, the analog phase detector does not require power supply and is not affected by power supply noise. As a result, the noise floor of the analog phase detector is much lower than the phase noise of the reference signal. Therefore, the phase noise of the final output of the clock reference is only related to the reference signal and is not related to the noise floor of the PLL.

[0061] 2. Using a low-frequency oscillator with ultra-low phase noise can further achieve low phase noise. This is because the near-end noise value of the clock reference signal depends on the reference noise, which in turn depends on the near-end phase noise of the low-frequency oscillator.

[0062] 3. Using an ultra-low phase noise high-frequency oscillator can further achieve low phase noise. This is because the far-end noise value of the clock reference signal depends on the far-end phase noise of the high-frequency oscillator.

[0063] 4. The power supply to the oscillator needs to be filtered; the frequency modulation pin of the low-frequency oscillator is controlled by the output voltage of the DAC, and the DAC output needs to be specially filtered to avoid the oscillator being affected by noise interference from the DAC.

[0064] 5. The analog phase detector in the analog phase-locked loop scheme can only detect phase, not frequency. When the oscillator is first started, the phase detector of the analog phase-locked loop cannot work properly because there is a frequency difference between the reference signal and the feedback signal. Therefore, an auxiliary phase-locked loop needs to be added first to assist in locking, so that the reference signal and the feedback signal are in the same frequency, and then switch to the analog phase-locked loop to finally achieve analog phase-locked output.

[0065] 6. The auxiliary phase-locked loop has a locking indication function. It can only be switched to the analog phase-locked loop after the auxiliary loop is locked.

[0066] 7. Simulated phase-locked loop with lockout indication function. As long as the lockout voltage is within the preset range, the simulated phase-locked loop can be considered to be locked.

[0067] Please see Figure 3 Based on the above scheme, in order to better understand the reference clock signal generating device provided in the embodiments of the present invention, specific examples are listed below for detailed description:

[0068] The reference signal source has an automatic switching function between internal and external references. After the external reference input is amplified and filtered, the input signal is detected. If an input signal is detected, the system switches to the external reference. If no input signal is detected, the system switches to the internal reference and uses an internal low-frequency oscillator as the reference signal. The switching between internal and external references is achieved by using a switch (the switching logic can also be set to a certain signal strength threshold to determine the magnitude of the external reference signal. If the signal strength is less than the threshold, the system switches to the internal reference).

[0069] The internal reference signal of the phase-locked loop uses a low-frequency oscillator with ultra-low phase noise, and the power supply needs to be filtered; the control voltage is controlled by a DAC, and the DAC output needs to be specially filtered to avoid the oscillator being affected by DAC noise.

[0070] For high-frequency oscillators, either a temperature-controlled crystal oscillator or a surface acoustic wave (SAW) oscillator can be selected based on the required clock reference frequency range, both of which can achieve the best far-end phase noise.

[0071] The reference signal after the second multiplexer is filtered and then amplified. After amplification, it enters the frequency multiplier. The multiplication factor is adjustable and depends on the ratio of the reference frequency to the output frequency. After frequency multiplication, the signal is filtered and amplified again. After amplification, the signal is divided or coupled to split it into two paths. One path enters the analog phase-locked loop as a reference signal, and the other path enters the auxiliary phase-locked loop as a reference signal.

[0072] The phase-locked loop (PLL) outputs a control voltage, which is sent to the voltage-controlled terminal of a high-frequency oscillator (VLO) to enable the oscillator to output the required frequency. The oscillator output is then divided into three paths via a power divider or coupling. The first path is input to an analog PLL as its feedback signal. The second path is input to an auxiliary PLL as its feedback signal. The third path outputs to a lower-level power divider, resulting in four paths of power distribution. After amplification and filtering, the output provides a clock reference signal for the signal source. The auxiliary PLL includes a digital PLL and a loop filter, while the analog PLL includes an analog phase detector and a loop filter. The loop filter can be either a passive or active filter, depending on the requirements.

[0073] When in operation, the switch is first switched to the auxiliary phase-locked loop. The auxiliary phase-locked loop is set according to the frequency division ratio of 1. The phase detector of the auxiliary phase-locked loop outputs the corresponding control voltage based on the frequency difference between the reference signal and the feedback signal. After passing through the corresponding loop filter, the voltage is output to the voltage control terminal of the high-frequency oscillator, so that the high-frequency oscillator outputs the required frequency.

[0074] After the controller detects the auxiliary loop lock signal, it switches to the analog phase-locked loop and simultaneously shuts down the auxiliary phase-locked loop to prevent interference with the analog phase-locked loop. At this time, the frequency-multiplied reference signal and the high-frequency oscillator have the same frequency. The analog phase detector of the analog phase-locked loop outputs the corresponding control signal based on the phase difference between the reference signal and the feedback signal. After passing through the corresponding loop filter, the control signal is output to the voltage-controlled terminal of the high-frequency oscillator, enabling the high-frequency oscillator to output the required frequency. The controller detects the analog phase-locked loop lock signal, indicating that the clock reference has been locked and the system can operate normally.

[0075] When the controller detects that the analog phase-locked loop has lost lock, it re-executes the previous step, that is, switches to the auxiliary loop, locks the auxiliary loop, and then switches back to the analog loop to lock it again.

[0076] The key to achieving low phase noise in the reference clock signal generation device of this invention lies in the ultra-low phase noise low-frequency oscillator, ultra-low phase noise high-frequency oscillator, analog phase detector, and auxiliary phase-locked loop (PLL). Without the auxiliary PLL, the system cannot function properly. Since the analog phase detector lacks internal frequency dividers, charge pump circuits, etc., and is a passive device requiring no power supply and unaffected by power supply noise, its noise floor is extremely low, far lower than the phase noise of the reference and high-frequency signals. Therefore, the final PLL phase noise is only related to the oscillator phase noise and is independent of the PLL noise floor, ensuring that the phase noise of the clock reference output signal is unaffected by the PLL noise floor. Thus, this invention overcomes the limitation of digital PLL chip noise floor and significantly reduces the phase noise of the clock reference signal.

[0077] In the embodiments of this invention, the terms "first," "second," etc., are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same class, without limiting the number of objects; for example, the first object can be one or more.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A reference clock signal generator, characterized in that, It includes a reference signal source, an analog phase-locked loop, an auxiliary phase-locked loop, a first multiplexer, a first voltage-controlled oscillator, and a microcontroller; The reference signal source is used to transmit the reference signal to the analog phase-locked loop and the auxiliary phase-locked loop respectively through the first signal distributor; The output terminal of the analog phase-locked loop and the output terminal of the auxiliary phase-locked loop are respectively connected to the first input terminal and the second input terminal of the first multiplexer; wherein, the analog phase-locked loop includes an analog phase detector and a loop filter, and the auxiliary phase-locked loop includes a digital phase-locked loop and a loop filter; The auxiliary phase-locked loop is used to generate an initial control voltage based on the reference signal and the first feedback signal output by the first voltage-controlled oscillator, and transmits the initial control voltage to the voltage control terminal of the first voltage-controlled oscillator through the first multiplexer switch. The microcontroller is used to perform signal lock detection on the output signal of the auxiliary phase-locked loop. When the auxiliary phase-locked loop completes signal lock, it controls the first multiplexer switch to switch to the analog phase-locked loop and disconnects the auxiliary phase-locked loop to prevent the auxiliary phase-locked loop from interfering with the analog phase-locked loop. The microcontroller is also used to configure the parameters of the auxiliary phase-locked loop. The analog phase-locked loop is used to output a control signal through an analog phase detector based on the reference signal and the second feedback signal output by the first voltage-controlled oscillator, and transmit the control signal to the voltage control terminal of the first voltage-controlled oscillator through the first multiplexer, so that the first voltage-controlled oscillator outputs a clock signal based on the control signal.

2. The reference clock signal generating device according to claim 1, characterized in that, The reference signal source includes a first reference source circuit, a second reference source circuit, and a second multiplexer switch; The output terminals of the first reference source circuit and the second reference source circuit are respectively connected to the first input terminal and the second input terminal of the second multiplexer switch, and the output terminal of the second multiplexer switch is connected to the output terminal of the reference signal source through a reference signal output circuit; The first reference source circuit is used to filter the received external reference signal and then transmit it to the reference signal output circuit through the second multiplexer switch; The second reference source circuit is used to generate an internal reference signal through a second voltage-controlled oscillator, and transmit the internal reference signal to the reference signal output circuit through the second multiplexer switch; wherein, the control voltage of the second voltage-controlled oscillator is obtained by filtering the voltage signal output by the DAC; The microcontroller is also used to switch the second multiplexer switch based on the magnitude of the external reference signal transmitted by the first reference source circuit.

3. The reference clock signal generating device according to claim 1, characterized in that, The microcontroller is also used to perform signal lock detection on the output signal of the analog phase-locked loop. When it is detected and determined that the analog phase-locked loop has lost signal lock, it controls the first multiplexer switch to switch to the auxiliary phase-locked loop.

4. The reference clock signal generating device according to claim 1, characterized in that, The output terminal of the first voltage-controlled oscillator is connected to a second signal distributor; wherein, the first voltage-controlled oscillator outputs the first feedback signal through the first output terminal of the second signal distributor, the first voltage-controlled oscillator outputs the second feedback signal through the second output terminal of the second signal distributor, and the first voltage-controlled oscillator outputs the clock signal through the third output terminal of the second signal distributor.

5. The reference clock signal generating device according to claim 4, characterized in that, The third output terminal of the second signal distributor is connected to a power divider, which is used to divide the clock signal output by the first voltage-controlled oscillator through the third output terminal of the second signal distributor into multiple channels.

6. The reference clock signal generating device according to claim 4, characterized in that, The first signal distributor is a power divider or a coupler, and the second signal distributor is a power divider or a coupler.

7. The reference clock signal generating device according to claim 2, characterized in that, The first reference source circuit is specifically used to filter, amplify, and filter the received external reference signal in sequence, and then transmit it to the reference signal output circuit through the second multiplexer switch.

8. The reference clock signal generating device according to claim 2, characterized in that, The reference signal output circuit consists of a first filter, a first amplifier, a frequency multiplier, a second filter, and a second amplifier connected in series.

9. The reference clock signal generating device according to claim 8, characterized in that, The frequency multiplier is an adjustable frequency multiplier, and the frequency multiplication factor of the adjustable frequency multiplier is determined based on the ratio of the frequency of the input reference signal of the adjustable frequency multiplier to the preset output frequency.

10. The reference clock signal generating apparatus according to any one of claims 1-9, characterized in that, The first voltage-controlled oscillator is a temperature-controlled crystal oscillator or a surface acoustic wave oscillator.

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