Calibration apparatus, method and lidar for pipelined analog-to-digital conversion circuit

Abstract

The application discloses a calibration device and method for a pipeline analog-digital conversion circuit and a laser radar, wherein the analog-digital conversion circuit comprises a pipeline analog-digital conversion circuit, the pipeline analog-digital conversion circuit comprises a front-end conversion module with at least one conversion module and a back-end conversion module with at least one conversion module, and the calibration method comprises the following steps: inputting a test analog signal into the pipeline analog-digital conversion circuit, so that the front-end conversion module receives the test analog signal and outputs a corresponding analog residual error signal to the back-end conversion module; acquiring residual error digital information corresponding to the analog residual error signal; and judging whether the gain of the front-end conversion module has a deviation according to the residual error digital information. By adopting the above scheme, the gain of the pipeline analog-digital conversion circuit is verified, the effective gain error is calibrated, the accuracy of the pipeline analog-digital conversion circuit is improved, and the power consumption requirement under the same accuracy is reduced.

Description

Technical Field

[0001] This specification relates to the field of integrated circuit technology, and in particular to a calibration device, method, and lidar for pipelined analog-to-digital converter circuits. Background Technology

[0002] Many physical quantities in nature (such as speed, pressure, temperature, sound, etc.) change continuously over time and take continuous values ​​in amplitude. Such continuously changing physical quantities are called analog quantities, and the signals that represent analog quantities are called analog signals.

[0003] Another type of physical quantity corresponding to analog quantities is called digital quantities. These are values ​​acquired at a series of discrete moments, and their magnitudes and increases or decreases are integer multiples of the quantization. In other words, they are a series of signals that are discrete in both time and value. Signals representing digital quantities are called digital signals.

[0004] With the widespread use of computers, most electronic systems use computers to process signals. However, computers cannot directly process analog signals, only digital signals. Therefore, it is necessary to convert analog signals into digital signals, which led to the development of analog-to-digital (A / D) conversion technology. The circuit that converts analog signals into digital signals can be called an analog-to-digital converter circuit.

[0005] The analog-to-digital conversion process mainly includes: 1) During the sampling phase, the analog signal is sampled to obtain a time-discrete, amplitude-continuous analog sampled signal. Here, amplitude continuity means that the amplitude is not quantized and is still the same as the amplitude of the analog signal; 2) During the hold phase, the amplitude of the analog signal (i.e., the sampled value) when switching from the sampling phase to the hold phase is held to obtain a time-discrete analog hold signal with the sampled value as the amplitude. A quantization unit is selected, and the sampled value is divided by the quantization unit and rounded to the integer to realize signal quantization (digitization) and obtain a time-discrete and numerically discrete digital quantity; 3) The digital quantity is encoded to obtain the corresponding thermometer code and form a digital signal.

[0006] To facilitate computer use, a binary encoding method is generally used to obtain a thermometer code of a certain number of bits. The number of bits in the thermometer code is usually used to represent the number of bits in the digital signal, such as a 10-bit digital signal. The more bits used in the digital signal, the more accurately it reflects the analog signal.

[0007] In the quantization process of analog-to-digital conversion, multiple comparators are typically used to compare the analog hold signal to obtain the quantization result. Therefore, with other parameters remaining constant, the more comparators there are, the higher the quantization accuracy and the more accurate the output digital signal. However, due to limitations in space layout, cost, performance, and other factors, simply increasing the number of comparators cannot yield a digital signal with more bits.

[0008] For example, to convert an analog signal into a 10-bit digital signal, in principle, one could use 1023 comparators to output 1024 digital values, and then encode these digital values ​​to obtain a 10-bit digital signal. However, a 10-bit digital signal would require thousands of comparators, making this approach impractical in real-world scenarios.

[0009] To obtain digital signals with more bits per second using a given number of comparators, the structure of analog-to-digital (ADC) circuits has been optimized, resulting in various types such as successive approximation, integrating, voltage-to-frequency conversion, hierarchical, and pipelined ADCs. Successive approximation, integrating, and voltage-to-frequency conversion ADCs are mainly used in low-to-medium speed, low-precision ADC scenarios. Hierarchical and pipelined ADCs, on the other hand, can be used in faster, higher-precision ADC scenarios, such as high-speed transient signal processing.

[0010] The pipelined analog-to-digital converter (ADC) circuit contains a hierarchical quantization structure, using multiple low-precision conversion modules to perform sampling, quantization, and encoding conversions. Each conversion module utilizes a small number of comparators to achieve fast analog-to-digital conversion at that level, making it the mainstream choice for achieving high-speed, high-precision ADCs.

[0011] In a pipelined analog-to-digital converter (ADC) circuit, after completing the conversion, the current conversion module needs to subtract the analog component acquired at this stage from the received signal and amplify the result to a level suitable for the next stage's conversion. However, in practice, due to the finite gain error, the actual gain (i.e., the actual amplification factor) may deviate from the theoretical gain (i.e., the theoretical amplification factor), increasing the error in subsequent processing and affecting the accuracy of the pipelined ADC circuit's output.

[0012] The current solution is to sacrifice circuit power consumption to provide higher gain (i.e., amplification factor) and bandwidth. Although this reduces the impact of finite gain error to some extent, it still cannot guarantee accurate output results from pipelined analog-to-digital converter circuits. Summary of the Invention

[0013] In view of this, embodiments of this specification provide a calibration device, method, and lidar for pipelined analog-to-digital converter circuits, which enables gain verification of pipelined analog-to-digital converter circuits, facilitates calibration of effective gain error, thereby improving the accuracy of pipelined analog-to-digital converter circuits and reducing power consumption requirements for the same accuracy.

[0014] This specification provides a calibration method for an analog-to-digital conversion circuit, wherein the analog-to-digital conversion circuit includes a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit includes a front-end conversion module having at least one conversion module and a back-end conversion module having at least one conversion module, and the calibration method includes: The test analog signal is input into the pipeline-type analog-to-digital converter circuit so that the front-end conversion module receives the test analog signal and outputs the corresponding analog residual signal to the back-end conversion module; Obtain the residual digital information corresponding to the analog residual signal; Based on the residual digital information, determine whether there is a deviation in the gain of the front-end conversion module.

[0015] This specification also provides a calibration device for an analog-to-digital conversion circuit. The analog-to-digital conversion circuit includes a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit includes a front-end conversion module having at least one conversion module, a back-end conversion module having at least one conversion module, and a digital calculation module. The digital calculation module is adapted to calculate output digital information based on the thermometer code and corresponding digital domain weights output by each conversion module. The calibration device includes: The signal generation module is adapted to generate a test analog signal and input the test analog signal into the pipelined analog-to-digital converter circuit, so that the front-end conversion module receives the test analog signal and outputs a corresponding analog residual signal to the back-end conversion module; The deviation detection module is adapted to acquire residual digital information corresponding to the analog residual signal, and determine whether there is a deviation in the gain of the front-end conversion module based on the residual digital information.

[0016] This specification also provides a lidar system, comprising: a detection device, an analog-to-digital conversion circuit, and a calibration device as described in any of the above embodiments; wherein: The detection device is adapted to acquire echo signals and output analog signals to be processed to the analog-to-digital conversion circuit. The analog-to-digital conversion circuit is adapted to perform analog-to-digital conversion on the analog signal to be processed by the detection device or the test analog signal of the calibration device; it includes a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit includes a front-end conversion module with at least one conversion module, a back-end conversion module with at least one conversion module, and a digital computing module; The calibration device is adapted to calibrate the pipeline-type analog-to-digital converter circuit based on the generated test simulation signal.

[0017] The calibration method for analog-to-digital converter circuits provided in the embodiments of this specification converts the analog residual signal measurement in the analog domain into the calculation of residual digital information in the digital domain. The gain of the front-end conversion module is then verified using the residual digital information, thereby avoiding secondary errors generated by measuring the analog residual signal and improving the calibration accuracy of the effective gain error. Furthermore, the calibration method provided in the embodiments of this specification is implemented based on the existing hardware architecture of pipelined analog-to-digital converter circuits. Combined with existing logic operation devices, it can achieve good calibration results, effectively reducing the hardware cost and implementation complexity required for calibration, improving the calibration response speed and execution speed, resulting in higher calibration efficiency and greater universality. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this specification, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of an existing pipeline-type analog-to-digital converter circuit.

[0020] Figure 2 This is a schematic diagram of the connection of an existing sub-analog-to-digital converter unit.

[0021] Figure 3 This is a connection diagram of an existing gain digital-to-analog converter unit.

[0022] Figure 4 It is an input-output graph of an existing conversion module.

[0023] Figure 5 yes Figure 4 The corresponding input-output curves after the gain of the conversion module is reduced.

[0024] Figure 6 This is a flowchart of a calibration method for an analog-to-digital conversion circuit as described in the embodiments of this specification.

[0025] Figure 7a This is a schematic diagram of another existing pipeline-type analog-to-digital converter circuit.

[0026] Figure 7b This is a schematic diagram of another existing pipeline-type analog-to-digital converter circuit.

[0027] Figure 8 This is a graph showing the input signal and digital residual information of the front-end conversion module in the embodiments of this specification.

[0028] Figure 9a This is a schematic diagram of an existing ramp generator circuit.

[0029] Figure 9b yes Figure 9a The waveform of the analog signal output by the ramp generator circuit shown is shown.

[0030] Figure 10 This is a structural diagram of an existing 12-bit precision pipelined analog-to-digital converter circuit.

[0031] Figure 11 This is a schematic diagram showing the connection between an analog-to-digital conversion circuit and a calibration device in one of the embodiments of this specification.

[0032] Figure 12 This is a structural diagram of a calibration device for an analog-to-digital conversion circuit, as described in the embodiments of this specification.

[0033] Figure 13 This is a structural diagram of a lidar system as described in the embodiments of this specification. Detailed Implementation

[0034] To enable those skilled in the art to better understand and implement the solutions provided in this specification, the following is a schematic description of existing pipeline-type analog-to-digital converter circuits in conjunction with the accompanying drawings and specific application scenarios.

[0035] refer to Figure 1 A schematic diagram of an existing pipelined analog-to-digital converter circuit is provided. In practical applications, such as... Figure 1 As shown, the pipelined analog-to-digital converter circuit P0 may include: a clock generation sub-circuit 01, a bandgap reference sub-circuit 02, a sample-and-hold amplifier module 03, N cascaded conversion modules, and a digital calculation module 04. The following sections describe each component of the pipelined analog-to-digital converter circuit P0.

[0036] The clock generation sub-circuit 01, which is the clock source of the pipelined analog-to-digital converter circuit P0, is adapted to generate multiple non-overlapping clock signals and provide multiple non-overlapping clock signals to the sample-and-hold amplifier module 03 and the stage conversion modules Stage1 to StageN respectively, thereby using different timing control to make the devices in the sample-and-hold amplifier module 03 and the stage conversion modules Stage1 to StageN work alternately.

[0037] The bandgap reference sub-circuit 02, which is the reference signal source of the pipelined analog-to-digital converter circuit P0, is adapted to generate reference current and reference voltage, and provide the generated reference current and reference voltage to the sample-and-hold amplifier module 03 and the conversion modules Stage1~StageN respectively.

[0038] Specifically, in an optional example, such as Figure 1 As shown, the bandgap reference sub-circuit 02 may include: a bandgap generation module 021, a reference current generation module 022, and a reference voltage generation module 023.

[0039] The bandgap generation module 021, namely the bandgap reference source of the pipelined analog-to-digital converter circuit P0, is suitable for providing temperature-insensitive reference electrical signals, such as reference voltage signals and reference current signals.

[0040] The reference current generation module 022, which is the reference current source of the pipelined analog-to-digital converter circuit P0, is adapted to generate a reference current based on the reference electrical signal and provide the generated reference current to the sample-and-hold amplifier module 03 and the conversion modules Stage1 to StageN respectively.

[0041] The reference voltage generation module 023, which is the reference voltage source of the pipelined analog-to-digital converter circuit P0, is adapted to generate a reference voltage based on the reference electrical signal and provide the generated reference voltage to the sample-and-hold amplifier module 03 and the conversion modules Stage1 to StageN respectively.

[0042] Furthermore, since the reference voltage is typically used to drive the capacitor, and the capacitor has charging and discharging times, in order to enable the capacitor to perform efficient charging and discharging operations and provide accurate setup time for the reference voltage generation module 023, the bandgap reference sub-circuit 02 may also include a reference voltage buffer module 024, adapted to buffer the reference voltage output by the reference voltage generation module 023. The reference voltage buffer module 024 may include a reference buffer.

[0043] Furthermore, since pipeline-type analog-to-digital converter circuits typically require two reference voltages of different levels, such as a positive reference voltage and a negative reference voltage, the reference voltage generation module 023 needs to perform level shifting to generate two reference voltages of different levels. Therefore, the reference voltage buffer module 024 ensures the accuracy and settling time of the reference voltage for the reference voltage generation module 023.

[0044] The sample-and-hold amplifier module 03 is adapted to sample the analog signal input to the pipelined analog-to-digital converter circuit P0 to obtain an analog hold signal VC, and stably maintain the amplitude of the analog hold signal VC until the next sampling stage arrives for the next sampling. This ensures that no time deviation occurs when subsequent cascaded conversion modules process the signal. The sample-and-hold amplifier module 03 may include a sample-and-hold amplifier (SHA).

[0045] It is understood that the above sampling implementation method can be set according to specific scenarios and needs, and this specification does not limit it.

[0046] The N cascaded conversion modules may specifically include conversion module Stage1, conversion modules Stage2 through StageN-1, and conversion module StageN. Furthermore, the levels of each conversion module are set according to their cascading order, such as... Figure 1 In the diagram, Stage1 is the first level of the conversion module, Stage2 is the second level, and so on.

[0047] In each conversion module Stage1 to StageN, the first-level conversion module Stage1 to the (N-1)th-level conversion module StageN-1 adopt the same internal structure. Taking the first-level conversion module Stage1 as an example, as follows... Figure 1 As shown, the conversion module Stage1 may include: a sub-ADC unit 11 and a gain digital-to-analog converter (MDAC) unit 12.

[0048] The sub-analog-to-digital converter 11 samples, quantizes, and encodes the received input signal to obtain the first-level thermometer code DS1, and outputs the first-level thermometer code DS1 to the gain digital-to-analog converter 12 and the digital calculation module 04, respectively. The number of thermometer codes that the sub-analog-to-digital converter 11 can generate is related to the precision of the sub-analog-to-digital converter 11. For example, if the precision of the sub-analog-to-digital converter 11 is x bits, then the sub-analog-to-digital converter 11 can generate 2... x -1 digit thermometer code.

[0049] The gain digital-to-analog converter unit 12 may include an arithmetic unit 121, a sub-digital-to-analog converter unit (Sub-DAC) 122, and an amplification unit 123. Typically, the precision of the gain digital-to-analog converter unit 12 is the same as that of the sub-DAC unit 11. For example, if the precision of the sub-DAC unit 11 is x bits, then the precision of the gain digital-to-analog converter unit 12 is also typically x bits.

[0050] Specifically, the sub-digital-to-analog converter 122 is adapted to receive the first-level thermometer code DS1 output by the sub-analog-to-digital converter 11, convert the first-level thermometer code DS1 into a corresponding first-level analog component, and output it to the arithmetic unit 121. The arithmetic unit 121 is adapted to receive the analog hold signal VC output by the sample-and-hold amplification module and the first-level analog component output by the sub-analog-to-digital converter 11, subtract the first-level analog component from the analog hold signal VC, and output the calculation result to the amplification unit 123. The amplification unit 123 is adapted to receive the calculation result output by the arithmetic unit 121, amplify the calculation result to obtain a first-level analog residual signal VR1 with the analog residual as the amplitude, and output it to the second-level conversion module Stage2. The amplification unit can be an operational transimpedance amplifier (OTA).

[0051] The conversion modules Stage2 to StageN-1 also include sub-analog-to-digital conversion units and gain digital-to-analog conversion units. For details, please refer to the relevant description of the conversion module Stage1 above, which will not be repeated here.

[0052] Therefore, based on the received input signal (i.e., the signal output by the previous stage conversion module), the conversion modules Stage2 to StageN-1 can obtain the corresponding level of thermometer code and analog residual signal, and output the corresponding level of thermometer code to the digital calculation module 04, and output the corresponding level of analog residual signal to the next stage conversion module. For details, please refer to... Figure 1 The conversion module Stage2 outputs the second-level thermometer code DS2 to the digital calculation module 04, and then to the next-level conversion module ( Figure 1 (Not shown in the image) Outputs the second-level analog residual signal VR2, and so on. The conversion module StageN-1 outputs the N-1 level thermometer code DSN-1 to the digital calculation module 04, and outputs the N-1 level analog residual signal VRN-1 to the next-level conversion module StageN.

[0053] For the Nth stage conversion module, since it is the last of the N cascaded conversion modules, stage N can consist only of sub-analog-to-digital conversion units. Figure 1 (not shown in the diagram) Based on the analog residual signal output by the N-1th stage conversion module StageN-1, the Nth stage thermometer code DSN is output to the digital calculation module 04.

[0054] It should be noted that the number of digits of the thermometer code output by each of the conversion modules Stage1 to StageN can be set according to specific scenarios and requirements. Each conversion module can output thermometer codes with the same number of digits or thermometer codes with different numbers of digits. This manual does not impose specific restrictions on this.

[0055] The digital calculation module 04 is adapted to add the thermometer codes output by each level of the conversion module in a staggered manner according to the level, thereby aligning the thermometer codes obtained by different level conversion modules at different times in time and performing binary conversion to obtain binary output codes. The number of output codes generated by the digital calculation module 04 is related to the precision of the digital calculation module 04. For example, if the precision of the digital calculation module 04 is m bits, then the digital calculation module 04 can generate 2... m -1 type of output code. Furthermore, the accuracy of the digital calculation module 04 can characterize the accuracy of the pipelined analog-to-digital converter circuit P0.

[0056] After introducing the framework of existing pipelined analog-to-digital converter circuits, the following specific embodiments illustrate the specific hardware structure and connection relationship of the sub-analog-to-digital converter unit and the gain digital-to-analog converter unit, in order to point out the problems existing in the prior art.

[0057] It should be noted that the sub-analog-to-digital converter (ADC) and gain ADC units in the following examples are for illustrative purposes only. In actual applications, conversion modules Stage1 to StageN may include the sub-analog-to-digital converters described below, or other types of sub-analog-to-digital converters; similarly, conversion modules Stage1 to StageN-1 may include the gain ADC units described below, or other types of gain ADC units. This specification does not impose any limitations on this.

[0058] In an optional example, such as Figure 2 The diagram shown is a connection schematic of an existing sub-analog-to-digital converter unit, in conjunction with a reference. Figure 1 ,exist Figure 2 In this context, a K-1 bit precision sub-analog-to-digital converter unit may include K resistors R1, R2 to R... K-2 R K-1 and R K K-1 comparators C1, C2 to C K-2 and C K-1 .

[0059] Reference Figure 1 and Figure 2 In the sub-analog-to-digital converter unit 11, resistor R k One end of resistor R1 is connected to the first reference voltage Vref1, and one end of resistor R1 is connected to the second reference voltage Vref2. K resistors R1 to R... K The resistors are connected end-to-end, with the first reference voltage Vref1 being greater than the second reference voltage Vref2. Therefore, the K resistors divide the voltage difference between the first reference voltage Vref1 and the second reference voltage Vref2.

[0060] For K-1 comparators C1 to C2 K-1 One input terminal is coupled between two different resistors, thereby connecting to comparison reference voltages with successively increasing voltage values. The other input terminal is connected to the input signal V. in , where the input signal V in It can be the analog hold signal output by the sample-and-hold amplifier circuit or the signal output by the previous stage conversion module.

[0061] Each comparator C1 to C K-1 The comparison reference voltage and input signal V are respectively connected to it. in The amplitudes are compared to obtain the comparison results d1~dk-1, and the comparison results d1~dk-1 are output as thermometer codes to the digital calculation module 04.

[0062] Among them, based on K-1 comparators C1 to C K-1 The order of magnitude of the input comparison reference voltages, and the comparators C1 to C2. K-1 The comparison results d1~dk-1 are arranged from low to high, meaning that the comparison result d1 output by comparator C1 is the least significant bit of the thermometer code. k-1 The output comparison result dk-1 is the most significant bit.

[0063] Furthermore, due to the comparators C1 to C... K-1 The reference voltages connected to the circuit increase sequentially, therefore, according to the input signal V... in The magnitude of the amplitude is determined by the change in the thermometer code starting from the least significant bit, and the input signal V is only represented when the logic value of the least significant bit in the thermometer code (e.g., logic value "1") is equal to the input signal V. in Only after the amplitude of the input signal V exceeds the comparison result of the corresponding reference voltage can the logic value of the next higher valid bit in the thermometer code potentially change. For example, as the input signal V... in As the amplitude increases, the thermometer code can change from "00……01" to "00……11", but it will not change to "00……10".

[0064] Accordingly, such as Figure 3The diagram shown is a connection schematic of an existing gain digital-to-analog converter unit, in conjunction with a reference. Figures 1 to 3 The gain digital-to-analog conversion unit may include an arithmetic unit 301, a sub-digital-to-analog conversion unit 302, and a transconductance amplifier 303. The arithmetic unit 301 may include a first switch CK1, a first capacitor CS, a second capacitor CF, a third switch CK3, and a fourth switch CK4. The sub-digital-to-analog conversion unit 302 may include a second switch CK2.

[0065] The first switch CK1, the first capacitor CS, and the second switch CK2 are each in a one-to-one correspondence, and multiple sets of coupled first switches CK1, first capacitor CS, and second switches CK2 can exist. The number of first switches CK1, first capacitor CS, and second switches CK2 exceeds the number of comparators included in the sub-analog-to-digital converter unit. For example, Figure 2 The neutron analog-to-digital converter unit includes K-1 comparators, then Figure 3 The gain digital-to-analog conversion unit may include K first switches CK1, K first capacitors CS and K second switches CK2.

[0066] K first switches CK1 are coupled to the inverting input terminal "-" of the transconductance amplifier 303 via a first capacitor CS; the second switch CK2 is a single-pole double-throw (SPDT) switch, with its stationary terminal connected to the first reference voltage Vref1 and the second reference voltage Vref2 respectively, and its moving terminal coupled between the first switches CK1 and the first capacitor CS. Furthermore, The moving end of the second switch CK2 in K-1 is controlled by the comparison result (i.e., thermometer code) of the corresponding comparator in the sub-analog-to-digital conversion unit. The other second switch CK2 is used to connect the common-mode signal.

[0067] The inverting input terminal "-" of the transconductance amplifier 303 is also connected to ground via the third switch CK3, and to its output terminal via two parallel second capacitors CF. The non-inverting input terminal "+" of the transconductance amplifier 303 is directly connected to ground. The output terminal of the transconductance amplifier 303 is also connected to ground via the fourth switch CK4.

[0068] During the sampling phase of the conversion module, the first switch CK1 and the third switch CK3 are turned on, the fourth switch CK4 is closed, and the first capacitor CS is connected to the input signal V. in Input signal V in The output of transconductance amplifier 303 can be shorted, which can be the analog hold signal output from the sample-and-hold amplifier circuit or the signal output from the previous stage conversion module. Assume the capacitance of the first capacitor CS is... In an ideal state, the amount of charge accumulated at the input terminal of the 303 transconductance amplifier is... for: ; During the amplification stage of the conversion module, K-1 second switches CK2 connect to the corresponding first reference voltage Vref1 or second reference voltage Vref2 according to the thermometer code output by the comparator. The reference signal connected to K-1 second switches CK2 can be used as the analog component of this stage, forming a closed-loop feedback loop of the transconductance amplifier through the second capacitor CF. The remaining second switch CK2 is connected to the common-mode signal.

[0069] Assume the capacitance value of the second capacitor CF is... In an ideal state (such as when the open-loop gain and bandwidth of the amplification unit are infinite), the amount of charge accumulated at the input terminal of the transconductance amplifier 303 is... for: ; in, This represents the comparison result of the i-th comparator. This represents the reference voltage value when the second switch CK2 of the i-th comparator is turned on; V in V represents the input signal of the transconductance amplifier 303. out This represents the output signal (i.e., the analog residual signal) of the transconductance amplifier 303.

[0070] Based on charge conservation, the input-output transfer function of the gain digital-to-analog converter unit can be obtained as follows: .

[0071] As can be seen from the above formula, under ideal conditions, the input and output of each conversion module in a pipelined analog-to-digital converter circuit have a linear relationship, and the slope is the theoretical gain.

[0072] For example, in conjunction with reference Figures 1 to 3 If the accuracy of a pipelined analog-to-digital converter (ADC) is 10 bits, its conversion range can be 0-1023 assuming the transconductance amplifier and comparator are in ideal condition. Without calibration and only performing tiered conversion, a pipelined ADC can include four cascaded conversion modules: a first-stage conversion module, a second-stage conversion module, a third-stage conversion module, and a fourth-stage conversion module.

[0073] The first-stage conversion module includes seven comparators with a precision of 3 bits, dividing the [0, 1023] interval into eight equal intervals, each spanning 128, with corresponding codes from 000 to 111. Based on the first-stage thermometer code output by the first-stage conversion module, it can be determined which interval the amplitude (i.e., the sampled value) of the analog hold signal falls into. For example, if the first-stage thermometer code is 010, it can be determined that the analog hold signal falls into the [256, 383] interval corresponding to 010. Furthermore, to facilitate the conversion work of the next-stage conversion module, after subtracting the first-stage analog component from the analog hold signal, the result is amplified by 8 times and output as the first-stage analog residual signal to the second-stage conversion module.

[0074] The second-stage conversion module includes seven comparators with a precision of 3 bits, dividing the interval corresponding to the first-stage thermometer code into eight intervals, each spanning 16 bits and numbered from 000 to 111. Based on the second-stage thermometer code output by the second-stage conversion module, it can be determined which interval the amplitude of the first-stage analog residual signal falls into. For example, if the second-stage thermometer code is 001, then the first-stage analog residual signal falls into the interval [272, 287] corresponding to 001. Furthermore, to facilitate the conversion work of the next-stage conversion module, after subtracting the second-stage component from the first-stage analog residual signal, the result is amplified by 8 times and output as the second-stage analog residual signal to the third-stage conversion module.

[0075] The third-level conversion module can include 15 comparators with a precision of 4 bits, thereby dividing the interval corresponding to the second-level thermometer code into 16 intervals, each spanning 1 and numbered from 0000 to 1111. Based on the third-level thermometer code output by the third-level conversion module, it can be determined which interval the amplitude of the second-level analog residual signal falls into. For example, if the third-level thermometer code is 0001, it can be determined that the second-level analog residual signal falls into the interval [273, 273] corresponding to 0001, that is, the sampled value is 273.

[0076] However, in practical circuits, the open-loop gain and bandwidth of the amplification unit in a pipelined analog-to-digital converter are finite, which may lead to finite gain error. Specifically, combined with... Figures 1 to 3 In a related embodiment, when considering the finite gain of the amplification unit and the small signal establishment, the input-output transfer function of the gain-to-analog converter unit becomes: ; Where LG represents loop gain, BW represents closed-loop bandwidth, and t represents time.

[0077] As can be seen from the above formula, the factors that cause finite gain error may include: the limitations of the performance of the amplification unit itself, which makes the loop gain not infinite and the closed-loop bandwidth not infinite; and the capacitor mismatch problem in the sampling stage and the amplification stage of the circuit, that is, there is an error between the first capacitor CS and the second capacitor CF, which causes the closed-loop gain to decrease.

[0078] Due to the finite gain error, the actual gain will deviate from the theoretical gain. Specifically, for example... Figure 4 The figure shown is an input-output curve diagram of an existing conversion module. The input signal V of this conversion module is used as an example. in The x-axis represents the x-axis, and the output signal V of the conversion module represents the x-axis. out A coordinate system is established with the vertical axis as the ordinate, and the conversion module has a precision of 2 bits. +Vref is the first reference voltage, and -Vref is the second reference voltage. +Vref and -Vref together form the theoretical analog domain output range of the conversion module. The dashed line represents the theoretical input-output curve of the conversion module under ideal conditions, while the solid line represents the actual input-output curve of the conversion module with finite gain error. Figure 4 In this system, the conversion module uses full-scale gain, meaning that the maximum output value of the theoretical input-output curve is located on the boundary of the theoretical analog domain output range.

[0079] Depend on Figure 4 It is known that the actual gain of the conversion module is greater than the theoretical gain, which leads to errors in the output signal (i.e., the analog residual signal). There may even be a part of the output signal that exceeds the theoretical analog domain output range. This part of the output signal will exceed the theoretical analog domain input range of the next-stage conversion module, making it impossible for the next-stage conversion module to measure the output signal, resulting in code loss.

[0080] Therefore, it can be seen that finite gain error will increase the error of subsequent processing and affect the accuracy of the output results of pipelined analog-to-digital converter circuits.

[0081] To reduce the impact of finite gain error, existing technologies typically employ Redundant Signed Digit (RSD) correction, which increases the error margin that the conversion module can withstand by reducing the gain of the amplification unit, reducing the number of comparators, and modifying the reference voltage.

[0082] Figure 5 for Figure 4 The corresponding input-output curves of the conversion module after gain reduction are shown. The dashed line represents the theoretical input-output curve of the conversion module under ideal conditions, while the solid line represents the actual input-output curve of the conversion module with finite gain error. (Refer to the reference...) Figure 4 and Figure 5 , Figure 5The gain of the conversion module in the middle is compared with the gain at full scale (i.e., Figure 4 The gain of the intermediate conversion module is reduced by 1 / 2. After the gain is reduced, there is a margin between the maximum output value of the theoretical input-output curve and the output range of the theoretical analog domain. Even if the finite gain error causes the actual gain of the conversion module to increase, the actual input-output curve may still be included in the output range of the theoretical analog domain, so that the next stage conversion module can measure the output signal.

[0083] However, because the original gain of the conversion module is reduced, additional cascaded conversion modules are needed to achieve the accuracy of the original pipelined analog-to-digital converter circuit. For example, referring to the above embodiment of the 10-bit pipelined analog-to-digital converter circuit, without changing the theoretical analog domain output range, the gain of the first to third stage conversion modules is reduced to half of the original value, leaving sufficient margin for each stage conversion module to accommodate errors. Additional cascaded conversion modules are then added, and the original accuracy is achieved by using more bits of thermometer code (e.g., 11 bits) and adjusting the number of overlapping bits in the staggered addition.

[0084] In summary, although the aforementioned digital redundancy bit correction scheme can expand the tolerance range of pipelined analog-to-digital converters for gain variations, thereby reducing the impact of finite gain errors to some extent, there is still a possibility of exceeding the theoretical analog domain output range, and it also increases circuit power consumption. Therefore, the existing technical solutions still cannot guarantee accurate output results from pipelined analog-to-digital converters.

[0085] To address the aforementioned technical problems, embodiments of this specification provide a calibration method for analog-to-digital converter (ADC) circuits. For pipelined ADC circuits included in the ADC circuit, the method determines whether there is a gain deviation in the pipelined ADC circuit by acquiring information in the digital domain of the analog residual signals transmitted between stages. This enables gain verification of the pipelined ADC circuit, facilitating the calibration of effective gain errors, thereby improving the accuracy of the pipelined ADC circuit and reducing power consumption requirements for equivalent accuracy.

[0086] To enable those skilled in the art to better understand and implement the concepts, implementation schemes, and advantages of this specification, the following detailed description is provided with reference to the accompanying drawings and specific embodiments.

[0087] Reference Figure 6This is a flowchart illustrating a calibration method for an analog-to-digital converter (ADC) circuit according to an embodiment of this specification. In this embodiment, the ADC circuit includes a pipelined ADC circuit. The cascaded conversion modules in the pipelined ADC circuit are divided into two groups. One group of conversion modules closer to the input terminal of the pipelined ADC circuit can be called the front-end conversion module, and the other group can be called the back-end conversion module. In other words, the pipelined ADC circuit includes a front-end conversion module with at least one conversion module and a back-end conversion module with at least one conversion module.

[0088] It should be noted that this manual only requires ensuring that both the front-end and back-end conversion modules include at least one level of conversion module. No specific restrictions are placed on the grouping method of the conversion modules. For example, refer to the reference... Figure 1 The front-end conversion module may include a first-level conversion module Stage1, and the back-end conversion module may include conversion modules at other levels.

[0089] Based on the grouping of the above-described pipelined analog-to-digital converter circuits, the calibration method provided in the embodiments of this specification can be implemented. Specifically, as follows: Figure 6 As shown, the calibration method may include the following steps: S01, a test analog signal is input to the pipelined analog-to-digital converter circuit, so that the front-end conversion module receives the test analog signal and outputs a corresponding analog residual signal to the back-end conversion module. The test analog signal is a known signal that changes over time.

[0090] S02, acquire the residual digital information corresponding to the analog residual signal. The residual digital information is the information of the analog residual signal in the digital domain.

[0091] S03, based on the residual digital information, determine whether there is a deviation in the gain of the front-end conversion module.

[0092] As can be seen from the above scheme, the analog residual signal measurement in the analog domain is converted into the residual digital information calculation in the digital domain. The gain of the front-end conversion module is then verified through the residual digital information, thereby avoiding the secondary error generated by measuring the analog residual signal and improving the calibration accuracy of the effective gain error. Furthermore, the calibration method provided in this specification is implemented based on the existing hardware architecture of the pipelined analog-to-digital converter circuit. Combined with existing logic operation devices, it can achieve good calibration results, thereby effectively reducing the hardware cost and implementation complexity required for calibration, improving the calibration response speed and execution speed, making the calibration more efficient, and having stronger universality.

[0093] It should be noted that, Figure 1The pipelined analog-to-digital converter circuit is only an example. In practical applications, as long as the pipelined analog-to-digital converter circuit includes a back-end conversion module and can obtain the residual digital information corresponding to the analog residual signal, the calibration method provided in the embodiments of this specification can be implemented. The actual hardware architecture in the pipelined analog-to-digital converter circuit (such as the connection relationship between hardware and the specific circuit structure) does not affect the implementation of the calibration method provided in the embodiments of this specification. That is, the calibration method provided in the embodiments of this specification has stronger universality.

[0094] For example, such as Figure 7a The diagram shown is a schematic of another existing pipelined analog-to-digital converter (ADC) circuit. In this circuit, P1 is a fully differential signal input / output structure. For a detailed implementation, please refer to [reference needed]. Figure 1 And related descriptions, which will not be repeated here. Figure 7b The diagram shown is a schematic of another existing pipelined analog-to-digital converter circuit, in which the pipelined analog-to-digital converter circuit P2 does not include a sample-and-hold amplifier module, thereby reducing circuit power consumption.

[0095] It is understood that, for ease of description, single lines are used to represent the signal flow process in some of the accompanying drawings in this specification, but these drawings can essentially be understood as including the case of fully differential signal input and output structure; and, in some of the drawings, other modules besides the conversion module and the digital calculation module are omitted.

[0096] In practice, the thermometer codes output by each level of the conversion module in the back-end conversion module can be obtained, and the residual digital information can be determined based on the obtained thermometer codes.

[0097] Specifically, since each conversion module in the pipeline-type analog-to-digital converter circuit has a digital domain weight, the thermometer code and the corresponding digital domain weight output by each conversion module in the back-end conversion module can be obtained, and the residual digital information can be obtained by weighted calculation based on the obtained thermometer code and the corresponding digital domain weight.

[0098] As shown above, by using the thermometer code obtained by quantization from the back-end conversion module in the pipelined analog-to-digital converter circuit and the set digital domain weights, the information of the residual analog signal output by the front-end conversion module in the digital domain can be calculated in reverse. This enables the indirect reading of the analog residual signal output by the front-end conversion module, allowing the residual digital information to effectively replace the analog residual signal for gain verification of the front-end conversion module. Furthermore, by making reasonable use of the existing hardware architecture of the pipelined analog-to-digital converter circuit, the hardware cost and implementation complexity required for calibration can be reduced, while the calibration response speed and execution speed can be improved, resulting in higher calibration efficiency.

[0099] In practical implementation, in order for the back-end conversion module to process the test simulation residual signal of the front-end conversion module, the test simulation residual signal output by the front-end conversion module should fall within the theoretical simulation domain input range of the back-end conversion module. Therefore, the theoretical simulation domain output range of the front-end conversion module matches the theoretical simulation domain input range of the back-end conversion module.

[0100] For example, refer to Figure 5 If the theoretical analog domain output range of the front-end conversion module is -Vref to +Vref, then the theoretical analog domain input range of the back-end conversion module can be -Vref to +Vref. For example, refer to... Figure 5 If the theoretical analog domain output range of the front-end conversion module is -0.5*Vref to +0.5*Vref, then the theoretical analog domain input range of the back-end conversion module can be -0.5*Vref to +0.5*Vref.

[0101] Since digital residual information is the information of analog residual signals between the front-end conversion module and the back-end conversion module in the digital domain, there is a correspondence between analog residual signals and digital residual information. Therefore, the theoretical analog domain output range of the front-end conversion module also has a corresponding theoretical digital domain output range, and the theoretical analog domain input range of the back-end conversion module also has a corresponding theoretical digital domain input range.

[0102] The theoretical digital domain output range is related to the digital domain weight corresponding to the least significant bit in the front-end conversion module and the digital correction method used, while the theoretical digital domain input range is related to the digital domain weight corresponding to the most significant bit in the back-end conversion module and the digital correction method used.

[0103] For example, such as Figure 8 The figure shows a graph of the input signal and digital residual information of the front-end conversion module. The vertical axis represents the residual digital information D corresponding to the analog residual signal output by the front-end conversion module. out1 The horizontal axis represents the input signal V of the front-end conversion module. in1 If the weight of the least significant bit in the front-end conversion module is W... LSB1 Furthermore, since the gain of each conversion module in the pipelined analog-to-digital converter circuit is reduced by half compared to the full-scale gain, the theoretical digital domain output range of the front-end conversion module can be 0.5 * W. LSB1 Up to 1.5* W LSB1 Therefore, the theoretical digital domain input range of the back-end conversion module can also be 0.5 * W. LSB1 Up to 1.5* W LSB1 .

[0104] Based on this, determining whether there is a deviation in the gain of the front-end conversion module according to the residual digital information may include: determining whether the measured digital domain output range corresponding to the residual digital information is consistent with the current theoretical digital domain output range of the front-end conversion module; if they are inconsistent, determining that there is an error in the gain of the front-end conversion module.

[0105] Here, "current" can be understood as the time period during which the gain deviation judgment of the front-end conversion module is being performed. The measured digital domain output range refers to the digital domain range obtained through the residual digital information, which characterizes the range of the analog residual signal actually output by the front-end conversion module in the digital domain (i.e., the actual digital domain output range of the front-end conversion module).

[0106] Specifically, since the test analog signal input to the pipelined analog-to-digital converter circuit changes over time, and the change of the test analog signal is known, multiple residual digital information can be obtained after multiple samplings. Based on the multiple residual digital information obtained, the measurement digital domain output range can be obtained, thereby determining whether there is a deviation in the gain of the front-end conversion module.

[0107] For example, continue to refer to Figure 8 As the simulated test signal changes, it is sampled five times, obtaining five sets of residual digital information. The test values ​​and corresponding residual digital information of the simulated test signal during sampling are used to form coordinates, yielding the expected value. Figure 8 Based on the test points Q1~Q5, the measurement digital domain output range of the front-end conversion module can be determined to be W. c1 To W c2 .pass Figure 8 It is quite obvious that the measured digital domain output range is inconsistent with the theoretical digital domain output range, which indicates that there is an error in the gain of the front-end conversion module.

[0108] Therefore, by making reasonable and efficient use of the existing hardware architecture of the pipelined analog-to-digital converter circuit, the difference between the actual digital domain output range and the theoretical digital domain output range of the front-end conversion module can be determined by measuring the digital domain output range obtained through residual digital information. This reduces the hardware cost and implementation complexity required for calibration, improves the calibration response speed and execution speed, and makes the calibration more efficient and more universal.

[0109] In practical implementation, in order to quickly obtain the measurement digital domain output range and reduce the amount of data, the pipelined analog-to-digital converter circuit can be sampled when the test analog signal changes to the boundary value of the theoretical digital domain output range. Then, the corresponding residual digital information is obtained, which is the boundary value of the theoretical digital domain output range. Thus, the measurement digital domain output range can be directly derived, reducing the amount of computation and improving the processing speed.

[0110] For example, such as Figure 8 As shown, it is possible to test the analog signal V in1 When the value changes to the measured value V1, the pipeline-type analog-to-digital converter circuit performs the conversion and obtains the residual digital information W corresponding to the analog residual signal. c1 This refers to a boundary value of the theoretical digital domain output range; correspondingly, it can be used to test the analog signal V. in1 When the value changes to the measured value V2, the pipeline-type analog-to-digital converter circuit performs the conversion and obtains the residual digital information W corresponding to the analog residual signal. c2 This represents another boundary value of the theoretical digital domain output range. The measured digital domain output range of the front-end conversion module is thus determined to be W. c1 To W c2 .

[0111] In practice, the measured value of the test simulation signal at the measurement time and the current theoretical digital domain output range of the front-end conversion module can be used to determine whether the measured gain corresponding to the residual digital information is consistent with the theoretical gain of the front-end conversion module; if they are inconsistent, it is determined that there is an error in the gain of the front-end conversion module.

[0112] The measured gain refers to the gain obtained through the residual digital information, which characterizes the gain of the analog residual signal actually output by the front-end conversion module in the digital domain (i.e., the actual digital domain gain of the front-end conversion module). Specifically, although the finite gain error will affect the gain of the amplification unit in the conversion module, i.e., the slope of the input-output curve of the conversion module will change, the reference... Figure 5 It can be seen that in the analog residual signal input V out The point where =0 has not changed, such as Figure 5 Point Q3. These points have corresponding points in the curve of the input and residual digital information of the front-end conversion module, such as... Figure 8 Point Q3 in the diagram. Therefore, these points can be used as reference points. Furthermore, since the changes in the test analog signal are known, the current measured value of the test analog signal can be determined, and thus combined with the residual digital information to form the coordinates of the measurement points. Based on the reference points and the measurement points, the actual slope, i.e., the measurement gain of the front-end conversion module, can be calculated.

[0113] Then, the measured gain corresponding to the residual digital information is compared with the theoretical gain of the front-end conversion module to determine whether they are consistent. If they are inconsistent, it is determined that the gain of the front-end conversion module has an error. Figure 8As shown, if the reference point is Q3 and the measurement point is Q4, the dashed line represents the theoretical curve corresponding to the test analog signal and residual digital information of the front-end conversion module. It can be concluded that the slope calculated from the reference point Q3 and the measurement point Q4 is greater than the slope of the theoretical curve.

[0114] Therefore, the existing hardware architecture of pipelined analog-to-digital converter circuits can be used in a reasonable and efficient manner. By measuring the gain obtained through residual digital information, the difference between the actual gain and the theoretical gain of the front-end conversion module can be determined. This reduces the hardware cost and implementation complexity required for calibration, improves the calibration response speed and execution speed, and makes the calibration more efficient and more universal.

[0115] In an optional example, refer to Figure 5 It can be seen that under the influence of finite gain error, the slope of the input-output curve will change, but at V out The point where =0 has not changed, such as Figure 5 Point Q3. These points have corresponding points in the curve of the input and residual digital information of the front-end conversion module, such as... Figure 8 Point Q3 in the diagram. Therefore, these points can be used as reference points. Furthermore, since the changes in the test analog signal are known, the current measured value of the test analog signal can be determined, and thus combined with the residual digital information to form the coordinates of the measurement points. Based on the reference points and measurement points, the actual slope, i.e., the measurement gain of the front-end conversion module, can be calculated, thereby deriving the measurement digital domain output range corresponding to the residual digital information, such as... Figure 8 With Q3 as the reference point and Q2 as the test point, the measured digital domain output range can be determined to be W. c1 To W c2 .

[0116] In practical implementation, to avoid misjudgments and improve the accuracy and reliability of the judgment results, multiple sets of residual digital information can be obtained to determine whether the gain of the front-end conversion module has a deviation, thus obtaining multiple judgment results. These multiple judgment results are then statistically analyzed to determine the final judgment result. For example, based on the proportion of results judged to have a deviation among the multiple judgment results, it can be finally determined whether the gain of the front-end conversion module has a deviation.

[0117] In practical implementation, when there is a gain deviation in the front-end conversion module, the gain of the front-end conversion module can be corrected. Specifically, such as... Figure 6 As shown, the calibration method for the analog-to-digital conversion circuit further includes the following step: S04, when there is a deviation, the weight of the digital domain corresponding to the front-end conversion module is adjusted according to the residual digital information.

[0118] The adjustment direction of the digital domain weight is to approach the actual gain of the front-end conversion module.

[0119] Since the calculation of output digital information requires weighted calculation using digital domain weights, the digital domain weights corresponding to the front-end conversion module can characterize the gain of the front-end conversion module in the digital domain. Based on this, by adjusting the digital domain weights corresponding to the front-end conversion module, the numerical calculation of the part related to the front-end conversion module in the calculation of output numerical information can be corrected, thereby indirectly modifying the theoretical digital domain output range of the front-end conversion module, so that the calculated output digital information can better reflect the actual conversion capability of the pipelined analog-to-digital converter circuit.

[0120] Therefore, by adjusting the digital domain weights to match the actual gain capability of the front-end conversion module, the reliability and accuracy of the output results of the pipelined analog-to-digital converter can be improved without changing the existing hardware architecture of the pipelined analog-to-digital converter, while reducing the power consumption requirements for the same accuracy.

[0121] Furthermore, in actual analog-to-digital conversion, the pipelined analog-to-digital converter circuit calibrated by the calibration method described in the embodiments of this specification has more accurate and reliable output digital information. Therefore, the value of the analog signal to be processed can be more accurately inferred based on the output value information of the calibrated pipelined analog-to-digital converter circuit.

[0122] In one feasible example, if the span of the theoretical digital domain output range of the front-end conversion module is greater than the span of the measured digital domain output range corresponding to the residual digital information, it indicates that the theoretical digital domain output range of the front-end conversion module is too large and the actual gain capability of the front-end conversion module is lower than the ideal gain capability. In this case, the digital domain weight corresponding to the front-end conversion module can be reduced, that is, the range span that the front-end conversion module can accommodate is reduced, so as to be closer to the actual output range of the front-end conversion module.

[0123] If the span of the theoretical digital domain output range of the front-end conversion module is smaller than the span of the measured digital domain output range corresponding to the residual digital information, it indicates that the theoretical digital domain output range of the front-end conversion module is too small and the actual gain capability of the front-end conversion module is higher than the ideal gain capability. In this case, the digital domain weight corresponding to the front-end conversion module can be increased, that is, the range span that the front-end conversion module can accommodate is expanded, thereby getting closer to the actual output range of the front-end conversion module.

[0124] Specifically, such as Figure 8As shown, the dashed diagonal line represents the span of the theoretical digital domain output range of the front-end conversion module; the solid diagonal line represents the span of the measurement digital domain output range corresponding to one type of residual digital information; and the dotted-dash diagonal line represents the span of the measurement digital domain output range corresponding to another type of residual digital information.

[0125] By increasing the weight of the digital field corresponding to the front-end conversion module, the dashed diagonal line can be made closer to the solid diagonal line; by decreasing the weight of the digital field corresponding to the front-end conversion module, the dashed diagonal line can be made closer to the dotted diagonal line.

[0126] In another feasible example, if the theoretical gain corresponding to the front-end conversion module is greater than the measured gain corresponding to the residual digital information, it indicates that the current theoretical gain of the front-end conversion module is too large and the actual gain capability of the front-end conversion module is lower than the ideal gain capability. In this case, the digital domain weight corresponding to the front-end conversion module can be reduced, thereby making the theoretical gain corresponding to the front-end conversion module closer to the actual gain of the front-end conversion module.

[0127] If the theoretical gain corresponding to the front-end conversion module is less than the measured gain corresponding to the residual digital information, it indicates that the current theoretical gain of the front-end conversion module is too small and the actual gain capability of the front-end conversion module is higher than the ideal gain capability. In this case, the digital domain weight corresponding to the front-end conversion module can be increased, thereby making the theoretical gain of the front-end conversion module closer to the actual gain of the front-end conversion module.

[0128] Specifically, such as Figure 8 As shown, the slope of the dashed line represents the theoretical gain of the front-end conversion module; the slope of the solid line represents the measurement gain corresponding to one type of residual digital information; and the slope of the dotted-dash line represents the measurement gain corresponding to another type of residual digital information.

[0129] By increasing the weight of the digital field corresponding to the front-end conversion module, the slope of the dashed line can be made closer to the slope of the solid line; by decreasing the weight of the digital field corresponding to the front-end conversion module, the slope of the dashed line can be made closer to the slope of the dotted line.

[0130] In practical implementation, the weight of the digital field in at least one conversion module of the front-end conversion module can be adjusted. Furthermore, the weight of the digital field corresponding to at least one valid bit in the conversion module can be adjusted. This specification does not impose specific limitations in this regard.

[0131] In practical implementation, since the output of the first-stage conversion module affects the processing results of subsequent circuits, the accuracy and reliability of the first-stage conversion module are of utmost importance to the pipelined analog-to-digital converter circuit. When adjusting the digital domain weights corresponding to the front-end conversion modules, the digital domain weights of the first-stage conversion module can be adjusted to improve the reliability and accuracy of the circuit.

[0132] In specific implementation, after determining that the gain of the front-end conversion module has a deviation based on the residual digital information, the correction information of the digital domain weight corresponding to the front-end conversion module can be determined based on the residual digital information. The correction information includes: adjustment direction and correction amount.

[0133] For example, correction information can be obtained based on the span difference between the theoretical digital domain output range and the measured digital domain output range, or the difference between the theoretical gain and the measured gain.

[0134] In practice, in order to reduce the amount of computation and quickly adjust the digital domain weights, after determining the adjustment direction based on the span difference between the theoretical digital domain output range and the measured digital domain output range or the difference between the theoretical gain and the measured gain, a preset correction step size can be obtained as the correction amount to obtain correction information. Thus, the digital domain weights of the front-end conversion module are adjusted according to the preset correction step size and adjustment direction.

[0135] In practical implementation, after the digital domain weight adjustment is completed, the test analog signal can be re-inputted into the pipelined analog-to-digital converter circuit to determine whether there is still a deviation in the gain of the front-end conversion module. The re-inputted test analog signal can be the previously input test analog signal or another newly acquired test analog signal; this specification does not impose specific limitations on this.

[0136] Furthermore, when judging the gain deviation again, the current theoretical digital domain output range of the front-end conversion module is determined by the previously adjusted digital domain weights. Therefore, by adjusting the digital domain weights through multiple gain deviation judgments, the digital domain weights are made to better reflect the actual gain of the front-end conversion module.

[0137] In practical implementation, to reduce the probability of missed detections and the number of gain adjustments, thereby improving calibration efficiency, multiple sets of residual digital information can be acquired. This ensures that when the gain of the front-end conversion module actually has a deviation, at least one judgment result indicating a gain deviation in the front-end conversion module can be obtained. Based on this judgment result, at least one set of correction information can then be obtained. Furthermore, after obtaining multiple sets of correction information based on the multiple sets of residual digital information, these correction information sets can be statistically analyzed to determine the final correction information used for digital domain weight adjustment.

[0138] In specific implementation, the test simulation signal can be a simulation signal that changes in a single direction or a simulation signal that changes in multiple directions; furthermore, the test simulation signal can be a linearly changing simulation signal or a nonlinearly changing simulation signal. For example, the test simulation signal can be a linear simulation signal that changes in a single direction, a nonlinear simulation signal that changes in a single direction, a linear simulation signal that changes in multiple directions, a nonlinear simulation signal that changes in multiple directions, etc., and this specification does not impose specific limitations on it.

[0139] The test simulation signal can be generated by a signal generator. Furthermore, linear simulation signals are easier to generate and control, and are more conducive to implementing the calibration methods provided in the embodiments of this specification.

[0140] In an optional example, a ramp generator can be used to obtain the test simulation signal. Specifically, such as... Figure 9a The diagram shown is a schematic of an existing ramp generator circuit. Figure 9a In the circuit, constant current source S1 supplies current I to capacitor C1, causing capacitor C1 to integrate and generate voltage vt, which provides voltage to the gate of transistor M1, one input terminal of driver AMP1, and one input terminal of hysteresis comparator AMP2; the source of transistor M1 is connected to another constant current source S2, which outputs current 2I; the gate of transistor M1 is connected to the output terminal of hysteresis comparator AMP2; the other input terminal of hysteresis comparator AMP2 is connected to reference voltage VCM; the output terminal of driver AMP1 outputs an analog signal VOUT; the output terminal of driver AMP1 is also grounded through capacitor C2 to achieve noise reduction.

[0141] The hysteresis comparator AMP2 controls the transistor M1 to turn on and off, causing capacitor C1 to charge and discharge, thus generating a linearly increasing and decreasing analog signal VOUT at the output of driver AMP1. (Refer to...) Figure 9b ,for Figure 9a The waveform diagram of the analog signal output by the ramp generator circuit is shown, where V0+ and V0- represent the peak values ​​of the analog signal, and the slope of the linear change of the analog signal VOUT is I / C.

[0142] Based on the linear relationship between the analog signal generated by the ramp generator and time, the output of the ramp generator can be connected to the input of a pipelined analog-to-digital converter (ADC) circuit within a specified time period. This allows the analog signal generated by the ramp generator during that time period to be used as a test analog signal input to the pipelined ADC circuit. The specified time period corresponds to the time period during which the ramp generator generates an analog signal that changes in a single direction (e.g., ...). Figure 9b The simulated signals in region ① and region ② can also correspond to the time periods during which the ramp generator generates simulated signals that change in multiple directions (e.g., ...). Figure 9b (Partial analog signals from regions ① and ②, etc.).

[0143] In specific implementation, multiple test analog signals can be acquired and input into the pipelined analog-to-digital converter circuit to statistically analyze the residual digital information corresponding to each test analog signal and determine whether there is a deviation in the gain of the front-end conversion module. Each test analog signal can vary in a single direction with different variations, i.e., each test analog signal has a different slope. Furthermore, when a deviation exists, the residual digital information corresponding to each test analog signal is statistically analyzed, and the digital domain weights of the corresponding front-end conversion module are adjusted. Specific details can be found in the descriptions of the aforementioned embodiments and will not be repeated here.

[0144] In specific implementation, such as Figure 6 As shown, the calibration method may further include the following steps: S05, determining whether the calibration termination condition is met; if so, acquiring the analog signal to be processed and performing analog-to-digital conversion; otherwise, continuing the calibration. This allows for control of the calibration duration.

[0145] The calibration termination conditions can be set based on the number of calibrations, calibration duration, and allowable deviation range (i.e., the range within which deviation can be considered to no longer exist), and this specification does not impose any limitations on these settings. To facilitate understanding and implementation of the calibration scheme provided in this specification by those skilled in the art, the following illustrative descriptions are provided in conjunction with the accompanying drawings and specific application scenarios.

[0146] In an optional example, such as Figure 10 The diagram shown is a structural diagram of an existing 12-bit precision pipelined analog-to-digital converter (ADC). The 12-bit precision pipelined ADC P3 includes seven conversion modules, namely, the first-stage conversion module (Stage 11) to the seventh-stage conversion module (Stage 17). Specific results of the conversion modules can be found in [reference needed]. Figure 1 The details and related content will not be elaborated here; the first-level conversion module Stage11 and the second-level conversion module Stage12 output 3 bits of the first-level thermometer code DS11 and the second-level DS12 respectively; the third-level conversion module Stage13 to the sixth-level conversion module Stage16 output 2 bits of the third-level to sixth-level thermometer codes DS13 to DS16 respectively; the seventh-level conversion module Stage17 outputs 4 bits of the seventh-level thermometer code DS17; the front-end conversion module 101 may include the first-level conversion module Stage11; the back-end conversion module may include the second-level conversion module Stage12 to the seventh-level conversion module Stage17.

[0147] When the numerical calculation module 103 performs staggered addition of the thermometer codes DS11~DS12 from the first-level conversion module Stage 11 to the seventh-level conversion module Stage 17, there is partial bit overlap between each level of the thermometer code, resulting in a 12-bit output code. See Table 1 below for details. Here, d12~d10 represent the most significant bit to the least significant bit of the first-level thermometer code DS11, and so on. d20~d73 represent the specific bits included in the second-level thermometer code DS12 to the seventh-level thermometer code DS17, respectively. Furthermore, Table 1 also shows the digital field weights corresponding to the first-level conversion module Stage 11 to the seventh-level conversion module Stage 17 as 512, 128, 64, 32, 16, 8, and 1, respectively.

[0148] Comparison Table 1

[0149] According to the above comparison table 1, the least significant bit of the previous stage thermometer code and the most significant bit of the next stage thermometer code coincide. The numerical calculation module 103 performs staggered addition according to the coincidence relationship shown in the comparison table 1 to obtain the 12-bit output code DSC.

[0150] Furthermore, based on the current digital field weights of the first-level conversion module (Stage 12) to the seventh-level conversion module (Stage 17), the digital output information DOUT corresponding to the 12-bit output code can be calculated using the following formula: DOUT= (d12*4+d11*2+d10*1)*512+ (d22*4+d21*2+d20*1)*128+ (d31*2+d30*1)*64+ (d41*2+d40*1)*32+ (d51*2+d50*1)*16+ (d61*2+d60*1)*8+ (d73*8+d72*4+d71*2+d70*1)*1.

[0151] By obtaining the thermometer codes (i.e., the second-level thermometer code DS12 to the seventh-level thermometer code DS17) and their corresponding digital field weights (i.e., 128~1) output by each level of the conversion module in the backend conversion module 102, the digital residual information Residue1 can be obtained: Residue1=(d22*4+d21*2+d20*1)*128+ (d31*2+d30*1)*64+ (d41*2+d40*1)*32+ (d51*2+d50*1)*16+ (d61*2+d60*1)*8+ (d73*8+d72*4+d71*2+d70*1)*1.

[0152] Based on the digital residual information Residue1, it is determined whether there is a deviation in the gain of the front-end conversion module. If a deviation exists, correction information is obtained based on the residual digital information Residue1, thereby adjusting the digital domain weights corresponding to the front-end conversion module 101. For example, the digital domain weights of the first-stage conversion module Stage 11 are modified to 512 + WE1, thereby indirectly modifying the theoretical digital domain output range of the front-end conversion module, making the calculated output digital information more reflective of the actual conversion capability of the 12-bit pipelined analog-to-digital converter circuit P3. Here, WE1 is the correction information, including the adjustment direction and correction amount. In addition, the adjustment direction can be represented by positive or negative signs. For details, please refer to the description of the relevant embodiments above, which will not be repeated here.

[0153] Therefore, when calculating the output numerical information DOUT, the adjusted digital field weights are used, i.e., DOUT=(d12*4+d11*2+d10*1)*(512+WE1)+( d22*4+d21*2+d20*1)*128+(d31*2+d30*1)*64+(d41*2+d40*1)*32+(d51*2+d50*1)*16+(d61*2+d60*1)*8+( d73*8+d72*4+d71*2+d70*1)*1, making the output numerical information more accurate and reliable.

[0154] It is understood that the embodiments described above provide multiple implementation schemes, and these implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending to multiple possible implementation schemes. These can all be considered as the implementation schemes disclosed and made public in this application.

[0155] This specification also provides calibration devices corresponding to the calibration methods described in any of the above embodiments. These devices will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the calibration methods discussed below can be referenced to the above embodiments and will not be repeated here. The calibration devices described below can be referred to in conjunction with the embodiments described above.

[0156] refer to Figure 11This is a schematic diagram of the connection between an analog-to-digital conversion circuit and a calibration device in an embodiment of this specification. In this embodiment, the analog-to-digital conversion circuit ADC1 may include a pipelined analog-to-digital conversion circuit P4, wherein the pipelined analog-to-digital conversion circuit P4 may include a front-end conversion module 11a having at least one conversion module, a back-end conversion module 11b having at least one conversion module, and the digital calculation module 11c.

[0157] For example, refer to Figure 11 The front-end conversion module 11a may include a first-level conversion module Stage 21, and the back-end conversion module 11b may include second-level conversion modules Stage 22 to Nth-level conversion modules Stage 2N. The digital calculation module 11c is adapted to calculate the temperature code (i.e., ...) output by each level of conversion modules Stage 21 to Stage 2N. Figure 11 The output code is calculated by combining the first-level thermometer code DS21 to the Nth-level thermometer code DS2N and the corresponding digital field weights.

[0158] The calibration device 110 is connected to the input terminal of the pipelined analog-to-digital converter circuit P4 and to the back-end conversion module 11b, and its specific structure is as follows: Figure 12 As shown. (Referencing reference 11 and...) Figure 12 The calibration device 110 may include: The signal generation module 111 is adapted to generate a test simulation signal and input the test simulation signal into the pipelined analog-to-digital converter circuit P4, so that the front-end conversion module 11a receives the test simulation signal and outputs a corresponding analog residual signal to the back-end conversion module 11b. The deviation detection module 112 is adapted to acquire residual digital information corresponding to the analog residual signal, and determine whether there is a deviation in the gain of the front-end conversion module 11a based on the residual digital information.

[0159] As can be seen from the above scheme, the analog residual signal measurement in the analog domain is converted into the residual digital information calculation in the digital domain. The gain of the front-end conversion module is then verified through the residual digital information, thereby avoiding the secondary error generated by measuring the analog residual signal and improving the calibration accuracy of the effective gain error. Furthermore, the calibration method provided in this specification is implemented based on the existing hardware architecture of the pipelined analog-to-digital converter circuit. Combined with existing logic operation devices, it can achieve good calibration results, thereby effectively reducing the hardware cost and implementation complexity required for calibration, improving the calibration response speed and execution speed, making the calibration more efficient, and having stronger universality.

[0160] It should be noted that the analog-to-digital conversion circuits in this specification may include other types besides pipeline-type analog-to-digital conversion circuits, and this specification does not impose any restrictions on this.

[0161] In specific implementation, such as Figure 12 As shown, the deviation detection module 112 may include any one of the following units: The first judgment unit 1121 is adapted to determine whether the output range of the measured digital domain corresponding to the residual digital information is consistent with the current theoretical digital domain output range of the front-end conversion module 11a; if they are inconsistent, it is determined that the front-end conversion module 11a has an error. The second judgment unit 1122 is adapted to determine whether the measurement gain corresponding to the residual digital information is consistent with the theoretical gain of the front-end conversion module 11a based on the measured value of the test simulation signal during the measurement time and the current theoretical digital domain output range of the front-end conversion module 11a; if they are inconsistent, it is determined that there is an error in the gain of the front-end conversion module 11a.

[0162] The specific implementation of the first judgment unit 1121 and the second judgment unit 1122 can be referred to the relevant content of the above calibration method, and will not be repeated here.

[0163] Therefore, by making reasonable and efficient use of the existing hardware architecture of pipelined analog-to-digital converter circuits, the difference between the actual and theoretical digital domain output range of the front-end conversion module can be determined by measuring the digital domain output range obtained through residual digital information. Alternatively, the difference between the actual and theoretical gain of the front-end conversion module can be determined by measuring the gain obtained through residual digital information. This reduces the hardware cost and implementation complexity required for calibration, improves the calibration response and execution speed, and makes the calibration more efficient and universally applicable.

[0164] In specific implementation, refer to Figure 11 The calibration device 110 can also be connected to the digital calculation module 11c. The deviation detection module 112 in the calibration device 110 is also adapted to, after determining that there is a deviation, instruct the digital calculation module 11c to adjust the digital domain weight corresponding to the front-end conversion module 11a according to the residual digital information.

[0165] Therefore, by adjusting the digital domain weights to match the actual gain capability of the front-end conversion module, the reliability and accuracy of the output results of the pipelined analog-to-digital converter can be improved without changing the existing hardware architecture of the pipelined analog-to-digital converter, while reducing the power consumption requirements for the same accuracy.

[0166] In specific implementation, in conjunction with reference Figure 11 and Figure 12 As shown, the deviation detection module 112 may further include any one of the following units: The first correction unit 1123 is adapted to instruct the digital calculation module 11c to reduce the digital domain weight corresponding to the front-end conversion module 11a when the span of the current theoretical digital domain output range of the front-end conversion module 11a is greater than the span of the measurement digital domain output range corresponding to the residual digital information; and to instruct the digital calculation module 11c to increase the digital domain weight corresponding to the front-end conversion module when the span of the current theoretical digital domain output range of the front-end conversion module 11a is less than the span of the measurement digital domain output range corresponding to the residual digital information. This makes the theoretical digital domain output range of the front-end conversion module 11a closer to the actual output range.

[0167] The second correction unit 1124 is adapted to instruct the digital calculation module 11c to reduce the digital domain weight corresponding to the front-end conversion module 11a when the theoretical gain corresponding to the front-end conversion module 11a is greater than the measurement gain corresponding to the residual digital information; and to instruct the digital calculation module 11c to increase the digital domain weight corresponding to the front-end conversion module 11a when the theoretical gain corresponding to the front-end conversion module 11a is less than the measurement gain corresponding to the residual digital information. This makes the theoretical gain corresponding to the front-end conversion module 11a closer to the actual gain of the front-end conversion module.

[0168] In specific implementation, such as Figure 11 and Figure 12 As shown, the calibration device 110 is connected to the output terminals of each conversion module in the back-end conversion module 11b; the deviation detection module 112 is adapted to detect the temperature codes (i.e., the output codes of the conversion modules in the back-end conversion module 11b) based on the output of each conversion module. Figure 11 The residual digital information is determined by using the thermometer code DS2M+1 (M+1 level) to the thermometer code DS2N (Nth level).

[0169] Specifically, in conjunction with reference Figure 11 and Figure 12 The deviation detection module may further include: Storage unit 1125 is adapted to store the thermometer code output by each level of the conversion module in the back-end conversion module 11b and the digital field weights corresponding to each level of the conversion module in the back-end conversion module 11b. The arithmetic unit 1126 is adapted to perform weighted calculations on the acquired thermometer code according to the digital field weights corresponding to each level of the conversion module in the back-end conversion module 11b, so as to obtain the residual digital information.

[0170] As shown above, by using the thermometer code obtained by quantization from the back-end conversion module in the pipelined analog-to-digital converter circuit and the set digital domain weights, the information of the residual analog signal output by the front-end conversion module in the digital domain can be calculated in reverse. This enables the indirect reading of the analog residual signal output by the front-end conversion module, allowing the residual digital information to effectively replace the analog residual signal for gain verification of the front-end conversion module. Furthermore, by making reasonable use of the existing hardware architecture of the pipelined analog-to-digital converter circuit, the hardware cost and implementation complexity required for calibration can be reduced, while the calibration response speed and execution speed can be improved, resulting in higher calibration efficiency.

[0171] In specific implementation, in conjunction with reference Figure 11 and 12 The signal generation module 111 is adapted to generate multiple analog signals and input each of the test analog signals into the pipeline-type analog-to-digital converter circuit P4, wherein each of the analog signals changes in a single direction and in a different manner.

[0172] The deviation detection module 112 is adapted to statistically analyze the residual digital information corresponding to each of the test analog signals and determine whether there is a deviation in the gain of the front-end conversion module 11a; and after determining that there is a deviation, it instructs the digital calculation module to adjust the digital domain weight corresponding to the front-end conversion module according to the statistically analyzed residual digital information corresponding to each of the test analog signals.

[0173] This reduces the probability of false positives and false negatives, decreases the number of gain adjustments, and improves calibration efficiency. In practical implementation, it is combined with reference... Figure 11 and 12 The deviation detection module 112 may further include a third judgment unit 1127, adapted to determine whether the calibration end condition is met. If so, the calibration ends; otherwise, the calibration continues. This allows control over the calibration duration.

[0174] This specification also provides a lidar using the analog-to-digital conversion circuit described in any of the above embodiments, which will be described in detail below with reference to the accompanying drawings.

[0175] In specific implementation, such as Figure 13 The diagram shown is a structural diagram of a lidar system according to an embodiment of this specification. The lidar system Laser1 may include: a detection device DE1, an analog-to-digital converter circuit ADC1, and a calibration device 110; wherein: The detection device DE1 is adapted to acquire echo signals and output the analog signal to be processed to the analog-to-digital converter circuit ADC1.

[0176] The analog-to-digital converter circuit ADC1 is adapted to perform analog-to-digital conversion on the analog signal to be processed by the detection device DE1 or the test analog signal of the calibration device 110; the analog-to-digital converter circuit ADC1 may include a pipelined analog-to-digital converter circuit P4, wherein the pipelined analog-to-digital converter circuit P4 may include a front-end conversion module 11a having at least one conversion module, a back-end conversion module 11b having at least one conversion module, and a digital computing module 11c; for details, please refer to the description of the relevant content above, which will not be repeated here.

[0177] The calibration device 110 is adapted to calibrate the pipeline-type analog-to-digital converter circuit P4 based on the generated test simulation signal.

[0178] In practical implementation, after the calibration device completes the calibration of the pipelined analog-to-digital converter (ADC), the theoretical gain (or theoretical digital domain output range) of the pipelined ADC is closer to the actual situation. Therefore, the ADC calibrated by the calibration device described in this embodiment has more accurate and reliable output digital information. The detection device is activated after the calibration device completes calibration to acquire echo signals and output the analog signal to be processed. After the ADC completes mode conversion of the analog signal to be processed, the value of the analog signal to be processed can be more accurately inferred based on the output value information of the pipelined ADC in the ADC.

[0179] In specific implementation, such as Figure 13 As shown, the lidar Laser1 may also include a control device CO1, which is adapted to control the calibration device 110 to calibrate the pipeline analog-to-digital converter circuit P4 after the lidar Laser1 is powered on, and to control the calibration device 110 to end the calibration after the calibration end condition is met, and to make the analog-to-digital converter circuit ADC1 perform analog-to-digital conversion processing on the analog signal to be processed.

[0180] In specific implementations, the detection device may include a photodetector. Specifically, the photodetector may include: a single-photon avalanche photodiode (SPAD) array, a silicon photomultiplier (SiPM), and an avalanche photodiode (APD).

[0181] In practical applications, the modules and units included in the calibration device provided in the embodiments of this specification can all be implemented using corresponding hardware circuits, devices, and various hardware combinations. For example, the signal generation module can be implemented using a signal generator circuit; the first judgment unit, the second judgment unit, the first correction unit, the second correction unit, etc., can be implemented using processing chips such as microcontrollers and field-programmable gate arrays (FPGAs); the storage unit can be implemented using random access memory (RAM), registers, etc. The embodiments of this specification do not impose any limitations on this.

[0182] It is understood that the embodiments described above provide multiple implementation schemes, and these implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending to multiple possible implementation schemes. These can all be considered as the implementation schemes disclosed and made public in this application.

[0183] It should be noted that the term "an embodiment" or "embodiment" as used in this specification refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this specification. Furthermore, in the description of this specification, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with terms such as "first" and "second" may explicitly or implicitly include one or more of that feature. Moreover, terms such as "first" and "second" are used to distinguish similar objects and are not necessarily used to describe a specific order or indicate importance. It is understood that such terms can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein.

[0184] While the embodiments disclosed in this specification are as described above, they are not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments in this specification. Therefore, the scope of protection of the embodiments in this specification should be determined by the scope defined in the claims.

Claims

1. A calibration method for analog-to-digital conversion circuits, characterized in that, The analog-to-digital conversion circuit includes a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit includes a front-end conversion module having at least one conversion module and a back-end conversion module having at least one conversion module, and the calibration method includes: The test analog signal is input into the pipeline-type analog-to-digital converter circuit so that the front-end conversion module receives the test analog signal and outputs the corresponding analog residual signal to the back-end conversion module; Obtaining residual digital information corresponding to the analog residual signal includes: obtaining the thermometer code and corresponding digital domain weights output by each conversion module in the back-end conversion module; performing weighted calculation based on the obtained thermometer code and corresponding digital domain weights to obtain the residual digital information; Based on the residual digital information, determine whether there is a deviation in the gain of the front-end conversion module; When a deviation exists, the digital domain weights corresponding to the front-end conversion module are adjusted according to the residual digital information, wherein the adjustment direction of the digital domain weights is: to approach the direction of the actual gain of the front-end conversion module.

2. The calibration method for analog-to-digital conversion circuits according to claim 1, characterized in that, The step of determining whether there is a deviation in the gain of the front-end conversion module based on the residual digital information includes any of the following: Determine whether the measured digital domain output range corresponding to the residual digital information is consistent with the current theoretical digital domain output range of the front-end conversion module; if they are inconsistent, determine that there is an error in the gain of the front-end conversion module. Based on the measured value of the test simulation signal at the measurement time and the current theoretical digital domain output range of the front-end conversion module, determine whether the measurement gain corresponding to the residual digital information is consistent with the theoretical gain of the front-end conversion module; When there is a discrepancy, it is determined that there is an error in the gain of the front-end conversion module.

3. The calibration method for analog-to-digital conversion circuits according to claim 1, characterized in that, The adjustment of the digital domain weights of the front-end conversion module based on the residual digital information includes any of the following: If the span of the theoretical digital domain output range of the front-end conversion module is greater than the span of the measured digital domain output range corresponding to the residual digital information, then the digital domain weight corresponding to the front-end conversion module is reduced. If the span of the theoretical digital domain output range of the front-end conversion module is smaller than the span of the measured digital domain output range corresponding to the residual digital information, then the digital domain weight corresponding to the front-end conversion module is increased. If the theoretical gain corresponding to the front-end conversion module is greater than the measurement gain corresponding to the residual digital information, then the digital domain weight corresponding to the front-end conversion module is reduced. If the theoretical gain corresponding to the front-end conversion module is less than the measurement gain corresponding to the residual digital information, then the digital domain weight corresponding to the front-end conversion module is increased.

4. The calibration method for analog-to-digital conversion circuits according to claim 1 or 2, characterized in that, The front-end conversion module includes a first-level conversion module.

5. The calibration method for analog-to-digital conversion circuits according to claim 1 or 2, characterized in that, The step of inputting the test analog signal into the pipeline-type analog-to-digital converter circuit includes: Multiple test analog signals are acquired and each test analog signal is input into the pipeline-type analog-to-digital converter circuit to statistically analyze the residual digital information corresponding to each test analog signal and determine whether there is a deviation in the gain of the front-end conversion module. Each test analog signal changes in a single direction and in a different way. When a deviation exists, the residual digital information corresponding to each of the test simulation signals is statistically analyzed, and the digital domain weights corresponding to the front-end conversion module are adjusted.

6. A calibration device for analog-to-digital conversion circuits, characterized in that, The analog-to-digital conversion circuit includes a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit includes a front-end conversion module with at least one conversion module, a back-end conversion module with at least one conversion module, and a digital calculation module, the digital calculation module being adapted to calculate output digital information based on the thermometer code and corresponding digital domain weights output by each conversion module; the calibration device includes: The signal generation module is adapted to generate a test analog signal and input the test analog signal into the pipelined analog-to-digital converter circuit, so that the front-end conversion module receives the test analog signal and outputs a corresponding analog residual signal to the back-end conversion module; The deviation detection module is adapted to acquire residual digital information corresponding to the analog residual signal, and determine whether there is a deviation in the gain of the front-end conversion module based on the residual digital information. After determining that there is a deviation, the module instructs the digital calculation module to adjust the digital domain weight corresponding to the front-end conversion module based on the residual digital information. The adjustment direction of the digital domain weight is: to approach the direction of the actual gain of the front-end conversion module. The deviation detection module includes: a storage unit, adapted to store the thermometer codes output by each level of the conversion module in the back-end conversion module and the digital domain weights corresponding to each level of the conversion module in the back-end conversion module; The arithmetic unit is adapted to perform weighted calculations on the acquired thermometer code according to the digital domain weights corresponding to each level of the conversion module in the back-end conversion module, so as to obtain the residual digital information.

7. The calibration device for analog-to-digital conversion circuits according to claim 6, characterized in that, The deviation detection module includes any one of the following units: The first judgment unit is adapted to determine whether the output range of the measured digital domain corresponding to the residual digital information is consistent with the current theoretical digital domain output range of the front-end conversion module; if they are inconsistent, it is determined that the front-end conversion module has an error. The second judgment unit is adapted to determine whether the measurement gain corresponding to the residual digital information is consistent with the theoretical gain of the front-end conversion module based on the measured value of the test simulation signal at the measurement time and the current theoretical digital domain output range of the front-end conversion module. When there is a discrepancy, it is determined that there is an error in the gain of the front-end conversion module.

8. The calibration device for analog-to-digital conversion circuits according to claim 6, characterized in that, The deviation detection module further includes any one of the following units: The first correction unit is adapted to instruct the digital calculation module to reduce the digital domain weight corresponding to the front-end conversion module when the span of the current theoretical digital domain output range of the front-end conversion module is greater than the span of the measured digital domain output range corresponding to the residual digital information. When the span of the theoretical digital domain output range of the front-end conversion module is smaller than the span of the measured digital domain output range corresponding to the residual digital information, the digital calculation module is instructed to increase the digital domain weight corresponding to the front-end conversion module. The second correction unit is adapted to instruct the digital calculation module to reduce the digital domain weight corresponding to the front-end conversion module when the theoretical gain corresponding to the front-end conversion module is greater than the measurement gain corresponding to the residual digital information. When the theoretical gain corresponding to the front-end conversion module is less than the measurement gain corresponding to the residual digital information, the digital calculation module is instructed to increase the digital domain weight corresponding to the front-end conversion module.

9. The calibration device for analog-to-digital conversion circuits according to claim 6 or 7, characterized in that, The front-end conversion module includes a first-level conversion module.

10. The calibration device for analog-to-digital conversion circuits according to claim 6 or 7, characterized in that, The signal generation module is adapted to generate multiple test simulation signals and input each of the test simulation signals into the pipeline-type analog-to-digital converter circuit, wherein each of the simulation signals changes in a single direction and in a different manner; The deviation detection module is adapted to statistically analyze the residual digital information corresponding to each of the test analog signals and determine whether there is a deviation in the gain of the front-end conversion module; and after determining that there is a deviation, it instructs the digital calculation module to adjust the digital domain weight corresponding to the front-end conversion module according to the statistically analyzed residual digital information corresponding to each of the test analog signals.

11. A lidar, characterized in that, include: The detection device, the analog-to-digital conversion circuit, and the calibration device according to any one of claims 6 to 10; wherein: The detection device is adapted to acquire echo signals and output analog signals to be processed to the analog-to-digital conversion circuit. The analog-to-digital conversion circuit is adapted to perform analog-to-digital conversion on the analog signal to be processed by the detection device or the test analog signal of the calibration device; it includes a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit includes a front-end conversion module with at least one conversion module, a back-end conversion module with at least one conversion module, and a digital computing module; The calibration device is adapted to calibrate the pipeline-type analog-to-digital converter circuit based on the generated test simulation signal.

12. The lidar according to claim 11, characterized in that, Also includes: The control device is adapted to control the calibration device to calibrate the pipelined analog-to-digital conversion circuit after the radar is powered on, and to control the calibration device to end the calibration after the calibration end conditions are met, and to cause the analog-to-digital conversion circuit to perform analog-to-digital conversion processing on the analog signal to be processed.

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