Pre-screening and tuning heterojunctions for topological quantum computers

Abstract

A method for evaluating a semiconductor-superconductor heterojunction in a qubit register for a topological quantum computer includes: measuring the radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; analyzing the mapping data to locate one or more regions in a parameter space that correspond to the complete topology of the semiconductor-superconductor heterojunction; measuring subRF conductance, including nonlocal conductance of the semiconductor-superconductor heterojunction, in each of the one or more regions in the parameter space to obtain refined data; and analyzing the refined data to locate the boundary of the complete topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction for at least one region in the one or more regions of the parameter space.

Description

Background Technology

[0001] A quantum computer is a physical machine configured to perform logical operations based on or influenced by quantum mechanical phenomena. Such logical operations can include, for example, mathematical calculations. Current interest in quantum computing technology stems from analyses suggesting that, when applied to certain types of problems, a properly configured quantum computer may be more computationally efficient than any practical non-quantum computer. These problems include computer modeling of natural and synthetic quantum systems applied to linear equations and machine learning systems, integer factorization, data search, and function optimization. Furthermore, it is predicted that the continued miniaturization of traditional computer logic structures will eventually lead to the development of nanoscale logic components exhibiting quantum effects, which must therefore be addressed according to the principles of quantum computing.

[0002] Different types of quantum computers operate based on different quantum mechanical phenomena. A "topological" quantum computer is one whose operations are based on non-Abelian topological phases of matter that may support "interleaved" quasiparticles. This type of quantum computer is expected to be less prone to quantum decoherence problems than other types of quantum computers, and therefore can serve as a relatively fault-tolerant quantum computing platform. Summary of the Invention

[0003] One aspect of this disclosure relates to a method for evaluating a semiconductor-superconductor heterojunction in a qubit register for a topological quantum computer. The method includes: measuring the radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data, and analyzing the mapping data to locate one or more regions in a parameter space consistent with the complete topology of the semiconductor-superconductor heterojunction. The method further includes: measuring subRF conductance, including nonlocal conductance of the semiconductor-superconductor heterojunction, in each of the one or more regions of the parameter space to obtain refined data, and analyzing the refined data to locate the boundary of the complete topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction for at least one region of the one or more regions of the parameter space.

[0004] This summary provides a simplified overview of the conceptual choices further described in the detailed embodiments. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. The claimed subject matter is not limited to addressing any or all of the shortcomings pointed out in any part of this disclosure. Attached Figure Description

[0005] Figure 1 An aspect of an example quantum computer is shown.

[0006] Figure 2 The Bloch sphere is shown as a graphical representation of the quantum state of a qubit in a quantum computer.

[0007] Figure 3 An aspect of an example signal waveform used to implement quantum gate operations in a quantum computer is shown.

[0008] Figure 4 An aspect of an example qubit architecture including a linear tetron array is shown.

[0009] Figure 5 An aspect of an example semiconductor-superconductor heterojunction device evaluated according to the method described herein is shown.

[0010] Figure 6 An aspect of an example method for evaluating semiconductor-superconductor heterojunctions for qubit registers in topological quantum computers is shown.

[0011] Figure 7 An aspect of an example radio frequency (RF) reflectometer test circuit is shown.

[0012] Figure 8 An aspect of an example method for measuring the RF junction admittance of a semiconductor-superconductor heterojunction is shown.

[0013] Figure 9 This shows the analysis of data from... Figure 8 This is an example of a method that uses data to find regions in the parameter space that correspond to the complete topology of a semiconductor-superconductor heterojunction.

[0014] Figure 10 It shows according to Figure 1 The method analyzes aspects of the mapped data.

[0015] Figure 11 An aspect of an example subRF conductivity test circuit is shown.

[0016] Figure 12 An aspect of an example method for measuring the subRF conductance of a semiconductor-superconductor heterojunction is shown.

[0017] Figure 13 This shows the analysis of data from... Figure 12 This section presents an example of a method that uses data to find the boundaries of complete topological phases in parameter space and the topological gaps in semiconductor-superconductor heterojunctions.

[0018] Figure 14 It shows according to Figure 13 The method is to analyze aspects of refined data.

[0019] Figure 15The effect of the smoothing potential at the right end of the semiconductor line is shown in a 1D model of a semiconductor-superconductor heterojunction.

[0020] Figure 16 The effect of the smoothing potential at the center of the semiconductor line is shown in a 1D model of a semiconductor-superconductor heterojunction.

[0021] Figure 17 The results of data analysis in the field / plunger parameter space of a 1D model of a semiconductor-superconductor heterojunction with potential bumps at the center of a semiconductor line are shown.

[0022] Figure 18 The results of the field / plunger parameter space data analysis for a strongly disordered 1D model of a semiconductor-superconductor heterojunction are presented.

[0023] Figure 19 Aspects of an example instrument configured to evaluate a semiconductor-superconductor heterojunction for a qubit register in a topological quantum computer are shown.

[0024] Figure 20 An aspect of an example method for constructing a topological quantum computer is shown. Detailed Implementation

[0025] Quantum computer architecture

[0026] Figure 1 Aspects of an example quantum computer 10 configured to perform quantum logic operations are shown (see below). While conventional computer memory stores digital data in bit arrays and performs bit-by-bit logic operations, quantum computers store data in qubit arrays and perform quantum mechanical operations on the qubits to implement the desired logic. Therefore, Figure 1 The quantum computer 10 includes at least one qubit register 12 containing an array of qubits 14. The illustrated qubit register is 8 qubits long; qubit registers including longer and shorter qubit arrays are also envisioned, as well as quantum computers including two or more qubit registers of arbitrary length.

[0027] The qubit 14 of the qubit register 12 can take various forms depending on the desired architecture of the quantum computer 10. While this disclosure relates to qubits implemented as quasi-particles in non-Abelian topological phases, a qubit may optionally include the following as non-limiting examples: a superconducting Josephson junction, trapped ions, trapped atoms coupled to a high-fine-cavity, atoms or molecules confined within a fullerene, ions or neutral dopant atoms confined within a host lattice, quantum dots exhibiting discrete spatial or spin-electronic states, electron-hole pairs in a semiconductor junction enclosed by an electrostatic trap, coupled quantum wire pairs, atomic nuclei addressable by magnetic resonance, free electrons in helium, molecular magnets, or metalloid carbon nanospheres. More generally, each qubit 14 may include any particle or particle system that can exist in two or more discrete quantum states, which can be measured and manipulated experimentally. For example, a qubit can be implemented in multiple processing states corresponding to different light propagation modes via linear optical elements (e.g., mirrors, beam splitters, and phase shifters) and in states accumulated in a Bose-Einstein condensate.

[0028] Figure 2 This is a diagram of the Bloch sphere 16, which provides a graphical description of some quantum mechanical aspects of a single qubit 14. In this description, the north and south poles of the Bloch sphere correspond to the standard basis vectors |0> and |1>, respectively. The set of points on the surface of the Bloch sphere includes all possible pure states |Ψ> of the qubit, while the internal points correspond to all possible mixed states. The mixed state of a given qubit may be caused by decoherence, which may occur due to poor coupling with the external degrees of freedom.

[0029] Now back Figure 1The quantum computer 10 includes a controller 18A. The controller includes at least one processor 20A and associated computer memory 22A. The processor 20A of the controller 18A can be operatively coupled to peripheral components (such as network components) to enable the quantum computer to be remotely operated. The processor 20A of the controller 18A can take the form of a central processing unit (CPU), a graphics processing unit (GPU), etc. Therefore, the controller can include conventional electronic components. The terms “classical” and “non-quantum” apply herein to any component that can be precisely modeled as a whole of particles, without regard to the quantum state of any individual particle. For example, classical electronic components include integrated microlithographic transistors, resistors, and capacitors. The computer memory 22A can be configured to store program instructions 24A that cause the processor 20A to perform any function or processing of the controller. The computer memory can also be configured to store additional data 26A. In an example where the qubit register 12 is a cryogenic or ultra-cryo-cryo device, the controller 18A can include control components capable of operating at cryogenic or ultra-cryo ... In such an example, the cryogenic control component can be operatively coupled to an interface component that can operate at ambient temperature.

[0030] The controller 18A of the quantum computer 10 is configured to receive multiple inputs 28 and provide multiple outputs 30. The inputs and outputs may each include digital and / or analog lines. At least some of the inputs and outputs may be data lines through which data is provided to and / or extracted from the quantum computer. Other inputs may include control lines through which the operation of the quantum computer can be adjusted or controlled.

[0031] Controller 18A is operatively coupled to qubit register 12 via quantum interface 32. The quantum interface is configured to exchange data bidirectionally with the controller. The quantum interface is also configured to exchange signals corresponding to the data bidirectionally with the qubit register. Depending on the architecture of quantum computer 10, such signals may include electrical, magnetic, and / or optical signals. As defined by the collective quantum state of the array of qubits 14, the controller can query and otherwise influence the quantum state held in the qubit register via the signals transmitted through the quantum interface. For this purpose, the quantum interface includes at least one modulator 34 and at least one demodulator 36, each operatively coupled to one or more qubits of the qubit register. Each modulator is configured to output a signal to the qubit register based on modulated data received from the controller. Each demodulator is configured to sense the signal from the qubit register and output data to the controller based on that signal. In some examples, the data received from the demodulator may be an observable estimate of a measurement of the quantum state held in the qubit register.

[0032] In some examples, a properly configured signal from modulator 34 can physically interact with one or more qubits 14 of qubit register 12 to trigger a measurement of the quantum state held in one or more qubits. Demodulator 36 can then sense the resulting signal emitted by one or more qubits according to the measurement and can provide data corresponding to the resulting signal to controller 18A. In other words, demodulator can be configured to output an estimate of one or more observables reflecting the quantum state of one or more qubits of qubit register based on the received signal and provide that estimate to controller. In a non-limiting example, modulator can provide appropriate voltage pulses or pulse sequences to the electrodes of one or more qubits based on data from controller to initiate the measurement. In short, demodulator can sense photon emission from one or more qubits and can apply the corresponding digital voltage level on the quantum interface line to controller. Generally, any measurement of a quantum mechanical state is defined by an operator O corresponding to the observable to be measured; the result R of the measurement is guaranteed to be one of the allowed eigenvalues ​​of O. In quantum computer 10, R is statistically related to the qubit register state prior to the measurement, but is not uniquely determined by the qubit register state.

[0033] Based on appropriate inputs from controller 18A, quantum interface 32 can be configured to implement one or more quantum logic gates to operate on quantum states stored in qubit register 12. While the function of each type of logic gate in a classical computer system is described according to a corresponding truth table, the function of each type of quantum gate is described by a corresponding operator matrix. The operator matrix operates (i.e., multiplies) on the complex vector representing the qubit register state and affects a specified rotation of that vector in Hilbert space.

[0034] For example, Adamamen HAD is defined as

[0035]

[0036] The HAD gate acts on a single qubit; it maps the fundamental state |0> to... Map |1> to Accordingly, when measuring, the HAD gate creates a superposition of states that show equal probabilities of |0> or |1>.

[0037] The phase gate S is defined as

[0038]

[0039] The S gate keeps the basic state |0> unchanged, but maps |1> to e. iπ / 2|1>. Therefore, the gate does not change the probability of measuring |0> or |1>, but the phase of the quantum state of the qubit will be shifted. This is equivalent to shifting ψ in Figure 2 Rotate 90 degrees along the latitude circle on the Bloch sphere.

[0040] Some quantum gates operate on two or more qubits. For example, the SWAP gate acts on two different qubits and swaps their values. This gate is defined as...

[0041]

[0042] The list of quantum gates and related operator matrices above is not exhaustive and is provided for illustrative purposes only. Other quantum gates include the following as non-limiting examples: Pauli-X gate, Pauli-Y gate, and Pauli-Z gate. Door, Additional phase-shifting door, Gates, controlled CX gates, controlled CY gates and controlled CY gates, as well as Tofoli gates, Fredkin gates, Ising gates and Deutsch gates.

[0043] Continue as Figure 1 As shown, a properly configured signal from the modulator 34 of the quantum interface 32 can physically interact with one or more qubits 14 of the qubit register 12 to enable any desired quantum gate operation. As described above, the desired quantum gate operation is a rotation of a specifically defined complex vector representing the state of the qubit register. To achieve the desired rotation O, one or more modulators of the quantum interface 32 can be used for a predetermined duration T. i Apply a predetermined signal level S i In some examples, such as Figure 3 As shown, multiple signal levels can be applied over multiple sequential or otherwise correlated durations to enable quantum gate operations on one or more qubits of a qubit register. Typically, each signal level S... i and each duration T i These are control parameters that can be adjusted through proper programming of the controller 18A.

[0044] The term "oracle" is used herein to describe a predetermined sequence of basic quantum gates and / or measurement operations that can be executed by the quantum computer 10. For example, an oracle can be used to transform the quantum states of the qubit register 12 to implement classical quantum gate operations or non-basic quantum gate operations, or to implement applied density operators. In some examples, an oracle can be used to formulate a predefined "black box" operation f(x), which can be incorporated into a complex sequence of operations. To ensure the companion operation, the oracle's mapping of n input qubits |x> to m output or auxiliary qubits |y> = f(x) can be defined as a quantum gate operation performed on n+m qubits. In this case, O can be configured to pass n input qubits unchanged, but combine the result of operation f(x) with the auxiliary qubits through an XOR operation, so that... As further described below, a state-ready oracle is an oracle configured to generate quantum states of a specified qubit length.

[0045] Implicit in this description is that each qubit 14 of the qubit register 12 can be queried via the quantum interface 32 to reliably reveal the standard basis vectors |0> or |1> characterizing the quantum state of that qubit. However, in some implementations, the measurement of the quantum state of a physical qubit may be erroneous. Therefore, any qubit 14 can be implemented as a logical qubit comprising a group of physical qubits that is measured according to an error-correction prediction that reliably reveals the quantum state of the logical qubit.

[0046] Topological quantum computer

[0047] In a topological quantum computer, the quantum state in each qubit is the state of two or more interleaved quasi-particles or "anyons" observed in a non-Abelian topological phase of matter. The worldlines of different anyons are quantum mechanically forbidden from intersecting or merging. This characteristic forces their paths to form stable braids that intertwine in spacetime. Anyons in these braids are more resistant to quantum decoherence, a source of error in quantum computing, compared to trapped particles used in other types of quantum computers. However, realizing a topological quantum computer requires the ability to design a suitable topological phase and manipulate the anyons within it.

[0048] Early experiments in topological quantum computing focused on two-dimensional “electron gases” of supercooled thin layers of gallium arsenide (GaAs) sandwiched between layers of aluminum gallium arsenide (AlGaAs) and manipulated in strong magnetic fields. Realizing a quantum computer using this architecture requires an interweaving of individual quasiparticle excitations with measurements based on arbitrary interferometry, including coherent quasiparticle transport over considerable distances.

[0049] A recently proposed one-dimensional topological qubit architecture appears to be more suitable for practical implementation. The proposed system utilizes a semiconductor-superconductor heterostructure, where superconductivity, strong spin-orbit coupling, and a magnetic field collectively form a topologically superconducting state supporting Majorana zero modes (MZMs). This novel architecture eliminates the need for moving quasiparticles by employing a "measure-only" approach, where a series of measurements achieves the same effect as interleaving operations. Instead of requiring quasiparticle movement through an interferometric measurement loop, this architecture leverages the distinction between a "fermion parity-protected topological phase" (the actual genus of the proposed heterostructure) and a true topological phase. Advantageously, the topological charge in the fermion parity-protected topological phase can be manipulated through electron tunneling into the MZM. The combined topological charge can be measured via the transport of MZM pairs in the presence of large charging energies.

[0050] Given these and other useful properties, MZMs can be used as the qubit basis for topological quantum computers. MZMs are created at the ends of semiconductor superconducting heterostructures tuned to topological states by appropriate magnetic fields and gate voltages. A series of practical implementations are described in Karzig et al.'s *Scalable Designs for Quasiparticle-Poisoning-Protected Topological Quantum Computation with Majorana Zero Modes*, arXiv:1610.05289v4 [cond-mat.mes-hall] 21 Jun 2017. Suitable heterostructure materials and material properties are described in Lutchyn et al.'s *Majorana Fermions and a Topological Phase Transition in Semiconductor-Superconductor Heterostructures*, arXiv:1002.4033v2 [cond-mat.supr-con] 13 Aug 2010. Example implementations include at least two topological superconducting segments in the qubit, with each qubit having a total of at least four Majorana zero modes. In contrast to non-degenerate quantum computing architectures where the two states of a qubit have different energies, the states used for quantum computing will be the degenerate ground state of the qubit. The degeneracy of the qubit state and the spatial separation of Majorana zero modes ensure long coherence times and the feasibility of precisely applying Clifford gate sets.

[0051] Figure 4An example of a topological qubit architecture including a linear tetron array 38 is shown. The linear tetron array includes segments 40 and 42 containing classical superconductors (such as aluminum (Al)), segment 44 containing semiconductors (such as indium arsenide (InAs) or indium antimonide (InSb)), and multiple MZMs 46. The length l of the non-topological segment is... c Much greater than the coherence length ξ corresponding to the non-topological region c The length l of the topological segment t It is much greater than the coherence length ξ of the topological region. Figure 4 The dashed box in the figure represents a single qubit in the form of a linear tetron. Additional topological superconducting links and semiconductor structures allow for appropriate measurements to manipulate and entangle linear tetrons.

[0052] like Figure 4 The qubit structures shown are difficult to fabricate with the reproducibility required for practical quantum computing. Due to material or fabrication defects, some candidate structures may not operate in the desired topological state. Even for candidate structures that operate in the desired topological state, the appropriate terminal bias and magnetic field levels required for qubit operations cannot always be predicted a priori. Therefore, candidate semiconductor-superconductor heterojunctions must be “pre-screened” to obtain appropriate topological behavior, and successful heterojunctions must be “tuned” to find suitable operational parameters before being incorporated into the qubit register.

[0053] Method Overview

[0054] This disclosure provides a method for pre-screening and refining candidate semiconductor-superconductor heterojunctions for topological qubits. The method includes a process of extracting “topological gaps” (see below) of candidate heterojunctions using at least two measurement stages followed by analysis. Measurements are performed on a device with three current-carrying contacts, one of which is superconducting (here referred to as a “three-terminal device”). The “mapping” stage of the method includes rapid radio frequency measurements that can coarsely identify promising regions. A subsequent “refining” stage includes slower sub-RF (e.g., DC) measurements performed on each promising region identified in the mapping stage. In some examples, the method uses a density-based clustering algorithm on both sides of zero bias peak (ZBP) data to extract predicted topological regions and classifies deviation trajectories using peak finding or machine learning. It improves the accuracy of previous methods by examining the stability of ZBP to changes in the cutoff gate voltage and by checking for gap closure at the boundaries of suspicious topological regions. Meta-analysis of the ZBP data is used to extract the probability of finding topological regions in many devices of the same fabrication. This feature can be used to characterize the growth and / or fabrication methods of the topological qubit structure.

[0055] As used in this paper, "false affirmations" identify ordinary systems as topological systems, while "false denials" identify topological systems as ordinary. The technique presented in this paper improves the basic ZBP search by including separate ZBP searches on both sides of the three-terminal device, thereby reducing the probability of false alarms. It also includes nonlocal measurements to extract band gaps in candidate systems, providing additional information for detecting topological gaps. Finally, it includes nondiscriminatory measurements within a parameter space region with predefined boundaries, thus eliminating false affirmations stemming from confirmation and selection biases (which could occur if the measurement region is manually selected).

[0056] Figure 5 An aspect of an example semiconductor-superconductor heterojunction device 48 evaluated according to the method described herein is shown. Generally, semiconductor-superconductor heterojunctions suitable for testing include at least three terminals supporting electronic admittance and conductance measurements, in addition to multiple electrostatic control terminals. Figure 5 The device 48 is a three-terminal device comprising a topological intermediate segment 50 coupled to a grounding probe 52 via a conventional superconductor, and two conventional probes 54R and 54L coupled to both ends of a semiconductor line. This geometry allows for simultaneous measurement of the tunneling characteristics of the topological phase at both ends of the intermediate segment 50, for correlation with the zero-bias characteristics on both sides. Furthermore, the non-local signal between the two conventional probes provides information about the lowest energy of the topological segment's expansion state, which can be used as a proxy for topological gaps (e.g., in a sufficiently long semiconductor line, the non-local signal is set to a bias value corresponding to the lowest energy expansion mode in the conductor). Therefore, the method presented in this paper does not directly measure the topological characteristics of the system, but rather measures a set of proxy variables that, as demonstrated by analytical calculations and numerical simulations, correlate well with topological invariants. Alternative criteria for identifying non-ordinary regions of the topology are as follows:

[0057] 1. The relevant zero-bias differential conductance peaks appear on both sides of the device, and the entire topology region exhibits well-separated Majorana.

[0058] 2. For low magnetic field values, the body of the system has a gap. As the magnetic field increases, the gap in the body should close and reopen within the topological region. The bandgap value in the conductor body can be detected in a three-terminal device by nonlocal conductivity measurement.

[0059] Within a region that satisfies the topological criteria in the parameter space, the size of the body gap can vary. In the context of this disclosure, the operational meaning of the term "topological gap" is the size of the maximum body gap in such a topological region.

[0060] In order to distinguish between topological and non-topological systems, this method must correctly identify topological regions in an idealized numerical test dataset. Therefore, the method presented in this paper demonstrates a high degree of overlap between the topologically identified regions and the numerically determined topological indices (e.g., as shown in the original text). Figure 10 (As shown). Furthermore, the method must correctly label currently known erroneous positive signature candidates as non-topological. These include:

[0061] 1. Ordinary local bound states caused by cutoffs, impurities, or smoothing potentials (e.g., quasi-Majorana mode pairs at the end of a device), which are examples of non-topological zero-bias peaks;

[0062] 2. Low-energy interstitial states caused by disorder (non-topological zero-bias peaks and possible unexpected interstitial closure / reopening characteristics);

[0063] 3. Ordinary gap closure without proper reopening in finite-size systems (e.g., Coulomb blocking systems), where a finite-size gap closes at a small field and causes oscillations in a low-energy state (pseudo-gap closure / reopening characteristic); and

[0064] 4. Ordinary closure-like characteristics caused by discrete state sets across zero energy (faulty gap closure / reopening characteristics).

[0065] This method reduces such false alarms by using data collected over a wide range of parameter values. Accidental or fine-tuned points should not persist with parameter variations as the topological phase would. Furthermore, this method correlates different indicators of the topological phase, as both criteria are yet to be verified—namely, the zero-bias conductance peak must appear simultaneously at both ends, and the system needs to demonstrate gap closure and reopening functionality in nonlocal conductance. Given these criteria, the aforementioned false alarms can be correctly identified because:

[0066] 1. The errors listed above, 1 and 2, certainly lack the characteristic of gap closure / reopening in nonlocal conductance; and

[0067] 2. Errors 3 and 4 indicate a lack of correlated and stable zero-bias peaks at both ends of the semiconductor line.

[0068] Different types of errors are bound to occur simultaneously and are not expected to remain stable with changes in the parameter space.

[0069] A remaining problem with this method is preventing erroneous negations, which will be addressed further below. Specifically, concrete construction examples combining features 1 and 4 with erroneous affirmative regions are addressed, as well as examples relevant to strongly disordered systems. While disorder leads to zero-bias peaks, it generally does not lead to extended regions of the associated ZBP. Similar stability requirements exclude potential erroneous affirmations 3 listed above.

[0070] This method follows these principles:

[0071] 1. The method must ensure that both of the criteria listed above can be verified.

[0072] 2. The measurement device needs the widest possible parameter space because:

[0073] a. The initial uncertainty regarding the existence and location of the topological phase may be high.

[0074] b. Checking the stability of the zero-bias peak in the parameter space helps to eliminate possible false positives.

[0075] c. It reduces unnecessary selection bias.

[0076] 3. The method should be completed within a reasonable timeframe (at most a few days) and require minimal human decision-making during implementation.

[0077] 4. Nonlocal conductivity measurements are currently much slower than local measurements, so they should be limited to promising candidate regions so that the method can be completed in a reasonable amount of time.

[0078] 5. For a given method execution, the measurement sequence should be predetermined and of finite length to prevent open search, especially in cases with a large parameter space, which could take a very long time and introduce selection bias. It is still permissible to improve the measurement sequence over time, for example, by applying lessons learned from previous runs.

[0079] 6. For a given method execution, the data analysis procedure should be determined before data collection and inspection, and should have predetermined outputs to avoid overfitting and confirmation bias, and to ensure the method yields results. Similarly, it is still permissible to allow the data analysis code to improve over time, for example, by using improved algorithms and applying lessons learned from previous runs.

[0080] In view of the above considerations, Figure 6 An aspect of example method 56 is illustrated for evaluating a semiconductor-superconductor heterojunction for a qubit register in a topological quantum computer. Method 56 includes a mapping phase 58 and a refinement phase 60. In some examples, the mapping and refinement phases can be formulated separately—for example, to evaluate new experimental setups or variations in implementation.

[0081] Mapping phases 5 and 8 and refinement phase 60 each include measurement and analysis. The mapping phase includes rapid RF measurements 62 of the normal superconductor (NS) junction admittance to provide mapping data. The measured quantities include the local conductance at each end of the semiconductor line within a wide parameter space of bias, field, plunger, and left / right cutoff gate voltages. In some examples, the “mapped data” from measurement 62 includes two 5D datasets: the RF signal and the field, left cutoff, right cutoff, plunger, and left or right bias. Correlation data analysis 64 then searches the parameter space for extended regions where a relevant ZBP exists. In some examples, the output of analysis 64 includes a list of “promising” regions in the 4D parameter space (field, left cutoff, right cutoff, plunger), ordered according to the probability of the existence of a complete topological phase with finite topological gaps.

[0082] Each promising region identified in this way is then iteratively studied further in refinement stage 60. The refinement stage includes a slower sub-RF measurement 66 using a lock-in amplifier and including the full conductance matrix for each promising region, both local and non-local conductance. In some examples, the “refinement data” from measurement 66 includes the full conductance matrix for each promising region as a function of bias. Related data analysis 68 on the full conductance matrix, particularly non-local conductance, is performed to generate information about the host gap behavior used to identify regions as topologies according to the aforementioned criteria. It also allows for a quantitative assessment of the gap size within each topological region. In some examples, analysis 68 includes a joint analysis based on local and non-local conductance to determine the boundaries (or absence) of topological phases within each measurement region. Furthermore, the value of the topological gap (if any) is determined for each region. In refinement stage 60, measurements of promising regions can be repeated with adjusted range and resolution—e.g., not indefinitely, but only where appropriate. Therefore, refinement stage 60 can include a feedback loop that tightly adjusts the bias range and / or resolution in the parameter space. For example, the feedback loop can include up to two iterations.

[0083] Upon completion of refinement stage 60, regions exhibiting optimal characteristics of the topological phase are identified. For example, this region can be defined by a combination of large gaps and high confidence in the topological features. To further increase confidence, an additional verification stage 70 can optionally be performed to conduct additional tests on the stability of the optimal region. In some examples, verification stage 70 includes verifying the ZBP in the region identified in refinement stage 60 by examining the stability of the ZBP to changes in the cutoff gate voltage. Such changes can be of any desired magnitude (including large changes). Furthermore, in examples where the semiconductor-superconductor heterojunction is one of a series of similarly fabricated semiconductor-superconductor heterojunctions, the verification stage can include meta-analysis of ZBP data across the series. Meta-analysis can be performed to calculate the probability of finding topological regions in other similarly fabricated semiconductor-superconductor heterojunctions.

[0084] As mentioned above, Figure 5 As shown, the measurements in method 56 are performed on a three-terminal device. We will now continue to discuss some limitations on the device under test with reference to this figure. Figure 5 The device 48 includes a semiconductor line 72, typically a nanowire. In some embodiments, the semiconductor line may include selectively grown region (SAG) nanowires. In device 48, the semiconductor nanowire 72 is approached by a superconductor 74. The superconductor extends laterally away from the hybrid line. Figure 5 The diagram shows a representative location of the MZM 75 in a scenario where device 48 operates within the topological mechanism. The "T" shape of the superconductor is not mandatory; the width of the vertical superconducting portion can extend to the entire length L of the device. Normal contacts 54R and 54L contact the semiconductor lines at each end of the device. Contact 52 is coupled to the superconductor 74, forming a device with three terminals suitable for electrical transport measurements. The entire device is covered by a dielectric layer (not shown). Electrostatic shut-off gates 76R and 76L are used to form a tunneling barrier at each end of the semiconductor line 72. Electrostatic plunger gate 78 modulates the chemical potential within the device.

[0085] In the illustrated example, the important dimensions include:

[0086] L: Maximum length of the topological region

[0087] Ls: The length of the superconducting segment connecting the topological region to the lead-grounded superconductor 74.

[0088] W: Width W of semiconductor line 72 (or more generally, cross-section),

[0089] Lc: The distance between the cutoff gate 76 and the superconductor 74.

[0090] Wc: Width of 76 for each cutoff gate.

[0091] LN: The spacing between each cutoff gate 76 and the associated normal lead 54.

[0092] The distance between the plunger gate 78 and the semiconductor line 72 can be important for the potential distribution within the lever arm and the semiconductor line, depending on the dielectric material used. Another variable is the geometry of the plunger gate 78 relative to the semiconductor line (wrapping the gate to the opposite side of the gate). If the plunger gate is wrapped around the semiconductor (wrapping the gate), the lever arm will be larger, resulting in a greater change in the chemical potential energy within the semiconductor line. Conversely, if the coupling between the plunger gate and the semiconductor line is too strong, small voltage noise on the plunger gate will have a greater impact, potentially artificially widening the chemical potential within the semiconductor line 72.

[0093] One of the most important parameters is the length L of the semiconductor line. Here, two effects compete. On the one hand, the semiconductor line needs to be long enough to avoid finite-size effects and to clearly characterize the topological phase transition and associated ZBP. On the other hand, longer lines increase the practical difficulty of growing or manufacturing the working device and may reduce nonlocal signals. In particular, as the length of the semiconductor line increases, it becomes more difficult to ensure sufficient uniformity within the semiconductor line and the absence of strong defects (such as poor contact with superconductors that suppress proximity effects). Currently, there is very little data available for devices longer than 2 μm. Theoretically, 5ξ represents the minimum length scale at which finite-size effects are sufficiently suppressed (where ξ is the topological coherence length). Even in clean lines, nonlocal signals are suppressed with increasing semiconductor line length. The aforementioned issues lead to a device quality-dependent upper limit for L in order to successfully extract nonlocal information.

[0094] The length Ls is chosen to suppress quasiparticle leakage to the center lead. The working estimate is Ls > l0ξs, where ξs is the coherence length of the superconductor 74 (Ls = 200 nm for disordered Al). In typical experiments, Ls can reach the millimeter scale, thus exceeding the minimum by several orders of magnitude.

[0095] Experimental evidence suggests that the distance Lc to the cutoff gate 76 must be well below 100 nm to avoid spurious end states and achieve high-resolution tunneling spectroscopy. The optimal choice of Lc and the design of the cutoff gate can be determined by combining simulations from electrostatics, practical transportation, and manufacturing capabilities. As a placeholder, a requirement of Lc < 40 nm can be used. It should be noted that the cutoff design can vary depending on the cutoff width Wc and the distance between the cutoff and the normal leads. For InSb lines, it may be necessary to reduce the spacing between the cutoff and the normal leads, as these lines are typically closed, and the cutoff must also open this portion of the line.

[0096] Please note that the linewidth W parameter is not necessarily important for the feasibility of the disclosed method, but it will affect the likelihood of obtaining positive results from the method. For example, the width controls the number of channels, and numerical simulations show that fewer channels are advantageous for achieving the topological phase.

[0097] Table 1 summarizes current estimates of various requirements for device geometry based on the materials currently used, and provides material-specific requirements for estimated device dimensions. For these values, the following estimates of the coherence length at the maximum gap point were used: ξ(InSb / Al) = 400 nm, ξ(InAs / Al) = 300 nm, and ξs = 200 nm.

[0098] quantity InSb / Al InAs / Al L >2.0μm >1.5μm Ls >2μm >2μm <![CDATA[L C ]]> <40nm <40nm

[0099] To obtain a system with a sufficiently large topological gap, appropriate materials must be selected. However, method 56 is independent of semiconductor wire materials. Although material stacking is still under investigation (theoretically and experimentally), current results indicate that InAs with a potential barrier and InSb without a potential barrier are promising choices for obtaining topological gaps within suitable energy ranges. In some examples, topological gaps in the range of 25 to 200 μeV may be suitable for supporting the operation of topological quantum computers. Narrower and wider ranges are also envisioned.

[0100] Because aluminum creates a hard-induced gap in the heterostructure, and there is no subgap state under zero field, aluminum is the superconductor currently chosen. Similarly, the method is largely independent of the choice of superconductor, as long as the measurement parameters are adjusted accordingly, for example, by increasing the bias scan range of the larger gap superconductor or by adjusting the size of the device based on the values ​​shown in Table 1.

[0101] The choice of dielectric depends largely on the SAG material stack used. The hybrid system sets limits on the temperature range to which a given material stack can be exposed. The maximum gate voltage (breakdown voltage V) that can be applied to the electrostatic gate before dielectric breakdown is also considered. break The breakdown voltage (V) is an important material quantity, and for a given dielectric layer and SAG material system, it is best to be known as it sets the fundamental constraints on device operation. The breakdown voltage can be measured either on the test device or determined by standard electrical characteristics (SEC) measurements. If experimentally feasible, one suggestion is to fabricate an identical device to the device under test near the same chip to measure the actual V. break .

[0102] Now back Figure 6Before detailed measurements are performed on the device, it may be qualified to determine whether it conforms to a set of standards. Therefore, method 56 includes an initial qualification phase 80. As described below, the initial qualification phase may include a preliminary assessment of conductivity, tunneling spectrum, and time stability.

[0103] Regarding device conductance, if the resistance between all three terminals of the device is <25kΩ, the device is considered conductive under a high bias voltage V. bias,high Measurements are taken under >2Δ, where Δ is the superconducting gap. For InSb-based devices, this may require first opening the channel by applying a positive voltage to the cutoff gate. Regarding gate pinch-off, all gate resistances to ground should be >500MΩ. All gates used to form the tunneling barrier (cutoff) must be individually pinched off. To test gate pinch-off, the conductance between the superconducting terminal and the corresponding normal terminal is measured as a function of the cutoff gate voltage under high bias. When the conductance reaches <0.005e 2 At / h, the device is considered pinch-off. To some extent, the plunger gate used to adjust the chemical potential in the topology should be adjustable via the device's conductivity. The effect of the plunger gate can be most easily tested using tunneling spectroscopy, as described further below, within the tunneling mechanism. Because all measurements can be performed in the same scanning direction, hysteresis of the cutoff gate and the plunger gate is acceptable. However, as detailed below, it is required that the state does not undergo a measurable shift in gate space after the hysteresis loop on either gate.

[0104] Regarding tunneling spectroscopy, once the cutoff gate is tuned to a high bias, the conductance is approximately 0.1e. 2 In the / h state, conductance is measured as a function of bias and gate voltage (plunger gate or tunneling gate) at zero magnetic field. The peak of the differential conductance versus bias should be clearly discernible at the bias around the expected induced superconducting gap and should not change position with small changes in gate voltage (assuming that the high bias conductance does not change significantly). At zero field and energies below the superconducting gap, the number of finite conductance features should be very low to reduce the possibility of false affirmations. Ideally, the zero-field conductance trace should have no discrete sub-gap state features. This can be quantified by requiring the average sub-gap conductance to be less than 1 / 4 of the high bias conductance.

[0105] Regarding time stability, in the tunneling effect, the high-bias conductance should be stable. This means that the conductance should not jump or drift more than Δg ~ 0.2e on a timescale of t = 10 minutes. 2 / h. Regarding RF response, the resonance used for rapid RF measurements should be identified for the specific device, for example, by comparing resonances in open and pinch-off states. For all terminals requiring rapid measurements, a resonance should be visible as a clear response to the corresponding tunneling gate function. Effective impedance matching is necessary to obtain optimal sensitivity to conductance variations. Based on The typical device has a resistance of approximately 200 nH and a resonator inductance of approximately 200 nH. The parasitic capacitance of the device should be less than 1 pF to achieve high sensitivity.

[0106] Briefly return Figure 6 Measurement 62 in mapping phase 58 may include benchmarking of electrical noise and energy broadening. This step is valuable because the energy broadening caused by the measurement setup will provide a lower limit for detectable topological gaps. To ensure that the broadening caused by electronic noise is negligible, the integrated voltage noise RMS amplitude between 1 Hz and 500 Hz should be less than 3 μV.

[0107] Figure 7 A sample measurement setup for an RF reflectometer is shown. In RF reflection measurements, a sample is connected to a transmission line via a resonator. The sampling resistor alters the impedance matching between the resonator and the transmission line, thus changing the reflection coefficient of the RF signal sent into the line. Each of the two normally conducting leads of the setup is connected to a resonator used for RF reflection measurements, which has resonant frequencies f0 on its left and right sides, respectively. l,res and f r,res The frequency difference between the resonators on the left and right sides should be greater than the linewidth of each resonator. An intermediate frequency (IF) source generates RF pulses within the frequency bandwidth of the readout system. These pulses are up-converted to the frequency range of the resonators connected to the device. For this purpose, a mixer with high (>30dB) carrier rejection mixes the IF signal with the local oscillator (LO) signal. The LO frequency must be eliminated from the acquisition system's f... ADC bandwidth and resonator frequency f l,res and f r,res The frequency difference between the two.

[0108] If the RF source does not have separate I and Q outputs, one of the upconversion sidebands must be filtered out. This can be done by selecting f LO >max f l,res ,f r,res To complete this, a cutoff frequency of f is installed between the up-converter mixer and the refrigerator's input port. LO The signal is reflected from the sample and passes through a low-noise amplifier. Then, it is down-converted using the original LO signal by a mixer, low-pass filtered to the bandwidth of the acquisition system, and then sent to the input of the acquisition system.

[0109] To measure local conductance using an RF reflectometer, the reflected RF signal value must be calibrated against the directly measured differential conductance, for example, using a lock-in amplifier at low frequencies. Since this is a sample-dependent process that can be performed in parallel with the actual measurement, it is described below along with the measurement operation.

[0110] To benefit from the fast acquisition rate, the gate and bias voltage scans on the device are hardware-triggered to minimize the time spent on software communication (typically around 10 ms). This can be done in a hardware-triggered two-dimensional scan synchronized with the acquisition system. One voltage ramps up with a sawtooth function and is sampled N times during each ramp, while the second voltage is sampled at a slower rate over M cycles of a faster ramp, resulting in an N×M point scan. To be compatible with the DC values ​​of the voltages applied to the contacts and gate, these voltage scans are applied to a low-pass filtered DC line. The fastest ramp rate must be below the cutoff frequency of the low-pass filter in the refrigerator line, typically 1 kHz.

[0111] Detailed mapping phase 58

[0112] Figure 8 Other aspects of measuring the radio frequency (RF) junction admittance of a semiconductor-superconductor heterojunction to obtain mapping data are shown. Figure 8 Method 62A illustrates a rapid measurement of local conductance via an RF reflectometer because it allows for rapid characterization of the device and identification of candidate topological regions based on ZBP correlations. This rapid measurement is therefore designed to meet the first of the two topological gap criteria specified above. The identification of these regions lays the foundation for the non-local measurements in refinement stage 60. The rapid local measurements of the three-terminal device are closely related to the rapid measurements of conventional NS junctions.

[0113] In method 62A at step 82, the magnetic field is set to 0T. At step 84, for each side of the three-terminal device, the reflected RF signal is measured at a large bias voltage (e.g., 1mV) as a frequency varying according to the estimated resonant frequency (100MHz per side) and the corresponding cutoff voltage from the open-channel setpoint (i.e., InAs typically 0V, InSb typically 1V) to 100mV exceeding the full pinch-off voltage. The resonant frequency f res The frequency at which the signal change is most significant as a function of the cutoff gate voltage, and the decreasing cutoff voltage V as a function of frequency in the reflected signal. tunn.res It has the smallest absolute value.

[0114] At 86, the frequency is fixed at f. res The cutoff voltage range V meets the following three conditions. c,min To V c,max Confirmed:

[0115] a. This range is hysteresis-free, as measured by reproducibility after the hysteresis loop.

[0116] b. The measured local conductivity is much higher than that of the superconducting gap (e.g., for Al, at 1 mV) at 0.05 e 2 / h and 0.2e 2 Between / h.

[0117] c. The nonlocal conductance signal measured by standard low-frequency lock-in amplifier technology is higher than the noise level.

[0118] For significant electrostatic crosstalk between the plunger and the cut-off (geometry and material specific), this step can be repeated for different values ​​of the plunger-gate voltage.

[0119] In 88, the RF readout power was optimized. In some examples, this process involved finding a region in the cutoff space that exhibited a distinct gap with a well-defined coherent peak. To do this, the RF readout power (from -80 dBm to -130 dBm in 1 dB steps) was scanned on each side of the sample (bottom of the refrigerator). For each RF power, a rapid scan of the bias voltage was performed on the corresponding side from -1.5Δ0 to 1.5Δ0 (Δ0 is the gap of the parent superconductor, resulting in a bias range of -350 μV to 350 μV for Al), with a maximum step size of 5 μV, and the reflected RF signal was measured. For each side, the maximum RF power that did not amplify the measurement characteristics, such as the coherence peak, was found and set as the operating RF power.

[0120] At 90°, the magnetic field angle was calibrated parallel to the semiconductor line. To achieve this, the magnetic field was set to a value where the superconducting gap is not closed for a field parallel to the semiconductor line, but the size of the magnetic field is significantly reduced for a field perpendicular to the semiconductor line; for example, 500 mT for InAs and InSb SAG. The magnetic field angle was scanned around the desired value for the line geometry, with the bias on one side of the device scanning from -1.5Δ0° to +1.5Δ0° (-350 μV to +350 μV for Al) for each angle value, with a maximum step size of 5 μV. The reflected RF signal was then measured. The field of view was set to the angle that produces the maximum gap size. The goal here is an alignment accuracy better than 2° in both the azimuth and polar angles.

[0121] In 92, the maximum magnetic field B for closing the gap in the superconductor bulk was determined. max In 94, from 0T to B in steps of 100mT. max Scan the magnetic field to perform RF-DC calibration. For each field value, perform the following additional calibration.

[0122] At step 96, the optimal RF readout frequency is measured. This can be done by repeating step 84. However, once the readout frequency has been identified, a faster method can be used. In one example, the cutoff gate voltage is set to V. c,res The drop in the reflected RF signal as a function of frequency has its minimum absolute value at zero field. The RF reflected signal is measured as a function of the RF frequency from 50 MHz to the resonant frequency at which the latest field value is found. The RF signal amplitude drop closest to the previously found drop is found and set as the RF readout frequency. The results of this measurement can be saved to a database.

[0123] At 98, RF-DC calibration curves were measured. On each side, the bias voltage was set to a high bias (e.g., 1 mV for Al) above the superconducting gap. Individual cutoff gate voltages were scanned from the open-channel setpoint (i.e., typically 0 V for InAs and 1 V for InSb) to 100 mV beyond the pinch-off voltage. For each cutoff voltage, the local conductance and reflected RF signal were measured using a lock-in amplifier on the corresponding side. These measurements were saved to a database for later use in establishing a calibration function between the reflected RF signal and the conductance.

[0124] At 100, the magnetic field is set back to 0T. At 102, the magnetic field increases from 0T to B in steps of ΔB. max The field step ΔB depends on the g factor and allows tracking of the state as the field moves. A reasonable range for InAs or InSb SAG is 10mT < ΔB < 50mT. For each value of the field, perform the following additional steps.

[0125] At 104, the cutoff gate potential changes from N. c =V in 15 independent steps on each side c,min Scan to V c,max To generate a total of 2N c Each configuration. This independent scanning is reasonable for local conductance measurements when the range of the lever arm and the cutoff gate scan used for cutoff plunger crosstalk is small enough that it does not change the effective plunger voltage beyond the plunger voltage step size. For each cutoff gate configuration, the following measurements are performed. Voltage limit V c,min and V c,max It was determined in 86.

[0126] At 106, a rapid scan is performed on the plunger voltage and bias voltage for each side. The plunger voltage starts from V... p,max Scanned to V p,min The plunger boundary varies depending on the material and is subject to upper and lower limits of the breakdown voltage (at a breakdown voltage V). breakThe 80% stop) and the possible range of the region of interest are limited. The latter ranges from a completely gapless state to a completely depleted state and requires theoretical input. The resolution of the plunger scan needs to be sufficient to resolve individual sub-gap states across the gap (depending on the lever arm). For each value of the plunger gate, the bias voltage of this terminal is scanned from -1.5Δ0 to +1.5Δ0 (A1 is -350μV to +350μV), with a resolution no greater than 5μV. The reflected RF signal is measured as a function of the plunger and bias voltages. The generated two-dimensional scan is saved to a database.

[0127] The mapping data generated as the output of method 62A includes the following:

[0128] 1. A calibration dataset consisting of two 2D cutoff field scans, one on the left and one on the right. For each point in the scan, three parameters are measured: the in-phase RF component, the out-of-phase RF component, and the conductance on the corresponding side.

[0129] 2. A measurement dataset consisting of two 5D field-left-truncate-right-truncate-plunger-bias scans, wherein the bias scans are performed on the left and right sides. For each point of this scan, two parameters are measured: the in-phase RF component and the out-of-phase RF component.

[0130] The goal of this stage of data analysis is to identify promising regions in the parameter space that may contain complete topological phases. Figure 9 This illustrates other aspects of finding one or more regions of the parameter space that correspond to the complete topology of a semiconductor-superconductor heterojunction by analyzing mapping data.

[0131] In method 64A, at step 108, the RF signal input is converted to conductance using a calibration dataset to define the transfer function. At step 110, each point in the (field, plunger, cutoff) parameter space is classified as (possibly) topological or ordinary, and the local conductance G of the bias trajectory measured from that point is used, along with the respective left and right terminals. ll G rr As input. In one example, classification can check for the presence of ZBP in two conductance trajectories.

[0132] The analysis of the mapped data includes density-based clustering of the ZBP data from both sides. 112 point clusters classified as topological are identified, and clusters whose volume or shape in the parameter space is considered incompatible with the topological phase are filtered out. In some examples, the cluster volume in the plunger voltage-magnetic field space must be greater than 0.03 V × T. The clusters that survive the filtering are promising regions where the topological phase exists. In some examples, this step can be implemented using density-based clustering for each 2D plunger field scan, and regions extending to zero magnetic field can be excluded. In 114, promising regions are ranked according to their probability of containing the topological phase. In some examples, the ranking score is determined by the average plunger gate voltage of each cluster, with priority associated with more negative gate voltages.

[0133] Figure 10 Aspects of the mapping data analysis according to Method 64A are illustrated. The analysis was illustrated and validated using a simulated dataset of InSb / Al nanowires with a length of L = 3 μm and a mean free path of 3 μm. From left to right, as a function of plunger gate (V) and magnetic field (T), the figure shows: the topological index Q calculated from the scattering matrix; a binary array where 1 corresponds to the ZBP on both sides of the device; and clustered ZBP Boolean data, with cluster colors corresponding to the fractions of the corresponding clusters (lower is better). With this data, regions containing the true topological regions can be identified for further analysis.

[0134] The results of the data analysis performed in the mapping phase 58 of method 56 determine the measurements to be performed in the subsequent refinement phase 60. For each promising region in the above sorting, the field extent, plunger, and cutoff values ​​surrounding that region are specified as inputs to the refinement phase. In some examples, the refinement phase can be performed on each identified region in the sorting order. It is necessary to minimize the latency between the end of the mapping phase measurement and the start of the refinement phase measurement to minimize the impact of gate drift, gate jump, and other issues. For this reason, it is important to perform the above data analysis in an efficient manner. Note that the raw data generated in the RF measurement phase can be very large: the total size of such existing RF datasets exceeds 100GB, and scaling and analysis can take several hours. Therefore, it is important to have a data pipeline so that the data can be quickly used for analysis on the computation cluster to avoid bottlenecks in method execution. Note that pipeline implementation may require different solutions for measurements performed at different locations. Data acquisition, transmission, and analysis should also be parallelized as much as possible. For example, because the data analysis requires a separate bias trajectory as input, the first step of the above data analysis can occur in parallel with data acquisition.

[0135] Detailed refinement stage 60

[0136] like Figure 11As shown, the differential conductance of the device being evaluated can be measured using standard low-frequency lock-in amplifier techniques. The total conductance matrix is ​​obtained by applying DC bias voltages V to the left and right terminals 54 respectively. bias,l / r and AC voltage δV l / r And two different AC excitation frequencies f i and f r These frequencies must be measured. They must be lower than the low-pass filter cutoff in the system, and low enough to minimize parasitic capacitance effects. To ensure this, the phase shift of the current relative to the voltage excitation must be less than 10°. The in-phase AC current δI flowing to the left or right... l / r The measurements were taken with the middle superconducting lead grounded. The ground connection must be low in ohms (i.e., typically less than a few kΩ) compared to the resistance of the other two lines to suppress parasitic voltage divider effects. For this purpose, a low-pass filter can be designed accordingly, or the superconducting lead can be grounded at the PCB level (cold ground).

[0137] This three-terminal setup allows for the measurement of all four elements of the conductance matrix G between the left (l) and right (r) terminals:

[0138]

[0139] Conductivity matrix element G ll =dI l / dV l and G rr =dI r / dV r Known as "local conductivity", element G lr =dI l / dV r and Gr l =dI l / dV r It is known as "nonlocal conductivity".

[0140] The input 66 used for refinement measurements includes regions in the space (shutdown gate, plunger gate, field) that are candidates for further investigation. In some examples, the size of the region in the plunger gate / field space can be increased by 20% to ensure that the refinement measurements fully capture the topological phase transition around each region.

[0141] Figure 12 Additional aspects of the sub-RF conductance of a semiconductor-superconductor heterojunction in each of one or more mapped regions of a parameter space are illustrated to obtain refined data. In particular, method 66A describes local and non-local conductance measurements suitable for extracting the bandgap of a semiconductor-superconductor heterojunction.

[0142] At 116 in method 66A, the magnetic field is set to the minimum field value in the candidate region. This field should be low enough that the induced gap remains open so that it can be observed whether it closes in the candidate region. At 118, for example in the candidate region, the cutoff gate is set to its minimum value. At 120, for V... L and V R Correct for small bias voltage offset (see Figure 11 This ensures that the extraction of antisymmetric components of both local and nonlocal signals is direct. This can be achieved by using V... L -V R Find the sum of absolute currents (|I) in the parameter space L |+|I R The minimum value of |) is used to achieve this. In 122, the magnetic field ramps up in the candidate region with a step size of ΔB. For each value of the field, a bias plunger scan is performed as described below.

[0143] At 124, the plunger voltage is set to the maximum plunger voltage (V) in the area to be explored. P,max The plunger voltage is in steps of ΔV. P From V max Scan to the minimum plunger voltage V in the area to be explored P,min In other examples, the plunger voltage can be scanned in the opposite direction. For each plunger voltage value, the bias voltage on the left terminal is scanned from -50μV to +50μV in steps of 5μV. If the data indicates that the topology gap is outside this window, the scan is repeated with a larger window size. The resulting two-dimensional scan is saved to a database.

[0144] The refined data generated by the slower full conductance matrix measurement is a dataset for each candidate region. Each dataset consists of two 3D field plunger bias scans, with the bias scanned on the left and right sides, respectively. For each point in the scan, two parameters are measured: the conductance on the left and right sides. In some examples, each conductance may include the full conductance matrix for the corresponding side of the device.

[0145] Figure 13 This illustrates finding other aspects of the boundaries of the complete topological phase in the parameter space and the topological gaps of the semiconductor-superconductor heterojunction for at least one region in one or more regions queried in method 66A by analyzing refined data. In some examples, the method shown is performed iteratively for each promising region.

[0146] In method 68A at step 126, step 110 of method 64A is repeated to verify that the measurement region is still promising and that the boundaries of the candidate topological regions may be adjusted. At this point, the analysis of the refined data includes verifying gap closure at the boundaries of each of one or more regions in the parameter space. At step 128, a check is performed based on the nonlocal conductance signal to determine which portion of the boundary of the promising region is gapless. At step 130, the gap size Δ at each point i within region j is... (j) Nonlocal conductance is extracted by thresholding. In 132, a score is assigned to a region based on the extent of the gapless boundary and the value of the gap within the candidate topological region. The score reflects the probability that the promising region is indeed topological and has gaps. In some examples, the score S is determined by S... i =X·Median i (△ (j) The definition is as follows. In 134, the maximum gap within each topological region is obtained, along with an estimate of the error. In some examples, the error bar is determined by the uncertainty of the nonlocal conductance threshold at the point of maximum gap.

[0147] The output of this analysis includes a set of probabilities corresponding to the regions identified in the mapping phase 58 of method 56, i.e., the probability of hosting a complete topological phase. Associated with each probability is the maximum (topological) gap within each (non-ordinary) region. Figure 14 This illustrates the use of method 68A with Figure 10 The same simulation is used to analyze aspects of the refined data. From left to right: gaps extracted from the nonlocal data; the fraction of ZBP clusters defined as the average gap within the region multiplied by the percentage of gapless boundaries; and the fraction of ZBP clusters identical to the middle plot but with the average gap replaced by the median gap within the region. The maximum gap within this region is 175 μeV. Therefore, the output of the entire method 56 is an estimate of the value of the topological gap in each promising region and its location in the explored parameter space.

[0148] Detailed examples of false affirmation and false negation

[0149] One potential problem with quasi-Majorana states is that they can appear as precursors to true topological mechanisms. This means that topological regions can be directly adjacent (in parameter space) to non-topological quasi-Majorana states. In this case, current algorithms that cluster relevant ZBP regions can identify regions that are too large during the mapping phase. In other words, the regions identified, including some quasi-Majorana states, can extend further while still containing topological regions. In this situation, either too much parameter space is identified as topological, or topological regions cannot be identified due to the lack of gap closure / reopening in quasi-Majorana mechanisms, thus rendering the current analysis in the refinement phase a failure.

[0150] The solution to this problem is to implement an alternative clustering algorithm during the refinement stage. This algorithm identifies lines of gap closure / reopening characteristics in the parameter space (especially the field-plunger space) and then determines the intersections of these lines with the relevant ZBP regions to find the topological phase. Note that this is primarily a data analysis problem during the refinement stage. The mapping stage remains suitable for identifying promising data regions that are examined more closely during the refinement stage.

[0151] The instability in the data analysis may be due to data truncation with a fixed cutoff voltage. Stability can be improved by using one or two cutoff gate potentials as an additional dimension in the refined data analysis. This should improve clustering and better utilize the available dataset.

[0152] The following examples address smooth potentials at the ends of semiconductor wires, which are associated with quasi-Majorana and false negation. The presence of long-term inhomogeneities (smooth potential changes) makes it more difficult to observe the closing / reopening of the gap, leading to false negation. Interestingly, smooth potential changes are also the mechanism by which quasi-Majorana patterns are expected. The interaction between the two effects is discussed here.

[0153] A typical scenario for the emergence of quasi-Majorana modes is when the system is tuned close to but outside the topological phase. Specifically, consider an example where, under a fixed magnetic field, the chemical potential μ is less than the critical chemical potential μc required to enter the topological phase. A smooth potential change can be interpreted as a spatially varying chemical potential μ(x) = μ0V(x), where V(x) is the potential. In the above case, as... Figure 15 As shown, a potential drop near the (right) end of the semiconductor line is possible to locally tune the system to the topological state μ(x) > μc, which results in a local Majorana mode pair. The latter indicates that the local conductance at the right end in a much lower field is a topological phase transition in the semiconductor line body (which can now be read by the local conductance at the other (left) end, where there is no smooth potential change).

[0154] Figure 15 The effect of the smoothed potential at the right end of the semiconductor line is shown in the 1D model. Left: Spatial dependence of the potential (bottom) and position of the superconducting shell achieved through the self-energy (orange, top) of the semiconductor line. Right: Conductivity matrix including the antisymmetric portion of the nonlocal conductance. Note that there is no gap reopening function in the nonlocal conductance. The only characteristic of the phase transition is the onset of weak Majorana oscillations.

[0155] Specifically, in Figure 15In the example, the phase transition at a fixed chemical potential is Bc≈2.7T. In Method 56, because there are no gap closure and reopening features in the nonlocal conductance, the ZBP appearing near B≈1T due to the quasi-Majorana mode will be correctly labeled as nontopological. However, even in the topological phase transition, there are no visible gap closure / reopening features. The reason is that the part of the system under the right-hand smooth potential has already undergone a phase transition, thus a gap appears when B crosses Bc. Because they are only evanescently coupled to the right lead, this suppresses the signal of the main mode during the phase transition. Note that in this particular model, the topological gap is 100 μeV, which is larger than we would expect in a real system. For smaller gaps, the nonlocal signal becomes larger, thus increasing the intensity of the gap closure / reopening feature. Nevertheless, gap closure / reopening is still difficult to observe because the signal of the finite-size oscillation also becomes stronger.

[0156] In summary, although quasi-Majorana modes at the ends of semiconductor lines do not lead to false positives in nonlocal conductance, the presence of quasi-Majorana modes increases the chance of false negatives once the system is tuned to the topological phase.

[0157] The second example addresses the smooth potential at the center of the semiconductor line that is definitely associated with the error. Here, we discuss the only definitive example, which can have ZBP at both ends of the semiconductor line, and an important feature in the nonlocal conductance can be interpreted as gap closure (and possible reopening), while most systems are non-topological.

[0158] This setting Figure 16 The semiconductor line is depicted as follows: the body of the semiconductor line is tuned to be non-topological, while the smooth potential bump at the center of the semiconductor line achieves the topological state of the potential. Therefore, it is conceivable that Majorana zero-mode pairs nucleate at the center of the semiconductor line. Although the chosen central region is too small for well-separated Majorana modes, the smoothness of the potential may result in close but weakly coupled quasi-Majorana modes at the center of the semiconductor line.

[0159] like Figure 16 As shown, due to the finite size effect, the corresponding zero modes can be detected as correlated ZBP in the conductance at each end. Furthermore, since the low-energy modes at the center overlap with those on both sides, they also contribute to the nonlocal conductance, which could be misinterpreted as gap closure.

[0160] Figure 16The effect of smoothing potential at the center of the semiconductor line is shown in the 1D model. Left: Spatial dependence of the potential (bottom) and location of the superconducting shell achieved through the self-energy (orange, top) of the semiconductor line. Right: Conductivity matrix including the antisymmetric portion of nonlocal conductance. Note that the quasi-Majorana mode nucleated in the central region is visible as a related ZBP due to finite size effects and also contributes to nonlocal conductance.

[0161] Figure 17 Data analysis in the field / plunger parameter space for the gap method is shown for a 1D model with a potential bump at the center of the semiconductor line. Left: Detected ZBP. Right: Gap determined from the data. In this case, the ZBP finder detects two overlapping regions: one centered at plunger = 0 (body topology region) and the other centered at plunger = 0.0025 (center bump topology). Because there is a small topological region at the center, and the effect of finite size is significant, it is currently unclear whether this situation represents a false positive (outside the body topology region). In fact, the finite size effect results in gap closure characteristics for each region (center and body) in the estimated gap extracted from the data.

[0162] This problematic example illustrates the value of continuing to develop the data analysis used in the method presented in this paper. Note that the ZBP clustering algorithm has identified two regions (the center and the body) as a single region. This example illustrates that non-topological regions adjacent to topological regions can be relatively difficult to separate and may require further refinement in the data analysis.

[0163] The third example involves non-topological ZBP due to strong disorder. Here is an example of a one-dimensional model with strong disorder. For illustration, Figure 18 Data analysis in the field / plunger parameter space of a strongly disordered 1D model is shown. Left: Points with relevant ZBP (red); Right: Extracted gap at each point in the parameter space. Although ZBP exists, Figure 18 The data indicates that the regions associated with the ZBP are sparse and largely discontinuous. Therefore, by increasing the requirements for the size and continuity of the identified regions, strongly disordered regions can be excluded using the gap method.

[0164] Instruments and Additional Methods

[0165] Although the features and examples disclosed herein relate to methods for evaluating semiconductor-superconductor heterojunctions for qubit registers used in topological quantum computers, such features and examples are also applicable to related instruments. Figure 19An aspect of an example instrument 136 configured to evaluate a semiconductor-superconductor heterojunction for a qubit register in a topological quantum computer is shown. The instrument includes a controller 18B. The controller includes at least one processor 20B and a computer memory 22B operatively coupled to the processor. The computer memory is configured to store instructions 24B that cause the processor to perform various measurement and analysis methods described herein. For this purpose, the processor may be operatively coupled to an RF admittance measurement device 138 and a sub-RF conductance measurement device 140. The RF admittance measurement device may include, for example... Figure 7 The features shown; the sub-RF conductivity measurement device may include, for example Figure 11 Features are shown. In the example shown, instrument 136 includes an interface 142 that couples the processor to the measuring device and also provides control signals to the electrostatic gate and magnet 144 of device 48.

[0166] The features and examples disclosed in this article also relate to methods for building topological quantum computers. Figure 20 An aspect of example method 146 for constructing a topological quantum computer is shown.

[0167] In method 146, at 148, a semiconductor-superconductor heterojunction with at least three terminals configured to support electronic admittance testing is fabricated. At 62, the admittance of the semiconductor-superconductor heterojunction is measured at the RF junction to obtain mapping data. At 64, by analyzing the mapping data, one or more regions in the parameter space corresponding to the complete topology of the semiconductor-superconductor heterojunction are located. At 66, the sub-RF conductance of the semiconductor-superconductor heterojunction is measured in each of the one or more regions in the parameter space to obtain refined data. At 68, by analyzing the refined data, the boundaries of the complete topological phase in the parameter space and the topological gaps of the semiconductor-superconductor heterojunction are located for at least one of the one or more regions in the parameter space. At 150, provided that the found boundaries and topological gaps are within their respective predefined ranges, the semiconductor-superconductor heterojunction is incorporated into the qubit register of a topological quantum computer. In the operation of the topological quantum computer constructed in this manner, one or more values ​​characterizing the boundaries in the parameter space can be used as tuning parameters for addressing the semiconductor-superconductor heterojunction in the qubit register.

[0168] For other contexts, the following references are provided.

[0169] T.O. Rosdahl, A. Vuik, M. Kjaergaard, and A.R. Akhmerov. Andreev rectifier: A nonlocal conductance signature of topological phase transitions, Phys. Rev. B 97, 045421 (2018).

[0170] Jeroen Danon, Anna Birk Hellenes, Esben Bork Hansen, Lucas Casparis, Andrew P. Higginbotham, and Karsten Flensberg, Nonlocal conductance spectroscopy of Andreev bound states: Symmetry relations and BCS charges, arXiv:1905.05438 [cond-mat] (2019), arXiv:1905.05438 [cond-mat].

[0171] G.C. Menard, G.L.R. Anselmetti, E.A. Martinez, D. Puglia, F.K. Malinowski, J.S. Lee, S. Choi, M. Pendharkar, C.J. Palmstrom, K. Flensberg, C.M. Marcus, L. Casparis, and A.P. Higginbotham, Conductance-matrix symme-tries of a three-terminal hybrid device, arXiv:1905.05505 [cond-mat] (2019), arXiv:1905.05505 [cond-mat].

[0172] Davydas Razmadze, Deividas Sabonis, Filip K. Malinowski, Gerbold C. Menard, Sebastian Pauka, Hung Nguyen, David MTvan Zanten, Eoin CTO'Farrell, Ju-dith Suter, Peter Krogstrup, Ferdinand Kuemmeth, and Charles M. Marcus, Radio-Frequency Methods for Majorana-Based Quantum Devices: Fast Charge Sensing andPhase-Diagram Mapping,Phys.Rev.Applied 11,064011(2019).

[0173] MITEQ AFS4-00100800-14-10P-4.

[0174] in conclusion

[0175] In summary, one aspect of this disclosure relates to a method for evaluating a semiconductor-superconductor heterojunction for a qubit register in a topological quantum computer. The method includes: measuring the radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; analyzing the mapping data to locate one or more regions in a parameter space consistent with the complete topology of the semiconductor-superconductor heterojunction; measuring subRF conductance, including nonlocal conductance of the semiconductor-superconductor heterojunction, in each of the one or more regions of the parameter space to obtain refined data; and analyzing the refined data to locate the boundary of the complete topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction for at least one region of the one or more regions of the parameter space.

[0176] In some embodiments, the analysis of the mapped data includes density-based clustering of zero-bias peak data from opposite ends of the semiconductor-superconductor heterojunction. In some embodiments, the method further includes verifying the ZBP by examining the stability of the zero-bias peak (ZBP) in each of one or more regions against changes in the cutoff gate voltage. In some embodiments, the analysis of the refined data includes verifying gap closure at the boundaries of each of one or more regions in the parameter space. In some embodiments, the semiconductor-superconductor heterojunction is one of a series of similarly fabricated semiconductor-superconductor heterojunctions, and the method further includes performing meta-analysis of the zero-bias peak data across the entire series to calculate the probability of finding a topological region in another similarly fabricated semiconductor-superconductor heterojunction. In some embodiments, measuring subRF conductance includes performing local and nonlocal conductance measurements suitable for extracting the bandgap of the semiconductor-superconductor heterojunction. In some embodiments, the semiconductor-superconductor heterojunction includes a semiconductor line and at least three terminals at opposite ends of the semiconductor line supporting admittance and conductance measurements. In some embodiments, the semiconductor-superconductor heterojunction includes multiple electrostatic control terminals.

[0177] Another aspect of this disclosure relates to an instrument configured to evaluate a semiconductor-superconductor heterojunction for a qubit register used in a topological quantum computer. The instrument includes: a controller having a processor and a computer memory operatively coupled to the processor, the controller being configured to: measure the radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; locate one or more regions in a parameter space corresponding to the complete topology of the semiconductor-superconductor heterojunction by analyzing the mapping data; measure subRF conductance including the nonlocal conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space to obtain refined data; and locate the boundary of the complete topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space by analyzing the refined data.

[0178] In some embodiments, the controller is configured to analyze zero-bias peak data from opposite ends of the semiconductor-superconductor heterojunction using density-based clustering. In some embodiments, the controller is also configured to verify the ZBP by examining the stability of the zero-bias peak (ZBP) in each of one or more regions against changes in the cutoff gate voltage. In some embodiments, the controller is configured to analyze refined data by verifying gap closure at the boundaries of each of one or more regions in the parameter space. In some embodiments, the semiconductor-superconductor heterojunction is one of a series of similarly fabricated semiconductor-superconductor heterojunctions, wherein the controller is configured to perform meta-analysis of the zero-bias peak data across the entire series to calculate the probability of finding a topological region in another similarly fabricated semiconductor-superconductor heterojunction. In some embodiments, the instrument is operatively coupled to an RF admittance measurement device and a subRF conductance measurement device.

[0179] Another aspect of this disclosure relates to a method for constructing a topological quantum computer. The method includes: fabricating a semiconductor-superconductor heterojunction having at least three terminals configured to support electronic admittance testing; measuring the radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding one or more regions in a parameter space consistent with the complete topology of the semiconductor-superconductor heterojunction by analyzing the mapping data; measuring subRF conductance, including nonlocal conductance of the semiconductor-superconductor heterojunction, in each of the one or more regions of the parameter space to obtain refined data; finding, by analyzing the refined data, the boundary of the complete topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction in the parameter space for at least one of the one or more regions; and, if the found boundary and topological gap are within their respective predefined ranges, incorporating the semiconductor-superconductor heterojunction into a qubit register of the topological quantum computer.

[0180] In some embodiments, the analysis of the mapped data includes density-based clustering of zero-bias peak data from opposite ends of the semiconductor-superconductor heterojunction. In some embodiments, the method further includes verifying the ZBP by examining the stability of the zero-bias peak (ZBP) in each of one or more regions against changes in the cutoff gate voltage. In some embodiments, the analysis of the refined data includes verifying gap closure at the boundaries of each of one or more regions in the parameter space. In some embodiments, the semiconductor-superconductor heterojunction is one of a series of similarly fabricated semiconductor-superconductor heterojunctions, and the method further includes performing meta-analysis of the zero-bias peak data across the entire series to calculate the probability of finding a topological region in another similarly fabricated semiconductor-superconductor heterojunction. In some embodiments, one or more values ​​characterizing the boundaries in the parameter space are used as tuning parameters for addressing the semiconductor-superconductor heterojunction in a qubit register.

[0181] Another aspect of this disclosure relates to a two-stage method for extracting topological phases. Importantly, this involves stage separation, so that the mapping stage allows for a wide search of the parameter space while still producing erroneous affirmations, while the refinement stage allows for a slow scan of the region of interest from the mapping stage to clear erroneous affirmations. Another aspect of this disclosure relates to using a density-based clustering algorithm on both sides of ZBP data to extract predicted topological regions. Importantly, this includes the clustering algorithm used for this purpose. It is considered the first systematic method for finding promising regions. Another aspect of this disclosure relates to mapping between RF and DC conductance for rapid conductance extraction in RF measurements. Importantly, this includes using mapping to bypass DC conductance measurements and still extracting the same data, but at a much faster speed due to the faster RF technology. Another aspect of this disclosure relates to classifying bias trajectories using peak finding or machine learning. Importantly, this includes the statistical characterization of the machine learning of topological trajectories and the peak finding effect. Another aspect of this disclosure relates to extracting gaps from nonlocal conductance trajectories, particularly using bias trajectories along with experimental noise or filtering and smoothing of bias / field scans. Importantly, this includes automatic gap extraction. Another aspect of this disclosure relates to improving the accuracy of prior methods by examining gap closures at the boundaries of suspicious topological regions. Importantly, this involves applying gap extraction from the data to classify regions as topological / ordinary. Another aspect of this disclosure relates to meta-analysis of ZBP data to extract the probability of finding topological regions in many devices of the same fabrication. This can be used to characterize growth / fabrication methods via topological phase diagrams. Another aspect of this disclosure relates to using any of the above to tune the qubits of a topological quantum computer.

[0182] It should be understood that the configurations and / or methods described herein are exemplary in nature, and these particular embodiments or examples should not be considered limiting, as many variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various actions shown and / or described may be performed in the order shown and / or described, in another order, in parallel, or omitted. Similarly, the order of the above processing can be changed.

[0183] The subject matter of this disclosure includes all novel and non-obvious combinations and sub-combinations of various processes, systems and configurations, as well as other features, functions, actions and / or properties disclosed herein, and any and all their equivalents.

Claims

1. A method for evaluating a semiconductor-superconductor heterojunction, said semiconductor-superconductor heterojunction being used in a qubit register of a topological quantum computer, said method comprising: The radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction is measured to obtain mapping data; The analysis of the mapping data is used to find one or more regions in the parameter space that correspond to the complete topology of the semiconductor-superconductor heterojunction. Measure the subRF conductance, including the nonlocal conductance of the semiconductor-superconductor heterojunction, in each of the one or more regions of the parameter space to obtain refined data; as well as By analyzing the refined data, the boundaries of the complete topological phase in the parameter space and the topological gaps of the semiconductor-superconductor heterojunction are located for at least one region in one or more regions of the parameter space.

2. The method according to claim 1, wherein the analysis of the mapping data includes: Density-based clustering is performed on the zero-bias peak data from opposite ends of the semiconductor-superconductor heterojunction.

3. The method according to claim 1, further comprising: The ZBP is verified by examining the stability of the zero bias peak ZBP in each of the one or more regions against the change in the cutoff gate voltage.

4. The method according to claim 1, wherein the analysis of the refined data includes: Verify that the gaps at the boundaries of each of the one or more regions in the parameter space are closed.

5. The method of claim 1, wherein the semiconductor-superconductor heterojunction is one of a series of similarly fabricated semiconductor-superconductor heterojunctions, the method further comprising performing meta-analysis on zero-bias peak data across the series of similarly fabricated semiconductor-superconductor heterojunctions to calculate the probability of finding a topological region in another similarly fabricated semiconductor-superconductor heterojunction.

6. The method of claim 1, wherein measuring the subRF conductance comprises: Local and non-local conductivity measurements suitable for extracting the bandgap of the semiconductor-superconductor heterojunction are performed.

7. The method of claim 1, wherein the semiconductor-superconductor heterojunction comprises a semiconductor line and at least three terminals, the at least three terminals supporting admittance and conductance measurements at opposite ends of the semiconductor line.

8. The method of claim 1, wherein the semiconductor-superconductor heterojunction includes a plurality of electrostatic control terminals.

9. An instrument configured to evaluate a semiconductor-superconductor heterojunction used in a qubit register of a topological quantum computer, the instrument comprising: A controller having a processor and computer memory operatively coupled to the processor, the controller being configured to: The radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction is measured to obtain mapping data; The analysis of the mapping data is used to find one or more regions in the parameter space that correspond to the complete topology of the semiconductor-superconductor heterojunction. Measure the subRF conductance, including the nonlocal conductance of the semiconductor-superconductor heterojunction, in each of the one or more regions of the parameter space to obtain refined data; as well as By analyzing the refined data, the boundaries of the complete topological phase in the parameter space and the topological gaps of the semiconductor-superconductor heterojunction are located for at least one region in one or more regions of the parameter space.

10. The instrument of claim 9, wherein the controller is configured to analyze the mapping data using density-based clustering on zero-bias peak data from opposite ends of the semiconductor-superconductor heterojunction.

11. The instrument of claim 9, wherein the controller is further configured to verify the ZBP by examining the stability of the zero bias peak ZBP in each of the one or more regions against the change in the cutoff gate voltage.

12. The instrument of claim 9, wherein the controller is configured to analyze the refined data by verifying gap closure at the boundaries of each of the one or more regions in the parameter space.

13. The instrument of claim 9, wherein the semiconductor-superconductor heterojunction is one of a series of similarly fabricated semiconductor-superconductor heterojunctions, wherein the controller is configured to perform meta-analysis on zero-bias peak data across the series of similarly fabricated semiconductor-superconductor heterojunctions to calculate the probability of finding a topological region in another similarly fabricated semiconductor-superconductor heterojunction.

14. The instrument of claim 9, wherein the instrument is operatively coupled to an RF admittance measurement device and a subRF conductance measurement device.

15. A method for constructing a topological quantum computer, the method comprising: Fabricate a semiconductor-superconductor heterojunction with at least three terminals configured to support electronic admittance testing; The radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction is measured to obtain mapping data; The analysis of the mapping data is used to find one or more regions in the parameter space that correspond to the complete topology of the semiconductor-superconductor heterojunction. Measure the subRF conductance, including the nonlocal conductance of the semiconductor-superconductor heterojunction, in each of the one or more regions of the parameter space to obtain refined data; By analyzing the refined data, the boundary of the complete topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction are found in at least one region of the one or more regions of the parameter space. as well as When the found boundaries and topological gaps are within the corresponding predefined ranges, the semiconductor-superconductor heterojunction is combined and stored in the qubit register of the topological quantum computer.

16. The method of claim 15, wherein the analysis of the mapping data comprises: Density-based clustering is performed on the zero-bias peak data from opposite ends of the semiconductor-superconductor heterojunction.

17. The method of claim 15, further comprising: The ZBP is verified by examining the stability of the zero bias peak ZBP in each of the one or more regions against the change in the cutoff gate voltage.

18. The method of claim 15, wherein the analysis of the refined data comprises: Verify that the gaps at the boundaries of each of the one or more regions in the parameter space are closed.

19. The method of claim 15, wherein the semiconductor-superconductor heterojunction is one of a series of similarly fabricated semiconductor-superconductor heterojunctions, the method further comprising: Meta-analysis was performed on zero-bias peak data across the series of similarly fabricated semiconductor-superconductor heterojunctions to calculate the probability of finding a topological region in another similarly fabricated semiconductor-superconductor heterojunction.

20. The method of claim 15, wherein one or more values ​​characterizing the boundary in the parameter space are used as tuning parameters for addressing the semiconductor-superconductor heterojunction in the qubit register.

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