Display device and method for manufacturing the same

Abstract

A display device according to an embodiment of the present application can include a substrate including a display area and a non-display area; a pixel circuit layer disposed on a first surface of the substrate and including at least one transistor; a display element layer disposed on the pixel circuit layer and including a light emitting element; a thin film encapsulation layer disposed on the display element layer; and a dummy part disposed in the non-display area and disposed on an edge of the substrate. The dummy part can include a transparent conductive material.

Description

Technical Field

[0001] This disclosure relates to a display device and a method for manufacturing the display device. Background Technology

[0002] With increasing interest in information display and growing demand for portable information media, the need for and commercialization of display devices has become a focus. Display devices can utilize a substrate made of resins such as polyimide, thus enabling the creation of flexible or foldable display devices.

[0003] Recently, in order to provide a wider screen while maintaining the same size, the development of display devices that apply the principle of zero bezel (i.e., meaning almost no bezel) to the bezel is underway. Summary of the Invention

[0004] Technical issues

[0005] The purpose of this disclosure is to provide a display device with improved reliability by minimizing defects that occur during a dry etching process by setting dummy patterns in the outer region of a substrate, the dry etching process setting a mother substrate including pixel units (or display units) on a unit basis (cell) (or display panel).

[0006] Another objective of this disclosure is to provide a display device that minimizes unused space.

[0007] Another object of this disclosure is to provide a method for manufacturing the above-described display device.

[0008] Technical solution

[0009] According to embodiments of this disclosure, a display device may include: a substrate, including a display area and a non-display area; a pixel circuit layer disposed on a first surface of the substrate and including at least one transistor; a display element layer disposed on the pixel circuit layer and including a light-emitting element; a thin-film encapsulation layer disposed on the display element layer; and a dummy unit disposed in the non-display area and on the edge of the substrate. Here, the dummy unit may include a transparent conductive material.

[0010] In embodiments of this disclosure, the dummy unit may include: a first dummy pattern disposed on a first surface of the substrate; and a second dummy pattern disposed on the first dummy pattern. Here, the first dummy pattern may be an etch stop element.

[0011] In embodiments of this disclosure, the pixel circuit layer may further include a buffer layer disposed on a substrate and at least one insulating layer disposed on the buffer layer, wherein at least one transistor is disposed on the buffer layer. Here, the second dummy pattern may cover at least a portion of the buffer layer and at least a portion of the insulating layer.

[0012] In embodiments of this disclosure, at least a portion of the first dummy pattern and at least a portion of the second dummy pattern may be superimposed on each other in a plane and in a cross-section.

[0013] In embodiments of this disclosure, the first dummy pattern and the second dummy pattern may have the same or different planar shapes.

[0014] In embodiments of this disclosure, the second dummy pattern may be positioned closer to the display area from the edge of the substrate than the first dummy pattern.

[0015] In embodiments of this disclosure, the width of the first dummy pattern and the width of the second dummy pattern may be the same or different from each other on the plane.

[0016] In embodiments of this disclosure, the display device may further include at least one dam unit disposed in a non-display area of ​​the substrate. A first dummy pattern and a second dummy pattern may be located between the edge of the substrate and the dam unit.

[0017] In embodiments of this disclosure, the display device may further include a light-blocking layer disposed between the first dummy pattern and the second dummy pattern in a non-display area. Here, the light-blocking layer may cover the dam unit.

[0018] In embodiments of this disclosure, the display device may further include an auxiliary layer disposed between the light-blocking layer and the second dummy pattern.

[0019] In embodiments of this disclosure, the second dummy pattern may cover at least a portion of the auxiliary layer. Here, the auxiliary layer may be a light-diffusing layer comprising scattering particles.

[0020] In embodiments of this disclosure, the thin-film encapsulation layer may include: a first encapsulation layer disposed on the display element layer; a second encapsulation layer disposed on the first encapsulation layer; and a third encapsulation layer disposed on the second encapsulation layer. Here, the second encapsulation layer may be an organic insulating layer, and the first and third encapsulation layers may be inorganic insulating layers.

[0021] In embodiments of this disclosure, the third encapsulation layer may cover at least a portion of the second dummy pattern.

[0022] In embodiments of this disclosure, the light-emitting element may include: a first electrode electrically connected to at least one transistor; an emitting layer disposed on the first electrode; and a second electrode disposed on the emitting layer. Here, the second dummy pattern may be disposed on the same layer as the second electrode and may include the same material as the second electrode.

[0023] In embodiments of this disclosure, the light-emitting element may include: a first semiconductor layer doped with a first conductive dopant; a second semiconductor layer doped with a second conductive dopant; and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

[0024] In embodiments of this disclosure, the display device may further include: a touch sensor disposed on a thin-film encapsulation layer. The touch sensor may include: a substrate layer disposed on a display element layer; a first conductive pattern disposed on the substrate layer; a first touch insulating layer disposed on the first conductive pattern; a second conductive pattern disposed on the first touch insulating layer; and a second touch insulating layer disposed on the second conductive pattern. Here, the substrate layer may be disposed on the second dummy pattern to cover at least a portion of the second dummy pattern.

[0025] In embodiments of this disclosure, the first dummy pattern and the second dummy pattern can protrude from the edge of the substrate in a direction away from the display element layer.

[0026] In embodiments of this disclosure, at least a portion of the first dummy pattern and at least a portion of the second dummy pattern may be in contact with each other.

[0027] In embodiments of this disclosure, the substrate may include a first surface on which dummy units are disposed and a second surface opposite to the first surface. Here, the width of the substrate may decrease in one direction from the first surface toward the second surface.

[0028] The above-described display device can be provided by the following steps, which include: preparing a mother substrate having at least two unit regions; forming a first dummy pattern at the edge of the unit regions; forming a pixel unit in each of the unit regions and forming a second dummy pattern superimposed on the first dummy pattern; forming a thin film encapsulation layer on the pixel unit and the second dummy pattern; and removing a portion of the mother substrate by performing a dry etching process, thereby setting the mother substrate on a display panel basis.

[0029] In embodiments of this disclosure, the first dummy pattern and the second dummy pattern may be superimposed on each other and include transparent conductive oxide.

[0030] Beneficial effects

[0031] According to embodiments of this disclosure, a display device with improved reliability can be provided by protecting the structure disposed on the mother substrate from the effects of etching gases by setting dummy patterns in the outer region of the substrate, the etching gases being used in the process of setting the mother substrate on a unit basis (a box or display panel).

[0032] Additionally, according to embodiments of this disclosure, when the mother substrate is configured on a unit basis (or display panel), a display device in which the invalid space of the outer area (or non-display area) of the display panel is minimized can be provided by using a dry etching method.

[0033] In addition, according to embodiments of this disclosure, a method for manufacturing the above-described display device can be provided.

[0034] The effects of the embodiments according to this disclosure are not limited to the above examples, and many more effects are included in this specification. Attached Figure Description

[0035] Figure 1 This is a perspective view schematically illustrating a display device according to an embodiment of the present disclosure.

[0036] Figure 2 yes Figure 1 A schematic cross-sectional view of the display device.

[0037] Figure 3 yes Figure 2 A schematic cross-sectional view of the display panel.

[0038] Figure 4 yes Figure 2 A schematic floor plan of the display panel.

[0039] Figure 5a and Figure 5b This illustrates an embodiment. Figure 4 The circuit diagram shows the electrical connections of the components included in a single pixel.

[0040] Figure 6 It is along Figure 4 A sectional view taken by line I-I'.

[0041] Figures 7 to 9 Is with Figure 4 The sectional view corresponding to line I-I' shows more details. Figure 6 This is an area of ​​the display panel shown.

[0042] Figures 10a to 10d This is a schematic plan view showing a method of manufacturing a display device according to an embodiment of the present disclosure.

[0043] Figure 11a It is along Figure 10a A sectional view taken from line II-II'. Figure 11b It is along Figure 10b A sectional view taken from line II-II'. Figure 11c It is along Figure 10c A sectional view taken from line II-II'. Figure 11d It is along Figure 10d The sectional view taken from line II-II'.

[0044] Figure 12 According to another embodiment Figure 6 The implementation method of the third encapsulation layer shown is similar to Figure 4 The sectional view corresponding to line I-I'.

[0045] Figure 13 Is with Figure 4 The sectional view corresponding to line I-I' shows more details. Figure 12 This is an area of ​​the display panel shown.

[0046] Figure 14 This illustrates an embodiment according to another embodiment. Figure 4 A schematic plan view of the display panel shown.

[0047] Figure 15 It is along Figure 14 The sectional view taken from line III-III'.

[0048] Figure 16 This illustrates a different embodiment. Figure 1 A schematic cross-sectional view of the display device.

[0049] Figure 17 yes Figure 16 A schematic cross-sectional view of the touch sensor.

[0050] Figure 18 yes Figure 16 A schematic plan view of the touch sensor.

[0051] Figure 19a It is shown schematically. Figure 18 A magnified plan view of a partial EA example.

[0052] Figure 19b It is along Figure 19a A sectional view taken by line V-V'.

[0053] Figure 20 It is along Figure 18 A sectional view taken from line IV-IV'.

[0054] Figure 21 It is along Figure 18A sectional view taken along line IV-IV', which shows more detail Figure 20 This is an area of ​​the display device shown.

[0055] Figure 22 It is along Figure 18 A cross-sectional view taken along line IV-IV', which shows a different embodiment. Figure 21 The second dummy pattern and insulating layer. Detailed Implementation

[0056] Because this disclosure can be modified in various ways and has various forms, specific embodiments will be shown in the accompanying drawings and described in detail in the specification. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed, and this disclosure includes all modifications, equivalents, and substitutions within the spirit and technical scope of this disclosure.

[0057] In describing each drawing, similar reference numerals are used for similar components. In the drawings, for clarity of this disclosure, the dimensions of the structures are shown enlarged from their actual dimensions. The terms "first" and "second," etc., may be used to describe various components, but the components should not be limited by these terms. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0058] It should be understood that, in this application, the terms "comprising" or "having," etc., are used to describe the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Furthermore, the statement that a portion of a layer, film, region, or plate is "on" another portion includes not only the case where the portion is "directly on" the other portion, but also the case where there are other portions between the portion and the other portion. Additionally, in this specification, when a portion of a layer, film, region, or plate is formed on another portion, the formation direction is not limited to the upward direction, but includes the portion being formed on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, or plate is formed "below" another portion, this includes not only the case where the portion is "directly below" the other portion, but also the case where there are other portions between the portion and the other portion.

[0059] In this application, when a component (e.g., a "first component") is operatively or communicatively coupled to or "connected" to another component (e.g., a "second component"), this should be understood as meaning that the component can be directly connected to the other component, or can be connected to the other component through another component (e.g., a "third component"). Conversely, when a component (e.g., a "first component") is "directly coupled to" or "directly connected" to another component (e.g., a "second component"), this can be understood as meaning that there is no other component (e.g., a "third component") between the component and the other component.

[0060] In the following description, preferred embodiments of the present disclosure and other matters necessary for those skilled in the art to readily understand the contents of the disclosure will be described in detail with reference to the accompanying drawings. In the following description, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0061] Figure 1 This is a perspective view schematically illustrating a display device according to an embodiment of the present disclosure. Figure 2 yes Figure 1 A schematic cross-sectional view of the display device. Figure 3 yes Figure 2 A schematic cross-sectional view of the display panel.

[0062] Reference Figures 1 to 3 The display device DD may include a display panel DP and a window WD.

[0063] This disclosure can be applied to the display device DD when the display device DD is an electronic device (such as a smartphone, television, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, netbook computer, workstation, server, PDA, portable multimedia player (PMP), MP3 player, medical device, camera, or wearable device) in which a display surface is applied to a surface.

[0064] The display device DD can be arranged in various shapes. For example, the display device DD can be arranged in the shape of a rectangular plate with two pairs of parallel sides, but this disclosure is not limited thereto. When the display device DD is arranged in the shape of a rectangular plate, one pair of sides can be set to be longer than the other pair of sides. In the drawings, the display device DD has corner portions formed by straight lines, but the disclosure is not limited thereto. According to an embodiment, the display device DD arranged in the shape of a rectangular plate can have a rounded (rounded) shape at the corner portion where one long side and one short side meet each other.

[0065] In embodiments of this disclosure, for ease of description, the display device DD has a rectangular shape having a pair of long sides and a pair of short sides, and the extension direction of the long sides is indicated as a second direction DR2, the extension direction of the short sides is indicated as a first direction DR1, and the direction perpendicular to the extension directions of the long sides and the short sides is indicated as a third direction DR3.

[0066] In embodiments of this disclosure, at least a portion of the display device DD may be flexible, and the display device DD may be folded at the flexible portion.

[0067] The display device DD may include a display area DD_DA for displaying an image and a non-display area DD_NDA disposed on at least one side of the display area DD_DA. The non-display area DD_NDA is the area in which no image is displayed. However, this disclosure is not limited thereto. According to embodiments, the shapes of the display area DD_DA and the non-display area DD_NDA can be designed relatively differently.

[0068] According to an embodiment, the display device DD may include a sensing area and a non-sensing area. The display device DD can not only display images through the sensing area, but also sense touch input performed on the display surface or sense light incident from the front. The non-sensing area may surround the sensing area, but this is an example and is not limited to this. According to an embodiment, a portion of the display area DA may correspond to the sensing area.

[0069] Display panel DP can display images. As display panel DP, self-emitting display panels can be used (such as organic light-emitting display panels (OLED panels) using organic light-emitting diodes as light-emitting elements, ultra-small light-emitting diode display panels (nanoscale LED display panels) using ultra-small light-emitting diodes as light-emitting elements, and quantum dot organic light-emitting display panels (QD OLED panels) using quantum dots and organic light-emitting diodes). Alternatively, non-emissive display panels (such as liquid crystal display panels (LCD panels), electrophoretic display panels (EPD panels), and electrowetting display panels (EWD panels)) can be used as display panel DP. When a non-emissive display panel is used as display panel DP, the display device DD may include a backlight unit that supplies light to the display panel DP.

[0070] The display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), and a thin-film encapsulation layer (TFE).

[0071] The substrate SUB can be a rigid substrate or a flexible substrate. Here, when the substrate SUB is a rigid substrate, it can be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate. When the substrate SUB is a flexible substrate, it can be one of a membrane substrate including polymeric organic materials and a plastic substrate. Additionally, the substrate SUB can include glass fiber reinforced plastic (FRP).

[0072] The pixel circuit layer (PCL) can be disposed on the substrate (SUB). Multiple thin-film transistors (TFTs) and lines connected to the TFTs can be disposed within the PCL. For example, each TFT can have a shape in which a semiconductor layer, a gate electrode, and source / drain electrodes are sequentially stacked, and an insulating layer is disposed between them. The semiconductor layer can include amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon, and organic semiconductors. The gate electrode and source / drain electrodes can include one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), but this disclosure is not limited thereto. Additionally, the PCL can include one or more insulating layers.

[0073] The display element layer (DPL) can be disposed on the pixel circuit layer (PCL). The display element layer (DPL) may include a light-emitting element that emits light. The light-emitting element may be, for example, an organic light-emitting diode (OLED), but this disclosure is not limited thereto. According to embodiments, the light-emitting element may be an inorganic light-emitting element comprising an inorganic light-emitting material or a light-emitting element that emits light by using quantum dots to change the wavelength of the emitted light (quantum dot display element). The organic light-emitting diode may have, for example, a shape in which an anode electrode, a hole transport layer, an organic emission layer, an electron transport layer, and a cathode electrode are sequentially stacked, but is not limited thereto.

[0074] A thin-film encapsulation layer (TFE) can be disposed on the display element layer (DPL). The TFE can be an encapsulation substrate, or it can have the shape of an encapsulation layer formed by multiple layers. When the TFE has the shape of an encapsulation layer, it can include inorganic and / or organic layers. For example, the TFE can have a shape in which inorganic layers, organic layers, and inorganic layers are sequentially stacked. The TFE prevents external air and moisture from penetrating into the display element layer (DPL) and the pixel circuit layer (PCL).

[0075] A window WD (Display Window) can be installed on the display panel DP to protect its exposed surfaces. The window WD protects the display panel DP from external impacts and provides an input and / or display surface to the user. The window WD can be bonded to the display panel DP using an optically clear adhesive (or bonding) component (OCA).

[0076] Window WD can have a multi-layered structure selected from glass substrates, plastic films, and plastic substrates. This multi-layered structure can be formed through a continuous process or by using an adhesive layer bonding process. Window WD, either entirely or partially, can be flexible.

[0077] A touch sensor (not shown) may be disposed between the display panel DP and the window WD. The touch sensor may be directly disposed on the surface of the display panel DP on which the image is displayed to receive user touch input. In embodiments of this disclosure, "directly disposed" may mean formed by a continuous process, in addition to being attached using a separate adhesive layer (or bonding layer).

[0078] Figure 4 yes Figure 2 A schematic floor plan of the display panel.

[0079] Reference Figures 1 to 4 The display panel DP may include a substrate SUB, a pixel PXL disposed on the substrate SUB, a driver disposed on the substrate SUB and driving the pixel PXL, and a line unit connecting the pixel PXL and the driver.

[0080] The base SUB can be formed from a region having an approximately rectangular shape. However, the number of regions disposed on the base SUB can vary, and the shape of the base SUB can have different shapes depending on the regions disposed on the base SUB.

[0081] The substrate SUB can be formed from an insulating material such as glass or resin. Additionally, the substrate SUB can be formed from a flexible material to be bent or folded, and can have a single-layer or multi-layer structure. For example, flexible materials may include at least one selected from polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. In embodiments of this disclosure, the substrate SUB can be formed from a flexible polyimide. However, the materials constituting the substrate SUB are not limited to the embodiments described above.

[0082] The base SUB may include a display area DA and a non-display area NDA. The display area DA may be an area where pixels PXL are set to display an image, and the non-display area NDA may be an area where pixels PXL are not set, or it may be an area where no image is displayed. For ease of description, Figure 4 Only one pixel PXL is shown, but multiple pixels PXL can be set in the display area DA of the base SUB.

[0083] The display area DA of the display panel DP can correspond to the display area DD_DA of the display device DD, and the non-display area NDA of the display panel DP can correspond to the non-display area DD_NDA of the display device DD.

[0084] A portion of the driver for driving pixel PXL and the wiring (not shown) connecting pixel PXL and the driver can be located in the non-display area NDA. The non-display area NDA can correspond to the bezel area of ​​the display device DD.

[0085] Pixels PXL can be disposed in the display area DA of the substrate SUB. Each of the pixels PXL can be the smallest unit for displaying an image. Pixels PXL can include light-emitting elements that emit white light and / or colored light. Each of the pixels PXL can emit light of any color among red, green, and blue, but is not limited thereto; each of the pixels PXL can emit light of cyan, magenta, or yellow, etc. Each of the pixels PXL can include a pixel circuit layer PCL disposed on the substrate SUB and a display element layer DPL disposed on the pixel circuit layer PCL.

[0086] Pixels PXL can be arranged in a matrix form along rows extending in the first direction DR1 and columns extending in the second direction DR2 intersecting the first direction DR1. However, the arrangement of pixels PXL is not particularly limited, and pixels PXL can be arranged in various forms. Pixels PXL have a rectangular shape in the accompanying drawings, but this disclosure is not limited thereto, and pixels PXL can be modified to various shapes. Furthermore, when multiple pixels PXL are provided, the multiple pixels PXL can be set to have different areas (or sizes). For example, in the case of pixels PXL emitting light of different colors, pixels PXL can be set with different areas (or sizes) or different shapes for each color.

[0087] The driver provides signals to each pixel PXL via the line unit and controls the driving of the pixel PXL. Figure 4 For ease of description, circuit units have been omitted; please refer to the following section. Figure 5a and Figure 5b Describe the line unit.

[0088] The driver may include a scan driver (not shown) that transmits scan signals to each of the pixels PXL along scan lines, a transmit driver (not shown) that provides transmit control signals to each of the pixels PXL along transmit control lines, a data driver (not shown) that provides data signals to each of the pixels PXL along data lines, and a timing controller (not shown). The timing controller can control the scan driver, transmit driver, and data driver.

[0089] Meanwhile, the display panel DP may include pixel units PX (or display units) and dummy units DMP spaced apart from the pixel units PX (or display units).

[0090] A pixel unit PX (or display unit) may include a pixel PXL for displaying an image and a thin-film encapsulation layer TFE disposed on the pixel PXL. For example, a pixel unit PX (or display unit) may include a pixel PXL disposed in a display area DA for displaying an image and a thin-film encapsulation layer TFE disposed on the pixel PXL to cover the pixel PXL.

[0091] A dummy unit (DMP) can be disposed in the non-display area NDA of the substrate SUB. The dummy unit DMP can be spaced apart from the pixel unit PX (or display unit) at a predetermined distance in a planar view and can be disposed along the edge of the substrate SUB. In embodiments of this disclosure, the dummy unit DMP can be disposed along all of the first sides S1 to the fourth sides S4 of the substrate SUB, but this disclosure is not limited thereto. When viewed in a planar view, one side of the dummy unit DMP can coincide with the edge of the substrate SUB, or it can protrude from the edge of the substrate SUB in a direction away from the pixel unit PX (or display unit) along a first direction DR1 (or a horizontal direction). For example, one side of the dummy unit DMP can protrude outward from the edge of the substrate SUB along the first direction DR1. Figure 4 In the diagram, for convenience, one side of the dummy element DMP is shown to coincide with the edge of the base SUB.

[0092] In embodiments of this disclosure, an example is provided in which the dummy unit DMP is arranged along the first side S1 to the fourth side S4 of the base SUB to have a shape forming a closed loop; however, this disclosure is not limited thereto. According to embodiments, the arrangement position and shape of the dummy unit DMP can be set differently when the shape of the base SUB is changed. For example, when the base SUB is formed as a circle, an ellipse, or a polygon, the dummy unit DMP can be arranged in a shape corresponding to a circle and forming a closed loop, a shape corresponding to an ellipse and forming a closed loop, or a shape corresponding to a polygon and forming a closed loop.

[0093] The dummy unit DMP may include a first dummy pattern DMP1 and a second dummy pattern DMP2. The first dummy pattern DMP1 and the second dummy pattern DMP2 may be superimposed on each other in a plane and may have the same or similar planar shapes. For example, each of the first dummy pattern DMP1 and the second dummy pattern DMP2 may have a shape forming a closed loop along the edge of the base SUB. See below. Figures 6 to 9 A detailed description of the dummy element (DMP).

[0094] Figure 5a and Figure 5bIt is shown that, according to the embodiments, it includes Figure 4 The circuit diagram shows the electrical connections of the components in a pixel.

[0095] exist Figure 5a and Figure 5b In China, it will not only include Figure 4 Each component in the pixels shown is collectively referred to as pixel PXL, and the area in which said component is disposed is collectively referred to as pixel PXL. Figure 5a and Figure 5b Each of the pixels PXL shown in the diagram can be included in the [image / database]. Figure 4 Any one of the pixels PXL in the display panel DP, and the pixels PXL can have substantially the same or similar structure to each other.

[0096] exist Figure 5a In this context, a pixel PXL can include an organic light-emitting diode (OLED) as a light-emitting element (LD). Figure 5b In this context, a single pixel PXL can include multiple ultra-small inorganic light-emitting diodes (LEDs) as small as micrometers or nanometers, which are formed in a structure in which nitride-based semiconductors are grown as light-emitting elements (LDs).

[0097] exist Figure 5a and Figure 5b The image shows an active pixel PXL connected to the i-th scan line Si and the i-th emission control line Ei in the i-th row (or pixel row) of the display area DA of the display panel DP, and the j-th data line Dj in the j-th column (or pixel column), and including seven transistors and a storage capacitor Cst.

[0098] Reference Figures 1 to 5a Each pixel PXL may include a light-emitting element LD and pixel circuitry 144 for driving the light-emitting element LD. In embodiments of this disclosure, the light-emitting element LD may be an organic light-emitting diode, but this disclosure is not limited thereto.

[0099] Pixel circuit 144 can be connected to the scan line Si and data line Dj of the corresponding pixel PXL. For example, when pixel PXL is located in the i-th row (i is a positive integer) and j-th column (j is a positive integer) of the display area DA of the display panel DP, pixel circuit 144 of pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. Additionally, according to an embodiment, pixel circuit 144 can also be connected to at least another scan line. For example, a pixel PXL located in the i-th row of the display area DA of the display panel DP can also be connected to the (i-1)-th scan line Si-1 and / or the (i+1)-th scan line Si+1. Furthermore, according to an embodiment, in addition to the first pixel power supply ELVDD and the second pixel power supply ELVSS, pixel circuit 144 can also be connected to a third power supply. For example, pixel circuit 144 can also be connected to the initialization power supply Vint.

[0100] The pixel circuit 144 may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0101] One electrode (e.g., the source electrode) of the first transistor T1 (driving transistor) can be connected via the fifth transistor T5 to the power line PL to which the voltage of the first pixel power supply ELVDD is applied, and the other electrode (e.g., the drain electrode) can be connected via the sixth transistor T6 to the light-emitting element LD. Additionally, the gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the driving current flowing between the first pixel power supply ELVDD and the second pixel power supply ELVSS via the light-emitting element LD in response to the voltage of the first node N1.

[0102] A second transistor T2 (a switching transistor) can be connected between the j-th data line Dj connected to pixel PXL and the source electrode of the first transistor T1. Additionally, the gate electrode of the second transistor T2 can be connected to the i-th scan line Si connected to pixel PXL. The second transistor T2 can be turned on when a scan signal with a gate on-state voltage (e.g., a low voltage) is supplied from the i-th scan line Si, so that the j-th data line Dj is electrically connected to the source electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj can be transmitted to the first transistor T1.

[0103] The third transistor T3 can be connected between the drain electrode of the first transistor T1 and the first node N1. Additionally, the gate electrode of the third transistor T3 can be connected to the i-th scan line Si. The third transistor T3 can be turned on when a scan signal supplying a gate-on voltage from the i-th scan line Si is applied, thereby electrically connecting the drain electrode of the first transistor T1 and the first node N1 to each other.

[0104] The fourth transistor T4 can be connected between the first node N1 and the initialization power supply line IPL to which the initialization power supply Vint is applied. Additionally, the gate electrode of the fourth transistor T4 can be connected to the previous scan line, for example, the (i-1)th scan line Si-1. The fourth transistor T4 can be turned on when a scan signal with a gate-on voltage is supplied to the (i-1)th scan line Si-1, so that the voltage of the initialization power supply Vint is transmitted to the first node N1. Here, the initialization power supply Vint can have a voltage equal to or less than the minimum voltage of the data signal.

[0105] The fifth transistor T5 can be connected between the power supply line PL to which the first pixel power supply ELVDD is connected and the first transistor T1. Additionally, the gate electrode of the fifth transistor T5 can be connected to a corresponding emitter control line, such as the i-th emitter control line Ei. The fifth transistor T5 can be turned off when an emitter control signal with a gate cutoff voltage is supplied to the i-th emitter control line Ei, and can be turned on under other conditions.

[0106] The sixth transistor T6 can be connected between the first transistor T1 and the light-emitting element LD. Additionally, the gate electrode of the sixth transistor T6 can be connected to the i-th emission control line Ei. The sixth transistor T6 can be turned off when the emission control signal with a gate cutoff voltage is supplied to the i-th emission control line Ei, and can be turned on under other conditions.

[0107] The seventh transistor T7 can be connected between the light-emitting element LD and the initialization power supply line IPL to which the initialization power supply Vint is applied. Furthermore, the gate electrode of the seventh transistor T7 can be connected to any scan line in the next stage, for example, the (i+1)th scan line Si+1. The seventh transistor T7 can be turned on when the scan signal with the gate on-state voltage is supplied to the (i+1)th scan line Si+1, so that the voltage of the initialization power supply Vint is supplied to the light-emitting element LD. At this time, the signal applied to the gate electrode of the seventh transistor T7 can be a signal with the same timing as the scan signal with the gate on-state voltage supplied to the (i)th scan line Si.

[0108] The storage capacitor Cst can be connected between the first node N1 and the power line PL to which the voltage of the first pixel power supply ELVDD is applied. The storage capacitor Cst can store data signals and voltages corresponding to the threshold voltage of the first transistor T1.

[0109] The first electrode (or anode electrode) of the light-emitting element LD can be connected to the first transistor T1 via the sixth transistor T6, and the second electrode (or cathode electrode) can be connected to the second pixel power supply ELVSS. The light-emitting element LD generates light (or rays) of a predetermined brightness in response to the amount of current supplied from the first transistor T1. The voltage value of the first pixel power supply ELVDD can be set to be higher than the voltage value of the second pixel power supply ELVSS, so that current can flow to the light-emitting element LD.

[0110] The light-emitting element (LD) can be, for example, an organic light-emitting diode (OLED). The LD can emit light of one color: red, green, or blue. However, this disclosure is not limited thereto.

[0111] Meanwhile, the structure of each pixel PXL is not limited to Figure 5a The embodiment shown is illustrated. For example, it goes without saying that various currently known pixel circuit structures 144 can be applied to each pixel PXL.

[0112] In the following text, refer to Figure 5b The description includes each pixel PXL of a plurality of light-emitting elements LD formed in a structure in which nitride-based semiconductors are grown.

[0113] Reference Figures 1 to 4 and Figure 5b Each pixel PXL may include a light-emitting unit (EMU) that generates light with a brightness corresponding to the data signal. Additionally, each pixel PXL may optionally include pixel circuitry 144 for driving the light-emitting unit (EMU).

[0114] According to an embodiment, the light-emitting unit (EMU) may include a plurality of light-emitting elements (LDs) connected in parallel between a first power line PL1 to which a voltage is applied by a first driving power supply VDD and a second power line PL2 to which a second driving power supply VSS is applied. For example, the EMU may include a first electrode EL1 (or a first alignment electrode) connected to the first driving power supply VDD via pixel circuit 144 and the first power line PL1, a second electrode EL2 (or a second alignment electrode) connected to the second driving power supply VSS via the second power line PL2, and a plurality of light-emitting elements (LDs) connected in parallel in the same direction between the first electrode EL1 and the second electrode EL2. In embodiments of this disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0115] Each of the light-emitting elements (LDs) included in the light-emitting unit (EMU) may include a first semiconductor layer and a second semiconductor layer (not shown) formed of different types of semiconductor layers, and an active layer (not shown) disposed between the first semiconductor layer and the second semiconductor layer. For example, each of the light-emitting elements (LDs) may be implemented as a light-emitting stack in which the first semiconductor layer, the active layer, and the second semiconductor layer are sequentially stacked in one direction. Here, the first semiconductor layer may be an n-type semiconductor layer, and the second semiconductor layer may be a p-type semiconductor layer.

[0116] Each of the light-emitting elements (LDs) may include a first terminal connected to a first driving power supply VDD via a first electrode EL1 and a second terminal connected to a second driving power supply VSS via a second electrode EL2. The first driving power supply VDD and the second driving power supply VSS may have different potentials. For example, the first driving power supply VDD may be set to a high potential power supply, and the second driving power supply VSS may be set to a low potential power supply. In this case, during the emission period of pixel PXL, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to be greater than or equal to the threshold voltage of the light-emitting element LD.

[0117] As described above, each light-emitting element LD connected in parallel in the same direction (e.g., forward direction) between a first electrode EL1 and a second electrode EL2, each supplied with a voltage of a different potential, can constitute each effective light source. Such effective light sources can be concentrated to constitute the light-emitting unit EMU of pixel PXL. The light-emitting element LD of the light-emitting unit EMU can emit light with a brightness corresponding to the driving current supplied through pixel circuit 144. For example, during each frame period, pixel circuit 144 can supply the light-emitting unit EMU with a driving current corresponding to the grayscale value of the corresponding frame data. The driving current supplied to the light-emitting unit EMU can be divided and can flow through the light-emitting element LD. Therefore, while each light-emitting element LD emits light with a brightness corresponding to the current flowing through it, the light-emitting unit EMU can emit light with a brightness corresponding to the driving current.

[0118] According to an embodiment, in addition to the light-emitting element LD constituting each effective light source, the light-emitting unit (EMU) may also include at least one ineffective light source. For example, at least a reverse light-emitting element LDr may also be connected between the first electrode EL1 and the second electrode EL2 of the light-emitting unit (EMU). The reverse light-emitting element LDr may be connected in parallel with the light-emitting element LD constituting the effective light source between the first electrode EL1 and the second electrode EL2, and may be connected between the first electrode EL1 and the second electrode EL2 in the opposite direction to the light-emitting element LD.

[0119] Pixel circuit 144 can be connected to the scan line Si and data line Dj of the corresponding pixel PXL. For example, when pixel PXL is set in the i-th (i is a positive integer) row and j-th (j is a positive integer) column of display area DA, pixel circuit 144 of pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of display area DA. In addition, pixel circuit 144 can also be connected to the control line CLI and the sensing line SENj of pixel PXL. Pixel circuit 144 may include first transistor T1 to third transistor T3 and storage capacitor Cst.

[0120] Except for changes in the connection positions of some components due to the change in transistor type, the construction and operation of the first transistor T1 and the second transistor T2 are similar to those described above. Figure 5a The construction and operation of the first transistor T1 and the second transistor are described, therefore their description is omitted.

[0121] The third transistor T3 is connected between the first transistor T1 and the sensing line SENj. For example, one electrode of the third transistor T3 can be connected to a terminal of the first transistor T1 that is connected to the first electrode EL1 (e.g., the source electrode), and the other electrode of the third transistor T3 can be connected to the sensing line SENj. Alternatively, when the sensing line SENj is omitted, the other electrode of the third transistor T3 can be connected to the j-th data line Dj.

[0122] According to an embodiment, the gate electrode of the third transistor T3 is connected to the control line CLI. Alternatively, when the control line CLI is omitted, the gate electrode of the third transistor T3 can be connected to the i-th scan line Si. The third transistor T3 can be turned on during a predetermined sensing period by a control signal supplied with a gate on-state voltage (e.g., a high level) to the control line CLI, thereby electrically connecting the sensing line SENj and the first transistor T1 to each other.

[0123] According to an embodiment, the sensing period can be a period for extracting characteristic information (e.g., the threshold voltage of the first transistor T1, etc.) of each pixel PXL disposed in the display area DA. During the aforementioned sensing period, by supplying a predetermined reference voltage to the first node N1 via the j-th data line Dj and the second transistor T2 to enable the first transistor T1 to conduct, the first transistor T1 can be turned on or each pixel PXL can be connected to a current source, etc. Furthermore, by supplying a control signal for the gate conduction voltage to the third transistor T3 to turn it on, the first transistor T1 can be connected to the sensing line SENj. Therefore, characteristic information of each pixel PXL, including the threshold voltage of the first transistor T1, can be extracted via the aforementioned sensing line SENj. The extracted characteristic information can be used to convert image data, thereby compensating for characteristic deviations between pixels PXL.

[0124] at the same time, Figure 5b An embodiment in which all of the first transistor T1 to the third transistor T3 are N-type transistors has been disclosed, but this disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 may be changed to a P-type transistor. Furthermore, Figure 5b An embodiment is disclosed in which the light-emitting unit (EMU) is connected between the pixel circuit 144 and the second driving power supply VSS; however, the light-emitting unit (EMU) can also be connected between the first driving power supply VDD and the pixel circuit 144. Parasitic capacitor C OLED It can be located between the first electrode EL1 and the second electrode EL2 of the light-emitting unit EMU.

[0125] The structure applicable to each pixel PXL in this disclosure is not limited to Figure 5a and Figure 5b In the embodiments shown, the corresponding pixel PXL can have various structures.

[0126] Figure 6 It is along Figure 4 A cross-sectional view taken by line I-I'. Figures 7 to 9 Is with Figure 4 The sectional view corresponding to line I-I' shows more details. Figure 6 This is an area of ​​the display panel shown.

[0127] exist Figures 6 to 9 In this disclosure, the structure of the dummy unit DMP and the pixel unit PX (or display unit) is simplified (e.g., each electrode is shown as a single electrode layer and each insulating layer is shown as a single insulating layer only), but this disclosure is not limited thereto.

[0128] In embodiments of this disclosure, "forming and / or disposed in the same layer" may mean forming in the same process, while "forming and / or disposed in different layers" may mean forming in different processes.

[0129] Additionally, in embodiments of this disclosure, the term "connection" between two components may refer to both electrical and physical connections.

[0130] Reference Figures 1 to 9 The display panel DP may include pixel units PX (or display units) disposed in the display area DA and dummy units DMP disposed in the non-display area NDA. Additionally, the display panel DP may include dam units DAM disposed in the non-display area NDA and located between the dummy units DMP and the pixel units PX (or display units).

[0131] A pixel unit PX (or display unit) may include a pixel PXL disposed on a substrate SUB and a thin-film encapsulation layer TFE covering the pixel PXL. Each of the pixels PXL may include a pixel circuit layer PCL disposed on the substrate SUB and a display element layer DPL disposed on the pixel circuit layer PCL.

[0132] The pixel circuit layer PCL may include a buffer layer BFL, a pixel circuit 144 disposed on the buffer layer BFL, and a protective layer PSV disposed on the pixel circuit 144.

[0133] The buffer layer BFL can be disposed and / or formed on a surface UF (or upper surface) of the substrate SUB. The buffer layer BFL prevents impurities from diffusing into the transistor T included in the pixel circuit 144. The buffer layer BFL can be an inorganic insulating layer comprising an inorganic material. The buffer layer BFL can include materials such as silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiON) and aluminum oxide (AlO) x The buffer layer BFL can be a single layer or a multilayer structure with at least two layers. When the buffer layer BFL is multilayered, each layer can be formed of the same material or different materials. The buffer layer BFL may be omitted depending on the material and processing conditions of the substrate SUB.

[0134] Pixel circuit 144 may include at least one transistor T. Transistor T may include a driving transistor Tdr for controlling the driving current of the light-emitting element LD and a switching transistor (not shown) electrically connected to the driving transistor Tdr. However, this disclosure is not limited thereto; in addition to the driving transistor Tdr and the switching transistor, pixel circuit 144 may also include circuit elements performing other functions. In the following embodiments, the driving transistor Tdr and the switching transistor are referred to as one transistor T or multiple transistors T. Here, the driving transistor Tdr may have the same characteristics as referenced... Figure 5a and Figure 5b The first transistor T1 described has the same construction as the reference transistor, and the switching transistor may have the same construction as the reference transistor. Figure 5a and Figure 5b The second transistor T2 described has the same construction. The driving transistor Tdr and the switching transistor can have substantially similar or identical structures. Therefore, the description of the driving transistor Tdr is used instead of the description of the switching transistor.

[0135] The driving transistor Tdr may include a semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE can be either the source electrode or the drain electrode, and the second terminal DE can be the other electrode. For example, when the first terminal SE is the source electrode, the second terminal DE can be the drain electrode.

[0136] A semiconductor pattern SCL can be disposed and / or formed on a buffer layer BFL. The semiconductor pattern SCL may include a first contact region contacting a first terminal SE and a second contact region contacting a second terminal DE. The region located between the first and second contact regions and superimposed on the gate electrode GE can be the channel region of the driving transistor Tdr. The semiconductor pattern SCL can be a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, or oxide semiconductor, etc. The channel region can be an undoped semiconductor pattern and can be an intrinsic semiconductor, but this disclosure is not limited thereto. According to an embodiment, the channel region can be a doped semiconductor pattern. The first and second contact regions can be doped semiconductor patterns.

[0137] The gate electrode GE can be disposed and / or formed on a semiconductor pattern SCL, with a gate insulating layer GI disposed between them. For example, the gate electrode GE can be disposed and / or formed on the gate insulating layer GI. The gate electrode GE can be formed of at least one metal or an alloy of these metals, such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Furthermore, the gate electrode GE can be formed as a single layer, but is not limited thereto, and can be formed as a multilayer in which at least two of the aforementioned metals and alloys are stacked.

[0138] The gate insulating layer GI can be disposed and / or formed on the semiconductor pattern SCL. The gate insulating layer GI can be an inorganic insulating layer comprising an inorganic material. For example, the gate insulating layer GI may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiON) and aluminum oxide (AlO) x The gate insulating layer GI is formed from at least one of the inorganic materials described above. However, the material of the gate insulating layer GI is not limited to the embodiments described above. According to an embodiment, the gate insulating layer GI may be formed from an organic insulating layer comprising organic materials. The gate insulating layer GI may be configured as a single layer, but may also be configured as a multilayer with at least two layers.

[0139] The corresponding first terminal SE and second terminal DE can contact the first and second contact areas of the semiconductor pattern SCL through contact holes passing through the interlayer insulating layer ILD and the gate insulating layer GI. For example, the first terminal SE can contact one of the first and second contact areas of the semiconductor pattern SCL, and the second terminal DE can contact the remaining contact areas of the first and second contact areas of the semiconductor pattern SCL. The first terminal SE and the second terminal DE can be formed of at least one of the metals such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of these metals. In addition, the first terminal SE and the second terminal DE can be formed as a single layer, but are not limited thereto, and can be formed as a multilayer in which at least two of the metals and alloys are stacked.

[0140] An interlayer insulating layer (ILD) can be disposed and / or formed on the gate electrode GE. The ILD can be an inorganic insulating layer comprising inorganic materials. For example, the ILD may include silicon oxide (SiO₂). x ), silicon nitride (SiN) x ), silicon oxynitride (SiON) and aluminum oxide (AlO) x At least one of the inorganic materials. The interlayer insulating layer (ILD) can be formed from a single layer or multiple layers. According to an embodiment, the interlayer insulating layer (ILD) can be an organic insulating layer including organic materials.

[0141] In the above embodiments, the first terminal SE and the second terminal DE of the driving transistor Tdr are electrically connected to separate electrodes of the semiconductor pattern SCL through contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD; however, this disclosure is not limited thereto. According to an embodiment, the first terminal SE of the driving transistor Tdr may be one of a first contact region and a second contact region adjacent to the channel region of the semiconductor pattern SCL, and the second terminal DE of the driving transistor Tdr may be the remaining contact region of the first contact region and the second contact region adjacent to the channel region of the semiconductor pattern SCL. In this case, the second terminal DE of the driving transistor Tdr can be electrically connected to the light-emitting element LD of each pixel PXL through a separate connection method including a bridge electrode or a contact electrode.

[0142] According to an embodiment, an interlayer insulating layer (not shown) can be provided and / or formed on the first terminal SE and the second terminal DE of the driving transistor Tdr. In this case, a first additional electrode (not shown, or a first connection electrode) corresponding to the first terminal SE and a second additional electrode (not shown, or a second connection electrode) corresponding to the second terminal DE can be provided and / or formed on the interlayer insulating layer. The first additional electrode (or the first connection electrode) can be electrically connected to the first terminal SE disposed below it through a contact hole passing through the interlayer insulating layer, and the second additional electrode (or the second connection electrode) can be electrically connected to the second terminal DE disposed below it through a contact hole passing through the interlayer insulating layer.

[0143] In embodiments of this disclosure, the transistor T included in the pixel circuit 144 may be constructed of an LTPS thin-film transistor, but this disclosure is not limited thereto, and it may be constructed of an oxide semiconductor thin-film transistor according to embodiments. Furthermore, the case where the transistor T is a thin-film transistor with a top-gate structure is described as an example, but this disclosure is not limited thereto. According to embodiments, the transistor T may be a thin-film transistor with a bottom-gate structure.

[0144] The protective layer PSV can be disposed and / or formed on the pixel circuit 144, which includes the driving transistor Tdr.

[0145] The protective layer PSV can be provided in the form of an organic insulating layer, an inorganic insulating layer, or an organic insulating layer disposed on an inorganic insulating layer. The inorganic insulating layer can include, for example, inorganic materials (such as silicon dioxide (SiO2)). x ), silicon nitride (SiN) x ), silicon oxynitride (SiON) and aluminum oxide (AlO) x The organic insulating layer may include at least one of the following: acrylic resin (polyacrylate resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0146] The display element layer (DPL) can be set and / or formed on the protective layer (PSV).

[0147] The display element layer (DPL) can be disposed on the protective layer (PSV) and can include a light-emitting element (LD). The LD can include a first electrode (AE) and a second electrode (CE), as well as an emission layer (EML) disposed between the two electrodes (AE and CE). In this case, one of the first electrode (AE) and the second electrode (CE) can be an anode electrode, and the remaining electrode can be a cathode electrode. When the LD is a front-surface emitting organic light-emitting diode (OLED), the first electrode (AE) can be a reflective electrode, and the second electrode (CE) can be a transmissive electrode. In embodiments of this disclosure, the case where the LD is a front-surface emitting organic light-emitting diode and the first electrode (AE) is an anode electrode is described as an example.

[0148] The first electrode AE ​​can be electrically connected to the second terminal DE of the driving transistor Tdr through a contact hole passing through the protective layer PSV. The first electrode AE ​​may include a reflective layer (not shown) capable of reflecting light or a transparent conductive layer (not shown) disposed on and / or beneath the reflective layer. For example, the first electrode AE ​​may be composed of multiple layers, including a lower transparent conductive layer formed of indium tin oxide (ITO), a reflective layer disposed on the lower transparent conductive layer and formed of silver (Ag), and an upper transparent conductive layer disposed on the reflective layer and formed of indium tin oxide (ITO). At least one of the transparent conductive layer and the reflective layer can be electrically connected to the second terminal DE of the driving transistor Tdr.

[0149] The display element layer (DPL) may further include a pixel defining layer (PDL) having an opening that exposes a portion of the first electrode AE ​​(e.g., the upper surface of the first electrode AE). The pixel defining layer (PDL) may be an organic insulating layer comprising an organic material. For example, the pixel defining layer (PDL) may be formed of an organic insulating material such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0150] The emitter layer (EML) can be disposed in the region corresponding to the opening of the pixel-defining layer (PDL). That is, the emitter layer (EML) can be disposed on one surface of the exposed first electrode (AE). The emitter layer (EML) can have a multilayer thin-film structure including at least a light-generating layer. The emitter layer (EML) may include a hole injection layer, a hole transport layer, a light-generating layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The hole injection layer injects holes; the hole transport layer has excellent hole transport performance and is used to increase the chance of hole-electron recombination by suppressing the movement of electrons not bound in the light-generating layer; the light-generating layer emits light through the recombination of injected electrons and holes; the hole blocking layer is used to suppress the movement of holes not bound in the light-generating layer; the electron transport layer is used to smoothly transport electrons to the light-generating layer; and the electron injection layer is used to inject electrons.

[0151] The color of the light generated in the light-generating layer can be one of red, green, blue, and white, but this embodiment is not limited to this. For example, the color of the light generated in the light-generating layer of the emission layer EML can be one of magenta, cyan, and yellow. The hole injection layer, hole transport layer, hole blocking layer, electron transport layer, and electron injection layer can be common layers connected in adjacent emission regions.

[0152] The second electrode CE can be disposed and / or formed on the emitter layer EML. The second electrode CE can be a common layer disposed for pixels PXL, but this disclosure is not limited thereto. The second electrode CE can be a transmissive electrode and can include a transparent conductive material (or substance). The transparent conductive material (or substance) can include transparent conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO)) and conductive polymers (such as PEDOT), etc.

[0153] A thin-film encapsulation layer TFE can be disposed and / or formed on the second electrode CE.

[0154] The thin-film encapsulation layer (TFE) can be formed as a single layer or as multiple layers. The TFE may include multiple insulating layers covering the light-emitting element (LD). Specifically, the TFE may include at least one inorganic layer and at least one organic layer. For example, the TFE may have a structure in which inorganic and organic layers are alternately stacked. According to an embodiment, the TFE may be an encapsulation substrate disposed on the light-emitting element (LD) and bonded to the substrate (SUB) by a sealant.

[0155] The thin-film encapsulation layer (TFE) may include a first encapsulation layer ENC1 to a third encapsulation layer ENC3. The first encapsulation layer ENC1 may be disposed and / or formed on the display element layer (DPL) and may be located over at least a portion of the display area (DA) and the non-display area (NDA). The second encapsulation layer ENC2 may be disposed and / or formed on the first encapsulation layer ENC1 and may be located over at least a portion of the display area (DA) and the non-display area (NDA). The third encapsulation layer ENC3 may be disposed and / or formed on the second encapsulation layer ENC2 and may be located over at least a portion of the display area (DA) and the non-display area (NDA). According to an embodiment, the third encapsulation layer ENC3 may be located over the entire display area (DA) and the non-display area (NDA). In embodiments of this disclosure, the first encapsulation layer ENC1 and the third encapsulation layer ENC3 may be formed of inorganic layers comprising inorganic materials, and the second encapsulation layer ENC2 may be formed of an organic layer comprising organic materials.

[0156] In the above embodiments, an example is described in which the display element layer DPL includes a light-emitting element LD composed of a front-surface emitting organic light-emitting diode having a first electrode AE, an emission layer EML, and a second electrode CE, but this disclosure is not limited thereto.

[0157] According to the embodiments, such as Figure 8 As shown, the display element layer DPL may include at least one ultra-small inorganic light-emitting element (LD) at the micrometer or nanometer scale formed in a structure in which a nitride-based semiconductor is grown. In this case, the display element layer DPL may include a first embankment pattern BNK1 and a second embankment pattern BNK2, a first alignment electrode EL1 and a second alignment electrode EL2, a first insulating layer INS1 and a second insulating layer INS2, and a first contact electrode CNE1 and a second contact electrode CNE2. Here, the light-emitting element LD may have the same characteristics as the referenced element. Figure 5b Each of the described light-emitting elements (LDs) has the same construction and each of the multiple light-emitting elements (LDs) can be replaced.

[0158] The first dam pattern BNK1 may be disposed and / or formed on the protective layer PSV and may be located in the emission region of each pixel PXL from which light is emitted. The first dam pattern BNK1 may support each of the first alignment electrode EL1 and the second alignment electrode EL2 to change the surface profile (or shape) of each of the first alignment electrode EL1 and the second alignment electrode EL2, thereby guiding the light emitted from the light-emitting element LD in the image display direction of the display device DD. The first dam pattern BNK1 may include an inorganic insulating layer formed of inorganic material or an organic insulating layer formed of organic material. According to an embodiment, the first dam pattern BNK1 may include a single layer of organic insulating layer and / or a single layer of inorganic insulating layer, but this disclosure is not limited thereto.

[0159] The second dam pattern BNK2 may surround at least one side of the peripheral region of each pixel PXL. The peripheral region may include a non-emitting region from which light is not emitted. The second dam pattern BNK2 may be a structure that defines (or separates) the emitting region of each of the pixels PXL, and may be, for example, a pixel defining layer PDL. The second dam pattern BNK2 may include at least one light-blocking material and / or reflective material to prevent light (or ray) leakage defects between pixels PXL.

[0160] Each of the first alignment electrode EL1 and the second alignment electrode EL2 may be disposed and / or formed on the first embankment pattern BNK1 to have a surface profile corresponding to the shape of the first embankment pattern BNK1. Each of the first alignment electrode EL1 and the second alignment electrode EL2 may be formed of a material with a constant reflectivity to allow light emitted from each of the light-emitting elements LD to travel in the image display direction of the display device. The first alignment electrode EL1 may be electrically connected to the second terminal DE of the driving transistor Tdr through a contact hole through the protective layer PSV, and the second alignment electrode EL2 may be electrically connected to and / or physically connected to the connection electrode E_CNT located in the non-display area NDA. The first alignment electrode EL1 may be an anode electrode, and the second alignment electrode EL2 may be a cathode electrode. In embodiments of this disclosure, the first alignment electrode EL1 may be a reference electrode. Figure 7 The first electrode AE ​​described corresponds to a certain structure, and the second alignment electrode EL2 can be the same as the reference electrode. Figure 7 The construction corresponding to the second electrode CE is described.

[0161] A light-emitting element (LD) can be disposed between a first alignment electrode EL1 and a second alignment electrode EL2, and can be electrically connected to each of the first alignment electrode EL1 and the second alignment electrode EL2. Each of the LDs can emit any of colored light and / or white light. The LDs can be disposed in the form of being sprayed into a solution, and can be injected into each pixel PXL. Each LD can include an emission stack pattern in which a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 are sequentially stacked along a direction (e.g., a first direction DR1). Additionally, each LD can include an insulating layer (not shown) surrounding the outer circumferential surface of the emission stack pattern.

[0162] In embodiments of this disclosure, the first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, or Sn. The active layer 12 may be disposed on the first semiconductor layer 11 and may be formed in a single quantum well structure or a multiple quantum well structure. The second semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg.

[0163] A light-emitting element (LD) may be disposed and / or formed on a first insulating layer INS1. Each of a first alignment electrode EL1 and a second alignment electrode EL2 may be disposed and / or formed between the first insulating layer INS1 and a protective layer PSV. The first insulating layer INS1 may fill the space between each light-emitting element LD and the protective layer PSV to stably support the light-emitting element LD. The first insulating layer INS1 may comprise an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material.

[0164] A second insulating layer INS2 may be disposed on and / or formed on the light-emitting element LD. The second insulating layer INS2 may be disposed on and / or formed on each of the light-emitting elements LD to cover a portion of the upper surface of each of the light-emitting elements LD, and may expose both ends of each of the light-emitting elements LD to the outside. The second insulating layer INS2 may also secure each of the light-emitting elements LD. When a gap (or space) exists between the first insulating layer INS1 and the light-emitting element LD before the formation of the second insulating layer INS2, the gap may be filled with the second insulating layer INS2.

[0165] On the first alignment electrode EL1, a first contact electrode CNE1 may be disposed and / or formed to stably electrically and / or physically connect one end of the first alignment electrode EL1 and each of the light-emitting elements LD. On the second alignment electrode EL2, a second contact electrode CNE2 may be disposed and / or formed to stably electrically and / or physically connect the second alignment electrode EL2 and the remaining end of each of the light-emitting elements LD. The first contact electrode CNE1 and the second contact electrode CNE2 may be formed of various transparent conductive materials to allow light emitted from each of the light-emitting elements LD and reflected by the first alignment electrode EL1 and the second alignment electrode EL2 to travel without loss in the image display direction of the display device.

[0166] At the same time, such as Figure 7 and Figure 8 As shown, some of the structures included in the pixel unit PX (or display unit) can be disposed in the non-display area NDA. For example, a portion of the pixel circuit layer PCL, a portion of the display element layer DPL, and the thin film encapsulation layer TFE can be disposed in the non-display area NDA.

[0167] The driver included in the pixel circuit layer PCL and the line unit included in the pixel circuit layer PCL and connecting the driver to the pixel PXL can be located in the non-display area NDA. The driver may include at least one driving transistor SDV_T formed by the same process as the driving transistor Tdr of the pixel unit PX (or display unit). The driving transistor SDV_T may include a semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The line unit may include a signal line SDV_SL connecting the driver and the pixel PXL. Here, the signal line SDV_SL may be a fan-out line.

[0168] Additionally, in the non-display area NDA, a power electrode PWE that receives the voltage of the second pixel power supply ELVSS or the second drive power supply VSS from the outside, and a connection electrode E_CNT connected to the power electrode PWE can be provided. For example... Figure 7 As shown, connecting electrode E_CNT can electrically connect the power supply electrode PWE and the second electrode CE of the light-emitting element LD. Additionally, as... Figure 8 As shown, connecting electrode E_CNT can electrically connect the power supply electrode PWE and the second alignment electrode EL2. Figure 7 As shown, the connecting electrode E_CNT can be formed using the same process as the first electrode AE ​​constituting the light-emitting element LD, and can include the same layer structure and materials as the first electrode AE. However, this disclosure is not limited thereto. According to embodiments, within the range of electrically connecting the power supply electrode PWE and the second electrode CE, the connecting electrode E_CNT can be disposed in the same layer as one of the conductive layers in the pixel circuit layer PCL. According to embodiments, as Figure 8 As shown, the connecting electrode E_CNT can be formed by the same process as the first alignment electrode EL1 and the second alignment electrode EL2, and can include the same layer structure and the same material as the first alignment electrode EL1 and the second alignment electrode EL2.

[0169] The dam unit DAM can be disposed along the edge of the display area DA and can be located between the dummy unit DMP and the pixel unit PX (or display unit) in the non-display area NDA. The dam unit DAM can include a first dam unit DAM1 and a second dam unit DAM2. The second dam unit DAM2 can be disposed outside the first dam unit DAM1. The first dam unit DAM1 can be formed simultaneously with the protective layer PSV included in the pixel circuit layer PCL. The second dam unit DAM2 can include a lower DAMP1 formed simultaneously with the protective layer PSV included in the pixel circuit layer PCL and an upper DAMP2 formed simultaneously with the pixel defining layer PDL included in the display element layer DPL. In the above embodiments, the dam unit DAM is formed simultaneously with the organic insulating layer included in the pixel unit PX (or display unit), but this disclosure is not limited thereto. According to embodiments, the dam unit DAM can be formed simultaneously with at least one insulating layer among the inorganic insulating layers included in the pixel unit PX (or display unit).

[0170] The dam unit DAM can prevent liquid organic material from spilling into the outer region of the substrate SUB during the process of forming an organic layer (e.g., a second encapsulation layer ENC2) included in the thin-film encapsulation layer TFE.

[0171] The dummy element DMP is located outside the dam element DAM and can be disposed along the edge (or outer region) of the base SUB. In embodiments of this disclosure, the dummy element DMP may include a first dummy pattern DMP1 and a second dummy pattern DMP2.

[0172] In embodiments of this disclosure, the first dummy pattern DMP1 may be located in the non-display area NDA between the substrate SUB and the pixel circuit layer PCL. For example, the first dummy pattern DMP1 may be located between the substrate SUB and the buffer layer BFL. The first dummy pattern DMP1 may be disposed along the edge (or outer region) of the substrate SUB and may be superimposed on the edge (or outer region) of the substrate SUB.

[0173] The first dummy pattern DMP1 can be used as an etching stop to prevent the substrate SUB from being over-etched by etching gases during the manufacturing process of the display device DD. For this purpose, the first dummy pattern DMP1 can be formed of a material (or substance) that is less affected by etching gases, so as to prevent a portion of the substrate SUB from being over-etched when the parent substrate is set on a per-cell display panel DP basis by performing a dry etching method. For example, the first dummy pattern DMP1 may include a transparent conductive material (or substance). The transparent conductive material (or substance) may include transparent conductive oxides (TCOs) such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO).

[0174] In embodiments of this disclosure, the second dummy pattern DMP2 may be located between the pixel circuit layer PCL and the thin-film encapsulation layer TFE in the non-display area NDA. The second dummy pattern DMP2 may be disposed on the first dummy pattern DMP1 and surrounding one end of the pixel circuit layer PCL to prevent the end of the pixel circuit layer PCL located in the non-display area NDA from being exposed to the outside. That is, the second dummy pattern DMP2 can serve as a protective member protecting one end of the pixel circuit layer PCL. The second dummy pattern DMP2 can minimize damage to structures disposed on a surface UF (or upper surface) of the substrate SUB (e.g., the buffer layer BFL and the insulating layer disposed on the buffer layer BFL) during the manufacturing process of the display device DD. For this purpose, the second dummy pattern DMP2 may be formed of a material (or substance) that is less affected (or less affected) by the etching gases used in the dry etching process. The second dummy pattern DMP2 may include the same material (or substance) as the first dummy pattern DMP1. For example, the second dummy pattern DMP2 may include a transparent conductive oxide.

[0175] The second dummy pattern DMP2 can be formed using the same process as some of the structures included in the display element layer DPL. For example, as Figure 7 As shown, when the second electrode CE included in the display element layer DPL is composed of a transmission electrode, the second dummy pattern DMP2 can be formed using the same process as the second electrode CE, and can include the same material as the second electrode CE. However, this disclosure is not limited thereto. According to embodiments, the second dummy pattern DMP2 can be formed using a different process than the second electrode CE, and can be disposed on a layer different from the layer of the second electrode CE.

[0176] Additionally, according to the embodiments, such as Figure 8 As shown, the second dummy pattern DMP2 can be formed using the same process as the first contact electrode CNE1 and the second contact electrode CNE2 included in the display element layer DPL, and can include the same material as the first contact electrode CNE1 and the second contact electrode CNE2.

[0177] In both plan and cross-section, the first dummy pattern DMP1 and the second dummy pattern DMP2 can be superimposed on each other. When viewed in cross-section, the first dummy pattern DMP1 and the second dummy pattern DMP2 can extend from edge end A in the non-display area NDA of the substrate SUB along the first direction DR1 and can be located within a range that does not overlap with the dam unit DAM. Here, edge end A of the substrate SUB can be the edge where one surface UF (or upper surface) of the substrate SUB contacts a side surface, which connects one surface UF (or upper surface) and another surface BF (or rear surface). However, this disclosure is not limited thereto, and the positions of the first dummy pattern DMP1 and the second dummy pattern DMP2 can be varied within a range that ensures electrical insulation from the driver disposed in the non-display area NDA.

[0178] Each of the first dummy pattern DMP1 and the second dummy pattern DMP2 can remain electrically isolated from any signal (or voltage) applied from the outside. Furthermore, each of the first dummy pattern DMP1 and the second dummy pattern DMP2 can remain electrically isolated from any signal (or voltage) predetermined in the display device DD to which it is applied.

[0179] In embodiments of this disclosure, the width W2 of the second dummy pattern DMP2 in the first direction DR1 and the width W1 of the first dummy pattern DMP1 in the first direction DR1 may be different from each other. For example, the width W2 of the second dummy pattern DMP2 in the first direction DR1 may be greater than the width W1 of the first dummy pattern DMP1 in the first direction DR1, but this disclosure is not limited thereto. According to an embodiment, conversely, the width W1 of the first dummy pattern DMP1 in the first direction DR1 may be greater than the width W2 of the second dummy pattern DMP2 in the first direction DR1. Additionally, according to an embodiment, the width W2 of the second dummy pattern DMP2 in the first direction DR1 and the width W1 of the first dummy pattern DMP1 in the first direction DR1 may be the same as each other.

[0180] The first dummy pattern DMP1 and the second dummy pattern DMP2 can protrude from the edge end A of the substrate SUB along the first direction DR1 in a direction away from the pixel unit PX (or display unit). For example, the first dummy pattern DMP1 and the second dummy pattern DMP2 can protrude outward from the edge end A of the substrate SUB. That is, the first dummy pattern DMP1 and the second dummy pattern DMP2 can include protrusions that do not overlap with the substrate SUB and face the outside of the substrate SUB. In embodiments of this disclosure, the ends of the protrusions of the first dummy pattern DMP1 and the second dummy pattern DMP2 can coincide with each other. The width d of the protrusion of the first dummy pattern DMP1 in the first direction DR1 and the width d of the protrusion of the second dummy pattern DMP2 in the first direction DR1 can be the same as each other. For example, the width d of each of the first dummy pattern DMP1 and the second dummy pattern DMP2 in the first direction DR1 can be about 0 μm to 5 μm, but this disclosure is not limited thereto. In the above embodiments, the width d of the first dummy pattern DMP1 in the first direction DR1 and the width d of the second dummy pattern DMP2 in the first direction DR1 are the same, but this disclosure is not limited thereto. According to embodiments, the width d of the protrusion of the first dummy pattern DMP1 in the first direction DR1 and the width d of the protrusion of the second dummy pattern DMP2 in the first direction DR1 may be different from each other.

[0181] A portion of the substrate SUB can be removed during the process of manufacturing the mother substrate (not shown) in units of a display panel DP, so that the first dummy pattern DMP1 and the second dummy pattern DMP2 can protrude outward from the edge end A of the substrate SUB.

[0182] A light-blocking layer LBL can be disposed in the non-display area NDA. The light-blocking layer LBL can be disposed between the first dummy pattern DMP1 and the second dummy pattern DMP2. For example, the light-blocking layer LBL can be disposed on the interlayer insulating layer ILD disposed in the pixel circuit layer PCL and located in the non-display area NDA, and can be disposed between the first dummy pattern DMP1 and the second dummy pattern DMP2, but this disclosure is not limited thereto. According to embodiments, the light-blocking layer LBL can be disposed on one of the insulating layers included in the pixel circuit layer PCL and located in the non-display area NDA, or it can be disposed on one of the insulating layers included in the display element layer DPL and located in the non-display area NDA. In embodiments of this disclosure, the light-blocking layer LBL can be a visibility prevention component that prevents the first dummy pattern DMP1 and the second dummy pattern DMP2 from being easily identified by a user. The light-blocking layer LBL can be formed of a material (or substance) having a certain level of dielectric constant and absorbing and / or blocking light. For example, the light-blocking layer LBL can include a black matrix.

[0183] According to an embodiment, when manufacturing a large-area display device DD, display panels DP are manufactured by splicing. In this case, to minimize the distance between adjacent display panels DP, part or all of the drivers located in the non-display area NDA can be located on the other surface BF (or rear surface) of the substrate SUB of the corresponding display panel DP. In this case, part or all of the drivers can be located on an insulating layer (not shown) positioned on the other surface BF (or rear surface) of the substrate SUB, and can be electrically connected to the conductive layer of the pixel circuit layer PCL located on one surface UF (or upper surface) of the substrate SUB through contact holes passing through the substrate SUB and the insulating layer.

[0184] According to the embodiments, such as Figure 9 As shown, the auxiliary layer ADL can be disposed in the non-display area NDA. The auxiliary layer ADL can be disposed and / or formed between the light blocking layer LBL and the second dummy pattern DMP2.

[0185] In embodiments of this disclosure, the auxiliary layer ADL can be a component that diffuses and / or scatters light entering from the outside, thereby additionally preventing the visibility of the first dummy pattern DMP1 and the second dummy pattern DMP2. For example, the auxiliary layer ADL can be formed of a diffuse ink material having a constant level or higher reflectivity. The diffuse ink material can be formed by including, for example, polystyrene (PS) or polymethyl methacrylate (PMMA), a solvent, a polystyrene (PS) or polymethyl methacrylate (PMMA) copolymer, and additives, but this disclosure is not limited thereto. According to embodiments, the auxiliary layer ADL can include a polymer material having light transmittance. For example, the polymer material can include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, and polymethyl methacrylate. However, the material (or substance) of the auxiliary layer ADL is not limited to the embodiments described above and can be selected from various materials (or substances) capable of easily diffused and / or scattered light entering from the outside.

[0186] According to an embodiment, the auxiliary layer ADL may include fine-particle DFPs. In this case, the auxiliary layer ADL may include fine-particle DFPs for light diffusion and / or light scattering dispersed in a medium such as a transparent adhesive. The fine-particle DFPs may be referred to as diffuse particles or scattering particles, etc. The fine-particle DFPs may have a size from tens of nm to several μm, but this disclosure is not limited thereto. The adhesive may include a transparent material such as acrylic, polyurethane, or epoxy resin. Transparent particles or white particles may be used as the fine-particle DFPs.

[0187] Transparent particles can be, for example, transparent organic particles or transparent inorganic particles. For example, organic particles can include acrylic particles of homopolymers or copolymers of methyl methacrylate (MMA), acrylic acid, glycidyl methacrylate, ethyl acrylate (EA), isobutyl acrylate, n-butyl acrylate, and 2-ethylhexyl acrylate; olefin particles (such as polyethylene, polystyrene, and polypropylene); acrylic acid and olefin copolymer particles; or multilayer, multi-component particles formed by forming homopolymer particles and then coating the homopolymer particles with different types of monomers. Inorganic particles can include, for example, precipitated silica, glass beads, and diamond. As white particles, titanium dioxide (TiO2), zinc oxide (ZnO), barium sulfate (BaSO4), calcium carbonate (CaCO3), magnesium carbonate (MgCO3), aluminum hydroxide (Al(OH)3), or clay can be used. Furthermore, as fine-particle DFP, the aforementioned transparent or white particles can be used alone or by mixing two or more of the aforementioned transparent or white particles.

[0188] Although the fine-particle DFPs described above have been shown to have the same size, this disclosure is not limited thereto. According to embodiments, the fine-particle DFPs may have different sizes. Furthermore, although the fine-particle DFPs are shown to be regularly distributed in the auxiliary layer ADL, this disclosure is not limited thereto. According to embodiments, the fine-particle DFPs may be irregularly distributed, such as being biased to one side in the auxiliary layer ADL.

[0189] When light enters the non-display area NDA from the outside, the auxiliary layer ADL can diffuse and / or scatter the light to disperse it in various directions. Therefore, the auxiliary layer ADL, together with the light-blocking layer LBL, can minimize the visibility of the first dummy pattern DMP1 and the second dummy pattern DMP2.

[0190] As described above, according to embodiments of the present disclosure, by setting dummy units (DMPs) along the edge of the substrate SUB, damage to the structure can be prevented by protecting the structure located at the edge of the substrate SUB during the process of setting the mother substrate in units of a display panel (DP) by dry etching.

[0191] Furthermore, according to embodiments of this disclosure, when the mother substrate is set on a unit of a display panel DP, the dry etching method is applied instead of the laser beam cutting method. Since there is no need to ensure additional space for preventing damage caused by the laser beam, the invalid space of the non-display area NDA can be minimized.

[0192] Figures 10a to 10d This is a schematic plan view showing a method of manufacturing a display device according to embodiments of the present disclosure. Figure 11a It is along Figure 10aA sectional view taken from line II-II'. Figure 11b It is along Figure 10b A sectional view taken from line II-II'. Figure 11c It is along Figure 10c A sectional view taken from line II-II'. Figure 11d It is along Figure 10d The sectional view taken from line II-II'.

[0193] In the following text, combined with Figures 10a to 10d as well as Figures 11a to 11d Described in order of manufacturing method Figure 6 and Figure 7 The display panel shown.

[0194] This specification describes the manufacturing steps of the display device performed sequentially according to the plan view and sectional view. However, it will be apparent that, unless the spirit of the disclosure is altered, some steps shown as being performed sequentially may be performed simultaneously, the order of the steps may be changed, some steps may be omitted, or additional steps may be included between the steps.

[0195] Reference Figures 4 to 7 , Figure 10a as well as Figure 11a Prepare the mother substrate MSUB. A carrier substrate (not shown) for supporting the mother substrate MSUB can be provided on the rear surface of the mother substrate MSUB. The mother substrate MSUB and the carrier substrate can be in contact with each other and can be attached to each other by electrostatic force or van der Waals force.

[0196] The mother substrate MSUB may include at least one unit region UNT1 and UNT2. For example, the mother substrate MSUB may include a first unit region UNT1 and a second unit region UNT2. Unit regions UNT1 and UNT2 may be portions corresponding to a separate display panel DP or a separate display device DD, and a separate display panel DP or a separate display device DD may be formed for each of the unit regions UNT1 and UNT2.

[0197] The first unit region UNT1 and the second unit region UNT2 may have the same size (or area) and may be arranged in a matrix form within the parent substrate MSUB, but this disclosure is not limited thereto. According to embodiments, the first unit region UNT1 and the second unit region UNT2 may have different sizes (or areas) within the parent substrate MSUB and may be arranged in various shapes depending on the size (or area) of the parent substrate MSUB. In embodiments of this disclosure, each of the first unit region UNT1 and the second unit region UNT2 may include a display area DA and a non-display area NDA.

[0198] The first unit region UNT1 and the second unit region UNT2 can be divided by a virtual line VL extending in the second direction DR2. The virtual line VL can divide a unit region UNT1 or UNT2 in a shape surrounding each of the first unit region UNT1 and the second unit region UNT2. In embodiments of this disclosure, the virtual line VL can be located between the first unit region UNT1 and the second unit region UNT2. Therefore, at least one side of the first unit region UNT1 can contact the second unit region UNT2, and the virtual line VL is positioned between the first unit region UNT1 and the second unit region UNT2. The mother substrate MSUB can be configured as a plurality of separate display panels DP along the virtual line VL.

[0199] The first unit region UNT1 and the second unit region UNT2, which are adjacent to each other, may be in contact with each other or may be spaced apart from each other. In the accompanying drawings, the first unit region UNT1 and the second unit region UNT2, which are adjacent to each other, are in contact with each other, and a virtual line VL is placed between them, but this disclosure is not limited thereto. According to an embodiment, the first unit region UNT1 and the second unit region UNT2, which are spaced apart from each other, may be divided by two or more virtual lines VL.

[0200] A first dummy pattern DMP1 is formed on one surface of the aforementioned mother substrate MSUB. The first dummy pattern DMP1 can be formed using a photolithography process with a mask, and the first dummy pattern DMP1 can be located in the non-display area NDA of each of the first unit region UNT1 and the second unit region UNT2.

[0201] Reference Figures 4 to 7 , Figure 10b as well as Figure 11b A pixel unit PX (or display unit), a driver, a circuit unit, a dam unit DAM, a light blocking layer LBL, and a second dummy pattern DMP2 are formed on a mother substrate MSUB on which a first dummy pattern DMP1 is disposed. The pixel unit PX (or display unit) may include multiple pixels PXL disposed in the display area DA in the first unit area UNT1 and the second unit area UNT2, and a thin-film encapsulation layer TFE covering the pixels PXL. The thin-film encapsulation layer TFE may be an encapsulation substrate covering the pixels PXL, the driver, the dam unit DAM, the light blocking layer LBL, and the second dummy pattern DMP2. When the thin-film encapsulation layer TFE is an encapsulation substrate, the mother substrate MSUB may be a lower substrate, and the thin-film encapsulation layer TFE may be an upper substrate.

[0202] Each of the pixels PXL may include a pixel circuit layer PCL disposed on a substrate SUB and a display element layer DPL disposed on the pixel circuit layer PCL. Pixels PXL and the like can be formed by various processes, for example, multiple depositions and / or photolithography can be used to form pixels PXL and the like.

[0203] Here, the second dummy pattern DMP2 can be positioned in the non-display area NDA of each of the first unit region UNT1 and the second unit region UNT2, and the second dummy pattern DMP2 can be formed along the edge of the mother substrate MSUB. Alternatively, the second dummy pattern DMP2 can be formed in the non-display area NDA between the first unit region UNT1 and the second unit region UNT2 based on a virtual line VL. When viewed in plan and section, the virtual line VL can be positioned between the first unit region UNT1 and the second unit region UNT2, bisecting the location of the second dummy pattern DMP2 in the non-display area NDA. One side and the other side of the second dummy pattern DMP2 bisected by the virtual line VL can be included in adjacent unit regions UNT1 and UNT2, respectively. For example, one side of the second dummy pattern DMP2 can be included in the first unit region UNT1, while the other side of the second dummy pattern DMP2 can be included in the second unit region UNT2.

[0204] When viewed in plan and cross-section, the second dummy pattern DMP2 can be superimposed on the first dummy pattern DMP1. In embodiments of this disclosure, the second dummy pattern DMP2 can be formed of a transparent conductive oxide and can be manufactured in the same process as the partial construction process of the pixel unit PX (or display unit). For example, the second dummy pattern DMP2 can be manufactured in the same process as the second electrode CE of the display element layer DPL, and the second dummy pattern DMP2 can include the same material as the second electrode CE. However, this disclosure is not limited thereto; according to embodiments, the second dummy pattern DMP2 can be formed in a separate step different from the steps of constructing the display element layer DPL.

[0205] The second dummy pattern DMP2 can be configured in a shape that surrounds a portion of the non-display area NDA located in each of the first unit region UNT1 and the second unit region UNT2. For example, the second dummy pattern DMP2 can be configured in a shape that surrounds one end of the pixel circuit layer PCL located in the non-display area NDA.

[0206] Reference Figures 4 to 7 , Figure 10c as well as Figure 11cAfter removing the carrier substrate from the rear surface of the mother substrate MSUB, a portion of the mother substrate MSUB is removed by performing a dry etching process in a vacuum chamber. At this time, the rear surface of the mother substrate MSUB can be the surface of the etched object, and one area corresponding to the display area DA of each of the first unit region UNT1 and the second unit region UNT2 can be covered by a mask.

[0207] Because the first dummy pattern DMP1 and the second dummy pattern DMP2 are positioned along the edge of the mother substrate MSUB, and the second dummy pattern DMP2 surrounds a portion of the structure located on the upper surface of the mother substrate MSUB, damage to this portion of the structure by the etching gas used in the dry etching process can be prevented. Furthermore, because the first dummy pattern DMP1, formed of a transparent conductive oxide less affected by the etching gas, is located directly on the upper surface of the mother substrate MSUB, over-etching of the mother substrate MSUB by the etching gas can be prevented.

[0208] A substrate SUB can be configured such that a portion of the parent substrate MSUB has been removed from it using an etching gas employed in a dry etching process. In this case, the substrate SUB, from which a portion has been removed by the aforementioned process, can have a side surface with an inverted conical shape. For example, the width of the substrate SUB can extend along a first direction DR1 from the top surface (refer to...). Figure 7 The “UF”) to the rear surface (refer to) Figure 7 The “BF” narrows. The substrate SUB can be the substrate of each of the first unit region UNT1 and the second unit region UNT2, and can have a reference. Figure 4 and Figure 7 The described base SUB has the same construction. As described above, when a portion of the parent base SUB is removed, the first dummy pattern DMP1 and the second dummy pattern DMP2 can be obtained from the edge end of the base SUB (refer to...). Figure 7 The “A” protrudes along the first direction DR1.

[0209] Reference Figures 4 to 7 , Figure 10d as well as Figure 11d The first dummy pattern DMP1 and the second dummy pattern DMP2, positioned adjacent to the dummy line VL, can be based on the dummy line (refer to...). Figure 10c The “VL” is separated, so a separate display panel DP can be set.

[0210] Figure 12 According to another embodiment Figure 6 The implementation method of the third encapsulation layer shown is similar to Figure 4 The sectional view corresponding to line I-I' Figure 13 Is with Figure 4The sectional view corresponding to line I-I' shows more details. Figure 12 This is an area of ​​the display panel shown.

[0211] about Figure 12 and Figure 13 The display panel described herein primarily focuses on details that differ from those in the above embodiments to avoid repetition. Parts not specifically described in this disclosure are consistent with the above embodiments, and the same reference numerals indicate the same components, and similar reference numerals indicate similar components.

[0212] Reference Figures 1 to 4 , Figure 12 as well as Figure 13 The display panel DP may include a substrate SUB, pixel units PX (or display units), a thin-film encapsulation layer TFE, dummy units DMP, and dam units DAM. The pixel unit PX (or display unit) may include pixels PXL disposed in the display area DA and a thin-film encapsulation layer TFE covering the pixels PXL. The pixel unit PX (or display unit) may include a pixel circuit layer PCL disposed on the substrate SUB, a display element layer DPL disposed on the pixel circuit layer PCL, and a thin-film encapsulation layer TFE disposed on the display element layer DPL.

[0213] In embodiments of this disclosure, the display element layer DPL may include at least one light-emitting element LD formed of an organic light-emitting diode. According to embodiments, the display element layer DPL may include at least one light-emitting element LD, the light-emitting element LD being as small as micrometers or nanometers, wherein... Figure 5b and Figure 8 The diagram shows an inorganic light-emitting diode formed by growing a nitride-based semiconductor structure. In this case, the display element layer DPL may further include a first dam pattern and a second dam pattern (see reference). Figure 8 (refer to "BNK1 and BNK2"), first alignment electrode and second alignment electrode (see reference) Figure 8 (EL1 and EL2), first insulating layer and second insulating layer (refer to) Figure 8 (INS1 and INS2) and the first contact electrode and the second contact electrode (refer to) Figure 8 (CNE1 and CNE2).

[0214] The dummy unit DMP may include a first dummy pattern DMP1 and a second dummy pattern DMP2 disposed in the non-display area NDA. The first dummy pattern DMP1 may be disposed on a surface UF (or upper surface) of the substrate SUB and may protrude from the edge A of the substrate SUB along a first direction DR1 in a direction away from the pixel unit PX (or display unit). The second dummy pattern DMP2 may be disposed on the light-blocking layer LBL and may cover the side surfaces of some components located on the upper surface of the substrate SUB. Similar to the first dummy pattern DMP1, the second dummy pattern DMP2 may protrude from the edge A of the substrate SUB along the first direction DR1 in a direction away from the pixel unit PX (or display unit).

[0215] An insulating layer INS may be disposed and / or formed on the second dummy pattern DMP2. The insulating layer INS prevents the second dummy pattern DMP2, formed of a transparent conductive oxide, from being exposed to the outside, thereby protecting the second dummy pattern DMP2. The insulating layer INS may be an inorganic insulating layer comprising inorganic materials. The insulating layer INS may include, for example, silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiON) and aluminum oxide (AlO) x At least one of the inorganic materials. In embodiments of this disclosure, the insulating layer INS may be integrally formed with a portion of the thin-film encapsulation layer TFE. For example, the insulating layer INS may be formed from an inorganic layer in the thin-film encapsulation layer TFE and may be integrally formed with the third encapsulation layer ENC3 corresponding to the uppermost (or outermost) layer of the display panel DP. However, this disclosure is not limited thereto. According to an embodiment, when the first encapsulation layer ENC1 formed from an inorganic layer in the thin-film encapsulation layer TFE is set to extend to the edge end A of the substrate SUB, the insulating layer INS may be integrally formed with the first encapsulation layer ENC1.

[0216] In the above embodiments, the insulating layer INS disposed on the second dummy pattern DMP2 is partially integrally disposed with the thin film encapsulation layer TFE, but this disclosure is not limited thereto. According to embodiments, the insulating layer INS may be disposed non-integrally with the thin film encapsulation layer TFE.

[0217] Figure 14 This illustrates a different embodiment. Figure 4 A schematic plan view of the display panel shown. Figure 15 It is along Figure 14 The sectional view taken from line III-III'.

[0218] about Figure 14 and Figure 15 The display panel is described in detail, which differs from the details of the above embodiments, to avoid repetition.

[0219] Reference Figures 1 to 3 , Figure 14 as well as Figure 15 The display panel DP may include dummy units DMP positioned along the edge of the substrate SUB. The dummy units DMP may be located in the non-display area NDA of the substrate SUB. The dummy units DMP may have a shape that forms a closed loop along the edge of the substrate SUB when viewed in a plane.

[0220] The dummy unit DMP may include a first dummy pattern DMP1 and a second dummy pattern DMP2. The first dummy pattern DMP1 and the second dummy pattern DMP2 may have the same planar shape and be stacked on top of each other. The width W3 of the first dummy pattern DMP1 in the first direction DR1 and the width W3 of the second dummy pattern DMP2 in the first direction DR1 may be the same as each other. Additionally, the width W4 of the first dummy pattern DMP1 in the second direction DR2 and the width W4 of the second dummy pattern DMP2 in the second direction DR2 may be the same as each other, but this disclosure is not limited thereto. According to an embodiment, the width W3 of each of the first dummy pattern DMP1 and the second dummy pattern DMP2 in the first direction DR1 may be greater than (or wider than) the width W4 of each of the first dummy pattern DMP1 and the second dummy pattern DMP2 in the second direction DR2, and vice versa.

[0221] The aforementioned display device DD may include a touch sensor between the display panel DP and the window WD. Hereinafter, a display device DD including a touch sensor is described.

[0222] Figure 16 This illustrates a different embodiment. Figure 1 A schematic cross-sectional view of the display device. Figure 17 yes Figure 16 A schematic cross-sectional view of the touch sensor.

[0223] about Figure 16 and Figure 17 This disclosure describes a display device, primarily focusing on details that differ from those in the above embodiments to avoid repetition. Parts not specifically described in this disclosure are consistent with the above embodiments; the same reference numerals indicate the same components, and similar reference numerals indicate similar components.

[0224] Reference Figure 1 , Figure 16 and Figure 17The display device DD may include a display module DM and a window WD. The display module DM may include a display panel DP and a touch sensor TS. The display panel DP may have a reference... Figures 2 to 7 The described display panel DP has the same construction. The window WD can have the same construction as the referenced one. Figure 2 The window WD described has the same construction and can be bonded to the display module DM using an optically transparent adhesive (or bonding) component OCA.

[0225] A touch sensor TS can be directly disposed on a surface on which an image of a display panel DP is displayed to receive touch input and / or hover input from a user. The touch sensor TS can sense touch capacitance through contact and / or proximity of a separate input tool (such as a user's hand or a similar conductor) to identify touch input and / or hover input from the display device DD. Here, touch input can mean a direct touch (or contact) by a user's hand or a separate input tool, and hover input can mean that a user's hand or a separate input tool is near the display device DD including the touch sensor TS but does not touch the display device DD. Additionally, the touch sensor TS can sense user touch operations and, in response to a touch operation, move an object displayed on the display device DD from its initial display position to another position. Here, touch operations can include at least one of a single touch, multiple touches, and touch gestures. For example, various touch operations can exist, including specific gestures (such as zooming in or out of text or an image by moving a predetermined distance while the user's finger is touching the touch surface of the touch sensor TS).

[0226] The touch sensor TS can have a multi-layer structure. The touch sensor TS may include at least one conductive layer and at least one insulating layer.

[0227] The touch sensor TS may include a substrate layer BSL, a first conductive pattern CP1, a first touch insulating layer TS_INS1, a second conductive pattern CP2, and a second touch insulating layer TS_INS2.

[0228] The first conductive pattern CP1 can be directly disposed on the thin-film encapsulation layer TFE of the display panel DP, but this disclosure is not limited thereto. According to an embodiment, another insulating layer (e.g., a substrate layer BSL) can be disposed between the first conductive pattern CP1 and the thin-film encapsulation layer TFE. In this case, the first conductive pattern CP1 can be directly disposed on the substrate layer BSL.

[0229] Each of the first conductive pattern CP1 and the second conductive pattern CP2 may have a monolayer structure or a multilayer structure stacked in the thickness direction (e.g., the third direction DR3). The monolayer conductive pattern may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), and alloys thereof. The transparent conductive layer may be a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). Alternatively, the transparent conductive layer may include PEDOT, metal nanowires, and graphene.

[0230] The conductive pattern of the multilayer structure may include multiple metal layers. The multiple metal layers may have a triple structure, such as titanium (Ti) / aluminum (Al) / titanium (Ti), but are not limited to this. The conductive pattern of the multilayer structure may include a transparent conductive layer and multiple metal layers.

[0231] In embodiments of this disclosure, each of the first conductive pattern CP1 and the second conductive pattern CP2 may include a sensor pattern and a sensing line.

[0232] Each of the first touch insulating layer TS_INS1 and the second touch insulating layer TS_INS2 may include an inorganic insulating layer containing inorganic materials or an organic insulating layer containing organic materials. The inorganic insulating layer may include, for example, silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiON) and aluminum oxide (AlO) x The organic insulating layer may include at least one of the following inorganic materials: acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0233] Figure 18 yes Figure 16 A schematic plan view of the touch sensor. Figure 19a It is shown schematically. Figure 18 Enlarged plan view of some EA examples, Figure 19b It is along Figure 19a A cross-sectional view of line V-V'.

[0234] Reference Figure 1 as well as Figures 16 to 19b The touch sensor TS may include a substrate layer BSL, which includes a sensing area SA capable of sensing touch input and a non-sensing area NSA surrounding at least a portion of the sensing area SA.

[0235] The substrate layer (BSL) can be formed from tempered glass, transparent plastic, or a transparent film. According to an embodiment, the substrate layer (BSL) can be omitted.

[0236] The sensing area SA can be disposed in the central region of the substrate layer BSL to overlap with the display area DA of the display panel DP. The sensing area SA can be disposed in a shape substantially the same as that of the display area DA, but this disclosure is not limited thereto. Sensor electrodes for sensing touch input can be disposed and / or formed in the sensing area SA.

[0237] The non-sensing area (NSA) can be disposed in the peripheral region of the substrate layer (BSL) to be superimposed on the non-display area (NDA) of the display panel (DP). Here, the peripheral region can be the area surrounding the central region of the substrate layer (BSL). Sensing lines (SL) electrically connected to sensor electrodes for receiving and transmitting sensing signals are disposed and / or formed in the non-sensing area (NSA). Additionally, pad units (PDA) connected to the sensing lines (SL) and electrically connected to the sensor electrodes of the sensing area (SA) can be disposed in the non-sensing area (NSA). The pad units (PDA) can include multiple pads (PD). The sensing lines (SL) can include multiple first sensing lines (SL1) and multiple second sensing lines (SL2).

[0238] The sensor electrode may include multiple sensor patterns SP, a first bridging pattern BRP1, and a second bridging pattern BRP2.

[0239] The sensor pattern SP may include a plurality of first sensor patterns SP1 and a plurality of second sensor patterns SP2 that are electrically insulated from the first sensor patterns SP1.

[0240] A first sensor pattern SP1 can be arranged on a first direction DR1 and electrically connected to an adjacent first sensor pattern SP1 via a first bridging pattern BRP1 to construct at least one sensor row. A second sensor pattern SP2 can be arranged on a second direction DR2 that intersects the first direction DR1 and electrically connected to an adjacent second sensor pattern SP2 via a second bridging pattern BRP2 to construct at least one sensor column.

[0241] Each of the first sensor pattern SP1 and the second sensor pattern SP2 can be electrically connected to a pad PD via a corresponding sensing line SL. For example, each of the first sensor patterns SP1 can be electrically connected to a pad PD via each first sensing line SL1, and each of the second sensor patterns SP2 can be electrically connected to a pad PD via each second sensing line SL2.

[0242] The first sensor pattern SP1 described above can be a driving electrode that receives a driving signal for detecting a touch position within the sensing area SA, and the second sensor pattern SP2 can be a sensing electrode that outputs a sensing signal for detecting a touch position within the sensing area SA. However, this disclosure is not limited thereto; the first sensor pattern SP1 can be a sensing electrode, and the second sensor pattern SP2 can be a driving electrode.

[0243] In embodiments of this disclosure, the touch sensor TS can identify a user's touch by sensing the change in mutual capacitance formed between the first sensor pattern SP1 and the second sensor pattern SP2.

[0244] In embodiments of this disclosure, each of the first sensor pattern SP1 and the second sensor pattern SP2 may have a mesh structure comprising multiple conductive fine lines.

[0245] Each of the first bridging patterns BRP1 is used for electrical connection to the first sensor pattern SP1 arranged parallel to the first direction DR1. Each of the first bridging patterns BRP1 may also be arranged in a form that extends along the first direction DR1.

[0246] Each of the second bridging patterns BRP2 is used for electrical connection to the second sensor pattern SP2 arranged parallel to the second direction DR2. Each of the second bridging patterns BRP2 may also be arranged in a form extending along the second direction DR2. In embodiments of this disclosure, each of the second bridging patterns BRP2 may be integrally arranged with the second sensor pattern SP2. When each of the second bridging patterns BRP2 is integrally arranged with the second sensor pattern SP2, the second bridging pattern BRP2 may be a region of the second sensor pattern SP2.

[0247] The touch sensor TS may include a first conductive pattern CP1 disposed on a substrate layer BSL, a first touch insulating layer TS_INS1 disposed on the first conductive pattern CP1, a second conductive pattern CP2 disposed on the first touch insulating layer TS_INS1, and a second touch insulating layer TS_INS2 disposed on the second conductive pattern CP2.

[0248] The first bridging pattern BRP1 disposed in the sensing area SA may be included in the first conductive pattern CP1, and the first sensor pattern SP1, the second sensor pattern SP2, and the second bridging pattern BRP2 may be included in the second conductive pattern CP2. Additionally, a portion of the sensing line SL disposed in the non-sensing area NSA may be included in the first conductive pattern CP1, while the remaining portion of the sensing line SL may be included in the second conductive pattern CP2. In this case, adjacent first sensor patterns SP1 in the first direction DR1 can be electrically and / or physically connected to each other through the first bridging pattern BRP1 and the contact hole CNT passing through the first touch insulating layer TS_INS1.

[0249] In the above embodiments, an example is described in which the first bridging pattern BRP1 is included in the first conductive pattern CP1, and the first sensor pattern SP1, the second sensor pattern SP2, and the second bridging pattern BRP2 are included in the second conductive pattern CP2; however, this disclosure is not limited thereto. According to embodiments, the first sensor pattern SP1, the second sensor pattern SP2, and the second bridging pattern BRP2 may be included in the first conductive pattern CP1, and the first bridging pattern BRP1 may be included in the second conductive pattern CP2.

[0250] Furthermore, in the above embodiments, an example was described in which the first conductive pattern CP1 is disposed on the substrate layer BSL and the second conductive pattern CP2 is disposed on the first touch insulating layer TS_INS1, but this disclosure is not limited thereto. According to the embodiments, the first conductive pattern CP1 may be disposed on the first touch insulating layer TS_INS1, and the second conductive pattern CP2 may be disposed on the substrate layer BSL.

[0251] Furthermore, in the above embodiments, an example was described in which the first sensor pattern SP1 and the second sensor pattern SP2 are disposed on the same layer, but this disclosure is not limited thereto. According to embodiments, the first sensor pattern SP1 and the second sensor pattern SP2 may be disposed on different layers.

[0252] Sensor electrodes disposed and / or formed in the sensing area SA may include dummy sensing electrodes (not shown) spaced apart from each other between the first sensor pattern SP1 and the second sensor pattern SP2. The dummy sensing electrodes may be floating electrodes and may not be electrically connected to the first sensor pattern SP1 and the second sensor pattern SP2. Because the dummy sensing electrodes are disposed in the sensing area SA, the boundary region between the first sensor pattern SP1 and the second sensor pattern SP2 is not visually discernible. Furthermore, the edge effect between the first sensor pattern SP1 and the second sensor pattern SP2 can be controlled by adjusting the width and thickness of the dummy sensing electrodes, thereby optimizing the capacitance between the first sensor pattern SP1 and the second sensor pattern SP2.

[0253] like Figure 18 and Figure 19a As shown, the touch sensor TS can be formed by a repeating arrangement of unit sensor blocks USB. The unit sensor block USB can be a dummy unit block having a predetermined region, which includes at least a portion of the sensor patterns SP adjacent in the first direction DR1 and adjacent in the second direction DR2 within the corresponding sensing region SA. Such a unit sensor block USB can be understood as corresponding to the smallest repeating unit of the arrangement of sensor patterns SP in the corresponding sensing region SA.

[0254] Each of the first sensing lines SL1 can be connected to a sensor row formed by a plurality of first sensor patterns SP1 arranged along the first direction DR1. Each of the second sensing lines SL2 can be connected to a sensor column formed by a plurality of second sensor patterns SP2 arranged along the second direction DR2.

[0255] Figure 20 It is along Figure 18 A sectional view taken from line IV-IV'. Figure 21 It is along Figure 18 A sectional view taken along line IV-IV', which shows more detail Figure 20 One area of ​​the display device shown. Figure 22 It is along Figure 18 A cross-sectional view taken along line IV-IV', which shows a different embodiment. Figure 21 The second dummy pattern and insulating layer.

[0256] about Figures 20 to 22 This disclosure describes a display device, primarily focusing on details that differ from those in the above embodiments to avoid repetition. Parts not specifically described in this disclosure are consistent with the above embodiments; the same reference numerals indicate the same components, and similar reference numerals indicate similar components.

[0257] Reference Figure 1 as well as Figures 16 to 22 The display device DD may include a display panel DP and a touch sensor TS.

[0258] The display panel DP may include a substrate SUB, pixel units PX (or display units), a thin-film encapsulation layer TFE, dummy units DMP, a light-blocking layer LBL, and a dam unit DAM. The pixel unit PX (or display unit) may include pixels PXL disposed in the display area DA and a thin-film encapsulation layer TFE covering the pixels PXL.

[0259] The touch sensor TS may include a substrate layer BSL, sensor electrodes, sensing lines SL, a first touch insulating layer TS_INS1, and a second touch insulating layer TS_INS2. The sensor electrodes may include multiple first bridging patterns BRP1, multiple sensor patterns SP, and multiple second bridging patterns BRP2. The multiple first bridging patterns BRP1 are included in a first conductive pattern CP1, and the multiple sensor patterns SP and multiple second bridging patterns BRP2 are included in a second conductive pattern CP2. Here, the sensor pattern SP may include multiple electrically isolated first sensor patterns SP1 and multiple second sensor patterns SP2. The sensing line SL may include a first metal layer MTL1 and a second metal layer MTL2. The first metal layer MTL1 is included in the first conductive pattern CP1, and the second metal layer MTL2 is included in the second conductive pattern CP2. The first metal layer MTL1 and the second metal layer MTL2 can be electrically connected to each other through contact holes passing through the first touch insulating layer TS_INS1.

[0260] The dummy unit DMP may include a first dummy pattern DMP1 and a second dummy pattern DMP2 disposed in the non-display area NDA. The second dummy pattern DMP2 may be disposed on the light blocking layer LBL and may cover some of the side surfaces of the structure located on the upper surface of the substrate SUB.

[0261] An insulating layer INS can be disposed and / or formed on the second dummy pattern DMP2. The insulating layer INS can be an inorganic insulating layer comprising inorganic materials. The insulating layer INS can be integrally disposed with the substrate layer BSL included in the touch sensor TS, or it can be formed from an inorganic layer in the thin-film encapsulation layer TFE and can be integrally disposed with the third encapsulation layer ENC3 corresponding to the uppermost (or outermost) layer of the display panel DP. In this case, the second dummy pattern DMP2 can be formed in the same process as the partial construction process of the display element layer DPL. For example, when the first electrode AE ​​included in the display element layer DPL is a transmission electrode formed of transparent conductive oxide, the second dummy pattern DMP2 can be formed in the same process as the first electrode AE. Additionally, when the second electrode CE included in the display element layer DPL is a transmission electrode formed of transparent conductive oxide, the second dummy pattern DMP2 can be formed in the same process as the second electrode CE.

[0262] In the above embodiments, the insulating layer INS is integrally disposed with a portion of the thin-film encapsulation layer TFE (e.g., the third encapsulation layer ENC3), or integrally disposed with the substrate layer BSL, which is a portion of the touch sensor TS; however, this disclosure is not limited thereto. According to embodiments, the insulating layer INS may be integrally disposed with another insulating layer included in the touch sensor TS. For example, as... Figure 22 As shown, the insulating layer INS can be integrally formed with the first touch insulating layer TS_INS1. In this case, the second dummy pattern DMP2 can be formed in the same process as the process for partially constructing the touch sensor TS. For example, the second dummy pattern DMP2 can be formed in the same process as the process for the second metal layer MTL2 of each sensing line SL and each second sensor pattern SP2.

[0263] In the accompanying drawings, the second touch insulating layer TS_INS2 does not cover a portion of the insulating layer INS, but this disclosure is not limited thereto. According to an embodiment, the second touch insulating layer TS_INS2 may completely cover the insulating layer INS.

[0264] According to this embodiment, by setting dummy units (DMPs) along the edge of the substrate SUB, a display device with improved reliability can be achieved by protecting the structure set on the substrate SUB during the process of setting the mother substrate in units of individual display panels (DPs) using a dry etching method.

[0265] Additionally, according to embodiments of this disclosure, a display device can be provided that minimizes the invalid space of the non-display area NDA.

[0266] Although this disclosure has been described with reference to the preferred embodiments described above, it will be understood by those skilled in the art or those with common knowledge in the art that various modifications and changes can be made to this disclosure without departing from the spirit and technical field of the disclosure described in the claims.

[0267] Therefore, the technical scope of this disclosure should not be limited to the content described in the specific embodiments of the specification, but should be defined by the claims.

Claims

1. A display device, the display device comprising: The substrate includes both the display area and the non-display area; A pixel circuit layer is disposed on a first surface of the substrate and includes at least one transistor; A display element layer is disposed on the pixel circuit layer and includes light-emitting elements; A thin-film encapsulation layer is disposed on the display element layer; as well as A dummy unit is disposed in the non-display area and on the edge of the substrate. The dummy unit comprises a transparent conductive material and protrudes from the edge of the substrate in a direction away from the display element layer.

2. The display device according to claim 1, wherein, The virtual unit includes: A first dummy pattern is disposed on the first surface of the substrate; and The second dummy pattern is placed on top of the first dummy pattern.

3. The display device according to claim 2, wherein, The first dummy pattern is an etch stop.

4. The display device according to claim 2, wherein, The pixel circuit layer further includes a buffer layer disposed on the substrate and at least one insulating layer disposed on the buffer layer, wherein the at least one transistor is disposed on the buffer layer, and The second dummy pattern covers at least a portion of the buffer layer and at least a portion of the insulating layer.

5. The display device according to claim 2, wherein, At least a portion of the first dummy pattern and at least a portion of the second dummy pattern are superimposed on each other in a plane and in a cross section.

6. The display device according to claim 2, wherein, The first dummy pattern and the second dummy pattern have the same or different planar shapes.

7. The display device according to claim 6, wherein, The second dummy pattern is positioned closer to the display area from the edge of the substrate than the first dummy pattern.

8. The display device according to claim 6, wherein, The width of the first dummy pattern and the width of the second dummy pattern are the same or different from each other on the plane.

9. The display device according to claim 2, further comprising: At least one dam unit is disposed in the non-display area of ​​the substrate. The first dummy pattern and the second dummy pattern are located between the edge of the substrate and the dam unit.

10. The display device according to claim 9, further comprising: A light-blocking layer is disposed in the non-display area between the first dummy pattern and the second dummy pattern.

11. The display device according to claim 10, wherein, The light-blocking layer covers the dam unit.

12. The display device according to claim 10, further comprising: An auxiliary layer is disposed between the light-blocking layer and the second dummy pattern.

13. The display device according to claim 12, wherein, The second dummy pattern covers at least a portion of the auxiliary layer.

14. The display device according to claim 12, wherein, The auxiliary layer is a light-diffusing layer that includes scattering particles.

15. The display device according to claim 2, wherein, The thin-film encapsulation layer includes: A first encapsulation layer is disposed on the display element layer; A second encapsulation layer is disposed on the first encapsulation layer; A third encapsulation layer is disposed on the second encapsulation layer, and The second encapsulation layer is an organic insulating layer, while the first encapsulation layer and the third encapsulation layer are inorganic insulating layers.

16. The display device according to claim 15, wherein, The third encapsulation layer covers at least a portion of the second dummy pattern.

17. The display device according to claim 2, wherein, The light-emitting element includes: The first electrode is electrically connected to the at least one transistor; An emitter layer is disposed on the first electrode; and The second electrode is disposed on the emission layer, and The second dummy pattern is disposed on the same layer as the second electrode and includes the same material as the second electrode.

18. The display device according to claim 2, wherein, The light-emitting element includes: The first semiconductor layer is doped with a first conductive dopant; The second semiconductor layer is doped with a second conductive dopant; and An active layer is disposed between the first semiconductor layer and the second semiconductor layer.

19. The display device according to claim 2, further comprising: A touch sensor is disposed on the thin-film encapsulation layer. The touch sensor includes: a substrate layer disposed on the display element layer; a first conductive pattern disposed on the substrate layer; a first touch insulating layer disposed on the first conductive pattern; a second conductive pattern disposed on the first touch insulating layer; and a second touch insulating layer disposed on the second conductive pattern. The substrate layer is disposed on the second dummy pattern to cover at least a portion of the second dummy pattern.

20. The display device according to claim 2, wherein, The first dummy pattern and the second dummy pattern protrude from the edge of the substrate in a direction away from the display element layer.

21. The display device according to claim 2, wherein, At least a portion of the first dummy pattern and at least a portion of the second dummy pattern are in contact with each other.

22. The display device according to claim 2, wherein, The substrate includes a first surface on which the dummy unit is disposed and a second surface opposite to the first surface, and The width of the substrate decreases along one direction from the first surface toward the second surface.

23. A method of manufacturing a display device, the method comprising: Prepare a parent substrate with at least two unit regions; A first dummy pattern is formed at the edge of the unit region; A pixel unit is formed in each of the unit regions, and a second dummy pattern is formed that overlaps with the first dummy pattern; A thin film encapsulation layer is formed on the pixel unit and the second dummy pattern; as well as A portion of the mother substrate is removed by performing a dry etching process, thereby setting the mother substrate on a display panel unit basis, and After the dry etching process, the first dummy pattern and the second dummy pattern protrude from the edge in a direction away from the display panel.

24. The method according to claim 23, wherein, The first dummy pattern and the second dummy pattern are superimposed on each other and include transparent conductive oxide.

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