Display substrate and display device

Abstract

A display substrate and a display device. The display substrate (100) comprises a first display area (110); a second display area (120) located on one side of the first display area (110) in a first direction X; and a transition area (130) located between the first display area (110) and the second display area (120). The first display area (110), the second display area (120) and the transition area (130) are provided with a plurality of pixels (210). The plurality of pixels (210) are arranged in an array along the first direction X and a second direction Y intersecting the first direction X. The pixel density of the first display area (110) is greater than the pixel density of the second display area (120) and the pixel density of the transition area (130). The transition area (130) is further provided with a row driving circuit (220). The row driving circuit (220) is configured to drive the plurality of pixels (210) in the first display area (110), the second display area (120) and the transition area (130) in rows. Thus, the display substrate (100) is provided with a transition area (130) between the first display area (110) and the second display area (120), and a row driving circuit (220) is provided in the transition area (130), so as to drive the first display area (110) and the second display area (120) on both sides of the transition area (130) to display.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, flexible display technology has been widely used in various display devices due to its advantages such as low power consumption, small size, portability, and diverse display modes. In order to improve the display quality and usage effect, the four-curved screen design has been widely used in smart electronic products such as mobile phones and tablets. The four-curved screen design combines the 3D glass cover (Cover Glass) bonding technology to bend the edges or corners of the display substrate according to a certain bending radius and form an arc to achieve a full three-dimensional display of the front and side, thereby achieving a 3D three-dimensional effect of the four-curved form, thereby creating a three-dimensional display immersion, which is in line with the future technology development trend. Summary of the invention

[0003] The embodiment of the present disclosure provides a display substrate and a display device. The display substrate provides a GIP (Gate in Pixel) design, that is, the display substrate sets a transition area in a high pixel density area and a low pixel density area, and sets a row driving circuit, such as a gate driving circuit (GOA), in the transition area, so as to drive the high pixel density area and the low pixel density area on both sides of the transition area for display.

[0004] At least one embodiment of the present disclosure provides a display substrate, comprising: a first display area; a second display area located on at least one side of the first display area in a first direction; and a transition area located between the first display area and the second display area, wherein the first display area, the second display area and the transition area are provided with a plurality of pixels, and the plurality of pixels are arranged in an array along the first direction and a second direction intersecting the first direction, the pixel density of the first display area is greater than the pixel density of the second display area and the pixel density of the transition area, and the transition area is further provided with a row driving circuit, and the row driving circuit is configured to drive the plurality of pixels in the first display area, the second display area and the transition area by row.

[0005] For example, in a display substrate provided in an embodiment of the present disclosure, the row driving circuit includes a plurality of row driving circuit units arranged along the second direction.

[0006] For example, in a display substrate provided in an embodiment of the present disclosure, each of the pixels includes a plurality of sub-pixels, each of the sub-pixels includes a pixel driving circuit and a driving electrode electrically connected to the pixel driving circuit, and the transition region includes: a plurality of pixel circuit islands, each of the pixel circuit islands is provided with a plurality of pixel driving circuits of at least one of the pixels; a plurality of first spacing regions, each of the first spacing regions is located between two adjacent pixel circuit islands in the first direction; and at least one driving spacing region, each of the driving spacing regions is also located between two adjacent pixel circuit islands in the first direction, and the driving spacing region is provided with the row driving circuit unit.

[0007] For example, in a display substrate provided in an embodiment of the present disclosure, the transition region also includes: a plurality of driving electrode islands, which are arranged corresponding to the plurality of pixel circuit islands, each of the driving electrode islands is provided with a plurality of driving electrodes of at least one pixel; and a plurality of second spacing regions, each of the second spacing regions being located between two adjacent driving electrode islands in the first direction.

[0008] For example, in a display substrate provided in an embodiment of the present disclosure, the widths of the multiple first spacer regions in the first direction are equal, the widths of the multiple second spacer regions in the first direction are equal, and the width of the first spacer region in the first direction is smaller than the width of the driving spacer region in the first direction.

[0009] For example, in a display substrate provided in an embodiment of the present disclosure, the widths of the multiple first spacer regions in the first direction are equal, the widths of the multiple second spacer regions in the first direction are equal, the widths of the second spacer regions in the first direction are 0.5-1.5 times the width of the driving spacer, and the widths of the first spacer regions in the first direction are smaller than the widths of the driving spacer in the first direction.

[0010] For example, in a display substrate provided in an embodiment of the present disclosure, the row driving circuit unit includes a first row driving circuit unit and a second row driving circuit unit, the first row driving circuit unit has an output end, and the output end of the first row driving circuit unit is configured to simultaneously drive a plurality of pixels belonging to the same row in the first display area, the second display area and the transition area.

[0011] For example, the display substrate provided by one embodiment of the present disclosure also includes: a plurality of connecting electrode structures, which are located on a side of the plurality of driving electrode islands close to the pixel circuit island in a direction perpendicular to the transition region, and the plurality of connecting electrode structures are respectively arranged in one-to-one correspondence with the plurality of driving electrode islands and the plurality of pixel circuit islands, and each of the connecting electrode structures includes a plurality of connecting electrodes to electrically connect the plurality of pixel driving circuits in the corresponding pixel circuit island with the plurality of driving electrodes in the corresponding driving electrode island.

[0012] For example, in a display substrate provided in an embodiment of the present disclosure, the pixel driving unit includes a driving transistor, and the driving transistor is disposed on a film layer corresponding to where the driving electrode is located, with an orthographic projection and a spacing therebetween from the corresponding driving electrode.

[0013] For example, in a display substrate provided in an embodiment of the present disclosure, the row driving circuit includes a gate driving circuit and a light-emitting control driving circuit, the row driving circuit unit includes a gate driving unit and a light-emitting control unit, and the at least one driving spacer includes two driving spacers, one of the two driving spacers is provided with the gate driving unit, and the other of the two driving spacers is provided with the light-emitting control unit.

[0014] For example, in a display substrate provided by an embodiment of the present disclosure, at least two first spacing areas are spaced between two of the driving spacing areas.

[0015] For example, in a display substrate provided in an embodiment of the present disclosure, the light emitting control unit includes: a first transistor, a gate of the first transistor is connected to a first clock signal line to receive a first clock signal, a first electrode of the first transistor is connected to a first node, and a second electrode of the first transistor is connected to an input terminal; a second transistor, a gate of the second transistor is connected to the first node, a first electrode of the second transistor is connected to a second node, and a second electrode of the second transistor is connected to the first clock signal line to receive the first clock signal; a third transistor, a gate of the third transistor is connected to the first clock signal line to receive the first clock signal, a first electrode of the third transistor is connected to the second node, and a second electrode of the third transistor is connected to a first power line to receive a first voltage; a fourth transistor, a gate of the fourth transistor is connected to the second clock signal line to receive a second clock signal, a first electrode of the fourth transistor is connected to the first node, and a second electrode of the fourth transistor is connected to a second electrode of a fifth transistor; a fifth transistor, a gate of the fifth transistor is connected to the second node, and a first electrode of the fifth transistor is connected to a second power line to receive a second voltage; a sixth transistor, a first electrode of the sixth transistor is connected to the second clock signal line to receive the the second clock signal, the second electrode of the sixth transistor is connected to the third node; the seventh transistor, the gate of the seventh transistor is connected to the second clock signal line to receive the second clock signal, the first electrode of the seventh transistor is connected to the third node, and the second electrode of the seventh transistor is connected to the fourth node; the eighth transistor, the gate of the eighth transistor is connected to the first node, the first electrode of the eighth transistor is connected to the fourth node, and the second electrode of the eighth transistor is connected to the second power line to receive the second voltage; the ninth transistor, the gate of the ninth transistor is connected to the fourth node, the first electrode of the ninth transistor is connected to the second power line to receive the second voltage, and the second electrode of the ninth transistor is connected to the output terminal; the tenth transistor, the first electrode of the tenth transistor is connected to the first power line to receive the first voltage, and the second electrode of the tenth transistor is connected to the output terminal; the first capacitor, the second electrode of the first capacitor is connected to the third node; the second capacitor, the second electrode of the second capacitor is connected to the second clock signal line to receive the second clock signal; and the third capacitor, the first electrode of the third capacitor is connected to the fourth node, and the second electrode of the third capacitor is connected to the second power line to receive the second voltage.

[0016] For example, in the display substrate provided in an embodiment of the present disclosure, the ninth transistor and the tenth transistor are spaced apart from the plurality of connection electrode structures in their orthographic projection on the film layer where the plurality of connection electrode structures are located.

[0017] For example, in a display substrate provided in an embodiment of the present disclosure, the gate driving unit includes: an input transistor, a first control transistor, a second control transistor, an output control transistor, a gate output transistor, a first noise reduction transistor, a second noise reduction transistor, and a voltage stabilizing transistor, a first scanning capacitor and a second scanning capacitor, the gate of the input transistor is connected to a third clock signal line, the second electrode of the input transistor is connected to an input end, and the first electrode of the input transistor is connected to a first scanning node; the gate of the first control transistor is connected to a first scanning node, the second electrode of the first control transistor is connected to the third clock signal line, and the first electrode of the first control transistor is connected to a second scanning node; the gate of the second control transistor is connected to a third clock signal line, the second electrode of the second control transistor is connected to a third power line, and the first electrode of the second control transistor is connected to the second scanning node; the gate of the output control transistor is connected to the second scanning node, the first electrode of the output control transistor is connected to a fourth power line, and the first electrode of the output control transistor is connected to a fourth power line. The first electrode of the first scanning capacitor is connected to the second scanning node, and the second electrode of the first scanning capacitor is connected to the fourth power line; the gate of the gate output transistor is connected to the third scanning node, the first electrode of the gate output transistor is connected to the second clock sub-signal line, and the second electrode of the gate output transistor is connected to the output end; the first electrode of the second scanning capacitor is connected to the third scanning node, and the second electrode of the second scanning capacitor is connected to the output end; the gate of the first noise reduction transistor is connected to the second scanning node, the first electrode of the first noise reduction transistor is connected to the fourth power line, and the second electrode of the first noise reduction transistor is connected to the second electrode of the second noise reduction transistor; the gate of the second noise reduction transistor is connected to the fourth clock signal line, and the first electrode of the second noise reduction transistor is connected to the first scanning node; and the gate of the voltage stabilizing transistor is connected to the third power line, the second electrode of the voltage stabilizing transistor is connected to the first scanning node, and the first electrode of the voltage stabilizing transistor is connected to the third scanning node.

[0018] For example, in the display substrate provided in an embodiment of the present disclosure, the output control transistor and the gate output transistor are arranged spaced apart from the multiple connecting electrode structures in orthographic projection on the film layer where the multiple connecting electrode structures are located.

[0019] For example, a display substrate provided by an embodiment of the present disclosure also includes: a plurality of first driving lines, configured to drive the plurality of gate driving units, the plurality of gate driving units being staggered in the first direction, each of the first driving lines including a first portion extending along the second direction and a second portion extending along the first direction, the first portion being connected to the corresponding gate driving unit, and the second portion connecting the first portions of two adjacent gate driving units.

[0020] For example, a display substrate provided by an embodiment of the present disclosure further includes: a data line, the first portion and the data line are located in a first source-drain metal layer, and the second portion is located in a second source-drain metal layer.

[0021] For example, in a display substrate provided by an embodiment of the present disclosure, each of the first driving lines is in a step shape.

[0022] For example, a display substrate provided by an embodiment of the present disclosure also includes: a plurality of second driving lines, configured to drive the plurality of light-emitting control units, the plurality of light-emitting control units being staggered in the first direction, each of the second driving lines including a third portion extending along the second direction and a fourth portion extending along the first direction, the third portion being connected to the corresponding light-emitting control unit, and the fourth portion connecting the third portions of two adjacent light-emitting control units.

[0023] For example, the display substrate provided by an embodiment of the present disclosure further includes a data line, the third portion and the data line are located in the first source-drain metal layer, and the fourth portion is located in the second source-drain metal layer.

[0024] For example, in a display substrate provided by an embodiment of the present disclosure, each of the second driving lines is in a step shape.

[0025] For example, in a display substrate provided by an embodiment of the present disclosure, a portion of the display substrate located in the second display area is bent in a direction perpendicular to the first display area.

[0026] For example, the display substrate provided by one embodiment of the present disclosure also includes: a third display area, located on one side of the first display area in the second direction, a plurality of pixels are arranged in the third display area, the pixel density of the third display area is substantially equal to the pixel density of the first display area, and the orthographic projection of the third display area on a reference line extending along the first direction overlaps with the orthographic projections of the first display area, the second display area and the transition area on the reference line.

[0027] For example, in a display substrate provided in one embodiment of the present disclosure, the second display area includes: a plurality of pixel islands arranged in an array along the first direction and the second direction, each of the pixel islands including at least one pixel; a first opening extending along the first direction and located between two adjacent pixel islands in the second direction; and a second opening extending along the second direction and located between two adjacent pixel islands in the first direction.

[0028] At least one embodiment of the present disclosure further provides a display device, comprising any of the display substrates described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0030] Figure 1A A schematic plan view of a display substrate provided in one embodiment of the present disclosure;

[0031] Figure 1B A connection diagram of a row driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0032] Figure 1C A schematic diagram of a gate driving unit in a display substrate provided by an embodiment of the present disclosure;

[0033] Figure 1D A schematic diagram of a light emitting control unit in a display substrate provided in an embodiment of the present disclosure;

[0034] Figure 2 A schematic plan view of another display substrate provided in one embodiment of the present disclosure;

[0035] Figure 3 A schematic plan view of another display substrate provided by an embodiment of the present disclosure;

[0036] Figure 4 A schematic plan view of another display substrate provided by an embodiment of the present disclosure;

[0037] Figure 5 A schematic plan view of another display substrate provided in one embodiment of the present disclosure;

[0038] Figure 6 A schematic plan view of another display substrate provided in one embodiment of the present disclosure;

[0039] Figure 7 An equivalent schematic diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0040] Figure 8 An equivalent circuit diagram of a light emitting control unit provided in one embodiment of the present disclosure;

[0041] Fig. 9 An equivalent circuit diagram of a gate driving unit provided in one embodiment of the present disclosure;

[0042] Fig.10 A schematic diagram of a second display area on a display substrate provided in one embodiment of the present disclosure; and

[0043] Fig.11 A schematic plan view of a display substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0046] Generally, the pixel density (PPI) of the four corner areas of the display substrate can be reduced, and a stretchable structure with an opening pattern can be provided in the four corner areas, so that the edge or corner of the display substrate can be bent according to a certain bending radius, thereby realizing a four-curved screen design. At this time, the greater the stretching amount of the stretchable structure located in the four corner areas, the lower the pixel density of the four corner areas, that is, the low pixel density area. On the other hand, the opening pattern of the stretchable structure needs to extend outside the low pixel density area to the cutting line. Therefore, the gate drive circuit (GOA circuit) in the low pixel density area cannot be placed outside the pixel in the conventional way.

[0047] In this regard, the embodiment of the present disclosure provides a display substrate and a display device. The display substrate includes a first display area; a second display area, located on one side of the first display area in a first direction; and a transition area, located between the first display area and the second display area, the first display area, the second display area and the transition area are provided with a plurality of pixels, and the plurality of pixels are arranged in an array along the first direction and the second direction intersecting the second direction, the pixel density of the first display area (i.e., the high pixel density area) is greater than the pixel density of the second display area (i.e., the low pixel density area) and the pixel density of the transition area, and the transition area is also provided with a row driving circuit, which is configured to drive the first display area, the second display area and the transition area by row. Thus, the display substrate provides a GIP (Gate in Pixel) design, that is, the display substrate is provided with a transition area in a high pixel density area and a low pixel density area, and a row driving circuit, such as a gate driving circuit (GOA), is provided in the transition area, so as to drive the high pixel density area and the low pixel density area on both sides of the transition area for display.

[0048] The display substrate and the display device provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0049] An embodiment of the present disclosure provides a display substrate. Figure 1A FIG. 1 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure. Figure 1A As shown, the display substrate 100 includes a first display area 110, a second display area 120 and a transition area 130; the second display area 120 is located at least on one side of the first display area 110 in the first direction X, and the transition area 130 is located between the first display area 110 and the second display area 120. The first display area 110, the second display area 120 and the transition area 130 are provided with a plurality of pixels 210, and the plurality of pixels 210 are arranged in an array along the first direction and the second direction intersecting the second direction, that is, the plurality of pixels 210 form a plurality of rows of pixels and a plurality of columns of pixels; the pixel density of the first display area 110 is greater than the pixel density of the second display area 120 and the pixel density of the transition area 130; the transition area 130 is further provided with a row driving circuit 220, and the row driving circuit 220 is configured to drive the plurality of pixels 210 in the first display area 110, the second display area 120 and the transition area 130 in rows. It is worth noting that a plurality of pixels are also arranged in the transition area provided in the embodiment of the present disclosure, and the transition area can be displayed together with the first display area and the second display area.

[0050] In the display substrate provided by the embodiment of the present disclosure, since the pixel density of the first display area is greater than the pixel density of the second display area and the pixel density of the transition area, the first display area is a high pixel density area, and the second display area is a low pixel density area. The display substrate inserts a transition area between the high pixel density area and the low pixel density area, and sets a row drive circuit in the transition area, so that the row drive circuit in the transition area can be used to drive the first display area, the second display area, and the transition area by row for display. Therefore, the display substrate does not need to set an additional area for placing the row drive circuit outside the low pixel density area. On the one hand, the frame width of the display substrate can be reduced, and on the other hand, it can solve the problem that the row drive circuit cannot be set in the four corner areas of the four-curved screen design due to the opening pattern.

[0051] In some examples, such as Figure 1A As shown, the second display area 120 is located at both sides of the first display area 110 in the first direction, and the two transition areas 130 are respectively located between the first display area 110 and the two second display areas 120 .

[0052] In some examples, such as Figure 1A As shown, the row driving circuit 220 includes a plurality of row driving circuit units 225 arranged along the second direction. For example, the row driving circuit 220 may be a gate driving circuit, and the row driving circuit unit 225 may be a gate driving unit, ie, a GOA unit.

[0053] In some examples, such as Figure 1A As shown, the driving circuit unit 225 includes a first row driving circuit unit 225A and a second row driving circuit unit 225B; the first row driving circuit unit 225A has an output terminal OUT on both sides of the first direction, so that the first row driving circuit unit 225A can simultaneously drive multiple pixels 210 belonging to the same row in the first display area 110, the second display area 120 and the transition area 130; the second row driving circuit unit 225B has an output terminal OUT on the side close to the first display area 110 in the first direction, and the second row driving circuit unit 225 is configured to only drive multiple pixels 210 belonging to the same row in the first display area 110.

[0054] In the display substrate provided in the embodiment of the present disclosure, the pixel density in the first display area 110 is greater than the pixel density in the second display area 120, so the number of rows of pixels 210 in the first display area 110 may be greater than the number of rows of pixels 210 in the second display area 120. At this time, by setting the row driving circuit unit 225 to include the above-mentioned first row driving circuit unit 225A and the second row driving circuit unit 225B, the first row driving circuit unit 225A is configured to simultaneously drive a plurality of pixels 210 belonging to the same row in the first display area 110, the second display area 120 and the transition area 130, and the second row driving circuit unit 225 is configured to only drive a plurality of pixels 210 belonging to the same row in the first display area 110, so that the pixels 210 in the first display area 110 and the second display area 120 with different pixel densities can be driven better.

[0055] Figure 1B FIG. 1 is a connection diagram of a row driving circuit in a display substrate provided by an embodiment of the present disclosure. Figure 1B As shown, the row driving circuit 220 includes a gate driving circuit 2202 and a light emitting control driving circuit 2204 ; the row driving circuit unit 225 includes a gate driving unit 2252 and a light emitting control unit 2254 .

[0056] like Figure 1B As shown, the gate drive circuit 2202 and the light control drive circuit 2204 are arranged in a step-like manner; a plurality of gate drive units 2252 can form a gate drive unit group 2252G, and then the plurality of gate drive unit groups 2252G are arranged at intervals in the first direction, that is, the plurality of gate drive unit groups 2252G are arranged in a staggered manner in the first direction. At this time, the plurality of gate drive units 2252 in a gate drive unit group 2252G can be cascaded with each other, and two adjacent gate drive unit groups 2252G are connected by connecting lines to transmit signals such as clock signals. Similarly, a plurality of light control units 2254 can form a light control unit group 2254G, and then the plurality of light control unit groups 2254G are arranged at intervals in the first direction, that is, the plurality of light control unit groups 2254G are arranged in a staggered manner in the first direction. At this time, the plurality of light control units 2254 in a light control unit group 2254G can be cascaded with each other, and two adjacent light control unit groups 2254G are connected by connecting lines to transmit signals such as clock signals.

[0057] like Figure 1BAs shown, since two adjacent gate drive unit groups 2252G are connected by connecting lines, and two adjacent light-emitting control unit groups 2254G are connected by connecting lines, the gate drive unit groups 2252G and light-emitting control unit groups 2254G located in the same column are arranged at intervals, for example, at intervals of one unit length, which may be the length of one gate drive unit or light-emitting control unit in the second direction. In other words, the gate drive unit groups 2252G and light-emitting control unit groups 2254G located in the same column and adjacent are arranged with intervals 2209, and the intervals 2209 may provide routing space.

[0058] Figure 1C A schematic diagram of a gate driving unit in a display substrate provided by an embodiment of the present disclosure; Figure 1D FIG. 1 is a schematic diagram of a light emitting control unit in a display substrate provided by an embodiment of the present disclosure. Figure 1C As shown, the output end of the gate driving unit 2252 is connected to the gate line 650A through the via 650H. At this time, the two parts of the gate line 650A located on both sides of the via 650H can be equivalent to the two output ends OUT of the gate driving unit 2252. Figure 1D As shown, the output end of the light emitting control unit 2254 is connected to the light emitting control line 660A through a via 660H. At this time, the two parts of the light emitting control line 660A located on both sides of the via 660H can be equivalent to the two output ends OUT of the light emitting control unit 2254.

[0059] Figure 2 FIG. 1 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure. Figure 2 As shown, the planar shape of the display substrate 100 is approximately a rounded rectangle, and the four corner areas of the display substrate 100, namely the second display area 120 mentioned above, can be bent, thereby realizing a four-curved screen design.

[0060] In some examples, such as Figure 2 As shown, the display substrate 100 further includes a third display area 180, in which a plurality of pixels 210 are arranged, and the pixel density of the third display area 180 is substantially equal to the pixel density of the first display area 110. The third display area 180 is located on one side of the first display area 110 in the second direction Y, and the orthographic projection of the third display area 180 on a reference line 500 extending along the first direction X overlaps with the orthographic projections of the first display area 110, the second display area 120, and the transition area 130 on the reference line 500.

[0061] For example, Figure 2As shown, the width of the orthographic projection of the third display area 180 on the reference line 500 extending along the first direction X is equal to the sum of the widths of the orthographic projections of the first display area 110 , the second display area 120 and the transition area 130 on the reference line 500 .

[0062] In some examples, such as Figure 2 As shown, the display substrate 100 further includes an edge driving circuit 280 located at least on one side of the third display area 180 in the first direction X. The edge driving circuit 280 is configured to drive the pixels 210 in the third display area 180 .

[0063] In some examples, such as Figure 1A and Figure 2 As shown, the portion of the display substrate 100 located in the second display area 120 is bent in a direction perpendicular to the first display area 110. For example, the display substrate 100 includes a light emitting side, that is, a side from which light emitted by the display substrate 100 is emitted, and the portion of the display substrate 100 located in the second display area 120 can be bent toward a side opposite to the light emitting side, thereby achieving a 3D stereoscopic effect in a curved surface form, thereby creating a three-dimensional immersive display experience.

[0064] In some examples, the second display region 120 may be provided with an opening pattern so as to be stretchable and bendable, while the first display region 110 and the transition region 130 are not provided with an opening pattern.

[0065] Figure 3 FIG. 1 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure. Figure 3 As shown, in the transition region 130, the pixel 210 may include a plurality of sub-pixels 215, each of which includes a pixel driving circuit 2152 and a driving electrode 2154 electrically connected to the pixel driving circuit 2152. At this time, the transition region 130 includes a plurality of pixel circuit islands 131, a plurality of first spacing regions 132 and at least one driving spacing region 133.

[0066] like Figure 3 As shown, each pixel circuit island 131 is provided with a plurality of pixel driving circuits 2152 of at least one pixel 210; Figure 3 It is shown that the six pixel driving circuits 2152 of two adjacent pixels 210 in the second direction are arranged in one pixel circuit island 131. It should be noted that the shortest distance between the pixel circuits in the above-mentioned pixel circuit island is shorter than the shortest distance between two adjacent pixel circuit islands. Figure 3 It is shown that the pixel circuit island includes pixel driving circuits for two pixels, but the embodiments of the present disclosure include but are not limited to this, and the pixel circuit island may be provided with pixel driving circuits for more pixels.

[0067] like Figure 3 As shown, each first spacing area 132 is located between two pixel circuit islands 131 adjacent in the first direction, each driving spacing area 133 is also located between two pixel circuit islands 131 adjacent in the first direction, and the driving spacing area 133 is provided with a row driving circuit unit 225. In the display substrate, the transition area 130 can be divided into a pixel circuit island 131, a first spacing area 132 and a driving spacing area 133, and the driving spacing area 133 is located between two pixel circuit islands 131 adjacent in the first direction, and is provided with a row driving circuit unit 225. Therefore, the display substrate can be provided with a pixel driving circuit 2152 in the pixel circuit island 131 for applying a data signal to the driving sub-pixel 215, and a row driving circuit unit 225 in the driving spacing area 133 for applying a row driving signal to the row driving circuit unit 225.

[0068] For example, when the display substrate is an organic light emitting diode display substrate, the driving electrode may be an anode; of course, the embodiments of the present disclosure include but are not limited to this.

[0069] In some examples, such as Figure 3 As shown, the transition region 130 further includes: a plurality of driving electrode islands 134 and a plurality of second spacing regions 135; the plurality of driving electrode islands 134 are arranged corresponding to the plurality of pixel circuit islands 131, and each driving electrode island 138 is provided with a plurality of driving electrodes 2154 of at least one pixel 210; for example, when a pixel 210 includes three sub-pixels 215 (for example, a red sub-pixel, a blue sub-pixel, and a green sub-pixel), each driving electrode island 138 may be provided with three driving electrodes 2154. Each second spacing region 135 is located between two adjacent driving electrode islands 134 in the first direction. It should be noted that the driving electrode islands and the pixel circuit islands belong to different film layers of the display substrate, and therefore may overlap each other.

[0070] In some examples, such as Figure 3As shown, the widths of the plurality of first spacing areas 132 in the first direction are equal, the widths of the plurality of second spacing areas 135 in the first direction are equal, and the width of the first spacing area 132 in the first direction is equal to the width of the driving spacing area 133 in the first direction. In the display substrate, since the widths of the plurality of second spacing areas 135 in the first direction are equal, the driving electrode islands 134 in the first direction are also equidistantly distributed, so that the pixels in the transition area can be ensured to emit light more evenly without defects such as bright lines or dark lines. On the other hand, the widths of the first spacing area 132 where the row driving circuit unit 225 is not arranged between two adjacent pixel circuit islands 131 in the first direction and the driving spacing area 133 where the row driving circuit unit 225 is arranged between two adjacent pixel circuit islands 131 in the first direction are the same. At this time, the pixel circuit islands 131 in the first direction are equidistantly distributed. As a result, the display substrate can ensure that the pixels in the transition area emit light more evenly without defects such as bright lines or dark lines, while having the advantages of simple layout.

[0071] Figure 4 FIG. 1 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure. Figure 4 As shown, the widths of the plurality of first spacing regions 132 (i.e., the spacing regions between adjacent pixel circuit islands 131 except the driving spacing regions 133) in the first direction are equal, the widths of the plurality of second spacing regions 135 (i.e., the spacing regions between adjacent driving electrode islands 134) in the first direction are equal, the width of the second spacing regions 135 in the first direction is smaller than the width of the driving spacing regions 133, and the width of the first spacing regions 132 in the first direction is smaller than the width of the driving spacing regions 133 in the first direction. In this display substrate, the widths of the plurality of second spacing regions 135 in the first direction are equal, thereby ensuring that the pixels in the transition region emit light more evenly without defects such as bright lines or dark lines. On the other hand, compared with Figure 3 The display substrate shown is different in that the pixel circuit islands 131 in the first direction are not equidistantly arranged, and the width of the first spacing area 132 between two adjacent pixel circuit islands 131 in the first direction where the row driving circuit unit 225 is not arranged is smaller than the width of the driving spacing area 133 between two adjacent pixel circuit islands 131 in the first direction where the row driving circuit unit 225 is arranged. Therefore, when the size of the transition area in the first direction or the pixel density of the transition area is large, the display substrate can increase the width of the driving spacing area 133 by reducing the width of the first spacing area 132, so that the row driving circuit unit 225 can be placed in the driving spacing area 133. Therefore, the display substrate can still have a high pixel density in the transition area while ensuring uniform pixel light emission in the transition area, thereby having better display quality. It should be noted that in Figure 4In the display substrate shown, the corresponding pixel circuit islands and driving electrode islands are staggered, so a connecting electrode is needed to connect the output end of the corresponding pixel circuit island with the driving electrode in the driving electrode island.

[0072] In some examples, the width of the first spacer 132 in the first direction is 0.5-1.5 times the width of the driving spacer 133 in the first direction, so that while ensuring uniform pixel illumination in the transition region, the transition region still has a higher pixel density, thereby having better display quality.

[0073] In some examples, such as Figure 4 As shown, the display substrate 100 also includes a plurality of connecting electrode structures 150, which are located between the plurality of pixel circuit islands 131 and the plurality of driving electrode islands 134 in a direction perpendicular to the transition region 130, that is, the plurality of connecting electrode structures 150 are located on one side of the plurality of driving electrode islands 131 close to the pixel circuit islands 131 in a direction perpendicular to the transition region 130; the plurality of connecting electrode structures 150 are respectively arranged in one-to-one correspondence with the plurality of driving electrode islands 134 and the plurality of pixel circuit islands 131, and each connecting electrode structure 150 includes a plurality of connecting electrodes 152 to electrically connect the plurality of pixel driving circuits 2152 in the corresponding pixel circuit island 131 with the plurality of driving electrodes 2154 in the corresponding driving electrode island 134.

[0074] In some examples, such as Figure 4 As shown, a pixel 210 includes three sub-pixels 215 , and a connection electrode structure 150 may include three connection electrodes 152 , so as to electrically connect three pixel driving circuits 2152 in the corresponding pixel 210 to three driving electrodes 2154 , respectively.

[0075] Figure 5 FIG. 1 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure. Figure 5 As shown, the pixel driving unit 2152 includes a driving transistor 2152T, and the driving transistor 2152T is disposed in an orthogonal projection on the film layer where the corresponding driving electrode 1254 is located, and is spaced from the corresponding driving electrode 2154. In the display substrate provided by the embodiment of the present disclosure, the pixel circuit island 131 and the driving electrode island 134 are disposed in an offset manner, so the driving transistor 2152T is disposed in an orthogonal projection on the film layer where the corresponding driving electrode 1254 is located, and is spaced from the corresponding driving electrode 2154.

[0076] Figure 6 FIG. 1 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure. Figure 6As shown, the row driving circuit 220 includes a gate driving circuit 2202 and a light-emitting control driving circuit 2204, and the row driving circuit unit 225 includes a gate driving unit 2252 and a light-emitting control unit 2254; at least one driving interval 133 includes two driving intervals 133, that is, the number of driving intervals 133 between a row of pixels 210 in the transition area 130 is two. At this time, one of the two driving intervals 133 is provided with a gate driving unit 2252, and the other of the two driving intervals 133 is provided with a light-emitting control unit 2254. Of course, the embodiments of the present disclosure include but are not limited to this, and the row driving circuit unit may also include other circuit units that apply signals along the row direction; in addition, the gate driving unit and the light-emitting control unit may also be provided in one driving interval at the same time.

[0077] In some examples, such as Figure 6 As shown, at least two first spacing areas 132 are spaced between two driving spacing areas 133. Thus, the display substrate can avoid uneven light emission caused by close driving spacing areas 133. In addition, the long distance between the two driving spacing areas 133 also facilitates wiring.

[0078] In some examples, such as Figure 6 As shown, the display substrate 100 also includes: a plurality of first driving lines 510, which are configured to drive a plurality of gate driving units 2202, the plurality of gate driving units 2202 are staggered in the first direction, each first driving line 510 includes a first portion 510A extending along the second direction and a second portion 510B extending along the first direction, the first portion 510A is connected to the corresponding gate driving unit 2202, and the second portion 510B connects the first portions 510A of two adjacent gate driving units 2202.

[0079] In some examples, such as Figure 6 As shown, the display substrate 100 further includes a data line 610 , the first portion 510A and the data line 610 are located in the first source-drain metal layer SD1 , and the second portion 510B is located in the second source-drain metal layer SD2 .

[0080] In some examples, such as Figure 6 As shown, each first driving line 510 is in a step shape.

[0081] In some examples, such as Figure 6As shown, the display substrate 100 also includes: a plurality of second driving lines 520, which are configured to drive a plurality of light-emitting control units 2204, the plurality of light-emitting control units 2204 are staggered in the first direction, each second driving line 520 includes a third portion 520A extending along the second direction and a fourth portion 520B extending along the first direction, the third portion 520A is connected to the corresponding light-emitting control unit 2204, and the fourth portion 520B connects the third portions 520A of two adjacent light-emitting control units 2204.

[0082] In some examples, such as Figure 6 As shown, the display substrate includes a data line 610, the third portion 520A and the data line 610 are located in the first source-drain metal layer SD1, and the fourth portion is located in the second source-drain metal layer SD2.

[0083] In some examples, such as Figure 6 As shown, each second driving line 520 is in a step shape.

[0084] Figure 7 FIG. 1 is an equivalent schematic diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure. Figure 7 As shown, the pixel driving circuit 2152 includes a first thin film transistor T21, a second thin film transistor T22, a third thin film transistor T23, a fourth thin film transistor T24, a fifth thin film transistor T25, a sixth thin film transistor T26, a seventh thin film transistor T27 and a storage capacitor Cst. The first thin film transistor T21 includes a first gate G1 and a first source S1 and a first drain D1 located on both sides of the first gate G1, the second thin film transistor T22 includes a second gate G2 and a second source S2 and a second drain D2 located on both sides of the second gate G2, the third thin film transistor T23 includes a third gate G3 and a third source S3 and a third drain D3 located on both sides of the third gate G3, the fourth thin film transistor T24 includes a fourth gate G4 and a fourth source S4 and a fourth drain D4 located on both sides of the fourth gate G4, the fifth thin film transistor T25 includes a fifth gate G5 and a fifth source S5 and a fifth drain S5 located on both sides of the fifth gate G5, the sixth thin film transistor T26 includes a sixth gate G6 and a sixth source S6 and a sixth drain D6 located on both sides of the sixth gate G6, and the seventh thin film transistor T27 includes a seventh gate G7 and a seventh source S7 and a seventh drain D7 located on both sides of the seventh gate G7. The storage capacitor Cst includes a first electrode block CE1 and a second electrode block CE2. It should be noted that, Figure 7 The pixel driving circuit shown adopts a 7T1C structure. However, the embodiments of the present disclosure include but are not limited to this, and the pixel driving circuit may also adopt other circuit structures.

[0085] For example, as shown in FIG7 , the reset signal line 640 is connected to the gate electrode G6 of the sixth thin film transistor T26; the sixth drain electrode D6 is connected to the third drain electrode D3, the third source electrode S3, the first drain electrode D1 and the fifth source electrode S5 are connected to the first node N1, the first source electrode S1, the second drain electrode D2 and the fourth drain electrode D4 are connected to the second node N2, and the fifth drain electrode D5 is connected to the seventh drain electrode D7. The sixth source electrode S6 and the seventh source electrode S7 are connected to the initialization signal line 630, the second source electrode S2 can be connected to the data line 610; the fourth source electrode S4 is connected to the power line 620, the gate line 650 is connected to the third gate electrode G of the third thin film transistor T23, and the light emitting control line 660 is connected to the fifth gate electrode G5.

[0086] The following will Figure 7 A working mode of the pixel driving circuit shown in FIG. 1 is schematically described. First, when a reset signal is transmitted to the reset signal line 640 and the seventh thin film transistor T7 is turned on, the residual current flowing through the anode of each sub-pixel is discharged to the sixth thin film transistor T6 through the seventh thin film transistor T7, thereby suppressing the luminescence caused by the residual current flowing through the anode of each sub-pixel. Then, when a reset signal is transmitted to the reset signal line 640 and an initialization signal is transmitted to the initialization signal line 630, the sixth thin film transistor T6 is turned on, and the initialization voltage Vint is applied to the first gate G1 of the first thin film transistor T1 and the first electrode block CE1 of the storage capacitor Cst through the sixth thin film transistor T6, so that the first gate G1 and the storage capacitor Cst are initialized. The initialization of the first gate G1 can turn on the first thin film transistor T1.

[0087] Subsequently, when a gate signal is transmitted to the gate line 650 and a data signal is transmitted to the data line 610, the second thin film transistor T2 and the third thin film transistor T3 are both turned on, and the data voltage Vd is applied to the first gate electrode G1 through the second thin film transistor T2 and the third thin film transistor T3. At this time, the voltage applied to the first gate electrode G1 is the compensation voltage Vd+Vth, and the compensation voltage applied to the first gate electrode G1 is also applied to the first electrode block CE1 of the storage capacitor Cst.

[0088] Subsequently, the power line 620 applies a driving voltage Vel to the second electrode block CE2 of the storage capacitor Cst, and applies a compensation voltage Vd+Vth to the first electrode block CE1, so that a charge corresponding to the difference between the voltages respectively applied to the two electrodes of the storage capacitor Cst is stored in the storage capacitor Cst, and the first thin film transistor T1 is turned on for a predetermined time.

[0089] Subsequently, when an emission control signal is applied to the light emitting control line 660, the fourth thin film transistor T4 and the fifth thin film transistor T5 are both turned on, so that the fourth thin film transistor T4 applies the driving voltage Vel to the fifth thin film transistor T5. When the driving voltage Vel passes through the first thin film transistor T1 turned on by the storage capacitor Cst, the driving current Id corresponding to the difference between the driving voltage Vel and the voltage applied to the first gate G1 through the storage capacitor Cst flows through the first drain region D3 of the first thin film transistor T1, and the driving current Id is applied to each sub-pixel through the fifth thin film transistor T5, so that the light emitting layer of each sub-pixel emits light.

[0090] Figure 8 FIG. 1 is an equivalent circuit diagram of a light emitting control unit provided in one embodiment of the present disclosure. Figure 8 As shown, the light emitting control unit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10 (also called an output transistor), a first capacitor C1, a second capacitor C2 and a third capacitor C3. The light emitting control unit adopts a 10T3C structure, and of course the embodiments of the present disclosure include but are not limited to this. It should be noted that the light emitting control unit is a light emitting control shift register. When a plurality of light emitting control shift registers are cascaded, the second electrode of the first transistor T1 in the first stage of the light emitting control shift register can be connected to the input end, and the input end is configured to be connected to the trigger signal line STV to receive the trigger signal as the input signal, and the second electrode of the first transistor T1 in the light emitting control shift register units of other stages is electrically connected to the output end of the previous stage of the light emitting control shift register unit to receive the output signal outputted by the output end OUT of the previous stage of the light emitting control shift register unit as the input signal, thereby realizing the shift output, so as to provide, for example, a row-by-row shifted light emitting control signal to the pixels arranged in the array in the display area of ​​the display substrate.

[0091] like Figure 8 As shown, the gate of the first transistor T1 is connected to the first clock signal line 310 to receive the first clock signal, the first electrode of the first transistor T1 is connected to the first node N1, and the second electrode of the first transistor T1 is connected to the input terminal. For example, when the light-emitting control unit is a first-stage light-emitting control unit, the input terminal is connected to the trigger signal line STV to receive the trigger signal, and when the light-emitting control unit is a light-emitting control unit of each stage other than the first-stage light-emitting control unit, the input terminal is connected to the output terminal OUT of the light-emitting control unit of the previous stage.

[0092] like Figure 8As shown, the second transistor T2, the gate of the second transistor T2 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the first clock signal line 310 to receive the first clock signal.

[0093] like Figure 8 As shown, the gate of the third transistor T3 is connected to the first clock signal line 310 to receive the first clock signal, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the first power line 410 to receive the first voltage.

[0094] like Figure 8 As shown, the gate of the fourth transistor T4 is connected to the second clock signal line 320 to receive the second clock signal, the first electrode of the fourth transistor T4 is connected to the first node N1, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.

[0095] like Figure 8 As shown, the gate of the fifth transistor T5 is connected to the second node N2, and the first electrode of the fifth transistor T5 is connected to the second power line 420 to receive the second voltage.

[0096] like Figure 8 As shown, a first electrode of the sixth transistor T6 is connected to the second clock signal line 320 to receive the second clock signal, and a second electrode of the sixth transistor T6 is connected to the third node N3.

[0097] like Figure 8 As shown, the gate of the seventh transistor T7 is connected to the second clock signal line 320 to receive the second clock signal, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0098] like Figure 8 As shown, a gate of the eighth transistor T8 is connected to the first node N1, a first electrode of the eighth transistor T8 is connected to the fourth node N4, and a second electrode of the eighth transistor T8 is connected to the second power line 420 to receive the second voltage.

[0099] like Figure 8 As shown, a gate of the ninth transistor T9 is connected to the fourth node N4, a first electrode of the ninth transistor T9 is connected to the second power line 420 to receive the second voltage, and a second electrode of the ninth transistor T9 is connected to the output terminal.

[0100] like Figure 8 As shown, a first electrode of the tenth transistor T10 is connected to the first power line 410 to receive the first voltage, and a second electrode of the tenth transistor T10 is connected to the output terminal.

[0101] like Figure 8As shown, the second electrode of the first capacitor C1 is connected to the third node N3; the second electrode of the second capacitor C2 is connected to the second clock signal line 320 to receive the second clock signal; the first electrode of the third capacitor C3 is connected to the fourth node N4, and the second electrode of the third capacitor C3 is connected to the second power line 420 to receive the second voltage.

[0102] It should be noted that Figure 8 The transistors in the light-emitting control unit shown are all described by taking p-type transistors as an example, that is, each transistor is turned on when the gate is connected to a low level (on level), and is turned off when it is connected to a high level (off level). At this time, the first pole of the transistor can be a source, and the second pole of the transistor can be a drain. Of course, the embodiments of the present disclosure include but are not limited to this, and each transistor can also use an n-type transistor or a mixture of p-type transistors and n-type transistors. It is only necessary to simultaneously connect the port polarity of the selected type of transistor according to the port polarity of the corresponding transistor in the embodiments of the present disclosure. In addition, the working principle of the light-emitting control unit can refer to the relevant introduction in the field, which will not be repeated here.

[0103] It should be noted that the transistors used in the light-emitting control unit can be thin-film transistors or field-effect transistors or other switching devices with the same characteristics. Here, thin-film transistors are used as examples for explanation. For example, the active layer (channel region) of the transistor is made of semiconductor materials, such as polycrystalline silicon (such as low-temperature polycrystalline silicon or high-temperature polycrystalline silicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, drain, etc. are made of metal materials, such as metal aluminum or aluminum alloy. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be indistinguishable in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is directly described as the first pole and the other pole is the second pole. In addition, in the embodiments of the present disclosure, the electrodes of the capacitor can be metal electrodes or one of the electrodes can be made of semiconductor materials (such as doped polycrystalline silicon).

[0104] In some examples, the ninth transistor T9 and the tenth transistor T10 are arranged on the film layer where the plurality of connection electrode structures 150 are located by orthogonal projection and spaced from the plurality of connection electrode structures 150, thereby preventing the signal on the connection electrode structure 150 from affecting the light-emitting control unit. Since the width-to-length ratio (W / L) of the channels of the ninth transistor T9 and the tenth transistor T10 is relatively large, by orthogonally projecting the ninth transistor T9 and the tenth transistor T10 on the film layer where the plurality of connection electrode structures 150 are located and spaced from the plurality of connection electrode structures 150, the connection electrode structures can be prevented from affecting the ninth transistor T9 and the tenth transistor T10, thereby improving the display brightness difference and color shift after the pixel emits light.

[0105] Fig. 9FIG. 1 is an equivalent circuit diagram of a gate driving unit provided by an embodiment of the present disclosure. Fig. 9 As shown, the gate driving unit 2252 includes: an input transistor 241, a first control transistor 242, a second control transistor 243, an output control transistor 244, a gate output transistor 245, a first noise reduction transistor 246, a second noise reduction transistor 247, a voltage regulator transistor 248, a first scanning capacitor 251 and a second scanning capacitor 252. Therefore, the gate driving unit can adopt an 8T2C structure, of course, the embodiments of the present disclosure include but are not limited to this, and the gate driving unit can also adopt other circuit structures.

[0106] It should be noted that the above-mentioned gate driving unit is a gate scanning shift register; when multiple gate driving units are cascaded, the first electrode of the input transistor T1 in the first-stage gate driving unit is connected to the input end, and the input end is configured to be connected to the trigger signal line STV to receive the trigger signal as an input signal, while the first electrode of the input transistor T1 in the other stages of the gate driving unit is electrically connected to the output end of the previous stage of the gate driving unit to receive the output signal output by the output end OUT of the previous stage of the gate driving unit as an input signal, thereby realizing shift output for scanning the pixels in the display substrate row by row.

[0107] like Fig. 9 As shown, the gate of the input transistor 241 is connected to the third clock signal line 330, the second electrode of the input transistor 241 is connected to the input terminal, and the first electrode of the input transistor 241 is connected to the first scanning node SN1.

[0108] like Fig. 9 As shown, the gate of the first control transistor 242 is connected to the first scan node SN1, the second electrode of the first control transistor 242 is connected to the third clock signal line 330, and the first electrode of the first control transistor 242 is connected to the second scan node SN2.

[0109] like Fig. 9 As shown, the gate of the second control transistor 243 is connected to the third clock signal line 330, the second electrode of the second control transistor 243 is connected to the third power line 430, and the first electrode of the second control transistor 243 is connected to the second scan node SN2.

[0110] like Fig. 9 As shown, the gate of the output control transistor 244 is connected to the second scanning node SN2, the first electrode of the output control transistor 244 is connected to the fourth power line 440, and the second electrode of the output control transistor 245 is connected to the output end.

[0111] like Fig. 9As shown, the first electrode of the first scanning capacitor 251 is connected to the second scanning node SN2 , and the second electrode of the first scanning capacitor 251 is connected to the fourth power line 440 .

[0112] like Fig. 9 As shown, the gate of the gate output transistor 245 is connected to the third scanning node SN3, the first electrode of the gate output transistor 245 is connected to the fourth clock signal line 340, and the second electrode of the gate output transistor 245 is connected to the output end.

[0113] like Fig. 9 As shown, the first electrode of the second scanning capacitor 252 is connected to the third scanning node SN3, and the second electrode of the second scanning capacitor 252 is connected to the output end.

[0114] like Fig. 9 As shown, the gate of the first noise reduction transistor 246 is connected to the second scanning node SN2, the first electrode of the first noise reduction transistor 246 is connected to the fourth power line 440, and the second electrode of the first noise reduction transistor 246 is connected to the second electrode of the second noise reduction transistor 247.

[0115] like Fig. 9 As shown, the gate of the second noise reduction transistor 247 is connected to the fourth clock signal line 340, and the first electrode of the second noise reduction transistor 247 is connected to the first scanning node SN1.

[0116] like Fig. 9 As shown, the gate of the voltage stabilizing transistor 248 is connected to the third power line 430, the second electrode of the voltage stabilizing transistor 248 is connected to the first scanning node SN1, and the first electrode of the voltage stabilizing transistor 248 is connected to the third scanning node SN3.

[0117] It should be noted that Fig. 9 The transistors in the gate drive unit shown in are all explained by taking p-type transistors as an example, that is, each transistor is turned on (on level) when the gate is connected to a low level, and is turned off (off level) when it is connected to a high level. At this time, the first electrode of the transistor can be a source electrode, and the second electrode of the transistor can be a drain electrode. Of course, the embodiments of the present disclosure include but are not limited to this. Each transistor can also use an n-type transistor or a mixture of p-type transistors and n-type transistors. It is only necessary to simultaneously connect the port polarity of the selected type of transistor according to the port polarity of the corresponding transistor in the embodiments of the present disclosure. In addition, the working principle of the gate drive unit can refer to the relevant introduction in the field, which will not be repeated here.

[0118] It should be noted that the transistors used in the gate drive unit can be thin film transistors or field effect transistors or other switching devices with the same characteristics. Here, thin film transistors are used as examples for explanation. For example, the active layer (channel region) of the transistor is made of semiconductor materials, such as polycrystalline silicon (such as low-temperature polycrystalline silicon or high-temperature polycrystalline silicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, drain, etc. are made of metal materials, such as metal aluminum or aluminum alloy. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be indistinguishable in structure. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is directly described as the first pole and the other pole is the second pole. In addition, in the embodiment of the present disclosure, the electrodes of the capacitor can be metal electrodes or one of the electrodes can be made of semiconductor materials (such as doped polycrystalline silicon).

[0119] In some examples, the output control transistor 244 and the gate output transistor 245 are arranged on the film layer where the multiple connection electrode structures 150 are located, and are spaced from the multiple connection electrode structures 150. Since the width-to-length ratio (W / L) of the channels of the output control transistor 244 and the gate output transistor 245 is relatively large, by arranging the output control transistor 244 and the gate output transistor 245 on the film layer where the multiple connection electrode structures 150 are located, the connection electrode structures can be prevented from affecting the output control transistor 244 and the gate output transistor 245, thereby improving the display brightness difference and color shift after the pixel emits light.

[0120] Fig.10 FIG. 1 is a schematic diagram of a second display area on a display substrate provided by an embodiment of the present disclosure. Fig.10 As shown, the second display area 120 includes: a plurality of pixel islands 1202 arranged in an array along the first direction and the second direction, each pixel island 1202 including at least one pixel; a first opening 1204 extending along the first direction and located between two adjacent pixel islands 1202 in the second direction; and a second opening 1206 extending along the second direction and located between two adjacent pixel islands 1202 in the first direction. Since the second display area is provided with the first opening and the second opening, i.e., the above-mentioned opening pattern, it can be easily bent and stretched.

[0121] At least one embodiment of the present disclosure further provides a display device. Fig.11 FIG. 1 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure. Fig.11As shown, the display device 900 includes any of the display substrates 100 described above. Since the display substrate 100 inserts a transition region between a high pixel density region and a low pixel density region, and sets a row driving circuit in the transition region, the row driving circuit in the transition region can be used to drive the first display region, the second display region, and a plurality of pixels in the transition region for display. The display substrate does not need to set an additional region for placing the row driving circuit outside the low pixel density region. On the one hand, the frame width of the display substrate can be reduced, and on the other hand, the problem that the row driving circuit cannot be set in the four corner regions of the four-curved screen design due to the opening pattern can be solved. Therefore, the display device has a narrower frame width and can realize a four-curved screen design.

[0122] For example, the display device mentioned above may be an electronic product with a display function, such as a television, a mobile phone, a computer, a navigator, an electronic picture frame, etc.

[0123] There are a few points to note:

[0124] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0125] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0126] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: A first display area; A second display area, located on at least one side of the first display area in the first direction; as well as a transition area, located between the first display area and the second display area, The first display area, the second display area and the transition area are provided with a plurality of pixels, the plurality of pixels are arranged in an array along the first direction and a second direction intersecting the first direction, and the pixel density of the first display area is greater than the pixel density of the second display area and the pixel density of the transition area. The transition region is further provided with a row driving circuit, and the row driving circuit is configured to drive the plurality of pixels in the first display region, the second display region and the transition region in rows, The row driving circuit comprises a plurality of row driving circuit units arranged along the second direction, each of the pixels comprises a plurality of sub-pixels, each of the sub-pixels comprises a pixel driving circuit and a driving electrode electrically connected to the pixel driving circuit, and the transition region comprises: a plurality of pixel circuit islands, each of the pixel circuit islands is provided with a plurality of the pixel driving circuits of at least one of the pixels; a plurality of first spacing areas, each of the first spacing areas is located between two adjacent pixel circuit islands in the first direction; and at least one driving spacing area, each of the driving spacing areas is also located between two adjacent pixel circuit islands in the first direction, and the row driving circuit unit is provided in the driving spacing area; The transition area also includes: a plurality of driving electrode islands, arranged corresponding to the plurality of pixel circuit islands, each of the driving electrode islands being provided with a plurality of the driving electrodes of at least one of the pixels; and A plurality of second spacing regions, each of the second spacing regions is located between two adjacent driving electrode islands in the first direction.

2. The display substrate according to claim 1, wherein: The widths of the plurality of first spacing regions in the first direction are equal, the widths of the plurality of second spacing regions in the first direction are equal, and the width of the first spacing region in the first direction is smaller than the width of the driving spacing region in the first direction.

3. The display substrate according to claim 1, wherein: The widths of the multiple first spacing areas in the first direction are equal, the widths of the multiple second spacing areas in the first direction are equal, the width of the second spacing areas in the first direction is 0.5-1.5 times that of the driving spacing areas, and the width of the first spacing areas in the first direction is smaller than the width of the driving spacing areas in the first direction.

4. The display substrate according to claim 1, wherein: The row driving circuit unit includes a first row driving circuit unit and a second row driving circuit unit, the first row driving circuit unit has an output end, and the output end of the first row driving circuit unit is configured to simultaneously drive multiple pixels belonging to the same row in the first display area, the second display area and the transition area.

5. The display substrate according to claim 1, further comprising: A plurality of connecting electrode structures are located on one side of the plurality of driving electrode islands close to the pixel circuit island in a direction perpendicular to the transition region, Among them, the multiple connecting electrode structures are arranged one by one corresponding to the multiple driving electrode islands and the multiple pixel circuit islands, and each connecting electrode structure includes multiple connecting electrodes to electrically connect the multiple pixel driving circuits in the corresponding pixel circuit island with the multiple driving electrodes in the corresponding driving electrode island.

6. The display substrate according to claim 5, wherein: The pixel driving unit comprises a driving transistor, and the driving transistor is arranged on the film layer where the driving electrode is located in an orthogonal projection and is spaced apart from the corresponding driving electrode.

7. The display substrate according to claim 6, wherein: The row driving circuit includes a gate driving circuit and a light emitting control driving circuit, and the row driving circuit unit includes a gate driving unit and a light emitting control unit. The at least one driving interval area includes two driving interval areas, one of the two driving interval areas is provided with the gate driving unit, and the other of the two driving interval areas is provided with the light emitting control unit.

8. The display substrate according to claim 7, wherein: At least two of the first spacing areas are spaced between two of the driving spacing areas.

9. The display substrate according to claim 7, wherein: The light emitting control unit comprises: A first transistor, wherein a gate of the first transistor is connected to a first clock signal line to receive a first clock signal, a first electrode of the first transistor is connected to a first node, and a second electrode of the first transistor is connected to an input terminal; a second transistor, wherein a gate of the second transistor is connected to the first node, a first electrode of the second transistor is connected to the second node, and a second electrode of the second transistor is connected to the first clock signal line to receive the first clock signal; a third transistor, wherein a gate of the third transistor is connected to the first clock signal line to receive the first clock signal, a first electrode of the third transistor is connected to the second node, and a second electrode of the third transistor is connected to the first power line to receive a first voltage; a fourth transistor, wherein a gate of the fourth transistor is connected to the second clock signal line to receive a second clock signal, a first electrode of the fourth transistor is connected to the first node, and a second electrode of the fourth transistor is connected to a second electrode of the fifth transistor; The fifth transistor, wherein a gate of the fifth transistor is connected to the second node, and a first electrode of the fifth transistor is connected to a second power line to receive a second voltage; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second clock signal line to receive the second clock signal, and a second electrode of the sixth transistor is connected to the third node; a seventh transistor, wherein a gate of the seventh transistor is connected to the second clock signal line to receive the second clock signal, a first electrode of the seventh transistor is connected to the third node, and a second electrode of the seventh transistor is connected to the fourth node; an eighth transistor, wherein a gate of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to the fourth node, and a second electrode of the eighth transistor is connected to the second power line to receive the second voltage; a ninth transistor, wherein a gate of the ninth transistor is connected to the fourth node, a first electrode of the ninth transistor is connected to the second power line to receive the second voltage, and a second electrode of the ninth transistor is connected to an output terminal; a tenth transistor, wherein a first electrode of the tenth transistor is connected to the first power line to receive the first voltage, and a second electrode of the tenth transistor is connected to the output terminal; A first capacitor, wherein a second electrode of the first capacitor is connected to the third node; a second capacitor, wherein a second electrode of the second capacitor is connected to the second clock signal line to receive the second clock signal; and A third capacitor, wherein a first electrode of the third capacitor is connected to the fourth node, and a second electrode of the third capacitor is connected to the second power line to receive the second voltage.

10. The display substrate according to claim 9, wherein: The ninth transistor and the tenth transistor are disposed spaced apart from the plurality of connection electrode structures in their orthographic projection on the film layer where the plurality of connection electrode structures are located.

11. The display substrate according to claim 7, wherein: The gate driving unit includes: an input transistor, a first control transistor, a second control transistor, an output control transistor, a gate output transistor, a first noise reduction transistor, a second noise reduction transistor, a voltage stabilizing transistor, a first scanning capacitor, and a second scanning capacitor. Wherein, the gate of the input transistor is connected to the third clock signal line, the second electrode of the input transistor is connected to the input terminal, and the first electrode of the input transistor is connected to the first scanning node; The gate of the first control transistor is connected to the first scan node, the second electrode of the first control transistor is connected to the third clock signal line, and the first electrode of the first control transistor is connected to the second scan node; The gate of the second control transistor is connected to the third clock signal line, the second electrode of the second control transistor is connected to the third power supply line, and the first electrode of the second control transistor is connected to the second scanning node; The gate of the output control transistor is connected to the second scanning node, the first electrode of the output control transistor is connected to the fourth power line, and the second electrode of the output control transistor is connected to the output end; A first electrode of the first scanning capacitor is connected to the second scanning node, and a second electrode of the first scanning capacitor is connected to the fourth power line; The gate of the gate output transistor is connected to the third scanning node, the first electrode of the gate output transistor is connected to the second clock sub-signal line, and the second electrode of the gate output transistor is connected to the output end; A first electrode of the second scanning capacitor is connected to the third scanning node, and a second electrode of the second scanning capacitor is connected to the output end; The gate of the first noise reduction transistor is connected to the second scanning node, the first electrode of the first noise reduction transistor is connected to the fourth power line, and the second electrode of the first noise reduction transistor is connected to the second electrode of the second noise reduction transistor; A gate of the second noise reduction transistor is connected to a fourth clock signal line, and a first electrode of the second noise reduction transistor is connected to the first scanning node; and The gate of the voltage stabilizing transistor is connected to the third power line, the second electrode of the voltage stabilizing transistor is connected to the first scanning node, and the first electrode of the voltage stabilizing transistor is connected to the third scanning node.

12. The display substrate according to claim 11, wherein: The orthographic projections of the output control transistor and the gate output transistor on the film layer where the plurality of connection electrode structures are located are spaced apart from the plurality of connection electrode structures.

13. The display substrate according to claim 7, further comprising: a plurality of first driving lines, configured to drive the plurality of gate driving units, Wherein, the multiple gate driving units are staggered in the first direction, each of the first driving lines includes a first part extending along the second direction and a second part extending along the first direction, the first part is connected to the corresponding gate driving unit, and the second part connects the first parts of two adjacent gate driving units.

14. The display substrate according to claim 13, further comprising: The data line, the first portion and the data line are located in a first source-drain metal layer, and the second portion is located in a second source-drain metal layer.

15. The display substrate according to claim 13, wherein: Each of the first driving lines is in a step shape.

16. The display substrate according to claim 7, further comprising: a plurality of second driving lines, configured to drive the plurality of light emitting control units, Among them, the multiple light-emitting control units are staggered in the first direction, and each of the second driving lines includes a third part extending along the second direction and a fourth part extending along the first direction, the third part is connected to the corresponding light-emitting control unit, and the fourth part connects the third parts of two adjacent light-emitting control units. 17 . The display substrate according to claim 16 , further comprising a data line, wherein the third portion and the data line are located in a first source-drain metal layer, and the fourth portion is located in a second source-drain metal layer.

18. The display substrate according to claim 16, wherein: Each of the second driving lines is in a step shape.

19. The display substrate according to any one of claims 1 to 18, wherein: A portion of the display substrate located in the second display area is bent in a direction perpendicular to the first display area.

20. The display substrate according to any one of claims 1 to 18, further comprising: a third display area, located on one side of the first display area in the second direction, Among them, a plurality of the pixels are arranged in the third display area, the pixel density of the third display area is substantially equal to the pixel density of the first display area, and the orthographic projection of the third display area on the reference line extending along the first direction overlaps with the orthographic projections of the first display area, the second display area and the transition area on the reference line.

21. The display substrate according to any one of claims 1 to 18, wherein: The second display area includes: A plurality of pixel islands are arranged in an array along the first direction and the second direction, each of the pixel islands comprising at least one pixel; a first opening extending along the first direction and located between two adjacent pixel islands in the second direction; and The second opening extends along the second direction and is located between two adjacent pixel islands in the first direction.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

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