Display substrate and manufacturing method thereof, and display device

Abstract

The present disclosure provides a display substrate and a manufacturing method thereof, and a display device. The display substrate includes: a display area and a non-display area surrounding the display area, the non-display area includes a packaging glue area surrounding the display area; the display substrate also includes: a packaging base layer and a fan-out layer; the packaging base layer is located in the packaging glue area; the fan-out layer is located in the non-display area, the fan-out layer includes a first multiplexing part, the orthographic projection of the first multiplexing part on the substrate of the display substrate at least partially overlaps with the orthographic projection of the first target area of ​​the packaging glue area on the substrate, and the first multiplexing part is multiplexed into the packaging base layer located in the first target area.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] In organic light-emitting diode (OLED) devices, the metal film layer and the organic functional layer are extremely sensitive to water vapor and oxygen. If water vapor and oxygen penetrate into the device, the device will age, the performance will deteriorate, and the luminous life of the device will be greatly shortened. Moreover, if water vapor and oxygen penetrate into the device, the organic matter and cathode in the device will oxidize, causing the luminous area of ​​the device to shrink, and even non-luminous areas to appear in the luminous area. Therefore, OLED display devices need to be encapsulated.

[0003] At present, the packaging method commonly used for flexible OLED devices is thin film packaging (English: Thin Film Encapsulation, referred to as: TFE), while the packaging method commonly used for rigid OLED devices is Frit packaging. Summary of the invention

[0004] The purpose of the present disclosure is to provide a display substrate and a manufacturing method thereof, and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a display area and a non-display area surrounding the display area, wherein the non-display area comprises a packaging glue area surrounding the display area; the display substrate further comprises:

[0007] A packaging base layer, wherein the packaging base layer is located in the packaging glue area;

[0008] A fan-out layer, wherein the fan-out layer is located in the non-display area, and the fan-out layer includes a first multiplexing part, wherein the orthographic projection of the first multiplexing part on the base of the display substrate at least partially overlaps with the orthographic projection of the first target area of ​​the packaging glue area on the base, and the first multiplexing part is multiplexed into a packaging base layer located in the first target area.

[0009] Optionally, the display substrate further includes: a first via structure, the first via structure is located in the first target area, and the first via structure can make the surface of the display substrate in the first target area facing away from the substrate uneven.

[0010] Optionally, the display substrate further comprises: at least two layers of a first gate insulating layer, a second gate insulating layer and an interlayer insulating layer stacked sequentially on the substrate in a direction away from the substrate;

[0011] The first via structure includes a plurality of first vias, and the first vias penetrate at least one of the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.

[0012] Optionally, the fan-out layer includes a plurality of fan-out lines, the plurality of fan-out lines include the first multiplexing part, and an orthographic projection of the fan-out lines on the substrate does not overlap with an orthographic projection of the first via structure on the substrate.

[0013] Optionally, the plurality of first via holes are divided into a plurality of via hole groups, and orthographic projections of the via hole groups on the substrate and orthographic projections of the fan-out lines on the substrate are alternately arranged along a first direction.

[0014] Optionally, the plurality of fan-out lines are located between the first gate insulating layer and the interlayer insulating layer.

[0015] Optionally, the plurality of fan-out lines include a plurality of first fan-out lines and a plurality of second fan-out lines, the plurality of first fan-out lines are located between the first gate insulation layer and the second gate insulation layer, and the plurality of second fan-out lines are located between the second gate insulation layer and the interlayer insulation layer;

[0016] The plurality of first fan-out lines and the plurality of second fan-out lines each include the first multiplexing portion.

[0017] Optionally, at least a portion of the encapsulation substrate layer is located between the first gate insulating layer and the second gate insulating layer.

[0018] Optionally, the display substrate further includes: a first power line and a second power line arranged in the non-display area;

[0019] The first power line comprises: a transmission portion and two first inlet portions, the transmission portion extends along a first direction, and at least a portion of the first inlet portion extends along a second direction; two ends of the transmission portion are respectively coupled to the two first inlet portions, the transmission portion is located between the display area and the first inlet portions, and the first direction intersects with the second direction;

[0020] The second power line includes: a peripheral portion and two second line inlet portions; the peripheral portion surrounds the display area, the peripheral portion has an opening, two ends of the peripheral portion at the opening are connected to the two second line inlet portions in a one-to-one correspondence, and at least a portion of the second line inlet portion extends along the second direction;

[0021] The orthographic projections of the two first line-inlet portions on the substrate are both located between the orthographic projections of the two second line-inlet portions on the substrate.

[0022] Optionally, the non-display area includes two corner areas arranged along the first direction, two second line-in portions correspond one-to-one to the two corner areas, and at least part of the second line-in portions is located in the corresponding corner areas.

[0023] Optionally, the first line feed portion includes a second multiplexing part, the orthographic projection of the second multiplexing part on the substrate at least partially overlaps with the orthographic projection of the second target area of ​​the packaging glue area on the substrate, and the second multiplexing part is multiplexed into a packaging substrate layer located in the second target area.

[0024] Optionally, the second line feed portion includes a third multiplexing part, the orthographic projection of the third multiplexing part on the substrate at least partially overlaps with the orthographic projection of the third target area of ​​the packaging glue area on the substrate, and the third multiplexing part is multiplexed into a packaging substrate layer located in the third target area.

[0025] Optionally, a plurality of second via holes are arranged on the second multiplexing part and / or the third multiplexing part.

[0026] Optionally, the display substrate further includes:

[0027] A gate driving circuit, wherein the gate driving circuit is located at two opposite sides of the display area along a first direction;

[0028] A plurality of first signal lines, wherein the plurality of first signal lines and the first power line are located on the same side of the display area, and the plurality of first signal lines are connected to the gate drive circuit to provide corresponding signals to the gate drive circuit; the first signal line comprises a fourth multiplexing portion, and an orthographic projection of the fourth multiplexing portion on the substrate at least partially overlaps with an orthographic projection of a fourth target area of ​​the packaging glue area on the substrate, and the fourth multiplexing portion is multiplexed into a packaging substrate layer located in the fourth target area.

[0029] Optionally, the packaging substrate layer includes:

[0030] at least two first encapsulation parts, the orthographic projections of the at least two first encapsulation parts on the substrate are located between the orthographic projections of the two first line-inlet parts on the substrate, the at least two first encapsulation parts are arranged along the first direction, and the first target area is defined between adjacent first encapsulation parts;

[0031] A surrounding encapsulation portion surrounds other sides of the display area except the side where the first encapsulation portion is located.

[0032] Optionally, the first packaging portion is coupled to the first power line; and the surrounding packaging portion is coupled to the second power line.

[0033] Optionally, the packaging substrate layer further includes:

[0034] A plurality of first conductive connection parts, wherein the plurality of first conductive connection parts and the first packaging part form an integrated structure, and the first packaging part is respectively coupled to the transmission part through the plurality of first conductive connection parts.

[0035] Optionally, the packaging substrate layer further includes:

[0036] A plurality of second conductive connection parts, wherein the plurality of second conductive connection parts and the surrounding packaging part form an integral structure;

[0037] A plurality of protrusions are disposed on the edge of the peripheral portion and / or the second line-inlet portion, and the surrounding packaging portion is coupled to at least some of the protrusions via the plurality of second conductive connection portions.

[0038] Optionally, a plurality of third via holes are provided on the first packaging portion and / or the surrounding packaging portion;

[0039] The display substrate is also provided with a plurality of groups of third sub-vias corresponding one-to-one to the plurality of third vias, each group of third sub-vias includes a plurality of third sub-vias, the orthographic projections of the plurality of third sub-vias on the substrate are located inside the orthographic projections of the corresponding third vias on the substrate, and the third sub-vias penetrate at least one of the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer.

[0040] Optionally, a diameter of the first via hole is smaller than a diameter of the third via hole.

[0041] Optionally, the display substrate comprises: a first gate insulating layer, a second gate insulating layer and an interlayer insulating layer which are sequentially stacked on the substrate in a direction away from the substrate;

[0042] The third sub-via hole penetrates the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer at the same time.

[0043] Based on the technical solution of the display substrate, a second aspect of the present disclosure provides a display device, comprising the above-mentioned display substrate.

[0044] Optionally, the display device further comprises a packaging cover plate arranged opposite to the display substrate, and the packaging cover plate and the display substrate are sealed by a frame sealing adhesive arranged in a packaging adhesive area.

[0045] Based on the technical solution of the display substrate, the third aspect of the present disclosure provides a method for manufacturing a display substrate, wherein the display substrate comprises: a display area and a non-display area surrounding the display area, wherein the non-display area comprises a packaging glue area surrounding the display area; the manufacturing method comprises:

[0046] Making a packaging base layer, wherein the packaging base layer is located in the packaging glue area;

[0047] A fan-out layer is manufactured, wherein the fan-out layer is located in the non-display area, and the fan-out layer includes a first multiplexing part, wherein an orthographic projection of the first multiplexing part on the base of the display substrate at least partially overlaps with an orthographic projection of a first target area of ​​the packaging glue area on the base, and the first multiplexing part is multiplexed into a packaging base layer located in the first target area. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure. In the drawings:

[0049] Figure 1 A schematic diagram of a packaging structure of a display substrate provided in an embodiment of the present disclosure;

[0050] Figure 2 A schematic diagram of the overall structure of a display substrate provided in an embodiment of the present disclosure;

[0051] Figure 3 A schematic diagram of the lower frame structure of a display substrate provided in an embodiment of the present disclosure;

[0052] Figure 4 for Figure 3 A magnified schematic diagram of part A;

[0053] Figure 5 for Figure 3 Schematic diagram of the fan-out lines near the middle A part;

[0054] Figure 6 A schematic diagram of the distribution of the first multiplexing part and the first via provided in an embodiment of the present disclosure;

[0055] Figure 7 for Figure 4 A schematic diagram of a first packaging portion;

[0056] Figure 8 A cross-sectional schematic diagram of a first via structure provided in an embodiment of the present disclosure;

[0057] Fig. 9 A schematic diagram of filling Frit glue in a first via structure provided in an embodiment of the present disclosure;

[0058] Fig.10 It is a schematic diagram of a cross section of Frit glue packaging in the related art;

[0059] Fig.11 A schematic cross-sectional view of a Frit glue package provided in an embodiment of the present disclosure;

[0060] Fig.12 for Figure 3 A magnified schematic diagram of part B;

[0061] Fig.13 for Figure 3 A magnified schematic diagram of part C;

[0062] Fig.14 A schematic diagram of a fan-out layer and a first packaging unit provided in an embodiment of the present disclosure;

[0063] Fig.15 for Fig.14 The enlarged schematic diagram of part D in the middle;

[0064] Fig.16 for Fig.14 Enlarged schematic diagram of part E in the middle. DETAILED DESCRIPTION

[0065] In order to further illustrate the display substrate and its manufacturing method, and the display device provided by the embodiments of the present disclosure, a detailed description is given below in conjunction with the accompanying drawings.

[0066] like Figure 1 As shown, the present disclosure provides a display panel, which includes: a substrate 30, an OLED device 40 arranged on the substrate 30, a plurality of spacers 50 arranged on the OLED device 40, and a cover plate 60 arranged on a side of the plurality of spacers 50 facing away from the substrate 30, wherein the cover plate 60 and the substrate 30 are bonded by Frit glue 70 to achieve encapsulation of the OLED device.

[0067] In the display panel provided by the present disclosure, the Frit packaging process is used for packaging, which not only simplifies the packaging process but also ensures the light output rate of the display panel when the display panel adopts a top-emitting structure.

[0068] However, when packaging the above display panel, the curing effect of the Frit glue and the bonding performance between the Frit glue and the substrate need to be improved.

[0069] See also Figure 2 , Figure 4 , Figure 6 , Figure 8 , Fig. 9 , Figures 14 to 16The embodiment of the present disclosure provides a display substrate, comprising: a display area 1 and a non-display area 2 surrounding the display area 1, wherein the non-display area 2 comprises a packaging glue area 20 surrounding the display area 1; the display substrate further comprises:

[0070] A packaging base layer, the packaging base layer is located in the packaging glue area 20;

[0071] A fan-out layer 22, wherein the fan-out layer 22 is located in the non-display area 2, and the fan-out layer 22 includes a first reused portion 220, wherein the orthographic projection of the first reused portion 220 on the base of the display substrate at least partially overlaps with the orthographic projection of the first target area of ​​the packaging glue area 20 on the base, and the first reused portion 220 is reused as a packaging base layer located in the first target area.

[0072] Exemplarily, the display substrate includes a display area 1 and a non-display area 2 . Exemplarily, the display area 1 includes a circle and a rectangle, and the non-display area 2 completely surrounds the display area 1 .

[0073] Exemplarily, the encapsulation base layer includes a metal layer with good reflective properties. Exemplarily, the encapsulation base layer includes: a first gate metal layer with good reflective properties, and part of the first gate insulating layer, part of the second gate insulating layer and part of the interlayer insulating layer in the display substrate. Exemplarily, the encapsulation base layer surrounds the display area 1. Exemplarily, the encapsulation base layer is arranged in the edge area of ​​the non-display area 2 away from the display area 1, so that after encapsulation, other functional structures arranged in the non-display area 2 can be surrounded.

[0074] Exemplarily, the fan-out layer 22 is located at the lower frame of the display substrate. Exemplarily, the display substrate also includes a driver chip disposed in the non-display area 2, and the fan-out layer 22 is used to connect the partial functional layer located in the display area 1 and the driver chip to achieve signal transmission between the partial functional layer and the driver chip.

[0075] Exemplarily, the encapsulation glue area 20 includes a first target area, and the orthographic projection of the first multiplexing portion 220 on the base of the display substrate is located inside the orthographic projection of the first target area of ​​the encapsulation glue area 20 on the base. Exemplarily, the first multiplexing portion 220 is multiplexed as an encapsulation base layer located in the first target area, that is, there is no need to additionally manufacture a dedicated encapsulation base layer in the first target area.

[0076] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present disclosure, by setting the encapsulation base layer in the encapsulation glue area 20, the curing effect of the Frit glue when encapsulating the display substrate is better improved. Moreover, by setting the first reuse part 220 to reuse the encapsulation base layer located in the first target area, the production of a large-area encapsulation base layer is avoided, and the production cost of the display substrate is effectively reduced.

[0077] In addition, since the morphology of the fan-out line layer itself will produce step differences, the surface of the display substrate in the first target area that is back to the base is uneven. In this way, when the display substrate is Frit packaged, the contact area between the Frit glue and the display substrate can be effectively increased, and the bonding performance between the Frit glue and the display substrate can be improved, thereby better improving the packaging capability and achieving good water vapor and oxygen barrier properties and sealing effects.

[0078] In some embodiments, the display substrate further includes: a first via structure 23, the first via structure 23 is located in the first target area, and the first via structure 23 can make the surface of the display substrate in the first target area facing away from the substrate uneven.

[0079] Exemplarily, the first via structure 23 includes a plurality of independent first vias 230, and the plurality of first vias 230 are distributed in the first target area. The first vias 230 can penetrate at least a portion of the insulating layer located in the first target area, so that the surface of the display substrate in the first target area facing away from the substrate is uneven.

[0080] like Fig.10 and Fig.11 As shown, in the display substrate provided in the above embodiment, by setting the first via structure 23 in the first target area, the surface of the display substrate in the first target area that is back to the base is uneven, so that when the display substrate is Frit packaged, the contact area between the Frit glue and the display substrate can be effectively increased, and the bonding performance between the Frit glue and the display substrate can be improved, thereby better improving the packaging capability and achieving good water vapor and oxygen barrier properties and sealing effects.

[0081] like Figure 4 , Figure 6 , Figure 8 and Fig. 9 As shown, in some embodiments, the display substrate further includes: at least two layers of a first gate insulating layer GI1, a second gate insulating layer GI2 and an interlayer insulating layer ILD disposed on the substrate are sequentially stacked in a direction away from the substrate;

[0082] The first via structure 23 includes a plurality of first vias 230 , and the first vias 230 penetrate at least one of the first gate insulating layer GI1 , the second gate insulating layer GI2 , and the interlayer insulating layer ILD.

[0083] Exemplarily, the display substrate includes a buffer layer 80, an active layer, a first gate insulating layer GI1, a first gate metal layer, a second gate insulating layer GI2, a second gate metal layer, an interlayer insulating layer ILD, a first source-drain metal layer, a planar layer, an anode layer, a light-emitting functional layer, and a cathode layer, which are sequentially stacked in a direction away from the base. Exemplarily, the display substrate may also include an interlayer insulating layer ILD and a second source-drain metal layer located between the first source-drain metal layer and the planar layer, and the second source-drain metal layer is located between the interlayer insulating layer ILD and the planar layer.

[0084] Exemplarily, the display substrate includes a sub-pixel driving circuit, the sub-pixel driving circuit includes a transistor and a capacitor, the active layer is used to form an active pattern in the transistor, the first gate metal layer is used to form a gate of the transistor and a plate of the capacitor, the second gate metal layer is used to form a plate of the capacitor, and the first source and drain metal layer is used to form a data line and some conductive connecting parts, etc.

[0085] Exemplarily, the display substrate includes a buffer layer 80, an active layer, a first gate insulating layer GI1, a first gate metal layer, an interlayer insulating layer ILD, a first source-drain metal layer, a flat layer, an anode layer, a light-emitting functional layer and a cathode layer, which are stacked in sequence in a direction away from the base. Exemplarily, the display substrate may also include an interlayer insulating layer ILD and a second source-drain metal layer located between the first source-drain metal layer and the flat layer, and the second source-drain metal layer is located between the interlayer insulating layer ILD and the flat layer. It is worth noting that in this case, the display substrate does not include a second gate metal layer and a second gate insulating layer GI2.

[0086] Exemplarily, the plurality of first via holes 230 are evenly distributed in the first target area.

[0087] Exemplarily, the first via 230 only penetrates the interlayer insulating layer ILD, and the orthographic projection of the first via 230 on the substrate overlaps or does not overlap with the orthographic projection of the fan-out layer 22 on the substrate. Exemplarily, the first via 230 penetrates the interlayer insulating layer ILD and the second gate insulating layer GI2 at the same time, and the orthographic projection of the first via 230 on the substrate does not overlap with the orthographic projection of the fan-out layer 22 on the substrate. Exemplarily, the first via 230 penetrates the interlayer insulating layer ILD, the second gate insulating layer GI2 and the first gate insulating layer GI1 at the same time, and the orthographic projection of the first via 230 on the substrate does not overlap with the orthographic projection of the fan-out layer 22 on the substrate.

[0088] Exemplarily, the size of the first via hole 230 includes 6 μm×6 μm, and the length and width of the first via hole 230 can be selected in the range of 1 μm to 10 μm, including end value.

[0089] The above-mentioned first via structure 23 includes a plurality of first vias 230, so that the depth of the first via 230 determines the depth of the depression of the surface of the display substrate in the first target area that is back to the base. The deeper the depression, the larger the contact area between the Frit glue and the display substrate during packaging, which is more conducive to improving the bonding performance between the Frit glue and the display substrate.

[0090] like Figures 2 to 6 , Figure 8 and Fig. 9 As shown, in some embodiments, the fan-out layer 22 includes multiple fan-out lines 221, and the multiple fan-out lines 221 include the first multiplexing part 220, and the orthographic projection of the fan-out lines 221 on the substrate does not overlap with the orthographic projection of the first via structure 23 on the substrate.

[0091] Exemplarily, the display substrate includes multiple gate lines and multiple data lines, the gate lines extend along a first direction, the data lines extend along a second direction, the first direction intersects with the second direction, and at least part of the gate lines and at least part of the data lines are located in the display area 1.

[0092] Exemplarily, the fan-out layer 22 includes a plurality of fan-out lines 221 , and the fan-out lines 221 can be coupled to corresponding data lines for transmitting data signals to the data lines.

[0093] Exemplarily, each fan-out line 221 includes a first segment and a second segment coupled to each other, the second segment is located between the display area 1 and the first segment, and the second segment is coupled to the corresponding data line. Exemplarily, the first segment extends along the second direction, and the second segment includes a portion extending along a third direction, and the third direction intersects both the first direction and the second direction. Exemplarily, the second segments included in the plurality of fan-out lines 221 are formed into a fan-shaped structure.

[0094] Exemplarily, the first section of each of the fan-out lines 221 includes the first multiplexing portion 220 .

[0095] It is worth noting that the line width of the fan-out lines 221 and the spacing between adjacent fan-out lines 221 can be set according to actual process requirements.

[0096] The above-mentioned setting of the orthographic projection of the fan-out line 221 on the substrate does not overlap with the orthographic projection of the first via structure 23 on the substrate, which can avoid the first via structure 23 from causing damage to the fan-out line 221 during the formation process, thereby well ensuring the reliability of the display substrate.

[0097] like Figure 4 As shown, in some embodiments, the plurality of first vias 230 are divided into a plurality of via groups 231 , and the orthographic projections of the via groups on the substrate and the orthographic projections of the fan-out lines 221 on the substrate are alternately arranged along a first direction.

[0098] Exemplarily, the plurality of first via holes 230 are divided into a plurality of via hole groups 231 , and each via hole group 231 includes a plurality of first via holes 230 arranged along the second direction.

[0099] Exemplarily, the via group 231 is divided into a plurality of sub-via groups 232 arranged along the second direction, each sub-via group 232 includes at least two first vias 230, and the sub-via groups 232 located on both sides of the same fan-out line 221 are staggered along the first direction. Exemplarily, in one sub-via group 232, the minimum distance between adjacent first vias 230 in the second direction is smaller than the minimum distance between two adjacent sub-via groups 232 in the second direction.

[0100] The above-mentioned arrangement of the orthographic projection of the via group on the substrate and the orthographic projection of the fan-out line 221 on the substrate are alternately arranged along the first direction, so that the first via structure 23 can be arranged in the gap between the fan-out lines 221, so that the first via 230 can be evenly distributed in the first target area, which is beneficial to improving the overall bonding performance of the Frit glue in the first target area.

[0101] like Figure 8 As shown, in some embodiments, the plurality of fan-out lines 221 are located between the first gate insulating layer GI1 and the interlayer insulating layer ILD.

[0102] like Figure 8 As shown, in some embodiments, the plurality of fan-out lines 221 are located between the first gate insulating layer GI1 and the second gate insulating layer GI2.

[0103] Exemplarily, the multiple fan-out lines 221 are made of the first gate metal layer, that is, the multiple fan-out lines 221 are made of the same layer and material as the gate of the transistor. The multiple fan-out lines 221 and the gate of the transistor can be formed in the same patterning process, which is conducive to simplifying the production process of the display substrate and reducing the production cost.

[0104] In some embodiments, the plurality of fan-out lines 221 include a plurality of first fan-out lines and a plurality of second fan-out lines, the plurality of first fan-out lines are located between the first gate insulation layer GI1 and the second gate insulation layer GI2, and the plurality of second fan-out lines are located between the second gate insulation layer GI2 and the interlayer insulation layer ILD;

[0105] The plurality of first fan-out lines and the plurality of second fan-out lines each include the first multiplexing portion 220 .

[0106] Exemplarily, the plurality of first fan-out lines are made of the first gate metal layer, and the plurality of second fan-out lines are made of the second gate metal layer. This arrangement enables the plurality of first fan-out lines to be formed in the same patterning process as the gate of the transistor, and enables the plurality of second fan-out lines to be formed in the same patterning process as the plate of the capacitor, thereby better simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0107] Exemplarily, the orthographic projection of the first fan-out line on the substrate and the orthographic projection of the second fan-out line on the substrate are alternately arranged along the first direction. Exemplarily, in the adjacent first fan-out line and the second fan-out line, the orthographic projection of the first fan-out line on the substrate and the orthographic projection of the second fan-out line on the substrate at least partially overlap. Exemplarily, in the adjacent first fan-out line and the second fan-out line, the orthographic projection of the first fan-out line on the substrate and the orthographic projection of the second fan-out line on the substrate have a spacing area, and at least part of the orthographic projection of the first via 230 on the substrate is located in the spacing area.

[0108] In the display substrate provided by the above embodiment, by setting the plurality of fan-out lines 221 to include a plurality of first fan-out lines and a plurality of second fan-out lines, the spacing between adjacent fan-out lines 221 can be effectively reduced, which is beneficial to reducing the height of the fan-out layer 22 in the second direction.

[0109] like Figure 8 As shown, in some embodiments, at least a portion of the encapsulation substrate layer (such as reference numeral 210 ) is located between the first gate insulating layer GI1 and the second gate insulating layer GI2 .

[0110] Exemplarily, at least a portion of the packaging base layer is made of the first gate metal layer, so that at least a portion of the packaging base layer can be formed in the same patterning process as other functional film layers made of the first gate metal layer, thereby better simplifying the production process of the display substrate and reducing the production cost of the display substrate.

[0111] like Figure 2 , Figure 3 , Fig.12 and Fig.13 As shown, in some embodiments, the display substrate further includes: a first power line and a second power line disposed in the non-display area 2;

[0112] The first power line includes: a transmission portion 240 and two first inlet portions 241, the transmission portion 240 extends along a first direction, and at least a portion of the first inlet portions 241 extends along a second direction; two ends of the transmission portion 240 are respectively coupled to the two first inlet portions 241, the transmission portion 240 is located between the display area 1 and the first inlet portions 241, and the first direction intersects with the second direction;

[0113] The second power line includes: a peripheral portion 250 and two second line inlet portions 251; the peripheral portion 250 surrounds the display area 1, the peripheral portion 250 has an opening, two ends of the peripheral portion 250 at the opening are connected to the two second line inlet portions 251 in a one-to-one correspondence, and at least a portion of the second line inlet portions 251 extends along the second direction;

[0114] The orthographic projections of the two first line inlet portions 241 on the substrate are both located between the orthographic projections of the two second line inlet portions 251 on the substrate.

[0115] Exemplarily, the first power line includes a positive power signal line VDD. The second power line includes a negative power signal line VSS. Exemplarily, the first power line is coupled to the positive power line in the display area 1 to provide a VDD signal to the positive power line in the display area 1; the second power line is coupled to the cathode of the display substrate to provide a VSS signal to the cathode.

[0116] Exemplarily, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0117] Exemplarily, the first power line includes a transmission portion 240 and two first inlet portions 241, the transmission portion 240 includes a strip structure, the transmission portion 240 extends along the first direction, and both ends of the transmission portion 240 can extend to two opposite corner areas of the display substrate along the first direction. Exemplarily, an opening is formed on the transmission portion 240 and / or the first inlet portion 241.

[0118] Exemplarily, at least a portion of the first incoming line portion 241 extends along the second direction, and the first incoming line portion 241 is respectively coupled to one end of the transmission portion 240 and a driving chip of the display substrate.

[0119] Exemplarily, the transmission portion 240 and the first line feeder portion 241 are formed as an integral structure. Exemplarily, the transmission portion 240 and the first line feeder portion 241 are made of the first source-drain metal layer.

[0120] Exemplarily, the peripheral portion 250 extends along the left frame, the upper frame and the lower frame of the display substrate, and forms an opening at the lower frame of the display substrate.

[0121] Exemplarily, at least a portion of the second line-in portion 251 extends along the second direction, and the second line-in portion 251 is respectively coupled to corresponding ends of the peripheral portion 250 and the chip of the display substrate.

[0122] Exemplarily, the peripheral portion 250 and the second line-in portion 251 are formed into an integral structure. Exemplarily, the peripheral portion 250 and the second line-in portion 251 are both made of the first source-drain metal layer.

[0123] Exemplarily, the orthographic projection of the transmission portion 240 on the substrate and the orthographic projections of the two first line inlet portions 241 on the substrate are both located between the orthographic projections of the two second line inlet portions 251 on the substrate.

[0124] like Figure 2 , Figure 3 , Fig.12 and Fig.13 As shown, in some embodiments, the non-display area 2 includes two corner areas arranged along the first direction, the two second line entry portions 251 correspond one-to-one to the two corner areas, and at least part of the second line entry portions 251 is located in the corresponding corner area.

[0125] Exemplarily, the two corner regions include a lower left corner region and a lower right corner region of the display substrate.

[0126] Exemplarily, the two first line inlet portions 241 correspond to the two corner areas one by one, and at least a portion of the first line inlet portions 241 is located in the corresponding corner area.

[0127] like Figure 2 , Figure 3 , Fig.12 and Fig.13 As shown, in some embodiments, the first line feed portion 241 includes a second multiplexing portion 2410, and the orthographic projection of the second multiplexing portion 2410 on the substrate at least partially overlaps with the orthographic projection of the second target area of ​​the packaging glue area 20 on the substrate, and the second multiplexing portion 2410 is multiplexed as a packaging substrate layer located in the second target area.

[0128] Exemplarily, the encapsulation glue area 20 includes a second target area, and the orthographic projection of the second multiplexing portion 2410 on the base of the display substrate is located inside the orthographic projection of the second target area of ​​the encapsulation glue area 20 on the base. Exemplarily, the second multiplexing portion 2410 is multiplexed as an encapsulation base layer located in the second target area, that is, there is no need to additionally manufacture a dedicated encapsulation base layer in the second target area.

[0129] In the display substrate provided by the above embodiment, the second multiplexing part 2410 is provided to reuse the packaging substrate layer located in the second target area, thereby avoiding the production of a large-area packaging substrate layer and effectively reducing the production cost of the display substrate.

[0130] like Figure 2 , Figure 3 , Fig.12 and Fig.13 As shown, in some embodiments, the second line input portion 251 includes a third multiplexing portion 2510, and the orthographic projection of the third multiplexing portion 2510 on the substrate at least partially overlaps with the orthographic projection of the third target area of ​​the packaging glue area 20 on the substrate, and the third multiplexing portion 2510 is multiplexed as a packaging substrate layer located in the third target area.

[0131] Exemplarily, the encapsulation glue area 20 includes a third target area, and the orthographic projection of the third multiplexing portion 2510 on the base of the display substrate is located inside the orthographic projection of the third target area of ​​the encapsulation glue area 20 on the base. Exemplarily, the third multiplexing portion 2510 is multiplexed as a packaging base layer located in the third target area, that is, there is no need to additionally manufacture a dedicated packaging base layer in the third target area.

[0132] In the display substrate provided by the above embodiment, the third multiplexing part 2510 is provided to reuse the packaging substrate layer located in the third target area, thereby avoiding the production of a large-area packaging substrate layer and effectively reducing the production cost of the display substrate.

[0133] like Fig.12 and Fig.13 As shown, in some embodiments, a plurality of second vias 27 are disposed on the second multiplexing part 2410 and / or the third multiplexing part 2510 .

[0134] Exemplarily, the plurality of second vias 27 are evenly distributed on the second multiplexing portion 2410 and / or the third multiplexing portion 2510 .

[0135] In the display substrate provided in the above embodiment, by providing a plurality of second vias 27 on the second multiplexing part 2410 and / or the third multiplexing part 2510, the contact area between the Frit glue and the second multiplexing part 2410 and / or the third multiplexing part 2510 can be effectively increased, and the bonding performance between the Frit glue and the display substrate can be improved, thereby better improving the packaging capability and achieving good water vapor and oxygen barrier properties and sealing effects.

[0136] like Figure 3 , Fig.12 and Fig.13 As shown, in some embodiments, the display substrate further includes:

[0137] A gate driving circuit, wherein the gate driving circuit is located at two opposite sides of the display area 1 along a first direction;

[0138] A plurality of first signal lines 281, wherein the plurality of first signal lines 281 and the first power line are located on the same side of the display area 1, and the plurality of first signal lines 281 are connected to the gate drive circuit to provide corresponding signals to the gate drive circuit; the first signal lines 281 include a fourth multiplexing portion 2821, and an orthographic projection of the fourth multiplexing portion 2821 on the substrate at least partially overlaps with an orthographic projection of a fourth target area of ​​the packaging glue area 20 on the substrate, and the fourth multiplexing portion 2821 is multiplexed as a packaging substrate layer located in the fourth target area.

[0139] Exemplarily, the display substrate further includes a gate driving circuit GOA, and the gate driving circuit can provide a corresponding scanning signal for the display substrate.

[0140] The specific types of the plurality of first signal lines 281 are various. For example, the plurality of first signal lines 281 include a frame start signal line, a clock signal line, a first level signal line, a second level signal line, etc. The gate drive circuit GOA is located on the left and right sides of the display area 1, and each of the first signal lines 281 is electrically connected to the gate drive circuit GOA and the drive chip in the display substrate.

[0141] Exemplarily, at least a portion of the first signal line 281 and the first power line are located on the same side of the display area 1 .

[0142] Exemplarily, the orthographic projection of the fourth multiplexing part 2821 on the substrate is located between the orthographic projection of the adjacent first line feeder 241 on the substrate and the orthographic projection of the second line feeder 251 on the substrate.

[0143] Exemplarily, the encapsulation glue area 20 includes a fourth target area, and the orthographic projection of the fourth multiplexed portion 2821 on the base of the display substrate is located inside the orthographic projection of the fourth target area of ​​the encapsulation glue area 20 on the base. Exemplarily, the fourth multiplexed portion 2821 is multiplexed as the encapsulation base layer located in the fourth target area, that is, there is no need to additionally manufacture a dedicated encapsulation base layer in the fourth target area.

[0144] In the display substrate provided by the above embodiment, the fourth multiplexing part 2821 is provided to reuse the packaging substrate layer located in the fourth target area, thereby avoiding the production of a large-area packaging substrate layer and effectively reducing the production cost of the display substrate.

[0145] like Figure 2 ,like Figures 13 to 16 As shown, in some embodiments, the packaging substrate layer includes:

[0146] At least two first encapsulation parts 210, the orthographic projections of the at least two first encapsulation parts 210 on the substrate are located between the orthographic projections of the two first inlet parts 241 on the substrate, the at least two first encapsulation parts 210 are arranged along the first direction, and the first target area is defined between adjacent first encapsulation parts 210;

[0147] The surrounding encapsulation portion 211 surrounds the other sides of the display area 1 except the side where the first encapsulation portion 210 is located.

[0148] Exemplarily, the first encapsulation part 210 includes a strip-shaped pattern. Exemplarily, the encapsulation substrate layer includes three first encapsulation parts 210, the three first encapsulation parts 210 are arranged along the first direction, and the first target area is provided between adjacent first encapsulation parts 210, that is, there are two first target areas. Exemplarily, the fan-out lines 221 can be divided into two groups, and the two groups of fan-out lines 221 correspond to the two first target areas one by one, and each group of fan-out lines 221 includes a first multiplexing part 220, and the first multiplexing part 220 in each group of fan-out lines 221 is multiplexed as the encapsulation substrate layer of the corresponding first target area.

[0149] Exemplarily, the surrounding packaging portion 211 surrounds the upper side, the left side and the right side of the display area 1 .

[0150] In the display substrate provided by the above embodiment, the manufacturing area of ​​the packaging base layer is effectively reduced, thereby reducing the manufacturing cost of the display substrate.

[0151] like Fig.12 and Fig.13 As shown, in some embodiments, the first packaging portion 210 is coupled to the first power line; and the surrounding packaging portion 211 is coupled to the second power line.

[0152] The first packaging part 210 is coupled to the first power line so that the first packaging part 210 has the same stable potential as the first power line; similarly, the surrounding packaging part 211 is coupled to the second power line so that the surrounding packaging part 211 has the same stable potential as the second power line; this avoids the first power line and the second power line being in a floating state, thereby better ensuring the working stability of the display substrate.

[0153] In addition, the first packaging part 210 is coupled to the first power line, and the surrounding packaging part 211 is coupled to the second power line, which is equivalent to increasing the area of ​​the first power line and the second power line, thereby effectively reducing the voltage drop generated on the first power line and the second power line.

[0154] like Fig.12 As shown, in some embodiments, the packaging substrate layer further includes:

[0155] A plurality of first conductive connection parts 212 are provided, wherein the plurality of first conductive connection parts 212 and the first packaging part 210 form an integrated structure, and the first packaging part 210 is coupled to the transmission part 240 respectively through the plurality of first conductive connection parts 212 .

[0156] Exemplarily, the plurality of first conductive connection portions 212 are sequentially arranged at intervals along a boundary of the first packaging portion 210 .

[0157] The multiple first conductive connection parts 212 and the first packaging part 210 are arranged to form an integrated structure, so that the multiple first conductive connection parts 212 and the first packaging part 210 can be formed in the same patterning process, which simplifies the production process of the display substrate and reduces the production cost of the display substrate.

[0158] The first packaging part 210 is configured to be coupled to the transmission part 240 respectively through the plurality of first conductive connection parts 212 , so as to better ensure the connection performance between the first packaging part 210 and the transmission part 240 .

[0159] like Fig.13 As shown, in some embodiments, the packaging substrate layer further includes:

[0160] A plurality of second conductive connection parts 213, wherein the plurality of second conductive connection parts 213 and the surrounding packaging part 211 form an integral structure;

[0161] A plurality of protrusions 252 are disposed on the edge of the peripheral portion 250 and / or the second line inlet portion 251 , and the surrounding packaging portion 211 is coupled to at least some of the protrusions 252 via the plurality of second conductive connection portions 213 .

[0162] Exemplarily, the plurality of second conductive connection portions 213 are sequentially spaced apart along a boundary surrounding the packaging portion 211 .

[0163] Exemplarily, the plurality of protrusions 252 form an integral structure with the peripheral portion 250 and / or an edge of the second line feed portion 251 .

[0164] The plurality of second conductive connection parts 213 and the surrounding packaging part 211 are arranged to form an integrated structure, so that the plurality of second conductive connection parts 213 and the surrounding packaging part 211 can be formed in the same patterning process, which simplifies the manufacturing process of the display substrate and reduces the manufacturing cost of the display substrate.

[0165] The surrounding packaging portion 211 is coupled to at least a portion of the protruding portions 252 through the plurality of second conductive connecting portions 213 , thereby better ensuring the connection performance between the surrounding packaging portion 211 and the peripheral portion 250 and / or the second line inlet portion 251 .

[0166] like Figure 4 As shown, in some embodiments, a plurality of third vias 291 are disposed on the first packaging portion 210 and / or the surrounding packaging portion 211;

[0167] The display substrate is also provided with a plurality of groups of third sub-vias 292 corresponding one-to-one to the plurality of third vias 291, each group of third sub-vias 292 includes a plurality of third sub-vias 292, the orthographic projections of the plurality of third sub-vias 292 on the substrate are located inside the orthographic projections of the corresponding third vias 291 on the substrate, and the third sub-vias 292 penetrate at least one of the interlayer insulating layer ILD, the second gate insulating layer GI2 and the first gate insulating layer GI1.

[0168] Exemplarily, the third via 291 and the third sub-via 292 are both rectangular vias, the size of the third via 291 is 40 μm*40 μm, the size of the third sub-via 292 is 6 μm*6 μm, and in a group of third sub-vias 292, the multiple third sub-vias 292 are distributed in an array, and the spacing between adjacent third sub-vias 292 is 3.5 μm.

[0169] Exemplarily, after the display substrate is manufactured and before packaging, the third sub-via 292 can expose the buffer layer 80 of the display substrate, so that when the Frit glue is subsequently formed, the Frit glue can penetrate into the third sub-via 292 and contact the buffer layer 80. After laser sintering, the packaging cover plate and the display substrate can be firmly bonded together.

[0170] Furthermore, the plurality of third via holes 291 and the plurality of third sub-via holes 292 provided on the packaging base layer effectively increase the contact area between the display substrate and the Frit glue, thereby effectively improving the packaging effect of the display substrate.

[0171] In some embodiments, the diameter of the first via hole is set to be smaller than the diameter of the third via hole.

[0172] The above configuration can not only set a larger number of first vias and improve the packaging effect of Frit glue, but also effectively avoid the overlap of the first vias and the fan-out lines, thus greatly reducing the difficulty of making the first vias.

[0173] In some embodiments, setting the display substrate includes: stacking a first gate insulation layer, a second gate insulation layer and an interlayer insulation layer on the substrate in sequence along a direction away from the substrate; the third sub-via simultaneously penetrates the interlayer insulation layer, the second gate insulation layer and the first gate insulation layer.

[0174] The above configuration increases the contact area between the display substrate and the Frit glue, thereby effectively improving the packaging effect of the display substrate.

[0175] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0176] In the display substrate provided by the above embodiment, by setting the packaging base layer in the packaging glue area 20, the curing effect of the Frit glue when the display substrate is packaged is better improved. Moreover, by setting the first reuse part 220 to reuse the packaging base layer located in the first target area, the production of a large-area packaging base layer is avoided, and the production cost of the display substrate is effectively reduced. In addition, in the display substrate provided by the above embodiment, by setting the first via structure 23 in the first target area, the surface of the display substrate in the first target area that is back to the substrate is uneven, so that when the display substrate is Frit packaged, the contact area between the Frit glue and the display substrate can be effectively increased, and the bonding performance between the Frit glue and the display substrate can be improved, thereby better improving the packaging capability and achieving good water vapor and oxygen barrier properties and sealing effects.

[0177] Therefore, the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the above-mentioned display substrate, which will not be described in detail here.

[0178] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, and a tablet computer.

[0179] In some embodiments, the display device further includes a packaging cover plate disposed opposite to the display substrate, and the packaging cover plate and the display substrate are sealed by a sealing glue disposed in a packaging glue area 20 .

[0180] Exemplarily, the frame sealing glue includes Frit glue.

[0181] When the display substrate is packaged using Frit glue and a packaging cover plate, a Frit glue layer surrounding the display substrate is formed in the packaging glue area 20 of the display substrate, the packaging cover plate is covered on the display substrate, and the Frit glue is cured through a laser sintering process, so that the functional structure in the display substrate is packaged between the base of the display substrate and the packaging cover plate.

[0182] The embodiment of the present disclosure further provides a method for manufacturing a display substrate, wherein the display substrate comprises: a display area 1 and a non-display area 2 surrounding the display area 1, wherein the non-display area 2 comprises a packaging glue area 20 surrounding the display area 1; the manufacturing method comprises:

[0183] Making a packaging base layer, wherein the packaging base layer is located in the packaging glue area 20;

[0184] A fan-out layer 22 is manufactured, and the fan-out layer 22 is located in the non-display area 2. The fan-out layer 22 includes a first reused part 220. The orthographic projection of the first reused part 220 on the base of the display substrate at least partially overlaps with the orthographic projection of the first target area of ​​the packaging glue area 20 on the base. The first reused part 220 is reused as a packaging base layer located in the first target area.

[0185] Exemplarily, the display substrate includes a display area 1 and a non-display area 2 . Exemplarily, the display area 1 includes a circle and a rectangle, and the non-display area 2 completely surrounds the display area 1 .

[0186] Exemplarily, the encapsulation substrate layer includes a metal layer with good reflective properties. Exemplarily, the encapsulation substrate layer surrounds the display area 1. Exemplarily, the encapsulation substrate layer is arranged at an edge area of ​​the non-display area 2 away from the display area 1, so that other functional structures arranged in the non-display area 2 can be surrounded after encapsulation.

[0187] Exemplarily, the fan-out layer 22 is located at the lower frame of the display substrate. Exemplarily, the display substrate also includes a driver chip disposed in the non-display area 2, and the fan-out layer 22 is used to connect the partial functional layer located in the display area 1 and the driver chip to achieve signal transmission between the partial functional layer and the driver chip.

[0188] Exemplarily, the encapsulation glue area 20 includes a first target area, and the orthographic projection of the first multiplexing portion 220 on the base of the display substrate is located inside the orthographic projection of the first target area of ​​the encapsulation glue area 20 on the base. Exemplarily, the first multiplexing portion 220 is multiplexed as an encapsulation base layer located in the first target area, that is, there is no need to additionally manufacture a dedicated encapsulation base layer in the first target area.

[0189] The manufacturing method includes: manufacturing a first via hole structure 23, wherein the first via hole structure 23 is located in the first target area, and the first via hole structure 23 can make the surface of the display substrate in the first target area facing away from the base uneven.

[0190] Exemplarily, the first via structure 23 includes a plurality of independent first vias 230, and the plurality of first vias 230 are distributed in the first target area. The first vias 230 can penetrate at least a portion of the insulating layer located in the first target area, so that the surface of the display substrate in the first target area facing away from the substrate is uneven.

[0191] In the display substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure, the curing effect of the Frit glue when the display substrate is packaged is better improved by setting the packaging base layer in the packaging glue area 20. In addition, by setting the first reuse part 220 to reuse the packaging base layer located in the first target area, the manufacturing of a large area packaging base layer is avoided, and the manufacturing cost of the display substrate is effectively reduced.

[0192] In addition, in the display substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure, by setting the first via structure 23 in the first target area, the surface of the display substrate in the first target area that is back to the substrate is uneven, so that when the display substrate is Frit packaged, the contact area between the Frit glue and the display substrate can be effectively increased, and the bonding performance between the Frit glue and the display substrate can be improved, thereby better improving the packaging capability and achieving good water vapor and oxygen barrier properties and sealing effects.

[0193] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0194] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0195] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0196] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0197] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: A display area and a non-display area surrounding the display area, wherein the non-display area includes a packaging glue area surrounding the display area; The display substrate further comprises: A packaging base layer, wherein the packaging base layer is located in the packaging glue area; A fan-out layer, the fan-out layer is located in the non-display area, the fan-out layer includes a first multiplexing portion, an orthographic projection of the first multiplexing portion on the base of the display substrate at least partially overlaps with an orthographic projection of a first target area of ​​the encapsulation glue area on the base, and the first multiplexing portion is multiplexed into an encapsulation base layer located in the first target area; The display substrate further includes: a first power line and a second power line disposed in the non-display area; The first power line comprises: a transmission portion and two first inlet portions, the transmission portion extends along a first direction, and at least a portion of the first inlet portion extends along a second direction; two ends of the transmission portion are respectively coupled to the two first inlet portions, the transmission portion is located between the display area and the first inlet portions, and the first direction intersects with the second direction; The second power line includes: a peripheral portion and two second line inlet portions; the peripheral portion surrounds the display area, the peripheral portion has an opening, two ends of the peripheral portion at the opening are connected to the two second line inlet portions in a one-to-one correspondence, and at least a portion of the second line inlet portion extends along the second direction; The orthographic projections of the two first line-inlet portions on the substrate are both located between the orthographic projections of the two second line-inlet portions on the substrate.

2. The display substrate according to claim 1, wherein: The display substrate further comprises: A first via structure, wherein the first via structure is located in the first target area, and the first via structure can make the surface of the display substrate in the first target area facing away from the base uneven.

3. The display substrate according to claim 2, wherein: The display substrate further comprises: at least two layers of a first gate insulating layer, a second gate insulating layer and an interlayer insulating layer which are sequentially stacked on the substrate in a direction away from the substrate; The first via structure includes a plurality of first vias, and the first vias penetrate at least one of the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.

4. The display substrate according to claim 3, wherein: The fan-out layer includes a plurality of fan-out lines, the plurality of fan-out lines include the first multiplexing portion, and an orthographic projection of the fan-out lines on the substrate does not overlap with an orthographic projection of the first via structure on the substrate.

5. The display substrate according to claim 4, wherein: The plurality of first via holes are divided into a plurality of via hole groups, and the orthographic projections of the via hole groups on the substrate and the orthographic projections of the fan-out lines on the substrate are alternately arranged along a first direction.

6. The display substrate according to claim 4, wherein: The plurality of fan-out lines are located between the first gate insulating layer and the interlayer insulating layer.

7. The display substrate according to claim 4, wherein: The plurality of fan-out lines include a plurality of first fan-out lines and a plurality of second fan-out lines, the plurality of first fan-out lines are located between the first gate insulating layer and the second gate insulating layer, and the plurality of second fan-out lines are located between the second gate insulating layer and the interlayer insulating layer; The plurality of first fan-out lines and the plurality of second fan-out lines each include the first multiplexing portion.

8. The display substrate according to claim 3, wherein: At least a portion of the encapsulation substrate layer is located between the first gate insulating layer and the second gate insulating layer.

9. The display substrate according to claim 1, wherein: The non-display area includes two corner areas arranged along the first direction, the two second line-in portions correspond to the two corner areas one by one, and at least a portion of the second line-in portions is located in the corresponding corner areas.

10. The display substrate according to claim 1, wherein: The first line feed portion includes a second multiplexing part, the orthographic projection of the second multiplexing part on the substrate at least partially overlaps with the orthographic projection of the second target area of ​​the packaging glue area on the substrate, and the second multiplexing part is multiplexed into a packaging substrate layer located in the second target area.

11. The display substrate according to claim 10, wherein: The second line feed portion includes a third multiplexing part, the orthographic projection of the third multiplexing part on the substrate at least partially overlaps with the orthographic projection of the third target area of ​​the packaging glue area on the substrate, and the third multiplexing part is multiplexed into a packaging substrate layer located in the third target area.

12. The display substrate according to claim 11, wherein: A plurality of second via holes are arranged on the second multiplexing part and / or the third multiplexing part.

13. The display substrate according to claim 1, wherein: The display substrate further comprises: A gate driving circuit, wherein the gate driving circuit is located at two opposite sides of the display area along a first direction; A plurality of first signal lines, wherein the plurality of first signal lines and the first power line are located on the same side of the display area, and the plurality of first signal lines are connected to the gate drive circuit to provide corresponding signals to the gate drive circuit; the first signal line comprises a fourth multiplexing portion, and an orthographic projection of the fourth multiplexing portion on the substrate at least partially overlaps with an orthographic projection of a fourth target area of ​​the packaging glue area on the substrate, and the fourth multiplexing portion is multiplexed into a packaging substrate layer located in the fourth target area.

14. The display substrate according to claim 3, wherein: The packaging substrate layer comprises: at least two first encapsulation parts, the orthographic projections of the at least two first encapsulation parts on the substrate are located between the orthographic projections of the two first line-inlet parts on the substrate, the at least two first encapsulation parts are arranged along the first direction, and the first target area is defined between adjacent first encapsulation parts; A surrounding encapsulation portion surrounds other sides of the display area except the side where the first encapsulation portion is located.

15. The display substrate according to claim 14, wherein: The first packaging portion is coupled to the first power line; and the surrounding packaging portion is coupled to the second power line.

16. The display substrate according to claim 15, wherein: The packaging substrate layer also includes: A plurality of first conductive connection parts, wherein the plurality of first conductive connection parts and the first packaging part form an integrated structure, and the first packaging part is respectively coupled to the transmission part through the plurality of first conductive connection parts.

17. The display substrate according to claim 15, wherein: The packaging substrate layer also includes: A plurality of second conductive connection parts, wherein the plurality of second conductive connection parts and the surrounding packaging part form an integral structure; A plurality of protrusions are disposed on the edge of the peripheral portion and / or the second line-inlet portion, and the surrounding packaging portion is coupled to at least some of the protrusions via the plurality of second conductive connection portions.

18. The display substrate according to claim 14, wherein: A plurality of third via holes are provided on the first packaging portion and / or the surrounding packaging portion; The display substrate is also provided with a plurality of groups of third sub-vias corresponding one-to-one to the plurality of third vias, each group of third sub-vias includes a plurality of third sub-vias, the orthographic projections of the plurality of third sub-vias on the substrate are located inside the orthographic projections of the corresponding third vias on the substrate, and the third sub-vias penetrate at least one of the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer.

19. The display substrate according to claim 18, wherein: The aperture of the first via hole is smaller than the aperture of the third via hole.

20. The display substrate according to claim 18, wherein: The display substrate comprises: a first gate insulating layer, a second gate insulating layer and an interlayer insulating layer which are sequentially stacked on the substrate in a direction away from the substrate; The third sub-via hole penetrates the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer at the same time.

21. A display device comprising the display substrate according to any one of claims 1 to 20.

22. The display device according to claim 21, wherein: The display device further comprises a packaging cover plate arranged opposite to the display substrate, and the packaging cover plate and the display substrate are sealed by a frame sealant arranged in a packaging sealant area.

23. A method for manufacturing a display substrate, the display substrate comprising: A display area and a non-display area surrounding the display area, wherein the non-display area includes a packaging glue area surrounding the display area; The production method comprises: Making a packaging base layer, wherein the packaging base layer is located in the packaging glue area; Manufacturing a fan-out layer, the fan-out layer is located in the non-display area, the fan-out layer includes a first multiplexing portion, an orthographic projection of the first multiplexing portion on the base of the display substrate at least partially overlaps with an orthographic projection of a first target area of ​​the encapsulation glue area on the base, and the first multiplexing portion is multiplexed into an encapsulation base layer located in the first target area; Making a first power line and a second power line disposed in the non-display area; The first power line comprises: a transmission portion and two first inlet portions, the transmission portion extends along a first direction, and at least a portion of the first inlet portion extends along a second direction; two ends of the transmission portion are respectively coupled to the two first inlet portions, the transmission portion is located between the display area and the first inlet portions, and the first direction intersects with the second direction; The second power line includes: a peripheral portion and two second line inlet portions; the peripheral portion surrounds the display area, the peripheral portion has an opening, two ends of the peripheral portion at the opening are connected to the two second line inlet portions in a one-to-one correspondence, and at least a portion of the second line inlet portion extends along the second direction; The orthographic projections of the two first line-inlet portions on the substrate are both located between the orthographic projections of the two second line-inlet portions on the substrate.

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