A method, system, device, and storage medium for thread branch execution.

Abstract

This application provides a thread branch execution method, system, device, and storage medium. The thread branch execution method is applied to a GPGPU processor, which includes a branch synchronization management stack. This stack manages branch control instructions synchronously based on the mask information corresponding to the control instructions. The thread branch execution method includes: obtaining the first mask information of the control instructions in the thread to be managed; obtaining the push / pop information of each control instruction in the branch synchronization management stack; and then executing it to obtain the branch synchronization execution result. The branch synchronization execution result includes no jump at the top of the stack when there are no active threads in the else path. This embodiment implements branch instructions without jumping when there are no active threads, thereby reducing the hardware overhead of branch instruction control management, eliminating the need for excessive management code or specific instruction token management, and saving time in branch instruction control management.

Description

Technical Field

[0001] This application relates to the field of graphics processing technology, specifically to a thread branching execution method, system, device, and storage medium. Background Technology

[0002] Graphics processors (GPUs) typically employ a threaded management approach, featuring a Single Instruction Multiple Thread (SIMT) architecture. This means multiple threads execute a single instruction concurrently. This design conserves logical resources such as fetching values, allowing the computing unit to access more hardware resources. However, when performing non-graphics calculations, if the program contains conditional statements and branches, the execution paths of different threads can differ. Some threads may use branches for conditional statements, while others may not. This leads to issues with thread branching and efficiency loss in SIMT.

[0003] In some existing technologies, conditional statements need to be inserted into the code sequence by the compiler or programmer (e.g., based on instruction token design), and the branching and synchronized thread bundles are managed through a synchronization thread instruction control stack. When execution reaches a certain point in the program, the thread bundle synchronization instruction is executed to synchronize the branch threads. However, the synchronization thread instruction control stack processes data according to a uniform data processing method and time processing cycle, which not only results in a large hardware overhead for branch synchronization management, but also a long processing time for branch synchronization and jumps, leading to a long cycle for branch instruction management.

[0004] Therefore, a new thread branching execution scheme is needed. Summary of the Invention

[0005] In view of this, embodiments of this specification provide a thread branch execution method, device, system, and storage medium applied to a GPGPU processor to realize the process of synchronous management of branch control instructions.

[0006] The embodiments in this specification provide the following technical solutions: This specification provides a thread branch execution method applied to a GPGPU processor. The GPGPU processor includes a branch synchronization management stack, which manages the synchronization of branch control instructions based on the mask information corresponding to the control instructions. The thread branch execution method includes: Obtain the first mask information of the control instructions in the thread to be managed; Based on the first mask information, obtain the push / pop information of each control instruction in the branch synchronization management stack; The branch synchronization execution result obtained by executing each control instruction in the branch synchronization management stack is determined based on the push / pop information. The branch synchronization execution result includes no jump at the top of the stack when there is no active thread in the else path.

[0007] This specification also provides a thread branch execution system applied to a GPGPU processor, employing the thread branch execution method as described in any of the technical solutions provided in this specification. The GPGPU processor includes a branch synchronization management stack and a thread control instruction module. The thread control instruction module sets stack item information for each control instruction. The branch synchronization management stack is used to synchronize the branch control instructions according to the mask information in the stack item information corresponding to each control instruction.

[0008] This specification also provides a thread branch execution device, including a memory, a GPGPU processor, and a computer program. The computer program is stored in the memory, and the GPGPU processor runs the computer program to execute the thread branch execution method described in any of the technical solutions provided in this specification.

[0009] This specification also provides a readable storage medium storing a computer program, which, when executed by a processor, is used to implement the thread branch execution method described in any of the technical solutions provided in this specification.

[0010] Compared with the prior art, the beneficial effects that at least one technical solution adopted in the embodiments of this specification can achieve include at least: Branch synchronization management is performed based on the mask information corresponding to the control instructions and the branch synchronization management stack. Branch instruction execution is optimized based on information such as stack popping and popping, so that branch instructions do not jump when there are no active threads, thereby reducing the hardware overhead of branch instruction control management. This enables branch instructions to run adaptively and flexibly in the branch synchronization management stack without the need for excessive management code or specific instruction token management, and also saves time for branch instruction control management, achieving efficient and flexible management and execution of branch control instructions. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the GPGPU processor with branch operation provided in the embodiments of this specification; Figure 2This is a flowchart illustrating a thread branch execution method provided in an embodiment of this specification; Figure 3 This is a schematic diagram of the structure of a thread branch execution system provided in the embodiments of this specification; Figure 4 This is a schematic diagram illustrating the stack item information within the branch synchronization management stack provided in the embodiments of this specification; Figure 5 This is a schematic diagram of a thread branch execution application provided in the embodiments of this specification; Figure 6 This is a schematic diagram illustrating the branch instruction information provided in the embodiments of this specification; Figure 7 This is a schematic diagram illustrating the information contained in the branch synchronization instruction provided in the embodiments of this specification; Figure 8 This is a schematic diagram of the branch instruction processing flow provided in the embodiments of this specification; Figure 9 This is a schematic diagram of the branch synchronization instruction processing flow provided in the embodiments of this specification. Detailed Implementation

[0013] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0014] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0016] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0017] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0018] In existing technologies, conditional statements need to be inserted into the code sequence by the compiler or programmer (e.g., based on instruction token design), and the branching and synchronized threads are managed through a synchronization thread instruction control stack. However, the synchronization thread instruction control stack processes data according to a uniform data processing method and time processing cycle. For example, it implements jumps when there are no active threads in the else path through instruction operations. This not only causes a large hardware overhead for branch synchronization management, but also results in a long processing time for branch synchronization and jumps, leading to a long cycle for branch instruction management.

[0019] In view of this, the inventors discovered that by combining branch instruction management with mask calculation, the number of instructions required to achieve the same function can be reduced. While reducing the number of instructions, each branch can reduce the pipeline flushing overhead caused by at least one PC value jump, thereby optimizing the internal scheduling and execution efficiency of the thread bundle.

[0020] Based on this, the embodiments of this specification propose a processing solution as follows: Figure 1 As shown, based on the GPGPU processor hardware architecture, a flexible management of branch instruction synchronization is implemented in the SIMT STACK (thread branch management stack). By setting up a branch synchronization management stack and combining it with mask calculation, the push / pop information of the execution of this branch synchronization management stack is obtained, thereby achieving the function of skipping unnecessary branch execution. Specifically, there is no need to insert unconditional jump instructions at the end of the branch to achieve the function of skipping unnecessary branch execution. This ensures that branch instructions do not jump when there are no active threads, thereby reducing the hardware overhead of branch instruction control and management, enabling branch instructions to run adaptively and flexibly, without the need for excessive management code or specific instruction token management, and also saving time for branch instruction control and management, achieving efficient and flexible management and execution of branch control instructions.

[0021] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0022] like Figure 2As shown in the figure, this specification provides a thread branch execution method, which may include steps S210 to S230. Step S210: Obtain first mask information of control instructions in the thread to be managed. Step S220: Obtain push / pop information of each control instruction in the branch synchronization management stack based on the first mask information. Step S230: Determine the branch synchronization execution result obtained by executing each control instruction in the branch synchronization management stack based on the push / pop information; the branch synchronization execution result includes no jump at the top of the stack when there is no active thread in the else path.

[0023] Specifically, the thread branch execution system, applied to GPGPU processors, see [link to relevant documentation]. Figure 3 The GPGPU processor includes a branch synchronization management stack and a thread control instruction module. The thread control instruction module sets stack item information for each control instruction, and the branch synchronization management stack manages the synchronization of branch control instructions based on the mask information in the stack item information corresponding to each control instruction. Therefore, compared to existing GPGPU processors, the GPGPU processor provided in this embodiment, when performing non-graphics computation, achieves flexible execution of thread condition judgments through the branch synchronization management stack, preventing branch instructions from jumping when there are no active threads. This reduces the hardware overhead of branch instruction control management, enabling adaptive and flexible branch instruction execution without requiring excessive management code or specific instruction token management, and also saves time in branch instruction control management, achieving efficient and flexible management and execution of branch control instructions. Any technical solution in this embodiment can also be applied to any processor containing a GPGPU processor architecture.

[0024] In some embodiments, the stack item information corresponding to the branch synchronization management stack includes: rPC, rMASK, PCelse, MASKelse, Is_part, and pair. Specifically, see [link to details regarding the stack item information of the branch synchronization management stack]. Figure 4Here, `rmask` represents the thread mask at the end of the branch, i.e., the thread mask representing the synchronization position; `Mask else` represents the thread mask executing `else`, i.e., the thread mask representing the jump; `PC else` represents the PC value at the start of the `else` branch, i.e., the jump position PC; `rPC` represents the branch synchronization position information; `is_part` indicates whether the stack item is fully occupied or only half occupied (i.e., during execution, `mask else` and `pc else` as a whole, and `rmask` as a whole, will be popped sequentially, and the `is_part` item is used to record whether a pop has occurred); `pair` is used to record whether the branch has actually occurred. Applying the above stack item information to the thread branch management process, mask information is set for control instructions, and the corresponding mask-related marking information (such as `is_part` and `pair`) for branch control instructions and branch synchronization control instructions is marked according to the mask information. This allows for flexible judgment of the execution of specific branch instructions during the execution of branch control instructions, ensuring that the stack top does not jump when there are no active threads in the `else` path.

[0025] In some embodiments, the stack item information in the corresponding stack of the branch synchronization management stack includes mask information. In conjunction with the above embodiments, the stack item information in the corresponding stack of the branch synchronization management stack includes: rmask representing the thread mask at the end of the branch, and Masklse representing the thread mask for executing else. When the control instruction runs within the branch synchronization management stack, the above two mask information points to the synchronization position mask information and the thread mask for taking a jump, respectively.

[0026] like Figures 2 to 4 As shown, the GPGPU processor in this embodiment of the specification manages branch control instructions synchronously by setting a branch synchronization management stack according to the mask information corresponding to the control instructions. This enables the GPGPU processor to perform non-graphics calculations. When the program contains conditional judgments and branches, the branch instructions can be run adaptively and flexibly. This optimizes the execution of branch instructions in the branch synchronization management stack, ensuring that branch instructions do not jump when there are no active threads. This reduces the hardware overhead of branch instruction control management, eliminates the need for excessive management code or specific instruction token management, and saves time in branch instruction control management, achieving efficient and flexible management and execution of branch control instructions.

[0027] Step S210: Obtain the first mask information of the control instructions in the thread to be managed. Specifically, obtain the first mask information corresponding to each control instruction in the thread to be managed. For example, the thread mask for the if path is represented as if mask, and the starting position of the else path is represented as PC else. Then, based on the first mask information, obtain the push / pop information of each control instruction in the branch synchronization management stack.

[0028] Step S220: Obtain the push / pop information of each control instruction in the branch synchronization management stack according to the first mask information. In some embodiments, the push / pop information includes marking the branch divergence and jump status of the control instructions, thereby facilitating flexible branching and synchronization management of each control instruction in the branch synchronization management stack.

[0029] Specifically, when executing branch control instructions in conjunction with the above embodiments, the first mask information, such as the if path thread mask (if mask) and the else path starting position (PC else), is obtained. Figure 4 As shown, the first mask information is judged. If the first mask information meets the corresponding judgment condition, the push / pop information of each control instruction is determined for the stack item information corresponding to the two types of thread branch instructions and branch synchronization instructions.

[0030] For example, push information is obtained by determining whether all active threads have jumped or whether an active branch has jumped. Similarly, pop information is obtained by determining whether the top branch of the stack has branched out or whether a jump has occurred. Specifically, push information is obtained by combining if mask and else mask, and pop information is obtained by combining is_part=1 and pair.

[0031] Step S230: Determine the branch synchronization execution result obtained by executing each control instruction in the branch synchronization management stack according to the push / pop information. The branch synchronization execution result includes no jump at the top of the stack when there is no active thread in the else path.

[0032] Specifically, the branch divergence information and jump information of each control instruction in the branch synchronization management stack are updated based on the stack item information corresponding to the branch control instruction. For example, branch divergence information represents branch divergence labels, and jump information represents jump branch labels. This includes labels indicating a branch has a divergence and no jump is needed, labels indicating a branch has no divergence and a jump is needed, labels indicating a branch has no divergence and no jump is needed, the top branch of the stack has a divergence, the top branch of the stack has no divergence and a jump is needed, and the top branch of the stack has no divergence and no jump is needed. Compared to existing technologies that implement jumps when there are no active threads in the else path through instruction operations, which incurs unnecessary hardware overhead on the thread instruction control stack and processor time overhead when there are no active threads in the else path, this approach achieves a more efficient result.

[0033] Existing technologies implement jumps when there are no active threads in the else path through instruction manipulation. However, the embodiments in this specification achieve this by setting up a branch synchronization management stack and combining it with mask calculation to obtain the push / pop information of the execution of the branch synchronization management stack. This enables the function of skipping unnecessary branch execution, ensuring that branch instructions do not jump when there are no active threads, i.e., that none of the stack top items jump. This reduces the hardware overhead of branch instruction control and management, enables branch instructions to run adaptively and flexibly, requires no excessive management code or specific instruction token management, and saves time in branch instruction control and management, achieving efficient and flexible management and operation of branch control instructions.

[0034] Specifically, based on the first mask information, the push / pop information of each control instruction within the branch synchronization management stack is obtained. This includes: determining the push / pop information of each control instruction based on the judgment conditions corresponding to the first mask information of each control instruction, combined with the stack item information within the stack corresponding to the control instruction. Push information can indicate whether a thread jumps or whether a branch control instruction occurs when a control instruction is pushed onto the stack, and pop information can indicate whether there is a branch at the top of the stack or a jump when a control instruction is popped from the stack.

[0035] For example, based on the thread mask of the if path in the control instruction (if mask) and the starting position of the else path (PC else), logical judgment is performed. If the if mask is all zeros, all threads jump, obtain the stack information, and mark the branch as having no branch and the branch as needing a jump. If the if mask is not all zeros, further judgment is made in conjunction with the else mask. For example, if a branch does occur, it is marked as having a branch and the branch does not need a jump. Alternatively, if all threads do not jump, it is marked as having no branch and the branch does not need a jump.

[0036] For example, after obtaining the control instruction push information, the stack top pop status is further determined. The first mask information, combined with the stack item information, is used to determine whether a branching marker has been applied at the top of the stack and whether a jump marker is needed. Specifically, this is determined using `is_part` and `pair` to mark whether the top branch has a branching pattern, or whether a jump marker is needed if the top branch has no branching pattern, or whether a jump marker is needed if the top branch has no branching pattern.

[0037] In some embodiments, execution management is mainly carried out on two types of instructions: thread branch instructions and branch-thread synchronization instructions. See [link to relevant documentation]. Figure 6 and Figure 7 The instructions show the information contained in thread branch instructions and the information contained in branch thread synchronization instructions, respectively. The operands are obtained by performing bitwise or logical operations on the source code and mask information; in this embodiment, logical operations are particularly preferred. For example... Figure 6 In the text, VS1 and VS2 represent different vector register source operands, such as... Figure 6 and Figure 7The offset represents the address of the destination instruction for the branch synchronization instruction. For example... Figure 6 and Figure 7 As shown, the thread branch instruction containment information and the branch thread synchronization instruction containment information are used to identify thread branch instructions and branch thread synchronization instructions during instruction execution to manage the execution program.

[0038] In some embodiments, determining the branch synchronization execution result based on the push / pop information includes: Based on the stack item information corresponding to the branch control instruction, update the branch branching information and jump information of each control instruction pushed onto the stack in the branch synchronization management stack; and based on the stack top information and push information corresponding to the branch synchronization control instruction, update the branch branching information and jump information of each control instruction popped from the stack in the branch synchronization management stack.

[0039] Specifically, the branch synchronization execution results obtained by executing each control instruction in the branch synchronization management stack are determined for two categories: thread branch instructions and branch thread synchronization instructions.

[0040] Combination Figure 4 The stack item information shown determines the branch synchronization execution result obtained from the control instructions in the branch synchronization management stack based on the push / pop information. For example... Figure 5 The system performs logical judgments by managing control commands and mask information, specifically based on the branch divergence and jump conditions recorded in the `is_part` and `pair` entries to obtain the branch synchronization result. `is_part` records whether a pop-up has occurred, and `pair` records whether a branch actually occurred. Furthermore, based on the `is_part` and `pair` entries, combined with... Figure 5 The branch synchronization result is obtained by acquiring the mask information of the branch management calculation. This enables flexible execution of thread condition judgments, preventing branch instructions from jumping when there are no active threads, thereby reducing the hardware overhead of branch instruction control and management, saving time, and achieving efficient and flexible management and execution of branch control instructions. `is_part` and `pair` are determined by `if mask` and `else mask`: `is_part` = 1 when there is no branch, and `pair` = 1 when there are no active threads in the `else` path. The `is_part` item is dynamically updated during the execution of branch thread synchronization instructions. Additionally... Figure 5 Wid represents the current thread bundle ID.

[0041] In some embodiments, based on the stack item information corresponding to the branch control instructions, the branch divergence information and jump information of each control instruction pushed onto the branch synchronization management stack are updated, including: if all active threads jump, then each branch control instruction is pushed onto the stack, and marked as "no branch divergence" and "branch requires jump". Alternatively, if all active threads do not jump, and it is determined that all active branches do not jump, then the stack item information of each branch control instruction is set, and marked as "no branch divergence" and "branch does not require jump". Alternatively, if all active threads do not jump, and it is determined that not all active branches jump, then each branch control instruction is pushed onto the stack and marked as "branch does not require jump" and "branch divergence has occurred".

[0042] Specifically, when processing thread branch instructions, the processor sends the source operands to the computation module and simultaneously sends the branch opcode and branch target address information to the branch synchronization management stack. The branch synchronization management stack receives the branch opcode and the mask calculation result information from the computation module and synchronizes them. Based on the mask calculation result, the branch situation can be divided into three categories: 1. If a branch does occur, mask-related marker information is pushed onto the stack, indicating whether the branch has diverged or does not require a jump. 2. If all threads do not jump, push information is pushed onto the stack, indicating whether the branch has no divergence or does not require a jump. 3. If all threads jump, push information is pushed onto the stack, indicating whether the branch has no divergence or requires a jump.

[0043] For example, refer to Figure 8 If the `if mask` is all zeros, all threads jump. The current active mask `rMask` and `is_part=0` are pushed onto the stack. The program jumps to the `else PC`, sets the PC to the jump position, sets the thread bundle mask to the jump thread mask given by the computation unit, and sends jump signals and pipeline flushing signals to relevant external modules. The stack is marked with "no branch" and "branch requires jump". Alternatively, if the `if mask` is not all zeros, but the `else mask` is all zeros, not all active threads jump, and it is determined that all active branches do not jump. The `pair` item is pushed onto the stack and marked as 1, `is_part=0`. The stack is marked with "no branch" and "branch does not require jump", and the PC is set to `PC+4`. Alternatively, if neither the `if mask` nor the `else mask` is all zeros, not all active threads jump, and it is determined that not all active branches jump. The `pair` item is pushed onto the stack and marked as 1, `pair=0`. The stack is marked with "branch has branch" and "branch does not require jump".

[0044] In some embodiments, based on the stack top information and push information corresponding to the branch synchronization control instructions, the branch divergence information and jump information of each control instruction popped from the branch synchronization management stack are updated, including: if there is a divergence marked at the top of the branch synchronization management stack, the branch synchronization control instruction stack top jump thread mask is set, and a jump signal and pipeline flush signal are sent to the relevant external modules, and the instruction fetch module fetches the instruction corresponding to the jump position at the top of the stack for execution. Alternatively, if there is no divergence marked at the top of the branch synchronization management stack, and it is determined that none of the active branches at the top of the stack jump, the thread bundle mask is set to the stack top synchronization thread mask, and a jump signal and pipeline flush signal are sent to the relevant external modules, fetching the synchronization position passed in by the branch synchronization control instruction. Alternatively, if there is no divergence marked at the top of the branch synchronization management stack, and it is determined that the active branch at the top of the stack jumps, the thread bundle mask is set to the stack top synchronization thread mask, and the PC is set to PC+4 for execution.

[0045] Specifically, when processing branch thread synchronization instructions, the processor sends the branch opcode and branch synchronization position information (rPC) to the branch synchronization management stack. Based on the current information at the top of the stack, the branch synchronization status can be divided into three categories: 1. The branch at the top of the stack has a divergence. 2. The branch at the top of the stack has no divergence and a jump is required. 3. The branch at the top of the stack has no divergence and no jump is required.

[0046] For example, refer to Figure 9 If the current stack top `is_part` = 0 and `pair` = 0, then the stack top is marked as having no divergence, the active branch at the top of the stack is determined not to jump, and execution continues at PC+4 using `rMask` as the mask. Alternatively, if `is_part` = 1, then the stack top is marked as having no divergence, the active branches at the top of the stack are determined not to jump, `else mask` is used as the mask, and execution jumps to the `else PC` program, marking `is_part` = 0, i.e., some items are popped from the stack. Alternatively, if `is_part` = 0 and `pair` = 1, then the stack top is marked as having divergence, the active branches at the top of the stack are determined to jump, and execution directly jumps to the rendezvous position PC using `rMask` as the mask. This ensures that branch instructions do not jump when there are no active threads, thereby reducing the hardware overhead of branch instruction control and management, eliminating the need for excessive management code or specific instruction token management, and saving time in branch instruction control and management.

[0047] In summary, by combining mask calculation with the stack item information corresponding to the control instructions, the push / pop information of control instructions on the stack can be flexibly marked, especially for marking whether branch instructions have occurred and jump situations. The judgment is based on a comprehensive consideration of `is_part` and `pair`. During runtime, the specific jump location is indicated by combining the mask information `rMask` and `else Mask` if a jump occurs; see [link to documentation]. Figure 4The code provides either the else PC or the rPC to determine the target address, where the rPC is provided by the "offset" in the instruction. The specific target address is determined based on whether a branch or jump occurs. Compared to existing technologies that implement jumps when there are no active threads in the else path through instruction operations, resulting in high hardware overhead and long management cycles for branch management, this method reduces the number of instructions and skips unnecessary branch execution. It eliminates the need to insert unconditional jump instructions at the end of branches to skip unnecessary branch execution. While reducing the number of instructions, it also reduces pipeline flushing overhead caused by at least one PC value jump each time a branch occurs, leading to improved internal scheduling efficiency within the thread bundle.

[0048] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the product embodiments described later are relatively simple since they correspond to the methods; relevant parts can be referred to the descriptions in the system embodiments.

[0049] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A thread branch execution method, characterized in that, Applied to a GPGPU processor, the GPGPU processor is provided with a branch synchronization management stack, which is used to synchronize and manage branch control instructions according to the mask information corresponding to the control instructions; The thread branch execution method includes: Obtain the first mask information of the control instructions in the thread to be managed; Based on the first mask information, obtain the push / pop information of each control instruction in the branch synchronization management stack; The branch synchronization operation result obtained by executing each control instruction in the branch synchronization management stack is determined based on the push / pop information. The branch synchronization operation result includes obtaining the mask, obtaining the stack information based on the mask information, thereby determining whether there is an active thread in the else path, and not jumping to the top of the stack when there is no active thread in the else path. The condition needs to use both if mask and else mask: If the mask is all zeros, all threads jump, push the currently active rMask and is_part=0 onto the stack, the program jumps to else PC to execute, sets PC to the jump position PC, sets the thread bundle mask to the jump thread mask given by the computing unit, and sends jump signals and pipeline flush signals to relevant external modules. Mark branches with no branches and branches that need to jump on the stack. If mask is not all zeros but else mask is all zeros, then all active threads will not jump, and it is determined that all active branches will not jump. Push the pair item onto the stack and mark it as 1, is_part=0. Mark the branches without divergence and branches that do not need to jump on the stack, and set PC to PC+4. If both mask and else mask are not all zero, then not all active threads will jump, and it is determined that not all active branches will jump. Push them onto the stack and mark is_part=1 and pair=0. Mark the branches that have diverged and the branches that do not need to jump on the stack. If the current stack top is_part = 0 and pair = 0, then the stack top is marked as unspecified, the active branch at the top of the stack is determined not to jump, and execution continues with PC+4 using rMask as the mask; or, if is_part = 1, then the stack top is marked as unspecified, the active branches at the top of the stack are determined not to jump, the else mask is used as the mask and the else PC program is executed, and is_part = 0 is marked, i.e., some items in the stack are popped; or, if is_part = 0 and pair = 1, then the stack top is marked as unspecified, the active branches at the top of the stack are determined to jump, and execution directly jumps to the rendezvous position PC using rMask as the mask.

2. The thread branch execution method according to claim 1, characterized in that, The stack item information in the branch synchronization management stack includes mask information.

3. The thread branch execution method according to claim 2, characterized in that, Based on the first mask information, obtain the push / pop information of each control instruction in the branch synchronization management stack, including: Based on the judgment conditions corresponding to the first mask information of each control instruction, and combined with the stack item information in the stack corresponding to the control instruction, the push / pop information of each control instruction is determined.

4. The thread branch execution method according to claim 3, characterized in that, Based on the push / pop information, determine the branch synchronization execution results obtained from the execution of each control instruction in the branch synchronization management stack, including: Based on the stack item information corresponding to the branch control instruction, update the branch branching information and jump information of each control instruction pushed onto the branch synchronization management stack. In addition, based on the stack top information and push information corresponding to the branch synchronization control instructions, update the branch branching information and jump information of each control instruction popped from the branch synchronization management stack.

5. The thread branch execution method according to claim 4, characterized in that, Based on the stack item information corresponding to the branch control instructions, update the branch divergence information and jump information of each control instruction pushed onto the branch synchronization management stack, including: If all active threads jump, then push each branch control instruction onto the stack, and obtain the branches marked as having no branches and branches that need to jump; Alternatively, if all active threads do not jump, and it is determined that all active branches do not jump, then set the stack item information in the stack of each branch control instruction and mark it as a branch without branching and a branch that does not need to jump. Alternatively, if all active threads do not jump, and it is determined that not all active branches jump, then each branch control instruction is pushed onto the stack and marked as "no branch jump required" or "branch divergence has occurred".

6. The thread branch execution method according to claim 4, characterized in that, Based on the stack top and push information corresponding to the branch synchronization control instructions, update the branch branching information and jump information of each control instruction popped from the branch synchronization management stack, including: If there is a divergence in the top marker of the branch synchronization management stack, the branch synchronization control instruction jumps to the thread mask at the top of the stack and sends a jump signal and pipeline flush signal to the relevant external modules. The instruction fetch module fetches the instruction corresponding to the jump position at the top of the stack and executes it. Alternatively, if there is no divergence in the top mark of the branch synchronization management stack, and it is determined that none of the active branches at the top of the stack will jump, then the thread bundle mask is set to the top synchronization thread mask, and a jump signal and pipeline flushing signal are sent to the relevant external modules, and the instruction fetching module fetches the synchronization position passed in by the branch synchronization control instruction. Alternatively, if there is no divergence in the top mark of the branch synchronization management stack, and it is determined that the active branch at the top of the stack has a jump, then the thread bundle mask is set to the top synchronization thread mask.

7. A thread branch execution system, characterized in that, The thread branch execution method as described in any one of claims 1-6 is adopted, wherein the GPGPU processor includes a branch synchronization management stack and a thread control instruction module; The thread control instruction module is used to set stack item information for each control instruction; The branch synchronization management stack is used to synchronize branch control instructions according to the mask information in the stack item information corresponding to each control instruction.

8. The thread branching execution system according to claim 7, characterized in that, The stack item information corresponding to the branch synchronization management stack includes: rPC, rMasK, PC else, Mask else, Is_part, and pair.

9. A thread branch execution device, characterized in that, include: The device includes a memory, a GPGPU processor, and a computer program, wherein the computer program is stored in the memory and the GPGPU processor runs the computer program to perform the thread branch execution method according to any one of claims 1-6.

10. A readable storage medium, characterized in that, The readable storage medium stores a computer program, which, when executed by a processor, is used to implement the thread branching method according to any one of claims 1-6.

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