Peripheral component interconnect attribute using address bit sharing

Abstract

The present disclosure relates to peripheral component interconnect attribute using address bit sharing. A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface can include a device side capable of first data exchange with the first external device and a system side capable of second data exchange with the memory device, wherein the system side is further capable of exchange of a platform hint between the first interface and the memory device. The system can further include a hint unit to populate the platform hint in an address bit.

Description

Technical Field

[0001] This disclosure is generally directed to data storage devices, and more specifically to sharing data between devices. Background Technology

[0002] Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard. The development and ongoing development of PCIe aims to improve upon or replace older bus standards. Other serial communication standards, such as the Universal Serial Bus (USB) standard, have established specifications for the cables, connectors, and protocols that facilitate machine-to-machine communication. Summary of the Invention

[0003] Newer versions of the PCIe protocol (e.g., version 3, version 4, etc.) have incorporated an optional attribute field called the redirection flag (ST) field, which stores attributes or platform hints to be used in memory access requests. The ST field allows devices to transmit platform hints to be applied to memory access requests. The actual use of such hints depends on the platform, not the requirements of the current PCIe specification. Examples of known platform hint usage include specifying the target cache for data to be written, the expected time of data usage, and other hints that can help optimize data transfer or memory usage.

[0004] Another optional feature offered by PCIe is the Relaxed Ordering (RO) field, which stores a hint specifying whether a transaction should follow strict ordering rules or whether a relaxed ordering is allowed. Other examples of fields that can be used to optimize performance but are not required include the Last-Level Cache (LLC) field, hidden fields, etc.

[0005] Although defined by the PCIe specification, many devices in use and under development do not support the use of optional fields (e.g., ST field, RO field, LLC field, hidden field, etc.). Therefore, previous data transaction methods were forced to either use devices that support optional fields or suffer from suboptimal performance. Embodiments of this disclosure aim to share and use indications supported by these optional fields (e.g., ST field, RO field, LLC field, hidden field, etc.), even when dealing with unsupported devices. The newer fields and platform hints provided therein can be used even for devices that do not inherently support platform hints, allowing for improved overall system performance when data transactions involve older or unsupported devices.

[0006] In the illustrative example, a system is disclosed comprising: a memory device and a first interface configured to connect to a first external device, wherein the first interface includes: a device side capable of performing a first data exchange with the first external device; a system side capable of performing a second data exchange with the memory device, wherein the system side is also capable of exchanging platform hints between the first interface and the memory device; and a hinting unit for filling platform hints in address bits.

[0007] In another example, a system-on-a-chip (SoC) is disclosed, comprising: a memory device; a first interface configured to communicate with a first device using a serial communication protocol, wherein the first interface enables the first device to write data to the memory device, and wherein the first interface is configured to transmit a platform hint to the memory device via address bits; and a second interface configured to communicate with a second device using a serial communication protocol, wherein the second interface enables the second device to read data written to the memory device by the first device.

[0008] In yet another example, a method for facilitating data transfer between a first device and a second device is disclosed, comprising: connecting the first device to a first interface; connecting the second device to a second interface; receiving data from the first device through the first interface; storing the data in a memory device; transmitting a platform prompt to the memory device, wherein the platform prompt is transmitted to the memory device through the first interface using address bits; and enabling the second device to retrieve the data stored in the memory device.

[0009] Additional features and advantages are described herein and will become apparent from the following description and figures. Attached Figure Description

[0010] This disclosure is described in conjunction with the accompanying drawings, which are not necessarily drawn to scale:

[0011] Figure 1 This is a block diagram illustrating a computing environment according to at least some embodiments of the present disclosure;

[0012] Figure 2 This is a block diagram illustrating another example of a computing environment according to at least some embodiments of the present disclosure;

[0013] Figure 3 This is a block diagram illustrating the data structures used according to at least some embodiments of the present disclosure;

[0014] Figure 4 This is a block diagram illustrating details of an interface according to at least some embodiments of the present disclosure; and

[0015] Figure 5This is a flowchart illustrating a method for facilitating data transmission between devices according to at least some embodiments of the present disclosure. Detailed Implementation

[0016] The following description provides only examples and is not intended to limit the scope, applicability, or configuration of the claims. Rather, the following description will provide those skilled in the art with a valid description for implementing the described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the spirit and scope of the appended claims.

[0017] From the following description and for computational efficiency reasons, it can be understood that system components can be placed anywhere appropriate within a distributed network of components without affecting the operation of the system.

[0018] Furthermore, it should be understood that the various links connecting the elements can be wired, traced, or wireless links, or any suitable combination thereof, or any other suitable known or later-developed element capable of providing data to and / or transmitting data from the connected elements. For example, the transmission medium used as a link can be any suitable electrical signal carrier, including coaxial cables, copper wires and optical fibers, electrical traces on a PCB, etc.

[0019] As used in this article, the phrases “at least one,” “one or more,” “or,” and “and / or” are open-ended expressions that are both operationally connected and separate. For example, each of the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C,” “A, B, and / or C,” and “A, B, or C” refers to: A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0020] As used herein, the term "automatic" and its variations refer to any suitable process or operation performed without substantial human input. However, a process or operation can be automatic even if its execution uses material or non-material human input, if the input is received prior to the execution of the process or operation. Human input is considered material if it influences how the process or operation is performed. It is agreed that human input used to perform a process or operation is not considered "material."

[0021] As used herein, the terms “determine,” “calculte,” and “compute,” and their variations, are used interchangeably and include any appropriate type of method, process, operation, or technique.

[0022] This document will describe various aspects of the disclosure with reference to the accompanying drawings, which are schematic diagrams of an idealized configuration.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries should be interpreted as having the same meaning as they have in the context of the relevant art and this disclosure.

[0024] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprise,” “comprises,” and / or “comprising” specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0025] Now for reference Figure 1-5 This disclosure describes various systems and methods for facilitating data transactions and transfers between devices. Embodiments of this disclosure address the problem of insufficient device support for specific attribute fields (e.g., platform hint attribute fields such as LLC fields, hidden hint fields, ST fields, RO fields, etc.) by utilizing unused address bits to convey attributes. As used herein, attributes conveyed in unused address bits or more may include platform hints. For example, a platform hint may correspond to a memory access hint or may be used to describe a device involved in a data transaction, the capabilities of the device involved in a data transaction, an interface involved in a data transaction, the capabilities of the interface involved in a data transaction, optimization parameters to be used in a data transaction (e.g., specifying a target cache for writing data, specifying the expected time of use for writing data, etc.), or other information describing combinations thereof.

[0026] Some embodiments consider using specific unused address bits, which may correspond to high address bits. Exemplarily and non-limitingly, PCIe interconnects and PCIe devices currently support 64-bit address sizes. While most PCIe devices do support the full 64-bit address, typical data transaction platforms only map a subset of the address range. For example, many currently available platforms use 40 to 56 bits for addressing, even if 64 bits are available for addressing.

[0027] Embodiments of this disclosure propose utilizing unused address bits. For example, a device driver may have the ability to fill in attributes or platform hints in addresses provided to the device for its use, based on the driver's knowledge of address usage. More specifically, the driver can be configured to fill address bits with platform hints or other attributes describing data payloads and memory control structures. In response to the driver, device hardware can be configured to transparently send platform hints or other attributes in full 64-bit address support without knowing that high address bits are being used to transmit information other than addressing information (e.g., platform hints or other attributes). In addition to unsupported standard features, embodiments of this disclosure also allow platforms to implement non-standard attribute sharing with minimal driver modifications.

[0028] First refer to Figure 1 An illustrative computing environment 100 is shown, in which a first device 108a is configured to participate in data exchange or data transactions with a second device 108b. System 104 can facilitate data transactions between the first device 108a and the second device 108b, and system 104 may also be referred to herein as a platform or system-on-a-chip (SoC).

[0029] System 104 is shown including a first interface 116a and a second interface 116b. The first interface 116a can be configured to connect directly or indirectly to a first device 108a. The second interface 116b can be configured to connect directly or indirectly to the second device 108b. In some embodiments, the first device 108a may correspond to a remote or external device relative to system 104, meaning that the first device 108a can be connected to the first interface 116a via one or more cables, links, etc. In some embodiments, the first device 108a may correspond to a remote device connected to the first interface 116a via a distributed communication network. In some embodiments, the first device 108a may correspond to a peripheral device directly attached to the first interface 116a or attached to the first interface 116a via a peripheral interconnect cable or card. The nature of the first interface 116a may depend on the nature of the first device 108a in use. Conversely, the nature of the first device 108a in use may depend on the nature of the first interface 116a.

[0030] The second device 108b may correspond to a device that is the same as or of a different type than the first device 108a. For example, the second device 108b may correspond to a remote or external device relative to system 104, meaning that the second device 108b can be connected to the second interface 116b via one or more cables, links, etc. In some embodiments, the second device 108b may correspond to a remote device connected to the second interface 116b via a distributed communication network. In some embodiments, the second device 108b may correspond to a peripheral device directly attached to the second interface 116b or attached to the second interface 116b via a peripheral interconnect cable or card. The nature of the second interface 116b may depend on the nature of the second device 108b in use. Conversely, the nature of the second device 108b in use may depend on the nature of the second interface 116b.

[0031] As described above, the first device 108a and the second device 108b can correspond to the same or different types of devices. As an example, the first device 108a can correspond to a peripheral device, while the second device 108b can correspond to a remote device. As another example, both the first device 108a and the second device 108b can correspond to either a remote device or a peripheral device. In some embodiments, the first interface 116a and the second interface 116b can correspond to the same or different types of interfaces. As a non-limiting example, both the first interface 116a and the second interface 116b can facilitate communication between the system 104 and the devices 108a and 108b via a serial communication protocol (e.g., PICe, USB, etc.).

[0032] System 104 is also shown to include a memory device 112, which can be shared and used to facilitate data transfer or data transactions between the first device 108a and the second device 108b. System 104 also includes a processor 120, a cache 124, and one or more drivers 128. Some or all of these components may be connected via a data bus, etc. For ease of discussion, system 104 is shown to have only two interfaces 116a, 116b. It should be understood that system 104 may include a greater number of interfaces (e.g., two, three, four, ..., ten, twenty, etc.). The number of interfaces provided in system 104 may vary without departing from the scope of this disclosure. As a non-limiting example, system 104 may be configured to have ten or more devices attached to it via dedicated interfaces, meaning that each device is connected to system 104 via a different interface. This means that system 104 may be designed to support data transfer between a large number of devices. Additional processor 120, memory device 112, and / or drivers 128 may also be required to support data transfer between a large number of devices.

[0033] Processor 120 may correspond to one or more computer processing devices. For example, processor 120 may be provided as silicon, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), any other type of integrated circuit (IC) chip, a collection of IC chips, etc. As a more specific example, processor 120 may be provided as a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), or multiple processing units configured to perform or implement the functions of system 104. As an example, processor 120 may be configured to execute one or more drivers 128 to operate or provide functionality to one or both of interfaces 116a, 116b. Driver 128 may be provided as instructions or instruction sets stored in memory device 112 or in a memory device other than memory device 112 (e.g., in the memory of processor 120).

[0034] As will be described in further detail herein, driver 128 may be executed at processor 120. Alternatively or additionally, driver 128 may be executed by a processor of an interface (e.g., a processor included in the first interface 116 and / or the second interface 116b). In some embodiments, driver 128 may be associated with a particular interface (e.g., the first interface 116a or the second interface 116b). To enable data transfer between the first device 108a and the second device 108b, processor 120 may execute a first driver associated with the first interface 116a and a second driver associated with the second interface 116b. In this way, processor 120 can coordinate the operation of the first interface 116a and the second interface 116b. Driver 128 may also be associated with memory device 112. Processor 120 may execute driver 128 associated with memory device 112 to facilitate data transfer or data transactions via memory device 112.

[0035] Memory device 112 may include any type of computer memory device or collection of computer memory devices. Non-limiting examples of memory device 112 include random access memory (RAM), read-only memory (ROM), flash memory, electrically erasable programmable ROM (EEPROM), dynamic RAM (DRAM), etc. Memory device 112 may be configured to store instruction sets, drivers 128, and / or data transferred between the first device 108a and the second device 108b. In cases where memory device 112 is used to store data transferred between the first device 108a and the second device 108b, memory device 112 may include buffer memory or any suitable computer memory device for temporary data storage.

[0036] Cache 124 may correspond to a memory location in or near processor 120. Cache 124 may be configured to store any information periodically accessed by processor 120 to facilitate data transfer. In some embodiments, cache 124 may be located between the data bus of processor 120 and system 104.

[0037] Now for reference Figure 2 This will describe another example of a computing environment according to at least some embodiments of the present disclosure. Figure 2 The computing environment illustrates a first device 108a as a first peripheral device 204a and a second device 108b as a second peripheral device 204b. System 104 is shown including interfaces particularly suited to support the first peripheral device 204a and the second peripheral device 204b. More specifically, system 104 is shown including a first PCIe interface 208a and a second PCIe interface 208b. The first PCIe interface 208a can be configured to connect the first peripheral device 204a to system 104. The second PCIe interface 208b can be configured to connect the second peripheral device 204b to system 104.

[0038] Although system 104 is Figure 2 The system is shown to have two PCIe interfaces 208a and 208b, but it should be understood that the system 104 can be configured to have more or fewer PCIe interfaces without departing from the scope of this disclosure. Furthermore, the system 104 can be configured to include one or more PCIe interfaces as well as one or more other interfaces (e.g., non-PCIe interfaces).

[0039] Now for reference Figure 3 This document describes an illustrative data structure 300 for facilitating data transmission or data transactions according to at least some embodiments of the present disclosure. The data structure 300 described herein is illustrative and can be used to facilitate data transmission or data transactions between a first device 108a and a second device 108b. Alternatively or additionally, the data structure 300 described herein can be used to facilitate data transmission or data transactions between a first peripheral device 204a and a second peripheral device 204b.

[0040] Data structure 300 is shown as including a receive queue pointer (RQ ptr) 304 and a completion queue pointer (CQ ptr) 308. RQ ptr 304 can be used to store data pointing to (e.g., links, pointers, references, etc.) one or more work queue elements (WQEs) 312 in the receive queue (RQ). CQ ptr 308 can be used to store data pointing to (e.g., links, pointers, references, etc.) one or more completion queue elements (CQEs) 316 in the completion queue (CQ). Each of the WQEs 312 may contain data pointing to (e.g., links, pointers, references, etc.) a receive data buffer 320. The receive data buffer 320 may correspond to a memory location or a specific sub-component of memory device 112.

[0041] Processor 120 can use data structure 300 to facilitate data transfer or data transactions. In some embodiments, first device 108a can use data structure 300 to transfer data to second device 108b. In this example, first device 108a can read WQE 312 and write data to one of data buffers 320 using a pointer read from WQE 312. After first device 108a has written data to data buffer 320, first device 108a can write a completion record in CQE 316 associated with the data buffer 320 where data was just written.

[0042] Processor 120 can then obtain CQE 316 associated with data buffer 320 that just received data from first device 108a, and generate appropriate control for second device 108b to read data from data buffer 320. In this example, system 104 can place the data written to data buffer 320 into shared memory device 112, while placing CQE 316 associated with data buffer 320 into processor 120's local cache 124.

[0043] The above process can still be supported even if the first device 108a and / or the second device 108b do not support advanced hint features (e.g., the device is a non-supporting device and is not designed to utilize platform hints or other attributes to make data transfer more efficient). To implement the data transfer as described above for a non-supporting device, the driver 128 of the first device 108a is configured to write a platform hint or attribute indicating the location of the CQE 316 in the access cache 124. In some embodiments, the platform hint or attribute may be written to the high bits and unused bits of the CQ ptr 308. Similarly, the driver 128 of the first device 108a may be configured to write a platform hint or attribute indicating the location of accessed data, and may write the platform hint or attribute to a buffer pointer within the WQE 312.

[0044] It is understood that some devices may be configured to support prompts and may not need to use unused address bits as described herein to share platform prompts or other attributes. Therefore, system 104 and one or more of its interfaces 116a, 116b may be configured to switch between two operating modes. In one mode (e.g., first prompt mode), the interface driver 128 may be configured to utilize unused address bits to share platform prompts or other attributes. In the other mode (e.g., second prompt mode), the interface driver 128 may be configured to use defined fields (e.g., ST, RO, etc.) to share platform prompts or other attributes.

[0045] Now refer to Figure 4 Additional details are provided to describe interface 116, which has the ability to operate in different prompting modes. Figure 4 In the example, interface 116 (which may correspond to examples of first interface 116a, second interface 116b, first PCIe interface 208a, or second PCIe interface 208b) is shown as including a deserializer 404 and multiple signal paths for transmitting information between the device side 412 and the system side 416 of interface 116. The device side 412 of interface 116 is exposed to device 108. Device side 412 may include mechanical and / or electrical interconnections capable of being directly connected to device 108 or a cable connected to device 108. When device 108 is connected to interface 412, a serial data link 420 can be established to transmit data between device 108 and interface 116.

[0046] The system side 416 of interface 116 may be exposed to system interconnect 408. System side 416 may include mechanical and / or electrical interconnects that enable interface 116 to exchange data with other components of system 104. In some embodiments, one or more links may be used on system side 416 to exchange information between interface 116 and system interconnect 408. In some embodiments, system side 416 may include one or more paths for exchanging data 424, address bits 428, and platform hints 432. Data 424 may be transmitted via a data path, while address bits 428 and platform hints 432 may be transmitted via an address path or other bits designated for transmitting platform hints or attributes.

[0047] Interface 412 may include a switch 436 for transmitting platform hint 432 to system interconnect 408. In some embodiments, switch 436 may correspond to a multiplexer or switching circuit configured to receive additional address bits 440 and hint bits 444. If device 108 is configured to utilize dedicated hint bits 444, switch 436 may be configured to transmit hint bits 444 at platform hint 432 to system interconnect 408. Alternatively, if device 108 is not configured to use dedicated hint bits 444, platform hints or attributes may be received via additional address bits 440, which are transmitted to system interconnect 408 via platform hint 432. In some embodiments, operation of switch 436 may be controlled by driver 128 of interface 116. Driver 128 may be configured to determine whether interface 116 should be in a first configuration in which additional address bits 440 are used to transmit platform hints or attributes, and then transmit them as platform hint 432 via system side 416. Driver 128 can also be configured to determine whether interface 116 can operate in a second configuration, in which cue bit 444 is transmitted as platform cue 432 via system side 416. In other words, driver 128 for interface 116 can be configured to determine whether interface 116 will operate in a first cue mode or a second cue mode. In this way, driver 128 for interface 116 can be considered to implement a cue unit that, in conjunction with the selectable operation of switch 436, enables interface 116 to support the sharing of platform cue 432, even if device 108 itself does not support cue bit 444.

[0048] In some embodiments, mode selection can determine whether the switch 436 provided at the output of deserializer 404 uses a hint bit 444 or additional address bits 440 to populate the platform hint 432. As a non-limiting example, if device 108 has ST / RO enabled, interface 116 can be configured by its driver 128 to pass the hint bit 444, which may correspond to ST and / or RO attributes, as the platform hint 432 to system side 416. If device 108 does not have ST / RO enabled, interface 116 can be configured by its driver 128 to transmit the platform hint contained in the additional address bits 440 as the platform hint 432. Any hint can be transmitted using the additional address bits 440. Non-limiting examples of hints that can be transmitted using the additional address bits 440 include LLC hints, hidden hints, ST attributes, and RO attributes. Receiving the platform hint 432, whether as a hint bit 444 or additional address bits 440, allows system 104 to optimize or increase efficiency associated with data transmission or data transactions. In some embodiments, platform hint 432 can be used to define the amount of time that data 424 should be temporarily stored in data buffer 320. In some embodiments, platform hint 432 can be used to specify at least one of the target cache for writing data 424 and / or the expected duration of use of data 424 for writing to memory device 112. In some embodiments, processor 120 can use platform hint 432 to determine how cache 124 is used and / or how memory device 112 is used.

[0049] Now for reference Figure 5 Additional details of a method 500 for facilitating data transfer between devices according to at least some embodiments of the present disclosure will be described. Method 500 begins by connecting a first device 108a to a first interface 116a of system 104 (step 504). The first device 108a may be electrically and / or mechanically connected to the first interface 116a. In some embodiments, the first device 108a is connected to the device side 412 of the first interface 116a, thereby establishing a serial data link 420 between the two. The first device 108a may communicate with the first interface 116a using a serial communication protocol.

[0050] Method 500 continues by connecting the second device 108b to the second interface 116b of system 104 (step 508). The second device 108b may be electrically and / or mechanically connected to the second interface 116b. In some embodiments, the second device 108b is connected to the device side 412 of the second interface 116b, thereby establishing a serial data link 420 between the two. The second device 108b may communicate with the second interface 116b using a serial communication protocol, which may be the same as or different from the communication protocol used between the first device 108a and the first interface 116a.

[0051] When the first device 108a begins the process of writing data 424 into the memory device 112, method 500 then continues in the memory device 112, where it can subsequently be retrieved by the second device 108b. During this data transfer, method 500 may include receiving data 424 from the first device 108a (step 512). Data 424 may be received via the first interface 116a. In some embodiments, data 424 may be stored in the memory device 112 (step 516). Before, during, or after this data transfer process, the first interface 116a may be configured to transmit a platform hint 432 to the processor 120 (step 520). In some embodiments, the platform hint 432 may be transmitted via the first interface 116a using additional address bits 440. In some embodiments, the platform hint 432 may be transmitted via the first interface 116a using defined hint bits 444.

[0052] Upon receiving platform prompt 432, the processor 120, which controls data transfer between the first device 108a and the second device 108b, may optionally use platform prompt 432 to control the storage of data 424 and / or the amount of time data 424 is stored in memory (step 524). Once data 424 is written to memory device 112, the second device 108b can retrieve data 424 from its storage location (step 528). In some embodiments, the second device 108b may use one or more of platform prompts 432 to assist in retrieving data 424 from memory.

[0053] Specific details are set forth in the description to provide a thorough understanding of the embodiments. However, those skilled in the art will understand that the embodiments can be practiced without these specific details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail to avoid obscuring the embodiments.

[0054] Although illustrative embodiments of this disclosure have been described in detail herein, it should be understood that the inventive concept can be practiced and employed in other ways, and the appended claims are intended to be construed as including such variations, unless limited by the prior art.

Claims

1. A system for facilitating data transactions and transmissions between devices, comprising: Memory devices; A first interface configured to connect to a first external device, wherein the first interface includes: On the device side, it is able to perform a first data exchange with the first external device; On the system side, it is capable of performing a second data exchange with the memory device, wherein the system side is also capable of exchanging platform hints between the first interface and the memory device; and The prompting unit, when operating in a first prompting mode, fills the platform prompt in the address bits, and when operating in a second prompting mode, fills the platform prompt in the defined prompt field; Processor; and A cache memory coupled to the processor, wherein the processor utilizes the platform hints and the cache memory to facilitate data transfer between the first external device and the second external device via the memory device, wherein the data transfer includes data in the first data exchange and data in the second data exchange.

2. The system of claim 1, wherein the platform prompt includes a memory access prompt.

3. The system of claim 1, wherein the address bits include unused address bits.

4. The system of claim 3, wherein the first external device includes a first peripheral device, wherein the first interface includes a first peripheral component interconnect interface, and wherein, The unused address bits correspond to the high address bits.

5. The system of claim 4, further comprising: A second peripheral component interconnect interface, configured to connect to a second peripheral device, wherein the second peripheral component interconnect interface includes: On the device side, it is able to exchange third data with the second peripheral device; On the system side, it is capable of a fourth data exchange with the memory device, wherein the system side of the second peripheral component interconnect interface is also capable of exchanging additional platform hints between the second peripheral component interconnect interface and the memory device; and The second prompting unit fills the additional platform prompt in the additional address bits.

6. The system of claim 1, wherein the memory device includes one or more data buffers configured to temporarily store data written therein by the first external device for at least a predetermined amount of time.

7. The system of claim 6, wherein the predetermined time amount is determined at least in part based on the platform prompt.

8. The system of claim 1, wherein the platform hint includes a memory access hint, and wherein the memory access hint includes at least one of the following: last-level cache LLC hint, hidden hint, redirection marker ST, and loose sort RO attribute.

9. The system of claim 1, wherein the platform prompts at least one of the target cache for writing data and the expected time of use of the data written to the memory device by the first external device.

10. A system-on-a-chip (SoC), comprising: Memory devices; A first interface is configured to communicate with a first device using a serial communication protocol, wherein the first interface enables the first device to write data to the memory device, and wherein the first interface is configured to transmit a platform prompt to the memory device via an address bit when operating in a first prompt mode, and to transmit the platform prompt to the memory device in a defined prompt field when operating in a second prompt mode. as well as A second interface is configured to communicate with a second device using the serial communication protocol, wherein the second interface enables the second device to read data written to the memory device by the first device.

11. The SoC of claim 10, wherein the platform hint includes a memory access hint specifying at least one of a target cache for data written to the memory device and an expected time of use of the data written to the memory device.

12. The SoC of claim 10, wherein the platform hint includes a memory access hint, and wherein the first interface includes a first peripheral component interconnect interface.

13. The SoC of claim 12, wherein the first peripheral component interconnect interface includes a switch for changing between the first prompting mode and the second prompting mode.

14. The SoC of claim 12, wherein the defined hint field includes at least one of a turn flag (ST) field and a loose sort (RO) attribute field.

15. The SoC of claim 10, wherein the first device includes at least one of a first peripheral device and a first remote device, wherein the second device includes at least one of a second peripheral device and a second remote device, and wherein the first interface includes a deserializer.

16. The SoC of claim 10, wherein the serial communication protocol includes at least one of the Peripheral Component Interconnect Fast PCIe protocol and the Universal Serial Bus (USB) protocol.

17. A method for facilitating data transmission between a first device and a second device, the method comprising: Connect the first device to the first interface; Connect the second device to the second interface; Receive data from the first device through the first interface; The data is stored in a memory device; When operating in the first prompt mode, the platform prompts the use of address bits to transmit the information to the memory device through the first interface; When operating in the second prompt mode, the platform prompt is transmitted to the memory device through the first interface using the defined prompt fields; as well as This enables the second device to retrieve the data stored in the memory device.

18. The method of claim 17, wherein the platform prompt includes a memory access prompt, and wherein, The memory access hints are used by the controller of the memory device to optimize the storage of the data in the memory device.

19. The method of claim 18, wherein the memory access hint specifies at least one of a target cache of data stored in the memory device and an expected time of use of the data stored in the memory device.

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