Comparator offset voltage test circuit

Abstract

A comparator offset voltage testing circuit, one end of a parallel circuit of a feedback resistor Rf and a feedforward capacitor Cf is connected to a comparator output terminal Vout, the other end is connected to a negative input terminal of the comparator, the negative input terminal of the comparator is connected to a positive input terminal of the comparator and a positive terminal of a voltage source through an input resistor Ri respectively, a negative terminal of the voltage source is grounded, the comparator offset voltage Vos can be obtained from the formula V OS =V out ÷(1+R f / R i ), the testing circuit is simple, the testing precision is high, and when the comparator is working normally, the added circuit will not affect the working and performance of the comparator.

Description

Technical Field

[0001] This invention relates to comparator offset voltage testing technology, and in particular to a comparator offset voltage testing circuit, which uses a feedback resistor R f and feedforward capacitor C f One end of the parallel circuit is connected to the comparator output terminal V. out The other end is connected to the negative input of the comparator, which is connected to the input resistor R. i Connect the comparator's positive input terminal and the positive terminal of the voltage source respectively, with the negative terminal of the voltage source grounded. This allows us to obtain the value from formula V. OS = V out ÷ (1 + R f / R i The comparator offset voltage V is obtained. os The test circuit is simple, the test accuracy is high, and the added circuit will not affect the operation and performance of the comparator when the comparator is working normally. Background Technology

[0002] A voltage comparator can be viewed as an operational amplifier with a gain approaching infinity. The function of a voltage comparator is to compare the magnitudes of two voltages (the output voltage's high or low level indicates the relationship between the two input voltages): when the voltage at the "+" input is higher than the voltage at the "-" input, the voltage comparator outputs a high level; when the voltage at the "+" input is lower than the voltage at the "-" input, the voltage comparator outputs a low level. The inputs of a voltage comparator are analog quantities, while the output is a digital quantity (high or low level). For simplicity, this article will simply refer to the voltage comparator as a comparator.

[0003] Figure 1 These are two common comparator structures: (a) has an open-drain output stage, and (b) has a push-pull output stage. Figure 1 (a) The comparator with an open-drain output stage includes a first preamplifier operational amplifier A1 with a positive input terminal In+ and a negative input terminal In-. The output of A1 is sequentially connected to a second inverter I2, a third inverter I3, and a fourth inverter I4. The output of I4 is connected to an NMOS output transistor M. nout The gate, M nout The source is grounded, M nout The drain is connected to the output voltage terminal V. out The other path is through pull-up resistor R. pu Connect to the power supply voltage terminal. Figure 1 (b) The comparator with a push-pull output stage includes a second preamplifier operational amplifier A2 with a positive input terminal In+ and a negative input terminal In-. The output of A2 is sequentially connected to the fifth inverter I5, the sixth inverter I6, and the seventh inverter I7. The output of I7 is connected to the NMOS output transistor M.nout The gate, M nout The source is grounded, M nout The drain is connected to the output voltage terminal V. out Connect PMOS output transistor M pout The drain, M pout The source terminal of A2 is connected to the power supply voltage terminal, and the other output terminal of A2 is sequentially connected to the eighth inverter I8, the ninth inverter I9, and the tenth inverter I1. 10 I 10 The output terminal is connected to the PMOS output transistor M. pout The gate.

[0004] The main technical specifications of a comparator are speed and accuracy. The comparator's speed determines the shortest time interval in which it can correctly interpret an analog signal; accuracy, specifically the offset voltage, determines the minimum voltage difference in which the comparator can correctly interpret an analog signal. Therefore, comparator chips need to be able to accurately measure both speed and accuracy. Testing comparator speed is not technically difficult, but due to the unique nature of comparators not being able to be used in a closed-loop system, accurately measuring the comparator's offset voltage is challenging.

[0005] by Figure 1 Taking a comparator as an example, A1 and A2 are preamplifier operational amplifiers, contributing to the offset voltage; they can be connected in a closed-loop configuration. The comparator circuit also contains I2~I... 10 These inverter circuits are used to shape and amplify the outputs of pre-amplified operational amplifiers A1 and A2. Because the inverters have very high gain, the comparators cannot be stably connected in a closed loop, making it impossible to test the comparator offset voltage using a closed-loop method. Traditional methods for testing comparator offset voltage include... Figure 2 As shown, the comparator operates in open-loop mode. One input is fixed to a DC voltage, while the other input is a precisely adjustable DC voltage. The comparator's output state is observed: when the input voltage difference is large, the comparator outputs a stable "0" or "1"; when the input voltage difference approaches the offset voltage, the comparator output becomes both "0" and "1"; then, by fine-tuning the input voltage to make the probabilities of outputting "0" and "1" equal, the comparator is in a metastable state, and the voltage difference at the input terminals at this point is the comparator's offset voltage. If the offset voltage is to be observed for an extended period due to external factors such as temperature and power supply voltage, the metastable state of the comparator needs to be actively sought continuously, placing high demands on the complexity of the entire test system control. Therefore, it is best to incorporate offset voltage measurability design during the comparator chip design phase to simplify the development of the test system. Summary of the Invention

[0006] This invention addresses the defects or deficiencies in existing technologies by providing a comparator offset voltage testing circuit, which utilizes the feedback resistor Rf and feedforward capacitor C f One end of the parallel circuit is connected to the comparator output terminal V. out The other end is connected to the negative input of the comparator. The negative input of the comparator is connected to the positive input of the comparator and the positive terminal of the voltage source respectively through the input resistor Ri. The negative terminal of the voltage source is grounded. This can be obtained from the formula V... OS = V out ÷ (1 + R f / R i The comparator offset voltage V is obtained. os The test circuit is simple, the test accuracy is high, and the added circuit will not affect the operation and performance of the comparator when the comparator is working normally.

[0007] The technical solution of the present invention is as follows:

[0008] A comparator offset voltage testing circuit, characterized in that it includes a feedback resistor R f and feedforward capacitor C f The parallel circuit is constructed, with one end of the parallel circuit connected to the output terminal V of the comparator. out The other end of the parallel circuit is connected to the input resistor R. i One end of the input resistor R is connected to the negative input of the comparator. i The other end is connected to the positive input terminal of the comparator and the positive terminal of the voltage source, respectively, and the negative terminal of the voltage source is grounded. The offset voltage V of the comparator os = V out ÷ (1 +R f / R i ).

[0009] The voltage source has a setpoint of 0V, and R is selected. f >>R i .

[0010] The comparator is a comparator with an open-drain output stage, including a first pre-amplifier operational amplifier with a positive input terminal In+ and a negative input terminal In-. The output of the first pre-amplifier operational amplifier is connected to the first input terminal of the 21st NOR gate circuit. The output of the 21st NOR gate circuit is sequentially connected to the 11th inverter and the 12th inverter. The output of the 12th inverter is connected to the NMOS output transistor M. nout The gate of the first pre-amplified operational amplifier is connected to the source of the first NMOS switch, and the first NMOS switch is connected to the M... nout After the drains are interconnected, one path is connected to the output voltage terminal, and the other path is connected to the power supply voltage terminal through a pull-up resistor. The M... noutThe source of the transistor is grounded, and the second input terminal of the 21st NOR gate circuit and the gate of the first NMOS switch are respectively connected to the comparator offset voltage test mode selection unit circuit.

[0011] The comparator is a comparator with a push-pull output stage, including a second pre-amplifier operational amplifier with a positive input terminal In+ and a negative input terminal In-. The first output of the second pre-amplifier operational amplifier is connected to the source of a second NMOS switch, and the drain of the second NMOS switch is connected to the output voltage terminal. The second output of the second pre-amplifier operational amplifier is connected to the first input of a 22nd NOR gate circuit. The output of the 22nd NOR gate circuit is sequentially connected to a 13th inverter and a 14th inverter. The output of the 14th inverter is connected to an NMOS output transistor M. nout The gate of the M nout The source of M is grounded. nout The drain of the second pre-amplified operational amplifier is connected to the output voltage terminal. The third output of the second pre-amplified operational amplifier is connected to the first input terminal of the 21st NAND gate circuit. The output of the 21st NAND gate circuit is sequentially connected to the 15th inverter and the 16th inverter. The output of the 16th inverter is connected to the PMOS output transistor M. pout The gate of the M pout The source of M is connected to the power supply voltage terminal. pout The drain of the circuit is connected to the output voltage terminal. The second input terminal of the 21st NAND gate, the gate of the second NMOS switch, and the second input terminal of the 22nd NOR gate are respectively connected to the comparator offset voltage test mode selection unit circuit.

[0012] The comparator offset voltage test mode selection unit circuit includes a latch. The first input terminal of the latch is a first node, the second input terminal is connected to the power-on reset terminal por, the output terminal of the latch is a second node, the second node is connected to the input terminal of a first inverter, the output terminal of the first inverter is a third node, and the first node is connected to the power supply voltage terminal V through a current source. cc The other path is connected to the drain of the NMOS power transistor, the gate of the NMOS power transistor is grounded, and the source of the NMOS power transistor is connected to an RC circuit.

[0013] The third node is connected to the second input terminal of the 21st NOR gate circuit and the gate of the first NMOS switch, respectively.

[0014] The second node is connected to the second input terminal of the 21st NAND gate circuit, and the third node is connected to the second input terminal of the 22nd NOR gate circuit and the gate of the second NMOS switch, respectively.

[0015] The latch includes a first NAND gate circuit and a second NAND gate circuit. The first input terminal of the first NAND gate circuit is connected to the first node, the second input terminal of the first NAND gate circuit is connected to the second node, the output terminal of the first NAND gate circuit is connected to the first input terminal of the second NAND gate circuit, the second input terminal of the second NAND gate circuit is connected to the power-on reset terminal por, and the output terminal of the second NAND gate circuit is connected to the second node.

[0016] The RC circuit includes a first resistor R1 and a first capacitor C1. One end of R1 and one end of C1 are interconnected and connected to the source of the NMOS power transistor. The other end of R1 is connected to the positive input terminal In+, and the other end of C1 is grounded.

[0017] The timing rise of the por is greater than that of the V. cc The timing is lagging behind.

[0018] The technical effects of this invention are as follows: Compared with the prior art, the peripheral test circuit of this invention is simple and can directly test the offset voltage of the comparator with high accuracy; when the comparator is working normally, the added circuit will not affect the operation and performance of the comparator.

[0019] The present invention discloses a comparator in a comparator offset voltage test circuit, including a comparator with an open-drain output stage and a comparator with a push-pull output stage, both of which have offset voltage measurability design, thereby simplifying the development of the test system. Attached Figure Description

[0020] Figure 1 These are schematic diagrams of two common comparator structures in existing technology. Figure 1 Including Figure 1 (a) and Figure 1 (b). Figure 1 (a) is a comparator with an open-drain output stage. Figure 1 (b) is a comparator with a push-pull output stage.

[0021] Figure 2 It is aimed at Figure 1 The diagram shows the structural principle of the comparator used in the comparator offset voltage test.

[0022] Figure 3 This is a schematic diagram of the comparator offset voltage test mode selection unit circuit.

[0023] Figure 4 These are schematic diagrams of two comparator structures for implementing a comparator offset voltage test circuit according to the present invention. Figure 4 Including Figure 4(a) and Figure 4 (b). Figure 4 (a) is a comparator with an open-drain output stage. Figure 4 (b) is a comparator with a push-pull output stage.

[0024] Figure 5 This is a schematic diagram illustrating the principle of a comparator offset voltage testing circuit for implementing the present invention.

[0025] The reference numerals in the attached figures are listed below: V cc - Power supply voltage terminal; por- Power-on reset terminal; V out - Output voltage terminal; In+- Positive input terminal; In-- Negative input terminal; V os - Offset voltage; A1~A2 - First to second pre-amplification operational amplifiers; Opaout - Op-amp output (simply referred to as output); Comp - Comparator; I t - Current source; t1~t3- First node to third node; M nt -NMOS power transistor; M nout -NMOS output transistor; M pout -PMOS output transistor; M nsw1 ~M nsw2 - First to second NMOS switches; R1 - First resistor; R i -Input resistance; R f -Feedback resistor; R pu - Pull-up resistor; C1 - First capacitor; C f - Feedforward capacitor; N1~N2 - First to second NAND gate circuits; NAND 21 - 21st NAND gate; Nor 21 ~Nor 22 - NOR gates 21 to 22; I1 to I 16 - First to sixteenth inverters; L1 - First latch. Detailed Implementation

[0026] The following is in conjunction with the attached diagram ( Figures 3-5 The present invention will be described in conjunction with the embodiments.

[0027] Figure 3 This is a schematic diagram of the comparator offset voltage test mode selection unit circuit. Figure 4 These are schematic diagrams of two comparator structures for implementing a comparator offset voltage test circuit according to the present invention. Figure 4 Including Figure 4 (a) and Figure 4 (b). Figure 4 (a) is a comparator with an open-drain output stage. Figure 4 (b) is a comparator with a push-pull output stage. Figure 5 This is a schematic diagram illustrating the principle of a comparator offset voltage testing circuit implementing the present invention. (Reference) Figures 3 to 5 As shown, a comparator offset voltage test circuit includes a feedback resistor R. f and feedforward capacitor C f The parallel circuit is constructed, one end of which is connected to the output terminal V of the comparator Comp. out The other end of the parallel circuit is connected to the input resistor R. i One end of the comparator Comp is connected to the negative input terminal (-), and the input resistor R is connected to the negative input terminal (-). i The other end is connected to the positive input terminal (+) of comparator Comp and the positive terminal (+) of voltage source, respectively, and the negative terminal (-) of voltage source is grounded. The offset voltage V of comparator Comp is... os = V out ÷ (1 + R f / R i The voltage source has a setpoint of 0V, and R is selected. f >>R i .

[0028] The comparator Comp is a comparator with an open-drain output stage, including a first pre-amplifier operational amplifier A1 with a positive input terminal In+ and a negative input terminal In-. The output terminal Opaout of the first pre-amplifier operational amplifier A1 is connected to the 21st NOR gate circuit Nor. 21 The first input terminal of the 21st NOR gate circuit. 21 The output terminals are sequentially connected to the eleventh inverter I. 11 Twelfth inverter I 12 The twelfth inverter I 12 The output terminal is connected to the NMOS output transistor M. nout The gate of the first preamplifier operational amplifier A1, whose output terminal Opaout is connected to the first NMOS switch Mn, is another path connected to the first NMOS switch Mn. sw1 The source of the first NMOS switch M nsw1 With the M nout After the drains are interconnected, one path is connected to the output voltage terminal V. out The other path is through pull-up resistor R. pu Connect to power supply voltage terminal V cc The M nout The source of the 21st NOR gate is grounded. 21 The second input terminal and the first NMOS switch M nsw1 The gates of the circuits are respectively connected to the comparator offset voltage test mode selection unit circuit.

[0029] The comparator Comp is a comparator with a push-pull output stage, including a second pre-amplifier operational amplifier A2 with a positive input terminal In+ and a negative input terminal In-. The output terminal Opaout of the second pre-amplifier operational amplifier A2 is first connected to the second NMOS switch Mn. sw2 The source of the second NMOS switch Mn sw2 The drain is connected to the output voltage terminal V. out The output of the second preamplifier operational amplifier A2 is connected in the second path to the 22nd NOR gate circuit. 22 The first input terminal, the 22nd NOR gate circuit Nor 22 The output terminals are sequentially connected to the thirteenth inverter I. 13 Fourteenth inverter I 14 The fourteenth inverter I 14 The output terminal is connected to the NMOS output transistor M. nout The gate of the M nout The source of M is grounded. nout The drain is connected to the output voltage terminal V. out The third output of the second preamplifier operational amplifier A2 is connected to the 21st NAND gate circuit. 21 The first input terminal of the 21st NAND gate circuit 21 The output terminals are sequentially connected to the fifteenth inverter I. 15 Sixteenth Inverter I 16 The sixteenth inverter I 16 The output terminal is connected to the PMOS output transistor M. pout The gate of the M pout The source is connected to the power supply voltage terminal V. cc The M pout The drain is connected to the output voltage terminal V. out The 21st NAND gate circuit 21 The second input terminal, the second NMOS switch M nsw2 The gate and the 22nd NOR gate circuit Nor 22 The second input terminal is connected to the comparator offset voltage test mode selection unit circuit.

[0030] The comparator offset voltage test mode selection unit circuit includes a first latch L1. The first input terminal of the first latch L1 is a first node t1, and the second input terminal is connected to the power-on reset terminal por. The output terminal of the first latch L1 is a second node t2, which is connected to the input terminal of a first inverter I1. The output terminal of the first inverter I1 is a third node t3, and the first node t1 is connected to a current source I. t Connect to power supply voltage terminal Vcc The other path is connected to the NMOS power transistor M. nt The drain of the NMOS power transistor M nt The gate of the NMOS power transistor M is grounded. nt The source is connected to an RC circuit.

[0031] The third node t3 is connected to the 21st NOR gate circuit Nor. 21 The second input terminal and the first NMOS switch M nsw1 The gate.

[0032] The second node t2 is connected to the 21st NAND gate circuit. 21 The second input terminal, the third node t3 is respectively connected to the 22nd NOR gate circuit Nor 22 The second input terminal and the second NMOS switch M nsw2 The gate.

[0033] The first latch L1 includes a first NAND gate N1 and a second NAND gate N2. The first input of the first NAND gate N1 is connected to the first node t1, the second input of the first NAND gate N1 is connected to the second node t2, the output of the first NAND gate N1 is connected to the first input of the second NAND gate N2, the second input of the second NAND gate N2 is connected to the power-on reset terminal por, and the output of the second NAND gate N2 is connected to the second node t2. The RC circuit includes a first resistor R1 and a first capacitor C1. One end of R1 and one end of C1 are interconnected and connected to the source of the NMOS power transistor. The other end of R1 is connected to the positive input terminal In+, and the other end of C1 is grounded. The rising edge of the timing of por is earlier than that of V. cc The timing is lagging behind.

[0034] like Figure 3 The left side shows the comparator offset voltage test mode selection unit, and the right side shows the POR at V. CC The power-on timing. The mode selection unit includes current source I. t Power transistor M nt The system consists of a latch L1 composed of NAND gates N1 and N2, an inverter I1, a resistor R1, and a capacitor C1; the mode selection unit can be based on the power transistor M. nt To achieve the identification of the comparator's positive input signal In+, the gate of this power transistor is connected to ground. V CC Upon initial power-up, In+ is made greater than or equal to ground potential, therefore M nt Cut-off, current source I t Raise node t1 to V. CC V CCUpon initial power-up, por is initially low, resetting latch L1. Node t2 is high, and node t3 is low. After a period of time, por becomes high again, no longer affecting latch L1. This state is the normal operating mode of the comparator.

[0035] When it is necessary to test the comparator's offset voltage, In+ is supplied with a lower potential relative to ground for a duration greater than 6 R1. C1 is the time constant. At this point, Mn... t The circuit is on and the drain-source current is greater than the current source I. t Pulling node t1 low, then node t2 goes low and node t3 goes high; this state is the offset voltage test mode. Due to the latching effect of latch L1, as long as V... CC Without power loss, the circuit will remain in offset voltage test mode. Then, In+ can be the value required for offset voltage testing to perform offset voltage testing on the comparator.

[0036] Resistors R1 and C1 form a low-pass filter to prevent high-frequency negative pulses on the In+ pin from falsely triggering the offset voltage test mode when the comparator is working normally.

[0037] Figure 4 The comparators are designed to incorporate offset voltage measurability. (a) has an open-drain output stage, and (b) has a push-pull output stage. Figure 5 This is a test circuit for testing the comparator offset voltage after incorporating the circuit of the present invention. Preferably, the comparator power supply is a dual positive and negative power supply.

[0038] For the open-drain structure (a): In offset voltage test mode, node t3 is high, Nor 21 The output is low, therefore node ngate is low, thus M nout Deadline. M nsw1 Turn on the circuit, directly connecting the output node Opaout of the preamplifier operational amplifier A1 to the comparator output V. out Then press Figure 5 When configuring a test circuit, R can be selected. f Much larger than R i C f As a feedforward capacitor, it can stabilize the negative feedback loop. V can be obtained. OS = V out ÷ (1 + R f / R i This method is consistent with the commonly used test method for operational amplifier offset voltage, thus enabling direct and accurate testing of the comparator's offset voltage. In the comparator's normal operating mode, node t3 is low, Nor... 21 The output is controlled by the output node Opaout of A1, and M nsw1The cutoff time does not affect the normal operation of the comparator.

[0039] For push-pull structure (b): In offset voltage test mode, node t2 is low, Nand 21 The output is high, therefore the node pgate is high, thus M pout Deadline; node t3 is high, Nor 22 The output is low, therefore node ngate is low, thus M nout Deadline. M nsw2 Turn on the circuit, directly connecting the output node Opaout of the preamplifier operational amplifier A2 to the comparator output V. out .according to Figure 5 When configuring a test circuit, R can be selected. f Much larger than R i C f As a feedforward capacitor, it can stabilize the negative feedback loop. V can be obtained. OS = V out ÷(1 + R f / R i This method, consistent with common operational amplifier offset voltage testing methods, allows for direct and accurate measurement of the comparator's offset voltage. In normal comparator operation, node t2 is high and node t3 is low. (Nand...) 21 and Nor 22 The output is controlled by the output node Opaout of A2, and M nsw2 The cutoff time does not affect the normal operation of the comparator.

[0040] The advantages of this invention are that, compared with the prior art, the peripheral test circuit of this invention is simple and can directly test the offset voltage of the comparator with high test accuracy; when the comparator is working normally, the added circuit will not affect the operation and performance of the comparator.

[0041] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A comparator offset voltage testing circuit, characterized in that, Including the feedback resistor R f and feedforward capacitor C f The parallel circuit is constructed, with one end of the parallel circuit connected to the output terminal V of the comparator. out The other end of the parallel circuit is connected to the input resistor R. i One end of the input resistor R is connected to the negative input of the comparator. i The other end is connected to the positive input terminal of the comparator and the positive terminal of the voltage source, respectively, and the negative terminal of the voltage source is grounded. The offset voltage V of the comparator os = V out ÷ (1 +R f / R i ); The comparator is a comparator with an open-drain output stage, or the comparator is a comparator with a push-pull output stage. The comparator with an open-drain output stage includes a first pre-amplifier operational amplifier with a positive input terminal In+ and a negative input terminal In-. The output of the first pre-amplifier operational amplifier is connected to the first input terminal of a 21st NOR gate circuit. The output of the 21st NOR gate circuit is sequentially connected to an eleventh inverter and a twelfth inverter. The output of the twelfth inverter is connected to an NMOS output transistor M. nout The gate of the first pre-amplified operational amplifier is connected to the source of the first NMOS switch, and the first NMOS switch is connected to the M... nout After the drains are interconnected, one path is connected to the output voltage terminal, and the other path is connected to the power supply voltage terminal through a pull-up resistor. The M... nout The source of the NOR gate is grounded, and the second input terminal of the 21st NOR gate and the gate of the first NMOS switch are respectively connected to the comparator offset voltage test mode selection unit circuit. The comparator with a push-pull output stage includes a second pre-amplifier operational amplifier with a positive input terminal In+ and a negative input terminal In-. The first output of the second pre-amplifier operational amplifier is connected to the source of a second NMOS switch, and the drain of the second NMOS switch is connected to the output voltage terminal. The second output of the second pre-amplifier operational amplifier is connected to the first input of a 22nd NOR gate circuit. The output of the 22nd NOR gate circuit is sequentially connected to a 13th inverter and a 14th inverter. The output of the 14th inverter is connected to an NMOS output transistor M. nout The gate of the M nout The source of M is grounded. nout The drain of the second pre-amplified operational amplifier is connected to the output voltage terminal. The third output of the second pre-amplified operational amplifier is connected to the first input terminal of the 21st NAND gate circuit. The output of the 21st NAND gate circuit is sequentially connected to the 15th inverter and the 16th inverter. The output of the 16th inverter is connected to the PMOS output transistor M. pout The gate of the M pout The source of M is connected to the power supply voltage terminal. pout The drain of the circuit is connected to the output voltage terminal. The second input terminal of the 21st NAND gate, the gate of the second NMOS switch, and the second input terminal of the 22nd NOR gate are respectively connected to the comparator offset voltage test mode selection unit circuit.

2. The comparator offset voltage testing circuit according to claim 1, characterized in that, The voltage source has a setpoint of 0V, and R is selected. f >>R i .

3. The comparator offset voltage testing circuit according to claim 1, characterized in that, The comparator offset voltage test mode selection unit circuit includes a latch. The first input terminal of the latch is a first node, the second input terminal is connected to the power-on reset terminal por, the output terminal of the latch is a second node, the second node is connected to the input terminal of a first inverter, the output terminal of the first inverter is a third node, and the first node is connected to the power supply voltage terminal V through a current source. cc The other path is connected to the drain of the NMOS power transistor, the gate of the NMOS power transistor is grounded, and the source of the NMOS power transistor is connected to an RC circuit.

4. The comparator offset voltage test circuit according to claim 3, characterized in that, The third node is connected to the second input terminal of the 21st NOR gate circuit and the gate of the first NMOS switch, respectively.

5. The comparator offset voltage test circuit according to claim 3, characterized in that, The second node is connected to the second input terminal of the 21st NAND gate circuit, and the third node is connected to the second input terminal of the 22nd NOR gate circuit and the gate of the second NMOS switch, respectively.

6. The comparator offset voltage test circuit according to claim 3, characterized in that, The latch includes a first NAND gate circuit and a second NAND gate circuit. The first input terminal of the first NAND gate circuit is connected to the first node, the second input terminal of the first NAND gate circuit is connected to the second node, the output terminal of the first NAND gate circuit is connected to the first input terminal of the second NAND gate circuit, the second input terminal of the second NAND gate circuit is connected to the power-on reset terminal por, and the output terminal of the second NAND gate circuit is connected to the second node.

7. The comparator offset voltage test circuit according to claim 3, characterized in that, The RC circuit includes a first resistor R1 and a first capacitor C1. One end of R1 and one end of C1 are interconnected and connected to the source of the NMOS power transistor. The other end of R1 is connected to the positive input terminal In+, and the other end of C1 is grounded.

8. The comparator offset voltage test circuit according to claim 3, characterized in that, The timing rise of the por is greater than that of the V. cc The timing is lagging behind.

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