A layout verification method of a standard cell library

Abstract

The application discloses a layout verification method of standard cell library, which repeatedly calls each standard cell in the standard cell library, formulates the arrangement rule of the standard cell, arranges the called standard cell according to the arrangement rule, and generates a top module containing all the adjacent modes between all the standard cells; through the verification of the top module, it is realized that whether all the standard cells in the standard cell library and all the adjacent modes therebetween are correct can be obtained only through one-time verification, thereby reducing the repeated standard cell physical verification operation. In addition, according to the physical properties of different standard cells in the standard cell library, a plurality of temporary combination splicing modes are formulated, the temporary combination contains all the random calling and splicing of the standard cells, has randomness and high coverage, thereby reducing the repeated verification of each standard cell in the integrated circuit formulation stage, shortening the layout verification period, and improving the verification efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit layout design technology, and more specifically, to a layout verification method for a standard cell library. Background Technology

[0002] Standard cell libraries are required for the development of digital back-end systems for integrated circuits. A standard cell library is a collective term for the cell symbol library, cell circuit structure library, layout library, circuit performance parameter library, functional description library, development rules, and device model parameter library needed for integrated circuit development. Using pre-defined library cells for automatic logic synthesis and layout / routing can greatly improve development efficiency and accelerate time-to-market.

[0003] Typically, each process manufacturer provides corresponding standard cells for each process. Before the standard cell library is submitted to users, it needs to be verified to ensure that the individual specifications of all library cells fully comply with the physical and electrical specifications, and to ensure that placing any number of the same or different standard cells in any location will not result in any errors that violate the specifications when forming the target circuit module.

[0004] Currently, there are two common methods for verifying the layout of standard cell libraries. The first method involves arranging the standard cells according to certain rules and then verifying the layout. The second method uses specific techniques to automatically place and route the standard cell library using Automatic Placement and Routing (APR), arranging the standard cell library as needed. The advantage of the first method is that it allows for real-time verification during the standard cell layout design phase; however, it requires verification for each individual standard cell, leading to a large amount of repetitive work. The advantage of the second method is that it simulates the actual environment in which the standard cells are used, meeting basic usage scenarios. However, it cannot perform real-time verification during the layout design phase and cannot fully cover all possible standard cell layouts.

[0005] In view of the above, this application is hereby submitted. Summary of the Invention

[0006] The technical problem this invention aims to solve is that existing layout verification methods cannot cover all standard cell arrangements and result in a large number of repetitive verification operations. The goal is to provide a layout verification method for a standard cell library that allows for the verification of the correctness of all standard cells and their adjacency arrangements in the library with a single verification, thereby reducing repetitive physical verification operations of the standard cells.

[0007] This invention is achieved through the following technical solution:

[0008] A layout verification method for a standard cell library includes the following steps:

[0009] Determine whether the heights of all standard cells in the standard cell library are consistent.

[0010] If the heights are consistent, execute A1; otherwise, execute B1.

[0011] A1: Determine the type of the standard unit; if it is a single-row standard unit, execute a11 and a12; if it is a double-row standard unit, execute a21 and a22.

[0012] a11: Establish a first temporary splicing model, which is used to combine all the single-unit adjacency methods of the single-row standard unit to form a temporary combination of single-row standard units;

[0013] a12: Based on the first temporary splicing model, obtain a temporary combination of each single-row standard unit;

[0014] a21: Establish a second temporary splicing model, which is used to combine all the single-unit adjacency methods of the double-row standard unit to form a temporary combination of double-row standard units;

[0015] a22: Based on the second temporary splicing model, obtain a temporary combination of each double-row standard unit;

[0016] B1: Obtain the corresponding temporary assembly for each standard unit according to A1, and adjust the height of all the obtained temporary assemblies to be consistent;

[0017] Randomly assemble all temporary composites into a top-level module;

[0018] The top-level module is subjected to layout verification to obtain the layout verification result.

[0019] Furthermore,

[0020] The establishment of the first temporary splicing model includes the following steps:

[0021] Nine temporary placement areas are set up, which are used to place any single row of standard units in the standard unit library.

[0022] The nine temporary placement areas are arranged into a nine-square grid, with adjacent temporary placement areas connected together.

[0023] The nine temporary placement areas are numbered 1-9 in order from left to right and from top to bottom;

[0024] The standard unit placement method for temporary placement areas 1, 2, and 7 is set as follows: rotate the forward-facing standard unit 180° counterclockwise before placing it.

[0025] The standard unit placement method for temporary placement areas No. 3, No. 8 and No. 9 is set as follows: rotate the forward standard unit 180° counterclockwise and rotate it 180° around its plane before placing it.

[0026] The standard unit placement method for temporary placement areas 4 and 6 is set as follows: the standard unit facing forward is rotated 180° around its plane before placement;

[0027] The standard unit placement method for temporary placement area No. 5 is set as follows: place them directly according to the orientation of the standard unit.

[0028] Furthermore,

[0029] The establishment of the second temporary splicing model includes the following steps:

[0030] Six temporary placement areas are set up, and the temporary placement areas are used to place any double-row standard unit in the standard unit library;

[0031] The six temporary placement areas are arranged into two rows, one above the other, with each row containing three temporary placement areas, and adjacent temporary placement areas are joined together.

[0032] The six temporary placement areas are numbered 1-6 in order from left to right.

[0033] The standard unit placement method for temporary placement areas 1, 4, and 6 is set as follows: place them directly according to the orientation of the standard unit.

[0034] The standard unit placement method for temporary placement area No. 2 is set as follows: the standard unit facing forward is rotated 180° around its plane before placement.

[0035] The standard unit placement method for temporary placement areas No. 3 and No. 5 is set as follows: rotate the forward-facing standard unit 180° counterclockwise before placing it.

[0036] Furthermore,

[0037] Before determining whether the heights of all standard cells in the standard cell library are consistent, the following steps are included: obtaining the physical attributes and GDS data of each standard cell in the standard cell library, wherein the physical attributes include: the name, width, and number of height rows of the standard cell.

[0038] Furthermore,

[0039] Adjusting the height of all acquired temporary composites to be consistent includes the following steps:

[0040] Based on the height of the standard cell, all the acquired temporary assemblies are divided into multiple classes, and all temporary assemblies in each class have the same height.

[0041] Get the height row count of the temporary composite of each class, resulting in multiple height row counts;

[0042] Find the least common multiple of the number of height rows;

[0043] Based on the least common multiple and power line connection rules, the number of height rows of all temporary assemblies in each class is adjusted to make the number of height rows of all temporary assemblies the same.

[0044] Furthermore,

[0045] Adjusting the height row count of all temporary composites for each class includes the following steps:

[0046] For temporary assemblies with a height row number less than the least common multiple, the temporary assemblies are copied according to the least common multiple and the height row number multiple to obtain the main body of the temporary assemblies and multiple copies; each copy is then spliced ​​on top of the main body according to the power line connection rules.

[0047] Temporary assemblies with a height row number equal to the least common multiple are not processed.

[0048] Furthermore,

[0049] The step of randomly assembling all temporary assemblies into a top-level module includes the following steps:

[0050] Initialize the layout module to be verified;

[0051] Based on the number of width and height rows of the standard cells and the total number of temporary assemblies, set the size of the layout module to be verified, the size including the total width and total height of the layout module to be verified;

[0052] From bottom to top, fill the pre-sized layout modules to be verified row by row until the total height of the temporary assembly is equal to the total height of the layout modules to be verified, thus obtaining the top-level module;

[0053] The line-by-line filling includes the following steps:

[0054] C1: For the current row, randomly select one temporary combination to be placed from all the obtained temporary combinations;

[0055] C2: Determine whether the temporary assembly to be placed is the first randomly selected temporary assembly; if so, place the temporary assembly to be placed at the leftmost end of the current row; otherwise, concatenate the temporary assembly to be placed with the previous temporary assembly placed in the current row to form a temporary assembly queue.

[0056] C3: Repeat C1 to C2 until the gap between the total width of the temporary assembly queue and the total width of the layout module to be verified is less than the width of any temporary assembly.

[0057] Furthermore,

[0058] Setting the size of the top-level module includes the following steps:

[0059] Based on the width of the standard unit, obtain the total width after splicing all temporary assemblies in one line;

[0060] The number of random draws for each temporary assembly is calculated based on the coverage requirement.

[0061] The total width of the top-level module is calculated based on the total width and the number of random samplings.

[0062] The total number of rows in the top-level module is preset, and the total height of the top-level module is calculated based on the total number of rows and the height of a single temporary assembly.

[0063] Adjust the total height to minimize the difference between the total height and the total width.

[0064] Furthermore,

[0065] The step of randomly assembling all temporary assemblies into a top-level module also includes the following steps: swapping the standard units of temporary assemblies located in the same row in the left and right directions.

[0066] Furthermore,

[0067] The C3 further includes the following steps: filling the gap between the temporary assembly queue and the layout module to be verified using Fill standard cells.

[0068] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0069] 1. The present invention provides a layout verification method for a standard cell library, which repeatedly calls each standard cell in the standard cell library and formulates the arrangement rules of the standard cells. The standard cells are arranged according to the arrangement rules to generate a top-level module containing all the adjacency methods between all standard cells. By verifying the top-level module, it is possible to obtain whether all standard cells in the standard cell library and all their adjacency methods are correct with only one verification, thereby reducing repeated physical verification operations of standard cells.

[0070] 2. The present invention provides a layout verification method for a standard cell library. Based on the physical properties of different standard cells in the standard cell library, a variety of temporary assembly splicing methods are formulated. Since the temporary assembly contains all the standard cells randomly selected and spliced, it has randomness and high coverage, thereby reducing the repeated verification of each standard cell in the integrated circuit development stage, shortening the layout verification cycle, and improving the verification efficiency. Attached Figure Description

[0071] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0072] Figure 1 A schematic flowchart of the layout verification method for the standard cell library provided in this embodiment of the invention;

[0073] Figure 2 A simplified diagram of a forward standard unit provided in an embodiment of the present invention;

[0074] Figure 3 A schematic diagram of a random arrangement of standard units with a single height provided in an embodiment of the present invention;

[0075] Figure 4 A schematic diagram of the random arrangement of standard units with a height of double height provided in an embodiment of the present invention;

[0076] Figure 5 This is a schematic diagram of the standard unit adjacency arrangement provided in an embodiment of the present invention;

[0077] Figure 6 A schematic diagram of the upper and lower power line adjacency method of a single-height standard unit provided in an embodiment of the present invention;

[0078] Figure 7A schematic diagram of the upper and lower power line adjacency method of a dual-height standard cell provided in an embodiment of the present invention;

[0079] Figure 8 This is a schematic diagram illustrating an operation method for unifying the height of all standard units through a flipping process, as provided in an embodiment of the present invention.

[0080] Figure 9 This is a schematic diagram of a random arrangement of temporary assemblies provided in an embodiment of the present invention;

[0081] Figure 10 This is a schematic diagram illustrating the left-right direction swapping method of a temporary assembly provided in an embodiment of the present invention;

[0082] Figure 11 This is a schematic diagram of the filling method for the notch in the verification module provided in an embodiment of the present invention. Detailed Implementation

[0083] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0084] Example

[0085] Currently, common layout verification methods require verification of each standard cell, resulting in a large number of repetitive verification operations and failing to fully cover all possible standard cell arrangements. To address the shortcomings of existing layout verification methods, this embodiment provides a layout verification method for a standard cell library. This method requires only one verification to confirm the correctness of all standard cells in the library and their adjacency arrangements, thereby reducing a significant amount of repetitive manual layout verification work.

[0086] The implementation process of the layout verification method for this standard cell library is as follows: Figure 1 As shown, it includes the following steps:

[0087] Step 1: Obtain the physical attributes and GDS data of each standard cell in the standard cell library. The physical attributes of the standard cell include: the cell's name, width, and number of height rows; the GDS data serves as the input data.

[0088] It should be noted that a standard cell typically has a height of one number of rows, referred to as a row construction. However, for some complex standard cells, a single height may correspond to three, five, or even more row constructions. Conversely, a standard cell with a height of two rows may correspond to two, four, or other row constructions.

[0089] Step 2: Determine whether the heights of all standard cells in the standard cell library are consistent.

[0090] Since a core step in the layout verification method provided in this embodiment is to obtain a temporary combined module containing all standard cell arrangements, and it is necessary to ensure that the height of all randomly spliced ​​standard cells is consistent during the formation of the temporary combined module, the height of the standard cells needs to be determined before splicing the standard cells in the standard cell library into a temporary combined module according to all possible splicing methods.

[0091] Step 3: If it is determined in Step 2 that all standard cells in the standard cell library have the same height, then it is necessary to further determine whether the standard cell type is a single-height standard cell or a double-height standard cell.

[0092] Step 4: If it was determined in Step 3 that all standard cells in the standard cell library have a single height, then a first temporary splicing model is established. This first temporary splicing model is used to combine all the adjacency methods of single-row standard cells to form a temporary assembly of single-row standard cells. Based on the first temporary splicing model, a temporary assembly of each single-row standard cell is obtained.

[0093] The establishment of the first temporary splicing model includes the following steps:

[0094] Step 4.11: Set up 9 temporary placement areas, which are used to place any single row of standard units in the standard unit library;

[0095] Step 4.12: Arrange the nine temporary placement areas into a nine-square grid, with adjacent temporary placement areas adjacent to each other;

[0096] Step 4.13: Number the nine temporary placement areas sequentially from left to right and from top to bottom using the numbers 1-9;

[0097] Step 4.14: Set the standard unit placement method for temporary placement areas 1, 2, and 7 as follows: rotate the forward-facing standard unit 180° counterclockwise before placing it.

[0098] Step 4.15: Set the standard unit placement method for temporary placement areas 3, 8, and 9 as follows: rotate the forward standard unit 180° counterclockwise and rotate it 180° around its plane before placing it.

[0099] Step 4.16: Set the standard unit placement method for temporary placement areas 4 and 6 as follows: rotate the standard unit 180° around its plane before placing it.

[0100] Step 4.17: Set the standard unit placement method of temporary placement area No. 5 to: place directly according to the orientation of the standard unit.

[0101] Specifically, Figure 2 This is a simplified diagram of the forward standard cell. Figure 2 In the diagram, t, b, l, and r represent the top, bottom, left, and right sides of a standard cell, respectively, and "F" is a direction marker for a positive standard cell. The random arrangement of standard cells with a single height is as follows: Figure 3 As shown. According to Figure 3 In the random arrangement of standard units with a single height, there are nine temporary placement areas in a 3x3 grid shape for placing the standard units. To clearly illustrate the placement of standard units in each temporary placement area, this embodiment numbers the nine temporary placement areas 1-9 in order from left to right and from top to bottom. Based on the "F" direction markings of the standard units in each placement area, it can be seen that the standard units in temporary placement areas 1, 2, and 7 are obtained by rotating the positive standard units 180° counterclockwise; the standard units in temporary placement areas 3, 8, and 9 are obtained by rotating the positive standard units 180° counterclockwise and then rotating them 180° around their respective planes; the standard units in temporary placement areas 4 and 6 are obtained by rotating the positive standard units 180° around their respective planes; and the standard unit in temporary placement area 5 is simply a positive standard unit without any transformation.

[0102] Step 5: If it was determined in Step 3 that all standard cells in the standard cell library have a height of double height, then a second temporary splicing model is established. This second temporary splicing model is used to combine all the individual adjacency methods of double-row standard cells to form a temporary assembly of double-row standard cells. Based on the second temporary splicing model, a temporary assembly of each double-row standard cell is obtained.

[0103] in,

[0104] Establishing the second temporary splicing model includes the following steps:

[0105] Step 4.21: Set up 6 temporary placement areas, which are used to place any double-row standard unit from the standard unit library;

[0106] Step 4.22: Arrange the 6 temporary placement areas into two rows, each row containing 3 temporary placement areas, with adjacent temporary placement areas being adjacent to each other;

[0107] Step 4.23: Number the six temporary placement areas sequentially from left to right using the numbers 1-6;

[0108] Step 4.24: Set the standard unit placement method of temporary placement areas 1, 4 and 6 to: place them directly according to the orientation of the standard unit.

[0109] Step 4.25: Set the standard unit placement method of temporary placement area No. 2 as follows: rotate the forward standard unit 180° around its plane before placing it;

[0110] Step 4.26: Set the standard unit placement method for temporary placement areas 3 and 5 as follows: rotate the forward-facing standard unit 180° counterclockwise before placing it.

[0111] For details, please refer to Figure 2 and Figure 4 In the random arrangement of standard cells with a height of double height, there are six temporary placement areas for placing the standard cells. Similarly, to clearly illustrate the placement of standard cells in each temporary placement area, this embodiment numbers the six temporary placement areas 1-6 in order from left to right and from top to bottom. Similarly, according to the "F" direction marking of the standard cells in each placement area, it can be seen that the standard cells in temporary placement areas 1, 4, and 6 are directly positive standard cells without any transformation; the standard cells in temporary placement area 2 are obtained by rotating the positive standard cells 180° around their respective plane; the standard cells in temporary placement areas 3 and 5 are obtained by rotating the positive standard cells 180° counterclockwise.

[0112] It should be noted that,

[0113] (1) Figure 3 and Figure 4 In the diagram, the meanings of ①-⑥ marked on the adjacent edges of two adjacent standard units are as follows: Figure 5 As shown: ① represents the top edges of two standard units joined together; ② represents the top and bottom edges of two standard units joined together; ③ represents the bottom edges of two standard units joined together; ④ represents the left edges of two standard units joined together; ⑤ represents the left and right edges of two standard units joined together; ⑥ represents the right edges of two standard units joined together.

[0114] (2) Figure 6 As shown, the upper and lower power lines of a single-height standard cell are VDD and VSS, respectively. The standard cell is connected as follows... Figure 3 After being arranged as shown, this module already contains the following: Figure 5 The adjacent arrangement combinations shown are ①③④⑤⑥. However, for adjacent arrangement ②, due to the limitations of the power line connection rules, Figure 6 The single-height standard cell adjacency method shown will short-circuit the VSS / VDD lines and thus be disabled. Therefore, it can be concluded that... Figure 3 This already includes all possible combinations of adjacent arrangements of single-height standard units. Similarly, as... Figure 7 As shown, in the adjacency method of dual-height standard cells, there is no short circuit on the VSS / VDD lines. Therefore, Figure 4 It already includes all possible combinations of adjacent arrangements of single units in the double-height standard unit.

[0115] Step 6: If it is determined in step 2 that the heights of all standard cells in the standard cell library are inconsistent, then obtain the corresponding temporary assembly for each standard cell according to steps 3 and 4.

[0116] Step 7: Adjust the height of all temporary composite objects obtained in Step 6 to be the same. The specific implementation steps are as follows:

[0117] Step 7.1: Based on the height row number of the standard cell, divide all the obtained temporary assemblies into multiple classes, and all temporary assemblies in each class have the same height;

[0118] Step 7.2: Obtain the height row count of the temporary composite for each class, resulting in multiple height row counts;

[0119] Step 7.3: Obtain the least common multiple of the multiple height rows;

[0120] Step 7.4: Based on the least common multiple and power line connection rules, adjust the number of height rows of all temporary assemblies in each class so that the number of height rows of all temporary assemblies is the same.

[0121] in,

[0122] Step 7.4, which involves adjusting the height of all temporary composites for each class, includes the following steps:

[0123] Step 7.41: For temporary assemblies with a height row number less than the least common multiple, copy the temporary assemblies according to the least common multiple and the multiple of the height row number to obtain the main body of the temporary assemblies and multiple copies; sequentially splice each copy on top of the main body according to the power line connection rules.

[0124] Step 7.42: Temporary assemblies with a height row number equal to the least common multiple are not processed.

[0125] Regarding step 7, this embodiment uses... Figure 8Taking a standard cell library with various height values ​​as an example, after arranging the temporary assemblies using steps 3 and 4 above, since the heights of the various temporary assemblies are different, they should be flipped and copied to form temporary assemblies with uniform heights. For example, if a standard cell library has standard cells with two height values, 1 height and 3 height, arranging them using step 3 will result in temporary assemblies with heights of 3 and 9. Then, taking the least common multiple of 3 and 9 (9), all temporary assemblies are flipped to the least common multiple of 9 height. Therefore, a temporary assembly with a height of 3 height is flipped 3 times to achieve a height of 9 height. Since the temporary assembly with a height of 9 height already meets the least common multiple of 9 height, no additional flipping is required.

[0126] Step 8: Randomly assemble all temporary assemblies into a top-level module. The specific implementation steps are as follows:

[0127] Step 8.1: Initialize the layout module to be verified;

[0128] Step 8.2: Based on the width and height of the standard cells and the total number of temporary assemblies, set the size of the layout module to be verified, whereby the size includes the total width and total height of the layout module to be verified;

[0129] Step 8.3: From bottom to top, fill the pre-sized layout modules to be verified line by line until the total height of the temporary assembly is equal to the total height of the layout modules to be verified, thus obtaining the top-level module;

[0130] The line-by-line filling includes the following steps:

[0131] C1: For the current row, randomly select one temporary combination to be placed from all the obtained temporary combinations;

[0132] C2: Determine whether the temporary assembly to be placed is the first randomly selected temporary assembly; if so, place the temporary assembly to be placed at the leftmost end of the current row; otherwise, concatenate the temporary assembly to be placed with the previous temporary assembly placed in the current row to form a temporary assembly queue.

[0133] C3: Repeat C1 to C2 until the gap between the total width of the temporary assembly queue and the total width of the layout module to be verified is less than the width of any temporary assembly.

[0134] Setting the size of the top-level module includes the following steps:

[0135] Based on the width of the standard unit, obtain the total width after splicing all temporary assemblies in one line;

[0136] The number of random draws for each temporary assembly is calculated based on the coverage requirement.

[0137] The total width of the top-level module is calculated based on the total width and the number of random samplings.

[0138] The total number of rows in the top-level module is preset, and the total height of the top-level module is calculated based on the total number of rows and the height of a single temporary assembly.

[0139] Adjust the total height to minimize the difference between the total height and the total width.

[0140] Regarding step 8, this embodiment uses... Figure 9 Taking the random arrangement of the temporary composite as an example, first, randomly select as shown... Figure 8 The temporary assemblies with uniform heights, as shown, are sequentially placed into the final verification layout module of a pre-defined size. Once the preset width is met, they move to the previous row and are randomly called again, until the preset maximum height is met. It is important to note that the final verification layout module should have a sufficiently large preset size to meet the full coverage requirement.

[0141] It should be noted that when arranging temporary assemblies randomly, the appropriate X-axis width of the verification module needs to be calculated based on the size and number of standard units. The X-dimensional sum of all the arranged temporary assemblies obtained in step 7 yields the preset total width of the verification module, K. Therefore, the total X-axis width of the verification module required for all temporary assemblies to be arranged at least once is K. Each additional random selection of a temporary assembly increases the coverage. Since the temporary assemblies obtained in step 7 already satisfy all single-unit adjacent arrangement methods, only the adjacent arrangement between different temporary assemblies needs to be considered. Then, based on the coverage requirement, the number of times each temporary assembly needs to be randomly selected, C, is calculated. The total width of the verification module required for all temporary assemblies to be selected C times is C×K. Considering the actual DRC verification effect, the temporary assemblies will not be set to just one row; setting them to a more square rectangle can have a better verification effect. The preset total arrangement is N rows, each row with a height of Y. The total height of the verification module is N×Y. Therefore, the total height N×Y of the verification module should be as close as possible to the total width C×K, making the verification module a more standard rectangle.

[0142] Step 9: When randomly selecting a temporary assembly disk and placing it into the verification module for assembly, the standard units of the temporary assemblies located in the same row can also be swapped left and right.

[0143] Specifically,

[0144] When randomly selecting the temporary assembly obtained in step 7, the left and right directions of the temporary assembly can be interchanged to satisfy the permutation and combination methods among all different temporary assemblies. For example... Figure 10 The left-left, right-right, and left-right arrangements between different temporary assemblies can all be included, thus encompassing all types of adjacency methods between different temporary assemblies. However, due to the limitations of power line connection rules, the up-down orientation of the temporary assemblies obtained in step 7 cannot be arbitrarily interchanged. According to Figure 10 As shown, as long as the temporary assembly obtained in step 7 is called twice (left and right), it can satisfy the left-left, right-right, and left-right adjacency arrangement with other temporary assemblies. Therefore, this real-time example requires a minimum of calls to a standard cell of height 1. Figure 2 The positive standard unit shown is retrieved 9 times. Figure 10 The standard cell module shown is called once on each side. Each standard cell needs to be called at least 18 times to meet the most basic coverage requirements. Through actual testing, calling the standard cell module on each side 4 to 6 times in step 7 can basically guarantee the verification requirements of the standard cell library. Increasing the number of calls will have less and less impact on coverage, but will increase the verification time.

[0145] Step 10: After obtaining the initial verification module, it is also necessary to use Fill standard cells to fill the gap between the temporary assembly queue and the layout module to be verified.

[0146] Specifically, the verification modules initially obtained by randomly arranging them in step 8 will have a large portion of their right-hand layout that cannot accommodate standard unit modules due to insufficient width, failing to reach the preset width C×K per row. This will result in... Figure 11 The layout shown has a gap on the right side due to inconsistent widths. This gap will cause a lot of layout DRC errors, such as DRC errors caused by inconsistent widths at the NW and VTH levels. Determining these errors will take a lot of effort. To avoid unnecessary errors, we need to fill the gap on the right side caused by inconsistent widths. Here we need to insert a Fill standard cell to fill it. The reason for choosing the Fill cell is that the Fill cell is commonly used for layout filling, and the Fill cell has various widths to choose from, so there will be no situation where it cannot be filled due to the width being too small.

[0147] In summary, the layout verification method for a standard cell library provided in this embodiment repeatedly calls each standard cell in the standard cell library and formulates arrangement rules for the standard cells. The called standard cells are then arranged according to these rules to generate a top-level module containing all adjacency patterns between all standard cells. By verifying the top-level module, the correctness of all standard cells and their adjacency patterns in the standard cell library can be obtained with only one verification, thereby reducing repetitive physical verification operations. Furthermore, based on the physical properties of different standard cells in the standard cell library, various splicing methods for temporary assemblies are formulated. Since these temporary assemblies contain all randomly called and spliced ​​standard cells, they possess randomness and high coverage, thereby reducing repeated verification of each standard cell during the integrated circuit development stage, shortening the layout verification cycle, and improving verification efficiency.

[0148] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A layout verification method for a standard cell library, characterized in that, Includes the following steps: Determine whether the heights of all standard cells in the standard cell library are consistent. If the heights are consistent, execute A1; otherwise, execute B1. A1: Determine the type of the standard unit; if it is a single-row standard unit, execute a11 and a12; if it is a double-row standard unit, execute a21 and a22. a11: Establish a first temporary splicing model, which is used to combine all the single-unit adjacency methods of the single-row standard unit to form a temporary combination of single-row standard units; a12: Based on the first temporary splicing model, obtain a temporary combination of each single-row standard unit; a21: Establish a second temporary splicing model, which is used to combine all the single-unit adjacency methods of the double-row standard unit to form a temporary combination of double-row standard units; a22: Based on the second temporary splicing model, obtain a temporary combination of each double-row standard unit; B1: Obtain the corresponding temporary assembly for each standard unit according to A1, and adjust the height of all the obtained temporary assemblies to be consistent; Randomly assemble all temporary composites into a top-level module; The top-level module is subjected to layout verification to obtain the layout verification result; Adjusting the height of all temporary assemblies to be consistent includes the following steps: Based on the height row count of the standard unit, all acquired temporary assemblies are divided into multiple categories, with all temporary assemblies in each category having the same height. The height row count of the temporary assemblies in each category is obtained, resulting in multiple height row counts. The least common multiple of the multiple height row counts is obtained. Based on the least common multiple and the power line connection rules, the height row count of all temporary assemblies in each category is adjusted to make the height row count of all temporary assemblies the same. Adjusting the height row count of all temporary composites for each class includes the following steps: For temporary assemblies with a height row count less than the least common multiple, the temporary assemblies are copied according to the multiple of the least common multiple and the height row count to obtain the main body of the temporary assemblies and multiple copies; each copy is then sequentially spliced ​​on top of the main body according to the power line connection rules; temporary assemblies with a height row count equal to the least common multiple are not processed.

2. The layout verification method for a standard cell library according to claim 1, characterized in that, The establishment of the first temporary splicing model includes the following steps: Nine temporary placement areas are set up, which are used to place any single row of standard units in the standard unit library. The nine temporary placement areas are arranged into a nine-square grid, with adjacent temporary placement areas connected together. The nine temporary placement areas are numbered 1-9 in order from left to right and from top to bottom; The standard unit placement method for temporary placement areas 1, 2, and 7 is set as follows: rotate the forward-facing standard unit 180° counterclockwise before placing it. The standard unit placement method for temporary placement areas No. 3, No. 8 and No. 9 is set as follows: rotate the forward standard unit 180° counterclockwise and rotate it 180° around its plane before placing it. The standard unit placement method for temporary placement areas 4 and 6 is set as follows: the standard unit facing forward is rotated 180° around its plane before placement; The standard unit placement method for temporary placement area No. 5 is set as follows: place them directly according to the orientation of the standard unit.

3. The layout verification method for a standard cell library according to claim 1, characterized in that, The establishment of the second temporary splicing model includes the following steps: Six temporary placement areas are set up, and the temporary placement areas are used to place any double-row standard unit in the standard unit library; The six temporary placement areas are arranged into two rows, one above the other, with each row containing three temporary placement areas, and adjacent temporary placement areas are joined together. The six temporary placement areas are numbered 1-6 in order from left to right. The standard unit placement method for temporary placement areas 1, 4, and 6 is set as follows: place them directly according to the orientation of the standard unit. The standard unit placement method for temporary placement area No. 2 is set as follows: the standard unit facing forward is rotated 180° around its plane before placement. The standard unit placement method for temporary placement areas No. 3 and No. 5 is set as follows: rotate the forward-facing standard unit 180° counterclockwise before placing it.

4. The layout verification method for a standard cell library according to claim 1, characterized in that, Before determining whether the heights of all standard cells in the standard cell library are consistent, the following steps are included: obtaining the physical attributes and GDS data of each standard cell in the standard cell library, wherein the physical attributes include: the name, width, and number of height rows of the standard cell.

5. The layout verification method for a standard cell library according to claim 4, characterized in that, The step of randomly assembling all temporary assemblies into a top-level module includes the following steps: Initialize the layout module to be verified; Based on the number of width and height rows of the standard cells and the total number of temporary assemblies, set the size of the layout module to be verified, the size including the total width and total height of the layout module to be verified; From bottom to top, fill the pre-sized layout modules to be verified row by row until the total height of the temporary assembly is equal to the total height of the layout modules to be verified, thus obtaining the top-level module; The line-by-line filling includes the following steps: C1: For the current row, randomly select one temporary combination to be placed from all the obtained temporary combinations; C2: Determine whether the temporary assembly to be placed is the first randomly selected temporary assembly; if so, place the temporary assembly to be placed at the leftmost end of the current row; otherwise, concatenate the temporary assembly to be placed with the previous temporary assembly placed in the current row to form a temporary assembly queue. C3: Repeat C1 to C2 until the gap between the total width of the temporary assembly queue and the total width of the layout module to be verified is less than the width of any temporary assembly.

6. The layout verification method for a standard cell library according to claim 5, characterized in that, Setting the size of the layout module to be verified includes the following steps: Based on the width of the standard unit, obtain the total width after splicing all temporary assemblies in one line; The number of random draws for each temporary assembly is calculated based on the coverage requirement. The total width of the layout module to be verified is calculated based on the total width and the number of random samplings. The total number of rows of the layout module to be verified is preset, and the total height of the layout module to be verified is calculated based on the total number of rows and the height of a single temporary assembly. Adjust the total height to minimize the difference between the total height and the total width.

7. The layout verification method for a standard cell library according to claim 5, characterized in that, The step of randomly assembling all temporary assemblies into a top-level module also includes the following steps: swapping the standard units of temporary assemblies located in the same row in the left and right directions.

8. The layout verification method for a standard cell library according to claim 5, characterized in that, The C3 further includes the following steps: filling the gap between the temporary assembly queue and the layout module to be verified using Fill standard cells.

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