Time tracking circuit for FRAM

Abstract

This application discloses a time tracking circuit for FRAM. Methods and apparatus for reading and / or writing to FRAM memory are also disclosed. An example memory circuit (100) includes: a controller (102) that outputs a signal to an input of a driver (106, 108); transistors (107, 109) coupled to the output of the driver (106, 108); a driver (106, 108) that outputs a first voltage to the transistor (107, 109) in response to receiving a signal; and transistors (107, 109) that, in response to receiving the first voltage, output a second voltage to a bit cell (120) after a transistor delay, wherein the transistors (107, 109) are selected based on the size of the memory circuit (100).

Description

[0001] This application is a divisional application of Chinese patent application 201710101207.1 entitled "Time Tracking Circuit for FRAM", filed on February 24, 2017. Technical Field

[0002] This disclosure generally relates to ferroelectric random access memory (FRAM), and more specifically to methods and apparatus for providing time tracking circuitry for FRAM. Background Technology

[0003] Ferroelectric random access memory (FRAM) is a non-volatile memory device comprising an array of bit cells. Each FRAM bit cell includes a ferroelectric capacitor that stores electrical charge. The charge corresponds to a logic value. The charge can be changed (e.g., written to) and / or read from the memory controller. Conventional FRAM circuits contain a certain number of rows and columns of bit cells (e.g., 512 rows and 72 columns). However, advances in FRAM technology have led to FRAM circuits with varying numbers of rows and columns. For example, FRAMs can include 32-512 rows and 8-144 columns, allowing up to 72,000 bits of non-volatile memory. Summary of the Invention

[0004] The examples disclosed herein provide time tracking circuitry in a memory array. The example devices disclosed herein include a controller for outputting a first signal and a second signal. Such examples include: a first driver that outputs a first voltage to a first transistor after a first delay corresponding to the size of a first transistor in response to receiving the first signal; and a first transistor that outputs a second voltage to a plate line of a bit cell. Such examples include: a second driver that outputs a third voltage to a second transistor after a second delay corresponding to the size of a second transistor in response to receiving the second signal; and a second transistor that outputs a fourth voltage to a bit line of a bit cell, wherein at least one of the first or second transistors is selected based on the memory size. Attached Figure Description

[0005] Figure 1 This is an example ferroelectric random access memory circuit that reads / writes to example bit cells.

[0006] Figure 2 yes Figure 1 Example bit cell.

[0007] Figure 3 This is a flowchart representation of example machine-readable instructions that can be executed to achieve... Figure 1 Example of ferroelectric random access memory circuit read and write Figure 1 Example bit cell.

[0008] Figure 4 Example used by Figure 1 Two example timing diagrams for example driver pulses output by the example plate driver.

[0009] Figure 5 Example used by Figure 1 Two example timing diagrams of example driver pulses for example write-back driver output.

[0010] Figure 6 This is a block diagram of an example processor platform that can be used to execute... Figure 3 Example instructions to implement Figure 1 Example ferroelectric random access memory circuit.

[0011] The accompanying drawings are not to scale. Wherever possible, the same reference numerals will be used throughout one or more drawings and accompanying written descriptions to refer to the same or similar parts. Detailed Implementation

[0012] Ferroelectric random access memory (FRAM) is a non-volatile memory circuit comprising an array of bit cells. An FRAM bit cell includes a ferroelectric capacitor to store charge. The stored charge associated with the ferroelectric capacitor represents a binary value (e.g., "1" or "0") that can be read. Reading a value from an FRAM array is a destructive process (e.g., once read, the stored value is lost). Therefore, once a value is read from a bit cell in the FRAM, that read value needs to be written back (e.g., flushed) to the bit cell. To read and / or write to bit cells in the FRAM, a delayed voltage pulse of a specific width is output through the FRAM driver (e.g., row driver, board driver, and / or bit line driver). Timing circuitry can be used to create this delay. The length of the delay is related to the minimum amount of time required for charge to flow through the transistor of the bit cell. As the size of the FRAM array (e.g., the number of rows and columns) increases, the load and capacitance associated with the FRAM array also increase. Therefore, voltage pulses required to program larger FRAM arrays need to be wider than those required to program smaller FRAM arrays. The optimal pulse width is related to the minimum amount of time required to store sufficient charge in the ferroelectric capacitors of the bit cells of the FRAM array.

[0013] Conventional FRAM arrays are designed to include a predetermined number of rows (e.g., 512 rows) and columns (e.g., 72 columns). Advances in FRAM technology have eliminated the need for a predetermined number of rows and / or columns for FRAM arrays. For example, zero-point cancellation (e.g., using capacitors to pull charge away from floating bit lines of the FRAM array) eliminates the required bit line / bit cell ratio, allowing a variable number of rows to be used in the FRAM array. Furthermore, smaller FRAM arrays do not require error correction codes associated with a large number of columns, allowing a variable number of columns to be used in smaller FRAM arrays. Conventional FRAM circuits utilize voltage pulses output by the drivers of the FRAM circuitry. These voltage pulses correspond to a predetermined width with a predetermined delay, used for reading and / or writing bit cells of the FRAM array, regardless of the size of the FRAM array (e.g., the number of rows and columns). However, FRAM arrays with smaller dimensions (e.g., a smaller number of rows and / or a smaller number of columns) can operate with voltage pulses of smaller delay and smaller width to optimize power consumption and speed. Adjusting the delay and pulse width can include timing circuitry for adjusting the FRAM array. However, sequential circuitry in custom FRAM designs can be complex and expensive. The examples disclosed in this article reduce the complexity and cost of designing various sequential circuits.

[0014] The examples disclosed herein utilize transistors of different sizes coupled to FRAM drivers of FRAM arrays of different sizes. Different sized transistors correspond to different delays and different pulse widths. Therefore, a fixed-timing circuit with the lowest possible delay can be used with transistors of different sizes to add additional delay. The different sized transistors affect the load on the FRAM driver, which in turn affects the delay and width of the driver's voltage pulses. The delay from the fixed-timing circuit is added to the delay associated with the transistors to output a pulse with a desired (e.g., optimal) delay. For example, the minimum required delay (e.g., optimal delay) for a plate pulse to read a bit cell from a small FRAM array could be 101 nanoseconds (ns), for a plate pulse to read a bit cell from a medium-sized FRAM array could be 103 ns, and for a plate pulse to read a bit cell from a large FRAM array could be 105 ns. In this example, a timing circuit creating a 100 ns delay can be used for small, medium, and large FRAM arrays. Small transistors with a 1ns delay can be used in small FRAM arrays (e.g., 100ns + 1ns = 101ns, the minimum required delay for small FRAM), medium transistors with a 3ns delay can be used in medium FRAM arrays (e.g., 100ns + 3ns = 103ns, the minimum required delay for medium FRAM), and large transistors with a 5ns delay can be used in large FRAM arrays (e.g., 100ns + 5ns = 105ns, the minimum required delay for large FRAM).

[0015] Different transistor sizes further correspond to different pulse widths. For example, a pulse from a driver coupled to a small transistor might correspond to an applied high voltage (e.g., 2V) of 14 ns, while a pulse from a driver coupled to a large transistor might correspond to an applied high voltage of 16 ns. As described above, smaller FRAM circuitry requires pulse widths smaller than those required for reading and / or writing bit cells in a larger FRAM array. Therefore, utilizing smaller transistors to meet the minimum required pulse delay of the FRAM array does not affect the ability to read and / or write FRAM bit cells. Using the examples disclosed herein, by adjusting the pulse delay and pulse width using transistors of different sizes coupled to the FRAM driver, it is possible to compile FRAM designs to optimize power, speed, and timing tolerances while minimizing cost.

[0016] Figure 1This is an example FRAM circuit 100 structured for storing data. The example FRAM circuit 100 includes an example FRAM controller 102, an example row driver 104, an example bit line driver 106, an example bit line transistor 107, an example board driver 108, an example board transistor 109, and an example FRAM array 110. The example row driver 104 outputs a voltage to the example FRAM array 100 via an example word line 112, the example bit line driver 106 controls the example bit line transistor 107 to output a voltage (e.g., Vdd) to the example FRAM array 100 via example bit line 114 and example complementary bit line 116, and the example board driver 108 controls the example board transistor 109 to output a voltage (e.g., Vdd) to the example FRAM array 100 via example board line 118. The example FRAM array 110 includes an example bit cell 120 and an example sense amplifier 122. The example FRAM circuit 100 is described in conjunction with a bit cell containing two transistors and two capacitors (2T-2C). Alternatively, the example FRAM circuit 100 may include bit cells having any number of transistors and / or capacitors (e.g., 1T-1C, 6T-2C, etc.). However, such FRAM circuit 100 may be arranged (e.g., connected) in slightly different ways to accommodate this bit cell configuration.

[0017] Example FRAM controller 102 controls the reading and / or writing of example bit cells (including example bit cell 120) in example FRAM array 110. Example FRAM controller 102 may be included in and / or coupled to an additional processor and / or computer system. Example FRAM controller 102 sends read instructions (e.g., read signals) and / or write instructions (e.g., write signals) to example drivers 104, 106, 108 to read and / or write example bit cells in example FRAM array 110. In some examples, FRAM controller 102 includes fixed-timing circuitry to output read signals and / or write signals after a predetermined delay. Example FRAM controller 102 also receives signals from example sense amplifiers (e.g., including example sense amplifier 122), which identify logic values ​​associated with charges stored in the bit cells in example FRAM array 110.

[0018] In response to receiving read and / or write signals from example FRAM controller 102, example drivers (e.g., example row driver 104, example bit line driver 106, and example board driver 108) output voltages to example FRAM array 110. Example drivers 104, 106, and 108 may include complementary metal-oxide-semiconductor (CMOS) circuitry. Example bit line driver 106 outputs control signals to one or more example bit line transistors 107 to output voltages to example bit lines 114 and example complementary bit lines 116 of example FRAM array 110. Example board driver 108 outputs control signals to one or more example board transistors to output voltages to example board lines 118 of example FRAM array 110. Example bit line transistors 107 and board transistors 109 are metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, example bit line transistors 107 and / or example board transistors 109 may be any type of transistor. Example bit-line transistor 107 and / or example board transistor 109 can be of various dimensions based on the resistance, capacitance, and / or transconductance of example transistors 107, 109. The dimensions of example transistors 107, 109 correspond to a specific delay. A specific delay is the amount of time (e.g., response time) taken for a driver of a specific size to output a voltage pulse in response to receiving a read / write signal. Additionally, the dimensions of example transistors 107, 109 correspond to a specific pulse width. As previously described, example row driver 104 outputs voltage on word lines (e.g., example word line voltage 112), example bit-line driver 106 outputs voltage on bit lines and complementary bit lines via example bit-line transistor 107 (e.g., example bit line voltage 114 and example complementary bit line voltage 116), and example board driver 108 outputs voltage on board lines via example board transistor 109 (e.g., example board line voltage 118).

[0019] Example FRAM array 110 is a memory array comprising any number of rows and / or columns of ferroelectric cells. As described above, as the number of rows and / or columns decreases, the load and capacitance associated with FRAM array 110 decrease. With both load and capacitance decreasing, the voltage pulses output by example drivers 104, 106, 108 can be optimized by reducing pulse width and delaying pulse width (e.g., optimizing power, speed, and timing tolerances). For example, in cases with lower power consumption and faster read / write cycles, shorter voltage pulses require less time to output high voltage. Example FRAM array 110 includes example bit cell 120 and example sense amplifier 122. Example bit cell 120 stores binary (e.g., logic) values ​​based on voltages applied to example bit cell 120 (e.g., word line voltage, bit line voltage, and board line voltage). Figure 2Further described, example bit cell 120 may include MOSFETs, each coupled to a separate ferroelectric capacitor. Alternatively, example bit cell 120 may include any number of MOSFETs and / or ferroelectric capacitors to store binary logic values. Example sense amplifier 122 is used to read the logic value stored in example bit cell 120. Example sense amplifier 122 may include a series of transistors configured to amplify the voltage differential between example bit line 114 and example complementary bit line 116 to a standard logic level. Sense amplifier 122 outputs the stored logic value of example bit cell 120 to example FRAM controller 102 based on the voltage differential. For example, sense amplifier 122 may output the logic value "1" when the voltage on example bit line 114 is higher than the voltage on example complementary bit line 116.

[0020] In operation, when the example FRAM controller 102 executes an instruction to read a logic value stored in example bit cell 120 of example FRAM 110, the example FRAM controller 120 sends an output (e.g., transmit) read signal to example drivers 104, 106, 108. The read signal indicates which bit cell the example drivers 104, 106, 108 should read. The example FRAM controller 102 may delay some of the read signal (e.g., the read signal for example bit line driver 106 and / or example board driver 108) while the voltage on example word line 112 reaches example bit cell 120. Once example board driver 108 receives the delayed read signal, board driver 108 outputs a voltage pulse of a specific width. Example board transistor 109 receives the voltage pulse and further widens the pulse due to the size of example board transistor 109. Additionally, each board transistor 109 includes a specific delay associated with the amount of time necessary to output the pulse after receiving the read signal. For example, a small example board transistor 109 can output a 10ns wide pulse with a 1ns delay in response to a received read signal. However, a large example board transistor 109 can output a 16ns wide pulse with a 5ns delay in response to a received read signal. The minimum amount of delay and / or pulse width is determined based on the number of columns in the example FRAM array 110. Therefore, the size of the example board transistor 109 is selected based on the column size of the example FRAM array 100.

[0021] When the example board driver 108 outputs a board pulse to the example board pulse line 118 via the example board transistor 109, the example bit line driver 106 floats both the example bit line 114 and the complementary bit line 116 (e.g., no output voltage is output on either example bit line 114 or complementary bit line 116), which allows the charge associated with the dipole orientation of the example bit cell 120 to discharge on either bit line 114 or complementary bit line 116. The example sense amplifier measures the voltage difference between bit line 114 and complementary bit line 116 to determine the logic value associated with bit cell 120 based on the voltage difference and sends the logic value to the example FRAM controller 102.

[0022] As described above, a read operation on example FRAM bit cell 120 is destructive. Therefore, once read, the logic stored in example bit cell 120 is lost. Therefore, example FRAM controller 102 writes back (e.g., refreshes) the stored logic to example bit cell 120. To write back the stored logic, example FRAM controller 102 sends write signals to example drivers 104, 106, and 108. The write signals instruct example drivers 104, 106, and 108 to write the previously stored value into example bit cell 120. In some examples, FRAM controller 102 initializes all bit cells of FRAM array 110 to a logic value (e.g., either "1" or "0") before restoring example bit cell 120. In this example, drivers 106, 109, and 104 can write the stored logic if it differs from the initialized logic value.

[0023] Example FRAM controller 102 can delay the write signal (e.g., the write signal for example bit line driver 106 and / or example board driver 108) while the voltage on example word line 112 reaches example bit cell 120. In some examples, the word line voltage can be maintained high for read operations. Once example bit line driver 108 receives the delayed write signal, bit line driver 106 outputs a voltage pulse of a specific width (e.g., either high voltage or ground) via the first example bit line transistor 107 after a specific delay on example bit line 114. Furthermore, the voltage pulse is supplemented (e.g., from high voltage to ground, or from ground to high voltage) and output to example complementary bit line 116 via the second example bit line transistor 107. The specific width and specific delay correspond to the size of example bit line transistor 107. For example, a small example bit line transistor 107 can output a 10ns wide pulse with a 1ns delay in response to receiving a write signal. However, a large example bit line transistor 107 can output a 16ns wide pulse with a 5ns delay in response to receiving a write signal. The minimum amount of delay and / or pulse width is determined based on the number or rows of the example FRAM array 110. Therefore, the size of the example bit line transistor 107 is selected based on the row size of the example FRAM array 100.

[0024] When bitline driver 106 outputs bitline pulses and complementary bitline pulses to example bitline pulse line 114 and example complementary bitline pulse line 116 via example bitline transistor 107, board driver 108 outputs a voltage (e.g., ground corresponds to writing "1" or 2V corresponds to writing "0") to example board line 118 via one of example board transistors 109, which allows one of the two ferroelectric capacitors associated with example bit cell 120 to change its dipole orientation (e.g., charge). Figure 2 Further description in the text states that the dipole orientation of a ferroelectric capacitor corresponds to a logic value.

[0025] Figure 2 This is an example of a sample bit cell 120 for storing logic values. Sample bit cell 120 is a 2T-2C bit cell; however, any number of transistors and / or capacitors can be used to store logic values. Sample bit cell 120 includes... Figure 1 Example word line 112, example bit line 114, example complementary bit line 116, and example board line 118. Example bit cell 120 further includes example MOSFETs 200, 204 and example ferroelectric capacitors 202, 206. In some examples, ferroelectric capacitors 202, 206 are initialized to a first (e.g., negative) dipole orientation.

[0026] During the write operation, example line drive 104 ( Figure 1A high voltage (e.g., 2V) is output on example word line 112, which is coupled to the gate of example MOSFET Q1 200. When the high voltage is output on example word line 112, example MOSFETs 200, 204 act like closed switches, causing a first ferroelectric capacitor 202 to be coupled to board line 118 and bit line 114, and a second ferroelectric capacitor 204 to be coupled to board line 118 and complementary bit line 114. If a "1" is to be written into example bit cell 120, example bit line driver 106 outputs a high voltage on example bit line 114 via example bit line transistor 107 and outputs ground on example complementary bit line 116. Therefore, example board driver 108 outputs ground on example board line 118 via example board transistor 109. In this example, there will be a voltage drop across the first example ferroelectric capacitor 202, which charges the ferroelectric capacitor 202 in a second (e.g., positive) dipole orientation. Because there is no voltage drop across the second ferroelectric capacitor 206 (e.g., maintaining a negative dipole orientation), it will not charge. If a "0" is to be written to example bit cell 120, example bit line driver 106 outputs a ground voltage on example bit line 114 and a high voltage on example complementary bit line 116. Therefore, example board driver 108 outputs a high voltage on example board line 118. In this example, there will be a voltage drop across the second example ferroelectric capacitor 206 that charges the example ferroelectric capacitor 206 in a positive dipole orientation. Because there is no voltage drop across the first example ferroelectric capacitor 202 (e.g., maintaining a negative dipole orientation), it will not charge. In this example, the charge stored in the first example ferroelectric capacitor 202 (e.g., positive dipole orientation) is associated with a first logic value (e.g., "1"), and the charge stored in the second example ferroelectric capacitor 206 (e.g., negative dipole orientation) is associated with a second logic value (e.g., "0").

[0027] During the read operation, example line drive 104 ( Figure 1A high voltage (e.g., 2V) is output on example word line 112, which is coupled to the gate of example MOSFET Q1 200. When the high voltage is output on example word line 112, example MOSFETs S 200, 204 behave like closed switches, causing a first ferroelectric capacitor 202 to be coupled to board line 118 and bit line 114, and a second ferroelectric capacitor 204 to be coupled to board line 118 and complementary bit line 114. Example bit line driver 106 floats the voltage on example bit line 114 and example complementary bit line 116 (e.g., no voltage is output on example bit line 114 and example complementary bit line 116). Therefore, example board driver 108 outputs a high voltage on example board line 118 via example board transistor 109. When a high voltage is output on example plate line 118, the high voltage is applied to ferroelectric capacitors 202 and 206, and small or large charges are discharged toward example bit line 114 and example complementary bit line 116 according to the dipole orientation in ferroelectric capacitors 202 and 206. For example, if the first example ferroelectric capacitor 201 has a negative dipole orientation (e.g., not charged) and the second example ferroelectric capacitor 206 has a positive dipole orientation (e.g., charged), applying a high plate line voltage will cause the second example ferroelectric capacitor 206 to change to a negative dipole orientation, resulting in a large charge being output on example complementary bit line 116. Furthermore, the first example ferroelectric capacitor 202 will output a small charge on example bit line 114 because the dipole orientation of ferroelectric capacitor 202 has not changed. In this example, the readout amplifier 122 ( Figure 1 The charge difference between example bit line 114 and example complementary bit line 116 is measured. If the charge on bit line 114 is greater than the charge on complementary bit line 116, the sense amplifier will send a signal to example memory controller 102. Figure 1 The sense amplifier outputs a first logic value (e.g., "1" or "0"). If the charge on bit line 114 is less than the charge on the complementary bit line 116, the sense amplifier outputs a second logic value (e.g., the opposite of the first value) to the example memory controller 102.

[0028] Despite implementation Figure 1 An example of an example FRAM circuit 100 is illustrated in Figure 1 China Times, Figure 1 The components, processes, and / or devices illustrated herein may be combined, separated, rearranged, omitted, eliminated, and / or implemented in any other way. Additionally, the example FRAM controller 102, example row driver 104, example bit line driver 106, example board driver 108, and / or more generally, Figure 1The example FRAM circuit 100 can be implemented by hardware, machine-readable instructions, software, firmware, and / or any combination of hardware, machine-readable instructions, software, and / or firmware. Thus, for example, there are example FRAM controllers 102, example row drivers 104, example bit line drivers 106, example board drivers 108, and / or more generally, Figure 1 The example FRAM circuit 100 may be implemented using analog and / or digital circuitry, logic circuitry, a programmable processor, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), and / or a field-programmable logic device (FPLD). When reading any of the device or system claims of this patent that cover purely software and / or firmware implementations, the example FRAM controller 102, example row driver 104, example bit line driver 106, example board driver 108, and / or more generally... Figure 1 At least one of the example FRAM circuits 100 is thus clearly defined as including a tangible computer-readable storage device or disk, such as a memory, a digital versatile optical disc (DVD), an optical disc (CD), a Blu-ray disc, and other storage software and / or firmware. Furthermore, Figure 1 Example FRAM circuit 100 includes, in addition to Figure 1 Other than or alternative to those listed Figure 1 The elements, processes and / or devices exemplified may include all or more of the exemplified elements, processes and devices or any one of them.

[0029] exist Figure 3 The diagram shows the methods used to implement Figure 1 A flowchart illustrating example machine-readable instructions for an example FRAM circuit 100 is provided. In the example, machine-readable instructions include those provided by means of instructions such as those shown in the following... Figure 6 The program executed by the processor 612 in the example processor platform 600 discussed. The program may be implemented as machine-readable instructions stored on a tangible computer-readable storage medium (such as a CD-ROM, floppy disk, hard disk drive, digital versatile optical disc (DVD), Blu-ray disc, or memory associated with the processor 612), but the entire program and / or portions thereof may optionally be executed by the device rather than by the processor 612 embodied in firmware or dedicated hardware. Additionally, although references... Figure 3 The flowchart shown in the example describes the sample program, but the implementation... Figure 1 Many other methods can be alternatively used for the example FRAM circuit 100. For example, the order of the executed blocks can be changed, and / or some of the described blocks can be altered, eliminated, or combined.

[0030] As mentioned above, Figure 3The example process can be implemented using coded instructions (e.g., computer and / or machine-readable instructions) stored on a tangible computer-readable storage medium such as a hard disk drive, flash memory, read-only memory (ROM), optical disc (CD), digital versatile optical disc (DVD), cache, random access memory (RAM), and / or any other storage device or storage disc in which information is stored for any duration (e.g., for extended periods, permanently, e.g., for temporary buffers, and / or for information caches). As used herein, the term tangible computer-readable storage medium is clearly defined to include any type of computer-readable storage device and / or storage disc and to exclude propagation signals and transmission media. As used herein, "tangible computer-readable storage medium" and "tangible machine-readable storage medium" may be used interchangeably. Additionally or alternatively, Figure 3 The example process can be implemented using coded instructions stored on a non-transitory computer and / or machine-readable medium, such as a hard disk drive, flash memory, read-only memory, optical disk, digital universal optical disk, cache, random access memory, and / or any other storage device or storage optical disk where information is stored for any duration (e.g., for extended time periods, permanently, e.g., for temporary buffers, and / or for information caching). As used herein, the term non-transitory computer-readable medium is clearly defined to include any type of computer-readable storage device and / or storage optical disk and to exclude propagation signals and transmission media. As used herein, when the phrase “at least” is used as a transition word in the preamble of a claim, it is an open-ended term in the same manner as the term “comprising” is open-ended.

[0031] Figure 3 Example flowchart 300 represents example machine-readable instructions, which can be derived from... Figure 1 Example FRAM circuit 100 performs to cause Figure 1 Example drivers 104, 106, and 108 read and / or write bit cells of the FRAM array. Although flowchart 300 combines... Figure 1 The example FRAM circuit 100 is described, but flowchart 300 is used to implement any type of FRAM circuit.

[0032] At block 302, example drivers 104, 106, and 108 receive read signals output by example FRAM controller 102. In some examples, the read signals sent to example bit line driver 106 and / or example board driver 108 may be delayed (e.g., a fixed delay). In such examples, FRAM controller 102 may include timing circuitry to generate the delay. In some examples, the read signals indicate which bit cells will be read.

[0033] At block 304, example row driver 104 outputs a high voltage (e.g., 2V) on example word line 112 of example FRAM array 110. As described above, applying a voltage on example word line 112 activates the transistors coupled to the bit cells of word line 112. After board driver 108 receives a fixed-delay read signal from FRAM controller 102, board driver 108 outputs a high voltage (e.g., 2V) on example board line 118 via example board transistor 109 (block 306). There is a second delay, which is associated with the amount of time required for board transistor 109 to output a high voltage in response to receiving the read signal. The optimal amount of total delay (e.g., fixed delay plus the second delay) is based on the number of columns in example FRAM array 110. Therefore, example board transistor 109 is selected such that the second delay (e.g., the delay associated with example board transistor 109) corresponds to the optimal delay (e.g., the second delay equals the optimal delay minus the fixed delay).

[0034] At box 308, the example readout amplifier determines the logic value stored in example bit cell 120 (e.g., corresponding to example word line 112 and example board line 118). Figure 2 As described, the example sense amplifier 120 determines the logic value based on the charge difference between example bit line 114 and example complementary bit line 116. As mentioned above, the read operation of the example FRAM array 110 is destructive. Therefore, once example bit cell 120 has been read, example FRAM controller 102 sends a write signal to example drivers 104, 106, 108 to write back to example bit cell 120. In some examples, the read signal sent by FRAM controller 102 includes an instruction to write back (e.g., refresh) the stored logic value after the read operation. In such examples, the write signal may not be necessary (e.g., the write operation automatically follows the read operation). If the write operation is a write-back operation following the read operation, example row driver 104 may continue to output a high voltage on example word line 112.

[0035] At block 310, example drivers 104, 106, and 108 receive example write signals. In some examples, the write signals sent to example bit line driver 106 and / or example board driver 108 may be delayed (e.g., a fixed delay). In such examples, FRAM controller 102 may include timing circuitry to generate the delay. In some examples, the write signals indicate which bit cells will be written.

[0036] At block 312, example bit line driver 106 outputs a first voltage (e.g., 2V or ground) on example bit line 114 of example FRAM array 110 via the first of example bit line transistors 107, depending on which value (e.g., "1" or "0") will be stored. While example bit line driver 106 outputs the first voltage on the example bit line, example bit line driver 106 also outputs a second complementary voltage on example complementary bit line 116 via the second of example bit line transistors 108. For example, if the voltage on example bit line 114 is 2V, the voltage on example complementary bit line 116 will be ground. A second delay exists, which is related to the amount of time required for bit line transistor 107 to output the first voltage in response to receiving a write signal. The optimal amount of total delay (e.g., fixed delay plus the second delay) is based on the number of rows in example FRAM array 110. Therefore, an example bit line transistor 107 is selected such that the second delay (e.g., the delay associated with the example bit line transistor 107) corresponds to the optimal delay (e.g., the second delay should be equal to the optimal delay minus the fixed delay).

[0037] At block 314, example board driver 108 outputs a board pulse voltage (e.g., 2V) on example board line 118 of example FRAM array 110 via one of example board transistors 109. Figure 2 As shown, the plate pulse voltage causes a voltage difference (e.g., switching dipole orientation) between (A) example plate line 118 and example bit line 114 or (B) example plate line 118 and example complementary bit line 116. The direction of the dipole orientation (e.g., positive or negative) of the example ferroelectric capacitors 202, 204 corresponds to the stored logic value.

[0038] Figure 4 The timing diagrams illustrate a comparison of optimal board pulse voltages for a 512-row FRAM array and an optimal board pulse voltage for a 32-row FRAM array. The illustrated timing diagrams include an example board pulse voltage 400 for the 512-row array, associated with an example fixed timing delay 402, an example first board transistor pulse delay 404, and an example first board pulse width 406. The illustrated timing diagrams also include an example board pulse voltage 408 for the 32-row array, associated with an example fixed timing delay 402, an example second board transistor pulse delay 410, and an example second board pulse width 412.

[0039] As described above, the optimal board pulse delay is the minimum amount of delay necessary to successfully read / write logic values ​​from / to example bit cells 120 of the example FRAM array 110. In some examples, the optimal board pulse delay is obtained from a lookup table and / or generated based on FRAM testing. The example fixed delay 402 is the delay associated with the timing circuitry of the example FRAM controller 102. In some examples, the fixed delay 402 is a predetermined amount of time that does not change based on different sizes of the FRAM array 110. The fixed delay 402 is less than the optimal board pulse delay, making it possible to add the delay associated with the board transistors (e.g., one of the example board transistors 109) to the fixed delay to total the optimal board pulse delay. In this way, for different sizes of FRAM arrays, the optimal delay can be achieved by adjusting the transistor sizes without adjusting the fixed timing circuitry. For example, the optimal delay for the example board pulse 400 for 512 rows is 105 ns. To achieve an optimal delay of 105ns, a large pulse transistor with a first example delay 404 (e.g., 5ns) is selected (e.g., 100ns fixed delay + 5ns pulse transistor delay = 105ns optimal delay). Furthermore, the optimal delay for the example board transistor pulse 408 used in row 32 is 102ns. To achieve an optimal delay of 102ns, a small transistor with a second example delay 410 (e.g., 2ns) is selected (e.g., 100ns fixed delay + 2ns pulse transistor delay = 102ns optimal delay).

[0040] As described above, the optimal board pulse width is the minimum board pulse width (e.g., the amount of time the board pulse is high) necessary for successfully reading a logic value from / writing a logic value to the example bit cell 120 of the example FRAM array 110. As the number of rows in the FRAM array 110 increases, the corresponding amount of capacitance in the FRAM array 110 increases, and the board pulse takes longer to reach the minimum voltage necessary for successfully reading / writing a logic value from / to the example bit cell 120. Therefore, the board pulse width needs to be wider for FRAM arrays with more rows to allow sufficient time for the board pulse to reach a sufficient voltage to program the example bit cell 120. In some examples, the optimal board pulse width is obtained from a lookup table and / or generated based on FRAM testing. In the example board pulse voltage 400 for 512 rows, the optimal board pulse width 406 is 16 ns. In the example board pulse voltage 408 for 32 rows, the optimal board pulse width 412 is 8 ns.

[0041] Figure 5Timing diagrams comparing optimal bit-line transistor pulse voltages for a 72-column FRAM array and bit-line transistor pulse voltages for an 8-column FRAM array are illustrated. The illustrated timing diagrams include an example bit-line transistor voltage 500 for the 72-column array, associated with an example fixed timing delay 502, an example first bit-line transistor delay 504, and an example first bit-line pulse width 506. The illustrated timing diagrams also include an example bit-line transistor pulse voltage 508 for the 8-column array, associated with an example fixed timing delay 502, an example second bit-line transistor delay 510, and an example second bit-line pulse width 512.

[0042] As described above, the optimal bit-line pulse delay is the minimum amount of delay necessary for successfully writing a logic value to the example bit cell 120 of the example FRAM array 110. In some examples, the optimal bit-line pulse delay is obtained from a lookup table and / or generated based on FRAM testing. The example fixed delay 502 is the delay associated with the timing circuitry of the example FRAM controller 102. In some examples, the example fixed delay 502 is a predetermined amount of time that does not change based on different sizes of the FRAM array 110. In this example, the fixed delay 502 is less than the optimal bit-line pulse delay, making it possible to write logic values ​​to bit-line transistors (e.g., Figure 1 The delay associated with the example bit-line transistor 107 is added to the fixed delay to total the optimal bit-line pulse delay. In this way, for different sized FRAM arrays, the optimal delay can be achieved by adjusting the transistor size without adjusting the fixed timing circuitry. For example, the optimal delay for the example bit-line pulse 500 for 72 columns is 123 ns. To achieve the 123 ns optimal delay, a large pulse transistor with a first example delay 504 (e.g., 13 ns) is selected (e.g., 110 ns fixed delay + 13 ns bit-line transistor delay = 123 ns optimal delay). Furthermore, the optimal delay for the example bit-line pulse 508 for 8 columns is 112 ns. To achieve the 102 ns optimal delay, a small transistor with a second example delay 510 (e.g., 2 ns) is selected (e.g., 110 ns fixed delay + 2 ns bit-line pulse transistor delay = 112 ns optimal delay). In some examples, the fixed delay 502 is associated with... Figure 4 Example fixed delay 402 is the same amount of delay. Alternatively, example fixed delay 502 and example fixed delay 402 may correspond to different amounts of time.

[0043] As described above, the optimal bit line pulse width is the minimum bit line pulse width (e.g., the amount of time the bit line pulse is high) necessary for successfully writing a logic value from the example bit cell 120 of the example FRAM array 110. As the number of columns in the FRAM array 110 increases, the corresponding amount of capacitance in the FRAM array 110 increases, and the bit line pulse takes longer to reach the minimum voltage required to successfully write a logic value to the example bit cell 120. Therefore, the bit line pulse width needed for an FRAM array with more columns needs to be wider to allow sufficient time for the bit line pulse to reach a sufficient voltage to program the example bit cell 120. In some examples, the optimal bit line pulse width is obtained from a lookup table and / or generated based on FRAM testing. For example, the optimal pulse width 506 for the example board pulse voltage 500 with 72 columns is 14 ns. The optimal pulse width 512 for the example board pulse voltage 508 with 8 columns is 9 ns.

[0044] Figure 6 It is capable of execution Figure 3 Instructions to achieve Figure 1 The example FRAM circuit 100 is a block diagram of an example processor platform 600. The processor platform 600 can be, for example, a server, a personal computer, a mobile device (e.g., a mobile phone, a smartphone, a tablet such as an iPad). TM Personal digital assistants (PDAs), Internet devices, or any other type of computing device.

[0045] The illustrated processor platform 600 includes a processor 612. The illustrated processor 612 is hardware. For example, the processor 612 can be implemented using integrated circuits, logic circuits, microprocessors, or microprocessors from any desired family or manufacturer.

[0046] The illustrated processor 612 includes local memory 613 (e.g., cache memory). Figure 6 Example processor 612 execution Figure 3 Instructions to achieve Figure 1An example FRAM controller 102, an example row driver 104, an example bit line driver 106, and an example board driver 108 are used to implement the example FRAM circuit 100. The illustrated processor 612 communicates via bus 618 with main memory, which includes non-volatile memory 614 and non-volatile memory 616. Volatile memory 614 can be implemented using synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. Non-volatile memory 616 can be implemented using flash memory and / or any other desired type of memory device. Access to main memory 614, 616 is controlled by a clock controller.

[0047] The illustrated processor platform 600 also includes interface circuitry 620. Interface circuitry 620 can be implemented using any type of interface standard, such as an Ethernet interface, a Universal Serial Interface (USB), and / or a PCI Express interface.

[0048] In the illustrated example, one or more input devices 622 are connected to interface circuitry 620. One or more input devices 622 allow user input of data and commands to the processor 612. These input devices can be implemented as, for example, sensors, microphones, cameras (still or video), keyboards, buttons, mice, touchscreens, trackpads, trackballs, isoelectric points, and / or voice recognition systems.

[0049] One or more output devices 624 are also connected to the illustrated interface circuitry 620. The output devices 624 can be implemented, for example, via display devices (e.g., light-emitting diodes (LEDs), organic light-emitting diodes (OLEDs), liquid crystal displays, cathode ray tube displays (CRTs), touchscreens, haptic output devices, and / or speakers). Therefore, the illustrated interface circuitry 620 typically includes a graphics driver card, a graphics card driver chip, or a graphics card driver processor.

[0050] The illustrated interface circuit 620 also includes communication devices such as transmitters, receivers, transceivers, modems, and / or network interface cards to facilitate data exchange with external machines (e.g., any kind of computing device) via network 626 (e.g., Ethernet connection, Digital Subscriber Line (DSL), telephone line, coaxial cable, cellular telephone system, etc.).

[0051] The illustrated processor platform 600 also includes one or more mass storage devices 628 for storing software and / or data. Examples of such mass storage devices 628 include floppy disk drives, hard disk drives, optical disks, Blu-ray disc drives, RAID systems, and digital universal optical disc (DVD) drives.

[0052] Figure 3 The encoded instructions 300 can be stored in a mass storage device 628, in volatile memory 614, in non-volatile memory 616 and / or in a removable tangible computer-readable storage medium such as a CD or DVD.

[0053] As can be understood from the above, the disclosed methods, apparatus, and various articles of art provide timing circuitry for FRAM. Advances in FRAM technology have led to FRAMs of various sizes. Smaller FRAMs correspond to smaller loads and smaller capacitances. Therefore, the voltage pulses used to read / write bit cells in a smaller FRAM array can include pulses with a smaller width and less delay compared to voltage pulses associated with larger FRAM circuitry. Reducing pulse width and delay preserves the power and optimal speed of the FRAM circuitry. However, creating various timing circuits for FRAM arrays of various sizes can be time-consuming and expensive. The examples disclosed herein utilize (A) fixed-timing circuitry associated with a fixed delay and (B) transistors of different sizes coupled to FRAM drivers associated with different transistor delays to output voltage pulses with optimal delay and width. For example, both smaller and larger FRAM circuits may include the same timing circuitry; however, the smaller FRAM will include smaller transistors and the larger FRAM circuit will include larger transistors. In this way, FRAM circuits of different sizes can output optimal delays by selecting transistors to couple to FRAM drivers with corresponding transistor delays, without the time and expense associated with creating custom timing circuits. Furthermore, selecting smaller transistors for smaller FRAM circuits creates narrower pulse widths. However, because smaller FRAMs have less capacitance than larger FRAMs, smaller FRAM circuits can operate with even narrower pulse widths.

[0054] Conventional techniques for providing time-tracking circuitry for FRAM arrays utilize a fixed time delay for all FRAM circuitry, regardless of the FRAM circuitry size. This conventional technique generates the delay and pulse width required to program the largest FRAM arrays (e.g., FRAMs with 72,000 bits). Therefore, the delay and pulse width required for smaller FRAM arrays (e.g., FRAMs with less than 72,000 bits) consume more power and are slower than those described herein. By using the examples disclosed herein, FRAM power and speed are optimized by selecting transistors associated with the optimal pulse delay and width.

[0055] Example memory circuitry is disclosed to provide time tracking for a memory array. This memory circuitry includes a controller to output a signal to an input of a driver. This memory circuitry includes a transistor coupled to the output of the driver. In this memory circuitry, the driver outputs a first voltage to the transistor in response to receiving a signal. In this example, the transistor outputs a second voltage to the bit cell after a transistor delay in response to receiving the first voltage; the transistor is selected based on the size of the memory circuitry.

[0056] In some example memory circuits, the controller is configured to output a signal after a predetermined delay. In some example memory circuits, the transistor is configured to output a second voltage to the board line of the bit cell. In some example memory circuits, the sum of the transistor delay and the predetermined delay is approximately the optimal read delay. In some example memory circuits, the optimal read delay corresponds to the minimum amount of delay time required to read the logic value stored in the bit cell. Some example memory circuits further include a ferroelectric random access memory (FRAM) array, where the minimum amount of delay corresponds to the number of bit cell rows in the FRAM array, wherein increasing the number of rows increments the minimum amount of delay.

[0057] In some example memory circuits, the second voltage is a second voltage pulse, wherein the transistor is further selected based on the width of the second voltage pulse, which is the minimum width necessary to read or write a logic value in the bit cell. In some example memory circuits, the transistors are configured to output the second voltage to the bit line of the bit cell. In some example memory circuits, the sum of the transistor delay and a predetermined delay is approximately the optimal write delay. In some example memory circuits, the optimal write delay corresponds to the minimum amount of delay time necessary to write a logic value to the bit cell. Some example memory circuits further include an FRAM array, where the minimum amount of delay corresponds to the number of columns of bit cells in the FRAM array, wherein increasing the number of columns increases the minimum amount of delay.

[0058] In some example memory circuits, the second voltage is a second voltage pulse, wherein the transistor is further selected based on the width of the second voltage pulse, which is the minimum width necessary to write a logic value into the bit cell. In some example memory circuits, the controller includes timing circuitry to generate a predetermined delay. In some example memory circuits, the bit cell includes a ferroelectric capacitor. In some example memory circuits, the transistor is configured to output a second voltage to program the bit cell to have a logic value by charging the ferroelectric capacitor. In some example memory circuits, the transistor is configured to output a second voltage to read the logic value of the bit cell by discharging the ferroelectric capacitor. In some example memory circuits, the transistor delay corresponds to the amount of time it takes for the transistor to output a second voltage in response to receiving a first voltage, and the transistor delay corresponds to the size of the transistor.

[0059] While certain example methods, apparatuses, and articles have been disclosed herein, the scope of this patent is not limited thereto. On the other hand, this patent covers all methods, apparatuses, and articles falling within the scope of the claims of this patent.

Claims

1. An integrated circuit device, comprising: A first number of bit cells, which are collectively coupled to a first board line and a first word line, wherein each of the first number of bit cells is further coupled to a corresponding bit line; A first plate transistor coupled to the first plate line, wherein the first plate transistor has a first size determined based on the first number, resulting in a delay corresponding to the first number of bit cells coupled to the first plate line; A second number of bit cells, which are collectively coupled to a second board line and a second word line, wherein each of the second number of bit cells is further coupled to a corresponding bit line, and wherein the second number is different from the first number; and A second plate transistor coupled to the second plate line, wherein the second plate transistor has a second size determined based on the second number, resulting in a delay corresponding to the second number of bit cells coupled to the second plate line.

2. The integrated circuit device according to claim 1, comprising: The controller is configured as follows: A first signal is provided to cause a voltage to be applied to the first word line coupled to the first bit cell of the first number of bit cells; A second signal is provided to cause the first board transistor to apply a voltage to the first board line; as well as Read the value from the first bit unit.

3. The integrated circuit device according to claim 2, wherein: The controller is configured to provide the second signal after a delay following the provision of the first signal.

4. The integrated circuit device of claim 3, wherein the delay lasts for a predetermined amount of time, and wherein the sum of the delay after the first signal is provided and the delay caused by the first board transistor is equal to or greater than the minimum amount of time required to read the value from the first bit cell.

5. The integrated circuit device of claim 1, wherein each bit unit of the first number of bit units comprises: A first transistor has a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal being coupled to the first word line; A first ferroelectric capacitor is coupled between the first current-conducting terminal of the first transistor and the first plate line; The second transistor has a control terminal, a first current conduction terminal, and a second current conduction terminal, the control terminal being coupled to the first word line; as well as A second ferroelectric capacitor is coupled between the first current-conducting terminal of the second transistor and the first plate line.

6. The integrated circuit device according to claim 1, comprising: A third number of bit cells, which are collectively coupled to a first bit line, wherein each of the third number of bit cells is further coupled to a corresponding word line; The first bit line transistor is coupled to the first bit line; A fourth number of bit cells, all coupled to a second bit line, wherein each of the fourth number of bit cells is further coupled to a corresponding word line, and wherein the fourth number is different from the third number; and A second bit-line transistor is coupled to the second bit-line, wherein the second bit-line transistor has a different size than the first bit-line transistor.

7. The integrated circuit device of claim 6, wherein the size of the first bit line transistor is determined based on the third quantity, and the size of the second bit line transistor is determined based on the fourth quantity.

8. The integrated circuit device according to claim 6, comprising: The controller is configured as follows: A first signal is provided to cause voltages to be applied to the first word line and the second word line, respectively, which are coupled to the first bit cell and the second bit cell in the third number of bit cells; A second signal is provided to cause the first bit line transistor to apply a voltage to the first bit line; as well as Write the value into the first bit cell.

9. The integrated circuit device according to claim 8, wherein: The controller is configured to provide the second signal after a delay following the provision of the first signal.

10. The integrated circuit device of claim 9, wherein the delay lasts for a predetermined amount of time, and wherein the sum of the delay and the delay caused by the first bit line transistor is equal to or greater than the minimum amount of time required to read the value from the first bit cell.

11. The integrated circuit device of claim 6, wherein each bit unit in the third number of bit units comprises: A first transistor has a control terminal, a first current conduction terminal, and a second current conduction terminal, the first current conduction terminal being coupled to the first bit line; A first ferroelectric capacitor is coupled between the second current-conducting terminal of the first transistor and the first plate line; The second transistor has a control terminal, a first current conduction terminal and a second current conduction terminal, the first current conduction terminal being coupled to the first bit line; as well as A second ferroelectric capacitor is coupled between the second current-conducting terminal of the second transistor and the second plate line.

12. An integrated circuit device comprising: A first number of bit cells, which are collectively coupled to a first bit line, wherein each of the first number of bit cells is further coupled to a corresponding word line; A first bit line transistor coupled to the first bit line, wherein the first bit line transistor has a first size determined based on the first number, resulting in a delay corresponding to the first number of bit cells coupled to the first bit line; A second number of bit units, which are collectively coupled to a second bit line, wherein each of the second number of bit units is further coupled to a corresponding word line, and wherein the second number is different from the first number; as well as A second bit line transistor coupled to the second bit line, wherein the second bit line transistor has a second size determined based on the second number, resulting in a delay corresponding to the second number of bit cells coupled to the second bit line.

13. The integrated circuit device of claim 12, comprising: The controller is configured as follows: A first signal is provided to cause voltages to be applied to a first word line and a second word line, respectively, the first word line and the second word line being coupled to a first bit cell and a second bit cell in the first number of bit cells; A second signal is provided to cause the first bit line transistor to apply a voltage to the first bit line; as well as Write the value into the first bit cell.

14. The integrated circuit device according to claim 13, wherein: The controller is configured to provide a second signal after a delay following the provision of the first signal.

15. The integrated circuit device of claim 14, wherein the delay lasts for a predetermined amount of time, and wherein the sum of the delay after the first signal is provided and the delay caused by the first bit line transistor is equal to or greater than the minimum amount of time required to read the value from the first bit cell.

16. The integrated circuit device of claim 12, comprising: A third number of bit cells, which are collectively coupled to a first plate line, wherein each of the third number of bit cells is further coupled to a corresponding bit line; The first plate transistor is coupled to the first plate line; A fourth number of bit cells, all coupled to a second plate line, wherein each of the fourth number of bit cells is further coupled to a corresponding bit line, and wherein the fourth number is different from the third number; and A second plate transistor is coupled to a second plate line, wherein the second plate transistor has a different size than the first plate transistor.

17. The integrated circuit device of claim 16, wherein the size of the first plate transistors is determined based on the third quantity, and the size of the second plate transistors is determined based on the fourth quantity.

18. A method for reading and / or writing to a memory, comprising: A read operation is performed on a capacitive memory array containing a set of bit line inputs / outputs, a set of word line inputs, and a set of board inputs in the following manner: Provide a first signal to the row driver circuit; Based on the first signal, the row driver circuit applies a first voltage to at least a subset of the set of word line inputs; After a first delay following the provision of the first signal, a second signal is provided to the board driver circuit. Based on the second signal, the board driver circuitry applies a second voltage to at least a subset of the set of board inputs, wherein the first delay associated with the second signal is less than the minimum read delay associated with the set of board inputs of the capacitive memory array, and the application of the second voltage is performed after the minimum read delay associated with the set of board inputs of the capacitive memory array. and Values ​​are received via the set of bit lines input / output.

19. The method of claim 18, further comprising: The write operation is performed on the capacitor memory array in the following manner: A third signal is provided to the row driver circuit; Based on the third signal, the row driver circuit applies a third voltage to at least a subset of the set of word line inputs; A fourth signal is provided to the bit line driver circuit after a second delay following the provision of the third signal; and Based on the fourth signal, the bit line driver circuit applies a fourth voltage to at least a subset of the set of bit line inputs / outputs, wherein the second delay associated with the fourth signal is less than the minimum write delay associated with the set of bit line inputs / outputs of the capacitive memory array, and the application of the fourth voltage is performed after the minimum write delay associated with the set of bit line inputs / outputs of the capacitive memory array.

20. The method of claim 19, wherein performing the write operation further comprises: A fifth signal is provided to the board driver circuit; and Based on the fifth signal, the board driver circuit applies a fifth voltage to at least a subset of the set of board inputs, while the fourth voltage is applied to at least a subset of the set of bit line inputs / outputs.

21. A memory system comprising: Memory circuit, comprising: Ferroelectric random access memory arrays, also known as FRAM arrays, include: A plurality of bit units, each of the plurality of bit units comprising at least one ferroelectric capacitor; A set of word line inputs coupled to the plurality of bit cells; and A set of board line inputs coupled to the ferroelectric capacitors of the plurality of bit cells, wherein the FRAM array has a minimum delay between the assertion of the word line signal on the set of word line inputs and the assertion of the board line signal on the set of board line inputs to initiate a read or write to a corresponding bit cell among the plurality of bit cells, the minimum delay being based on the number of bit cell columns in the FRAM array. A controller comprising a board line driver output to provide a first driver signal after a first delay following an assertion of the word line signal, wherein the controller includes timing circuitry to generate the first driver signal after the first delay; A board line driver, comprising an input coupled to the controller, the board line driver output for receiving the first driver signal, and a set of outputs providing a set of board line control signals in response to the first driver signal; and A set of transistors coupled to the set of outputs of the board line driver and the set of board line inputs of the FRAM array, wherein each transistor in the set of transistors comprises: A gate terminal, which is coupled to a corresponding output in the set of outputs of the board line driver; The second terminal is coupled to a corresponding board line input of the set of board line inputs of the FRAM array; and A third terminal, coupled to a voltage source, wherein each transistor in the set of transistors is configured to have a transistor delay such that a corresponding board line control signal is received at the gate terminal after the assertion of the word line signal with a second delay less than the minimum delay amount, and the transistor provides a board line signal to the corresponding board line input of the set of board line inputs of the FRAM array after the assertion of the word line signal with at least the minimum delay amount.

22. The memory system according to claim 21, wherein: The FRAM array further has a minimum pulse width for the board line signal based on the number of bit cell columns in the FRAM array, and Each of the set of transistors is further configured to provide the corresponding board line signal having a width of at least the minimum pulse width.

23. The memory system according to claim 21, wherein: The group of transistors is the first group of transistors; The FRAM array further includes a set of bit line inputs coupled to the plurality of bit cells; The FRAM array has a minimum bit line delay between the assertion of the word line signal and the assertion of the bit line signal on the set of bit line inputs; The controller further includes a bit line driver output to provide a second driver signal; and The memory circuit further includes: Bit line driver, comprising an input coupled to the bit line driver output to receive a second driver signal and a set of outputs providing a set of bit line control signals in response to the second driver signal; and The second set of transistors is coupled to the set of outputs of the bit line driver and the set of bit line inputs of the FRAM array.

24. The memory system of claim 23, wherein each transistor in the second group of transistors comprises: A gate terminal, which is coupled to a corresponding output in the set of outputs of the bit line driver; The second terminal is coupled to a corresponding bit line input in the set of bit line inputs of the FRAM array; and The third terminal is coupled to the voltage source.

25. The memory system of claim 24, wherein each of the second set of transistors is configured to have a transistor delay such that a corresponding bit line control signal is received at the gate terminal after the assertion of the word line signal at a third delay less than the minimum bit line delay, and the transistor provides a bit line signal to a corresponding bit line input of the set of bit line inputs of the FRAM array after at least the minimum bit line delay following the assertion of the word line signal.

26. The memory system of claim 23, wherein each of the plurality of bit cells comprises: A first ferroelectric capacitor, which is coupled to a corresponding plate line input in the set of plate line inputs; A first transistor is coupled between the first ferroelectric capacitor and the first bit line of the set of bit line inputs; A second ferroelectric capacitor is coupled to the corresponding plate line input; and The second transistor is coupled between the second ferroelectric capacitor and the second bit line of the set of bit line inputs.

27. The memory system of claim 21, wherein, as part of a read operation, the set of transistors provides the board line signal to the set of board line inputs of the FRAM array.

28. The memory system of claim 21, wherein, as part of a write operation, the set of transistors provides the board line signal to the set of board line inputs of the FRAM array.

29. A memory circuit comprising: A capacitor memory array comprising: Multiple units, each containing a corresponding capacitor; A set of word line inputs, which are coupled to the plurality of units; and A set of plate line inputs, which are coupled to the capacitors of the plurality of units; A controller that includes a board-line driver output to provide a first driver signal; A board line driver that includes an input to the controller, the board line driver output being coupled to the controller to receive the first driver signal, and a set of outputs to provide a set of board line control signals; A set of transistors coupled to the set of outputs of the board line driver and the set of board line inputs of the capacitor memory array, wherein: Each of the set of transistors is configured to provide a voltage to a corresponding board line input of the set of board line control signals in response to a corresponding board line control signal in the set of board line inputs of the capacitor memory array; and Each of the set of transistors has a delay such that the corresponding transistor receives the corresponding board line control signal at a first time less than a minimum board line delay after an assertion of a signal configured at the corresponding word line input of the set of word line inputs, and provides the voltage to the corresponding board line input at a second time at least the minimum board line delay after an assertion of the signal at the corresponding word line input. The minimum board line delay is the minimum delay required to enable reading or writing to a corresponding unit among the plurality of units.

30. The memory circuit of claim 29, wherein each of the set of transistors comprises: A gate terminal, which is coupled to a corresponding output in the set of outputs of the board line driver; The second terminal is coupled to a corresponding board line input in the set of board line inputs of the capacitor memory array; and The third terminal is coupled to a voltage source.

31. The memory circuit according to claim 29, wherein: The group of transistors is the first group of transistors; The capacitor memory array further includes a set of bit line inputs coupled to the plurality of cells; The controller further includes a bit line driver output to provide a second driver signal; and The memory circuit further includes: Bit line driver, comprising an input coupled to the controller of the bit line driver output to receive the second driver signal and a set of outputs to provide a set of bit line control signals; and The second set of transistors is coupled to the set of outputs of the bit line driver and the set of bit line inputs of the capacitor memory array.

32. The memory circuit according to claim 31, wherein: Each of the second set of transistors is configured to provide a voltage to a corresponding bit line input in the set of bit line control signals in response to a corresponding bit line control signal in the set of bit line control signals of the capacitor memory array; and Each of the second set of transistors has a delay such that the corresponding transistor receives the corresponding bit line control signal at a third time less than the minimum bit line delay after the signal assertion at the corresponding word line input of the set of word line inputs, and provides the voltage to the corresponding bit line input at a fourth time at least the minimum bit line delay after the signal assertion at the corresponding word line input.

33. The memory circuit of claim 31, wherein each of the second set of transistors comprises: A gate terminal, which is coupled to a corresponding output in the set of outputs of the bit line driver; The second terminal is coupled to a corresponding bit line input in the set of bit line inputs of the capacitor memory array; and The third terminal is coupled to a voltage source.

34. The memory circuit of claim 29, wherein, as part of a read operation, the set of transistors provides the voltage to the set of board line inputs of the capacitor memory array.

35. The memory circuit of claim 29, wherein, as part of a write operation, the set of transistors provides the voltage to the set of board line inputs of the capacitor memory array.

36. An integrated circuit device comprising: A capacitor memory controller, which includes word line outputs, bit line outputs, and board line outputs; A line driver that includes an input coupled to the word line output of the capacitive memory controller and a set of outputs providing a set of word line control signals; Bit line driver, which includes an input coupled to the bit line output of the capacitive memory controller and a set of outputs providing a set of bit line control signals; The first set of transistors is coupled to the set of outputs of the bit line driver and is configured to provide a set of bit line signals at a set of bit lines of the capacitor memory array. A board line driver that includes an input coupled to the board line output of the capacitor memory controller and a set of outputs providing a set of board line control signals; and A second set of transistors, coupled to the set of outputs of the board line driver, and providing a set of board line signals configured at a set of board lines of the capacitor memory array, wherein: The capacitor memory controller and the bit line driver are configured to provide the set of bit line control signals to the first set of transistors at a first time less than the minimum bit line delay of the capacitor memory array; and The first set of transistors is configured to provide the set of bit line signals at a second time that is at least the minimum bit line delay of the capacitor memory array; The minimum bit line delay is the minimum delay between the assertion of the word line control signal at the row driver output and the assertion of the bit line control signal at the bit line driver output, in order to enable reading or writing to the capacitive memory array.

37. The integrated circuit device according to claim 36, wherein: The capacitor memory controller and the board line driver are configured to provide the set of board line control signals to the second set of transistors at a third time less than the minimum board line delay of the capacitor memory array. and The second set of transistors is configured to provide the set of board line signals at a fourth time, which is at least the minimum board line delay of the capacitor memory array.

38. The integrated circuit device of claim 36, wherein each of the first group of transistors comprises: A gate terminal, which is coupled to a corresponding output in the set of outputs of the bit line driver; The second terminal is configured to be coupled to a corresponding bit line in the set of bit lines of the capacitor memory array; and The third terminal is coupled to a voltage source.

39. The integrated circuit device of claim 36, wherein each of the second set of transistors comprises: A gate terminal, which is coupled to a corresponding output in the set of outputs of the board line driver; The second terminal is configured to be coupled to a corresponding board line in the set of board lines of the capacitor memory array; and The third terminal is coupled to a voltage source.

40. The integrated circuit device of claim 36, wherein, as part of an operation comprising a group of read and write operations, the first group of transistors and the second group of transistors are configured to provide the set of bit line signals and the set of board line signals.

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