Reduce the maximum programming voltage during memory programming operations

Abstract

This invention describes systems and methods for reducing the maximum programming voltage during memory programming operations. An example memory device includes: a memory array comprising a plurality of memory cells electrically coupled to a plurality of word lines and a plurality of bit lines; and a controller coupled to the memory array, the controller performing operations including: identifying one or more memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target word line and one or more target bit lines; disconnecting the drain-side select gate and the source-side select gate of the memory array; discharging the unselected word line of the memory array to a predefined voltage level; and applying one or more programming voltage pulses to the target word line.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to reducing the maximum programming voltage during memory programming operations. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention Attached Figure Description

[0003] This disclosure will be more fully understood from the embodiments given below and from the accompanying drawings of various embodiments thereof.

[0004] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0005] Figure 2 This is a block diagram of a memory device communicating with a memory subsystem controller according to an embodiment.

[0006] Figure 3A A schematic diagram of a collection of memory cells arranged in a memory device.

[0007] Figure 3B The correlation between source-drain current and control gate voltage for two memory cells is illustrated schematically.

[0008] Figure 3C An example distribution of threshold control gate voltages for memory cells is schematically shown.

[0009] Figure 4 An example memory array is shown schematically.

[0010] Figure 5 An example memory device operating according to various aspects of this disclosure is illustrated schematically.

[0011] Figure 6 A fragment of an example memory array of a memory device operating according to various aspects of this disclosure is shown.

[0012] Figure 7 Examples of voltage waveforms applied to various portions of a memory array during programming operations performed using the systems and methods of this disclosure are shown.

[0013] Figure 8A flowchart illustrating an example method for performing memory programming operations according to some embodiments of the present disclosure.

[0014] Figure 9 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0015] Various aspects of this disclosure relate to reducing the maximum programming voltage during memory programming operations. One or more memory devices may be part of a memory subsystem, which may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with... Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0016] The memory subsystem may include high-density non-volatile memory devices, where data needs to be retained when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may contain one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. In some embodiments, each block may contain multiple sub-blocks. Each sub-block contains a set of memory cells (“cells”). A memory cell is an electronic circuit that stores information. Depending on the cell type, a memory cell may store one or more bits of information, and its charge level may define various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​such as “0” and “1” or combinations of these values. Each block and sub-block can be selectively accessed via memory access operations (e.g., read, write, erase operations).

[0017] Memory cells can be formed on a silicon wafer in an array of columns (hereinafter also referred to as "bit lines") and rows (hereinafter also referred to as "word lines"). A word line is one or more rows of memory cells in a memory device that are used with one or more bit lines to generate the address of each memory cell. The intersection of bit lines and word lines defines the address of the memory cell.

[0018] A block is a unit of memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. Each block may contain several sub-blocks, each defined by an associated pillar (e.g., a vertical conductive trace) extending from a shared bit line. A memory page (also referred to herein as a "page") stores one or more bits of binary data corresponding to data received from a host system. To achieve high density, strings of memory cells in a non-volatile memory device may be configured to comprise several memory cells comprising pillars at least partially surrounding a polysilicon channel material (i.e., a channel region). Memory cells may be coupled to access lines (i.e., word lines) to form a string array within a memory block (e.g., a memory array). The compact nature of certain non-volatile memory devices, such as 3D flash NAND memories, means that word lines are common for the many memory cells within a memory block. Some memory devices use certain types of memory cells (e.g., three-level cell (TLC) memory cells), which store three bits of data in each memory cell, enabling more applications to move from traditional hard disk drives to newer memory subsystems (e.g., NAND solid-state drives (SSDs)).

[0019] Memory access operations (e.g., programming (writing), erasing, etc.) can be performed relative to memory cells by applying word line bias voltages to the word lines to which the memory cells of the selected (target) subblock are connected. For example, a programming operation that can be performed in response to a write command received from the host may involve sequentially applying programming voltage pulses to the selected (target) word lines. In some embodiments, the programming pulse voltage may be sequentially ramped up from an initial voltage value (e.g., 0V) to a final voltage value (e.g., V). PGM MAX ).

[0020] In one approach, an Incremental Stepped Pulse Programming (ISPP) process or scheme can be employed to maintain a tight cell threshold voltage distribution for higher data reliability. In ISPP, a series of high-amplitude voltage level pulses with incremental values ​​(e.g., through predefined pulse step heights) are applied to the word lines to which one or more memory cells are connected, gradually increasing the voltage level of the memory cells above the word line voltage level corresponding to the memory access operation (e.g., the target programming level). The uniformly increasing pulses applied by the word line driver of the memory device allow the selected word line to ramp up or increase to the desired word line voltage level (V). wl This can be used for programming operations. Similarly, a series of voltage pulses with uniformly increasing voltage levels can be applied to the word lines to ramp up the word lines to the corresponding word line voltage levels during the execution of an erase operation.

[0021] A series of incremental voltage programming pulses are applied to selected word lines to increase the charge level of each memory cell connected to the word line, and consequently increase the threshold voltage. After each programming pulse, or after several programming pulses, a programming verification operation can be performed to determine whether the threshold voltage of one or more memory cells has increased to the desired programming level.

[0022] Since the programming voltage is generated by a charge pump on the die, reducing the maximum programming voltage will allow for a reduction in both die size and manufacturing cost. The systems and methods of this disclosure reduce the maximum programming voltage by applying a negative voltage to the pillars of the memory cell string while maintaining the same programming stress on the memory cells.

[0023] Therefore, performing a programming operation may involve floating the pillars of both the selected and unselected sub-blocks by disconnecting both the Select Gate Drain (SGD) and Select Gate Source (SGS) signals, which control the corresponding drain-side and source-side selection transistors coupled to each string of memory cells. Once the pillars are floating, the unselected word line can be discharged to a predefined potential, thus promoting a drop in the potential at the pillar of the selected sub-block to the corresponding negative potential. Therefore, programming voltage pulses that can be sequentially applied to the target (selected) word line can reduce the value of the negative potential of the pillar while maintaining the programming stress and programming inhibit stress at the same levels that would be achieved without applying a negative potential to the pillar, as described in more detail below.

[0024] Therefore, the advantages of this method include, but are not limited to, improving die size and bit power by reducing the maximum programming voltage.

[0025] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0026] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0027] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing power.

[0028] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0029] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and read data from memory subsystem 110.

[0030] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple independent communication connections, and / or combinations of communication connections.

[0031] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0033] Each memory device 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), stores one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0034] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading, writing, or erasing data and other such operations performed at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0036] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0037] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0040] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] In one embodiment, memory subsystem 110 includes memory interface component 113. Memory interface component 113 handles interactions between memory subsystem controller 115 and memory devices (e.g., memory device 130) of memory subsystem 110. For example, memory interface component 113 may send memory access commands corresponding to requests received from host system 120 to memory device 130, such as programming commands, read commands, or other commands. Additionally, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to confirmation of a read command or successful execution of a programming command. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0042] In one embodiment, memory device 130 includes a programming manager 134 configured to perform a corresponding memory access operation in response to receiving a memory access command from memory interface 113. In some embodiments, local media controller 135 includes at least a portion of programming manager 134 and is configured to perform the functions described herein. In some embodiments, programming manager 134 is implemented on memory device 130 using firmware, hardware components, or a combination thereof. In one embodiment, programming manager 134 receives a request from, for example, a requester of memory interface 113, for programming data into a memory array of memory device 130. The memory array may comprise an array of memory cells formed at the intersection of word lines and bit lines. In one embodiment, for example, memory cells are grouped into blocks, which may be further divided into sub-blocks, wherein a given word line is shared across several sub-blocks. In one embodiment, each sub-block corresponds to a separate plane in the memory array. A group of memory cells associated with a word line within a sub-block is called a physical page. In one embodiment, a memory array may exist in multiple portions, such as a first portion where sub-blocks are configured as SLC memory and a second portion where sub-blocks are configured as Multilevel Cell (MLC) memory (i.e., containing memory cells that can store two or more bits of information per cell). For example, the second portion of the memory array may be configured as TLC memory. The voltage levels of the memory cells in a TLC memory form a set of eight programming distributions, representing eight different combinations of the three bits stored in each memory cell. Depending on how it is configured, each physical page in a sub-block may contain multiple page types. For example, a physical page formed by a single-level cell (SLC) has a single page type called a lower logical page (LP). The MLC physical page type may contain LP and upper logical page (UP), the TLC physical page type is LP, UP, and additional logical page (XP), and the QLC physical page type is LP, UP, XP, and top logical page (TP). For example, a physical page formed by memory cells of the QLC memory type can have a total of four logical pages, where each logical page can store data that is different from the data stored in other logical pages associated with the physical page.

[0043] In one embodiment, the programming manager 134 may receive data to be programmed into the memory device 130 (e.g., a TLC memory device). Therefore, the programming manager 134 may perform a programming operation to program each memory cell to a desired programming level. In one embodiment, the programming manager 134 may float the pillars of both the selected and unselected sub-blocks by disconnecting both the Select Gate Drain (SGD) and Select Gate Source (SGS) signals, which control the respective drain-side and source-side selection transistors coupled to each string of memory cells. Once the pillars are floated, the unselected word line can be discharged to a predefined potential, thus promoting a drop in potential at the pillars of the selected sub-block to the corresponding negative potential. Therefore, programming voltage pulses that can be sequentially applied to the target (selected) word line can reduce the value of the negative potential of the pillars while maintaining the programming stress and programming inhibit stress at the same levels that would be achieved without applying a negative potential to the pillars, as described in more detail below.

[0044] Figure 2 A first device in the form of a presentable memory device 130 according to an embodiment and a presentable memory subsystem (e.g., Figure 1 A simplified block diagram of a second device communicating with a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0045] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 2 (Not shown in the image) can be programmed to one of at least two target data states.

[0046] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode the address signal. The address signal is received and decoded to access the memory cell array 104. The memory device 130 also includes an input / output (I / O) control circuitry 112 for managing command, address, and data inputs to and from the memory device 130. An address register 114 communicates with the I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 111 to latch the address signal before decoding. A command register 124 communicates with the I / O control circuitry 112 and the local media controller 135 to latch incoming commands.

[0047] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 111 to control them in response to addresses. In one embodiment, the local media controller 135 includes a programming manager 134 that can perform memory programming operations relative to memory device 130, as described herein.

[0048] The local media controller 135 also communicates with cache register 118. Cache register 118 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store the data while the memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 121 for transfer to memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 for output to memory subsystem controller 115; then, new data can be transferred from data register 121 back to cache register 118. Cache register 118 and / or data register 121 may form a page buffer (e.g., a portion thereof) of memory device 130. The page buffer may further include sensing devices ( Figure 2(Not shown) to sense the data status of the memory cells in the memory cell array 104, for example, by sensing the status of the data lines connected to the memory cells. The status register 122 can communicate with the I / O control circuitry system 112 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0049] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 136, and outputs data to memory subsystem controller 115 via I / O bus 136.

[0050] For example, commands can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 136 and then written to command register 224. Addresses can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 136 and then written to address register 214. Data can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. Data can then be written to data register 121 for programming memory cell array 104.

[0051] In this embodiment, cache register 118 may be omitted, and data may be written directly to data register 220. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to memory device 130 via an external device (e.g., memory subsystem controller 115).

[0052] In some implementations, additional circuitry and signals may be provided, and Figure 2The memory device 130 has been simplified. It should be understood that the reference... Figure 2 The functions of the various block components described need not be separated from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 2 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The function of a single block component. Furthermore, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations of I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0053] One or more memory devices of the memory subsystem 100 may be represented, for example, by a NAND memory device utilizing an array of transistors built on a semiconductor chip. Figure 3A As schematically illustrated, the memory cells of a memory device can be transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), having source (S) electrodes and drain (D) electrodes to allow current to flow through them. The source and drain electrodes can be connected to conductive bit lines (BLs), which can be shared by multiple memory cells. The memory device can comprise an array or memory cells connected to multiple word lines (WLs) and multiple bit lines (BLs), as shown in the diagram. Figure 4 The diagram is shown schematically. The memory device may further include circuitry for selectively coupling WL and BL to voltage sources that provide control gate and source-drain signals, as illustrated below for clarity and simplicity. Figure 4 omitted.

[0054] Refer again Figure 3A Memory cells 302 and 304 can be connected to the same bit line N and two different conductive word lines M and M+1, respectively. The memory cells may further have a control gate (CG) electrode to receive a voltage signal V. CG This controls the amount of current flowing between the source and drain electrodes. More precisely, a threshold can be used to control the gate voltage V. T (also referred to as the “threshold voltage” or simply the “threshold” in this paper), such that for V CG <V T The source-drain current may be low, but once the control gate voltage exceeds the threshold voltage, i.e., V0... CG >V T Then the current can be substantially increased. Transistors in the same memory device can be characterized by the distribution of their threshold voltages, i.e., P(V... T )=dW / dV T Therefore, dW = P(V)T )dV T This indicates that the threshold voltage of any given transistor is in the range [V]. T V T +dV T The possibilities within. For example, Figure 3B The source-drain current I is schematically shown. SD The correlation with the control gate voltages of two memory cells, such as memory cell 302 (solid line) and memory cell 304 (dashed line), which have different threshold control gate voltages.

[0055] To make the memory cell non-volatile, the cell can be further equipped with conductive islands-charge storage nodes, which can be connected through an insulating layer (in... Figure 3A The area depicted as a dashed line is electrically isolated from the control gate, source electrode, and drain electrode. It responds to an appropriately selected positive (relative to the source potential) control gate voltage V. CG The charge storage node can receive a charge Q, which can be permanently stored even after the memory cell is powered on, thus stopping the source-drain current. The charge Q can affect the threshold voltage P (V). T The distribution of Q). Typically, it is related to the distribution of uncharged charge storage nodes P(V). T In contrast, the presence of charge Q shifts the threshold voltage distribution toward higher voltages. This occurs because a stronger positive gate voltage V may be required. CG To overcome the negative potential of the charge Q at the charge storage node. If the charge sequence Q can be selectively... k (where 1≤k≤2) N If any charge Q is programmed (and then detected during a read operation) into a memory cell, the memory cell can be used as an N-bit storage unit. k Preferably, they are chosen to be sufficiently different from each other such that any two adjacent voltage distributions P(V) are such that... T Q k ) and P(V T Q k+1 ) do not overlap but are separated by valley margins, thus 2 N Distribution P(V) T Q k ) and 2 N -1 valley margin interval.

[0056] Figure 3C The diagram schematically illustrates the distribution of threshold-controlled gate voltages for a memory cell capable of storing three bits of data by programming the memory cell to at least eight charge states, which differ depending on the amount of charge on the cell's charge storage node. Figure 3C Showing 2 3-1 = 7 valley margins (VM) k 2 of the separated three-level cells (TLC) N = Threshold voltage P(V) for 8 different charge states T Q k The distribution of charge states. Therefore, it is programmed into charge state k-th (i.e., having charge Q deposited on its charge storage node). k The memory cell can store a specific combination of N bits (e.g., 0110 for N=4). This charge state Q k Valley margin VM can be detected during read operations. k Internal control gate voltage V CG Sufficient to open the cell to source-drain current while maintaining the previous valley margin VM k-1 The control gate voltage within is insufficient to open the cell to the source-drain current.

[0057] Memory devices can be classified according to the number of bits stored in each cell of the memory. For example, a single-level cell (SLC) memory has cells that can each store one bit of data (N=1). A multi-level cell (MLC) memory has cells that can each store up to two bits of data (N=2), a three-level cell (TLC) memory has cells that can each store up to three bits of data (N=3), and a four-level cell (QLC) memory has cells that can each store up to four bits of data (N=4). Generally, the operations described herein are applicable to memory devices with N bits (where N>1) of memory cells.

[0058] For example, a TLC may be able to exist in at least eight charge states Q. k One of them (where the first state can be the uncharged state Q1 = 0), its threshold voltage distribution is determined by the valley margin VM k Separating the data can be used to read data stored in memory cells. For example, if the read threshold voltage is determined to be 2 during a read operation... N Within a specific valley margin of -1, it can be determined that the memory cell is in a 2 N A specific charge state among the possible charge states. By identifying the right valley margin of the cell, the values ​​of all its N bits can be determined. The identifier of the valley margin (e.g., its coordinates, such as the location of the center and width) can be stored in the read level threshold register of the memory controller 215.

[0059] As mentioned above, the memory controller 215 can program the state of the memory cells, and then read them by setting the read threshold voltage V of the memory cells. TThis state is read by comparing it with one or more read level thresholds. The read operation can be performed after the memory cell has been placed in one of its charged states by a previous programming operation, which may include one or more programming passes. Each programming pass applies an appropriate programming voltage to a given word line to place the appropriate charge on the charge storage node of the memory cell connected to the word line.

[0060] The programming operation involves applying a sequence of programming voltage pulses to the selected word line. (See again...) Figure 3A The source (S) and drain (D) electrodes of a memory cell can be connected to a conductive bit line shared by multiple memory cells. Programming operations apply a sequence of programming voltage pulses to the control gate (CG) via the corresponding word line (WL). Each programming voltage pulse induces an electric field that pulls electrons to the charge storage node. After each programming pulse is applied to the selected word line, a verification operation can be performed by reading the memory cell to determine the threshold voltage V of the memory cell. T Has the desired value (voltage verification level) been reached? If the threshold voltage V of the memory cell... T Once the verification voltage associated with the desired state has been reached, the bit lines connected to the memory cells can be biased at the programming disable voltage, thus preventing further programming of the memory cells coupled to the bit lines, i.e., to prevent the threshold voltage V of the memory cells from being exceeded. T In response to a subsequent programming pulse applied to the selected word line, the bit is shifted upwards further.

[0061] Figure 5 The diagram schematically illustrates the three-dimensional structure of an example memory device operating according to various aspects of this disclosure. For example... Figure 5 As shown, the example memory device may include a memory cell string 500, which includes multiple memory cells 505 sharing a common pillar 540, a dielectric layer 550, and a storage layer 560. The memory cells may be electrically coupled to word lines, including dummy word lines 520 and active word lines 530. As used herein, a "dummy word line" refers to a word line with certain manufacturing defects that would prevent word lines from controlling multi-level cells (including MLCs and TLCs). Therefore, in some embodiments, dummy word lines may be used to control single-level cells. A selectable gate 510 controls the coupling of the pillar 540 to the corresponding bit line.

[0062] Figure 6 A fragment of an example memory array is shown, illustrating a memory device operating according to various aspects of this disclosure. For example... Figure 6 As shown, the memory array 606 may contain multiple memory cells arranged in rows (corresponding to conductive word lines 625) and columns (corresponding to conductive bit lines 620) of selected sub-blocks. Although Figure 6The two-dimensional structure is shown, but the systems and methods of this disclosure can also be implemented using memory arrays with various three-dimensional structures. In one embodiment, the example three-dimensional structure comprises a plurality of planes, such that each plane has Figure 6 The two-dimensional structure shown.

[0063] Each column of array 606 may contain a string of memory cells selectively connected to a common voltage source (SRC) 620. The common voltage source may be coupled to a reference voltage (e.g., "ground" (Gnd) or a power supply selectively configured to a desired voltage level). The string of memory cells may be connected in series between corresponding source-side selection transistors 630A to 630N controlled by a source-select-gate (SGS) signal 640 and corresponding drain-side selection transistors 612A to 612N controlled by a drain-select-gate (SGD) signal 615. Specifically, example memory array 606 includes selected word lines 625A and unselected word lines 625M (from...). Figure 6 Other word lines are omitted. Example memory array 606 further includes a set of bit lines 620A to 620N (from...). Figure 6 (Other bit lines omitted), the bit lines may be coupled to corresponding pillars 605A to 605N via corresponding selection transistors 612A to 612N controlled by the selected gate (SGD) signal 615.

[0064] Figure 7 Example voltage waveforms are shown applied to various portions of a memory array during programming operations performed using the systems and methods of this disclosure. In an illustrative example, the memory device controller identifies a target (selected) word line WL to be programmed via a programming operation. n One or more memory cells at the intersection point with the selected bit line.

[0065] Programming operations may involve connecting... Figure 6 The SGD and SGS signals 615 and 640 control both the drain-side and source-side gate selection, as schematically illustrated by waveforms 715 and 730. Figure 6 The unselected word line 625M is driven to a predefined voltage level V. UNSEL_WL1 As illustrated schematically by waveforms 715 and 730.

[0066] Next, the pillars 605 of both the selected and unselected sub-blocks are floated by disconnecting both the SGD and SGS signals, as illustrated schematically by waveforms 715 and 730.

[0067] Once the pillar floats Figure 6 The unselected word line 625M and / or the selected word line 625A can discharge to the predefined voltage level V. UNSEL_WL1 This causes the corresponding negative potential to appear in Figure 6On the pillar 605A of the selected sub-block, as schematically shown by waveform 735.

[0068] In some implementations, a seed voltage (e.g., V) may be applied. DD To increase the potential of the unselected subblock's support pillar 605N, thereby reducing the level of the unselected support pillar's programming prohibition stress, said level being equal to V. PGM -V UNSEL_PILLAR As illustrated in waveform 725.

[0069] Once the support floats, the voltage level V can be adjusted. PGM One or more programming voltage pulses are applied to Figure 6 The selected word line 625A is schematically shown by waveform 740. Therefore, the voltage level V of one or more programming voltage pulses applied to the selected word line 625... PGM Effectively reduce the negative potential value V of the selected sub-block support. SEL_PILLAR At the same time, the programming stress that maintains the same level is equal to V. PGM -V SEL_PILLAR And maintain the programming prohibition stress of the unselected pillar equal to V. PGM -V UNSEL_PILLAR And the programming-prohibited stress of the selected support is equal to V. PGM -V SEL_PILLAR As illustrated schematically from waveform 720 to 740.

[0070] In some implementations, in order to cut off the negative pillar potential, the virtual word line may be programmed to a high threshold voltage, for example, during the final stage of the manufacturing process of the memory device and / or after an erase operation is performed on the memory device.

[0071] In some implementations, a programming verification operation may be performed after one or more programming voltage pulses are applied. The programming verification operation may involve reading one or more memory cells to which the programming pulses have been applied in order to determine the threshold voltage V of the memory cell. T Has the desired value been reached?

[0072] Although the examples described above pertain to TLC programming algorithms, the systems and methods disclosed herein can be similarly applied to MLCs, QLCs, and other algorithms for programming memory cells capable of storing one or more bits of data.

[0073] Figure 8This is a flowchart illustrating an example method for performing memory programming operations according to some embodiments of the present disclosure. Method 800 may be performed by processing logic that may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. In some embodiments, method 800 is performed by… Figure 1 The memory subsystem controller 115 and / or local media controller 135 perform the operations. Although shown in a specific order or sequence, the order of operations may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated operations may be performed in different orders, and some operations may be performed in parallel. In addition, one or more operations may be omitted in various embodiments. Therefore, not all operations are required in every embodiment.

[0074] At operation 810, the controller implementing the method identifies one or more memory cells to be programmed. In the illustrative example, by Figure 1 The programming manager 134 implemented by the local media controller 135 can receive a request from the memory interface 113 of the memory subsystem controller 115 to perform a memory access operation on a specified memory device. In one embodiment, the memory access operation involves a programming operation to program an identified memory cell to a specified logic level. In one embodiment, the request to perform the memory access operation can identify one or more memory cells by specifying a word line and one or more bit lines, as described in more detail above.

[0075] At operation 820, the controller turns on the drain-side and source-side select gates controlled by the SGD and SGS signals, as described in more detail above.

[0076] At operation 830, the controller drives the unselected word line to a first predefined voltage level, as described in more detail above.

[0077] At operation 840, the controller disconnects the drain-side and source-side select gates controlled by the SGD and SGS signals, thereby causing the pillars of the selected and unselected subblocks to float, as described in more detail above.

[0078] At operation 850, the controller discharges the unselected word line to a second predefined voltage level, thereby causing the corresponding negative potential to appear on the pillar of the selected sub-block, as described in more detail above.

[0079] At operation 860, the controller applies a seed voltage (e.g., VDD) to the pillar of the unselected subblock, thereby reducing the level of the programming prohibition stress of the unselected pillar, as described in more detail above.

[0080] At operation 870, the controller applies one or more programming voltage pulses to the selected word line, as described in more detail above.

[0081] At operation 880, the controller performs a programming verification operation by reading the programming pulses applied to one or more memory cells to determine whether the threshold voltage VT of the memory cell has reached the desired value, as described in more detail above.

[0082] Figure 9 An example machine of computer system 900 is shown, wherein a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 900 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., run an operating system to perform corresponding...). Figure 1 (Operation of the programming manager 134). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0083] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is shown, it should also be understood that the term "machine" includes any collection of machines that individually or collectively execute (one or more) sets of instructions to perform any one or more of the methods discussed herein.

[0084] The example computer system 900 includes a processing device 902 that communicates with each other via a bus 930, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 918.

[0085] Processing device 902 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. Computer system 900 may further include a network interface device 908 for communication via network 920.

[0086] Data storage system 918 may include machine-readable storage medium 924 (also referred to as computer-readable medium, such as non-transitory computer-readable medium) storing one or more instruction sets 926 or software embodying any one or more of the methods or functions described herein. Instructions 926 may also reside wholly or at least partially within main memory 904 and / or processing device 902 during execution by computer system 900, which also constitute machine-readable storage medium. Machine-readable storage medium 924, data storage system 918, and / or main memory 904 may correspond to... Figure 1 The memory subsystem 110.

[0087] In one embodiment, instruction 926 includes instructions for implementing the corresponding Figure 1 The instructions for the function of the programming manager 134. Although the machine-readable storage medium 924 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions that are executed by a machine and causing a machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0088] Some parts of the previously described algorithms and symbolic representations of operations on data bits in computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and generally are, considered as a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for common use, it has proven convenient sometimes to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0089] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of a computer system into other data representing physical quantities similarly represented in the memory or registers or other such information storage systems of a computer system.

[0090] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0091] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to execute the methods. Structures for various such systems will be presented as described below. Furthermore, embodiments of this disclosure are described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0092] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0093] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory device comprising: A memory array comprising multiple memory cells electrically coupled to multiple word lines and multiple bit lines; as well as A controller, coupled to the memory array, performs operations including the following: Identify one or more memory cells for performing memory programming operations, wherein the memory cells are electrically coupled to a target word line and one or more target bit lines; Disconnect the drain-side select gate and the source-side select gate of the memory array, wherein a corresponding negative potential is presented on the selected pillar of the memory array in response to discharging the unselected word line of the memory array to a predefined voltage level. Charge the virtual word lines of the memory array to a predefined threshold voltage; as well as One or more programming voltage pulses are applied to the target word line.

2. The memory device of claim 1, wherein the operation further comprises: A programming verification operation is performed relative to one or more memory cells.

3. The memory device of claim 1, wherein disconnecting the drain-side select gate and the source-side select gate of the memory array causes the pillars of the memory array to float.

4. The memory device of claim 1, wherein the operation further comprises: A seed voltage is applied to the unselected sub-blocks of the memory array.

5. The memory device of claim 1, wherein the one or more programming voltage pulses are executed at an increased programming voltage level.

6. A computer-readable non-transitory storage medium comprising executable instructions, said executable instructions causing the controller, when executed by a controller managing a memory array comprising a plurality of memory cells, to: Identify a memory array, the memory array comprising a plurality of memory cells, one or more memory cells for performing memory programming operations, wherein the memory cells are electrically coupled to a target word line and one or more target bit lines; Disconnect the drain-side select gate and the source-side select gate of the memory array, wherein a corresponding negative potential is presented on the selected pillar of the memory array in response to discharging the unselected word line of the memory array to a predefined voltage level. Charge the virtual word lines of the memory array to a predefined threshold voltage; as well as One or more programming voltage pulses are applied to the target word line.

7. The computer-readable non-transitory storage medium of claim 6, further comprising executable instructions that, when executed by the controller, cause the controller to: A programming verification operation is performed relative to one or more memory cells.

8. The computer-readable non-transitory storage medium of claim 6, wherein disconnecting the drain-side select gate and the source-side select gate of the memory array causes the pillars of the memory array to float.

9. The computer-readable non-transitory storage medium of claim 6, further comprising executable instructions that, when executed by the controller, cause the controller to: A seed voltage is applied to the unselected sub-blocks of the memory array.

10. The computer-readable non-transitory storage medium of claim 6, wherein the one or more programming voltage pulses are executed at an increased programming voltage level.

11. A method for performing memory operations, comprising: A controller that manages a memory array comprising multiple memory cells identifies one or more memory cells for performing memory programming operations, wherein the memory cells are electrically coupled to a target word line and one or more target bit lines; Disconnect the drain-side select gate and the source-side select gate of the memory array, wherein a corresponding negative potential is presented on the selected pillar of the memory array in response to discharging the unselected word line of the memory array to a predefined voltage level. Charge the virtual word lines of the memory array to a predefined threshold voltage; as well as One or more programming voltage pulses are applied to the target word line.

12. The method of claim 11, further comprising: A programming verification operation is performed relative to one or more memory cells.

13. The method of claim 11, wherein disconnecting the drain-side select gate and the source-side select gate of the memory array causes the pillars of the memory array to float.

14. The method of claim 11, further comprising: A seed voltage is applied to the unselected sub-blocks of the memory array.

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