A method and structure for constructing a rewiring layer
By using a step-by-step etching method with a titanium/copper seed layer on the same wiring layer, the problems of increased package thickness and corrosion contamination in the redistribution layer construction were solved, thereby improving electrical performance and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-26
- Publication Date
- 2026-04-03
AI Technical Summary
Traditional redistribution layer construction methods lead to increased package thickness and wet corrosion contamination problems. In particular, when redistributing on the same layer, redistribution patterns of different materials and sizes are prone to corrosion discrepancies or abnormal appearances, affecting electrical performance and reliability.
A titanium/copper seed layer is used to arrange the first and second layers of wiring patterns on the same wiring layer. The copper and titanium layers are removed step by step using different etchants. The corrosion resistance of the titanium layer is used to protect the first layer of wiring patterns and avoid contamination and abnormalities.
It enables the arrangement of rewiring patterns with different heights, materials, and areas on the same wiring layer, solving the problems of increased package thickness and corrosion contamination, and ensuring electrical performance and reliability.
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Figure CN115295436B_ABST
Abstract
Description
Technical Field
[0001] This invention generally relates to the field of semiconductor packaging technology. Specifically, this invention relates to a method and structure for constructing a redistribution layer. Background Technology
[0002] In the semiconductor industry, the integration density of various electronic components is typically increased by continuously reducing the minimum feature size, allowing more electronic components to be integrated within a given area.
[0003] Redistribution layers (RDLs) can be used in various semiconductor packaging structures to reduce the minimum feature size. A redistribution layer refers to the interface between the chip and the package structure in a flip-chip assembly. Through a redistribution layer, the positions of the aluminum solder pads on the chip can be rearranged to meet the minimum solder ball spacing requirements and to arrange the new solder pads in an array. Furthermore, to reduce package size and thickness, redistribution lines of different sizes and materials can be fabricated on the same substrate to cover the height and material differences between the two redistribution layers, resulting in a complete and dimensionally accurate secondary redistribution structure.
[0004] However, traditional redistribution methods typically involve placing redistribution structures of different heights and materials on different stacks, resulting in a thicker package. Performing two photolithography and electroplating processes on the same seed layer to place the wiring on the same layer presents a significant challenge to the seed layer wet etching process. This is because the type of etching solution and etching rate used in wet etching differ for redistribution structures of different sizes and materials. The selection of etching solutions can influence each other, leading to contamination or etching of one layer of wiring, resulting in dimensional inconsistencies or abnormal appearances. In severe cases, this can cause electrical performance and reliability requirements to fail. Summary of the Invention
[0005] To at least partially solve the problems in the prior art where wiring on different stack-ups leads to increased package thickness and corrosion contamination is easily generated when wiring is performed multiple times on the same layer, the present invention proposes a redistribution layer construction method, comprising the following steps:
[0006] A first titanium / copper seed layer is disposed on the substrate;
[0007] Arrange a first rewiring pattern on the first titanium / copper seed layer;
[0008] Remove the first titanium / copper seed layer located on the non-patterned area of the substrate;
[0009] A second titanium / copper seed layer is disposed on the substrate on which the first wiring pattern is arranged;
[0010] A second wiring pattern is arranged on the second titanium / copper seed layer;
[0011] Remove the copper layer of the second titanium / copper seed layer located in the non-graphic area and above the first rewiring pattern; and
[0012] Remove the titanium layer of the second titanium / copper seed layer located in the non-graphic area and above the first rewiring pattern.
[0013] In one embodiment of the present invention, the substrate is specified to include a silicon substrate, a germanium substrate, a gallium nitride substrate, a gallium arsenide substrate, or an indium phosphide substrate.
[0014] In one embodiment of the present invention, the first and second titanium / copper seed layers are disposed on the substrate by physical vapor deposition.
[0015] In one embodiment of the present invention, a first super-wiring pattern is arranged on the first titanium / copper seed layer by photolithography and electroplating, and a second super-wiring pattern is arranged on the second titanium / copper seed layer.
[0016] In one embodiment of the present invention, the first overlay pattern and the second overlay pattern are different in at least one of the following aspects: height, material, and surface area.
[0017] In one embodiment of the present invention, the first wiring pattern and the second wiring pattern are arranged on the same wiring layer.
[0018] In one embodiment of the invention, the first and second titanium / copper seed layers are removed by desizing and wet etching.
[0019] In one embodiment of the present invention, the removal of the second titanium / copper seed layer by wet etching includes:
[0020] The copper layer of the second titanium / copper seed layer is etched using a first etchant, wherein the titanium layer of the second titanium / copper seed layer is configured such that the first rewiring pattern is isolated from the first etchant; and
[0021] The titanium layer of the second titanium / copper seed layer is etched by a second etchant.
[0022] The present invention also proposes a redistribution layer structure, which is constructed using the redistribution layer construction method, the redistribution layer structure comprising:
[0023] Substrate;
[0024] A first wiring pattern, which is connected to the substrate via a first titanium / copper seed layer; and
[0025] The second wiring pattern is connected to the substrate through a second titanium / copper seed layer, wherein the second wiring pattern and the first wiring pattern are located on the same wiring layer.
[0026] In one embodiment of the present invention, it is specified that in the redistribution layer structure, the first redistribution pattern and the second redistribution pattern are different from each other in at least one of the following aspects: height, material, and surface area.
[0027] This invention is based on the inventors' insight that traditional redistribution layer construction methods arrange different redistribution patterns on different wiring layers, significantly increasing the thickness of the package structure. Furthermore, if different redistribution patterns are arranged on the same wiring layer, the type of etching solution and etching rate used in wet etching differ for redistribution patterns of different sizes and materials, easily leading to contamination or corrosion of the redistribution patterns, resulting in dimensional inconsistencies or abnormal appearances. In severe cases, this can cause electrical performance and reliability to fail to meet requirements. The inventors discovered that the excellent corrosion resistance of titanium metal in the titanium / copper seed layer can be utilized. After the first and second redistribution patterns are arranged through secondary sputtering, photolithography, and electroplating, the copper layer of the second titanium / copper seed layer can be etched first with a first etching solution. At this point, the titanium layer of the second titanium / copper seed layer isolates the first redistribution pattern from the first etching solution, protecting it. Then, the titanium layer of the second titanium / copper seed layer is etched with a second etching solution, thus effectively solving the aforementioned problems in the prior art.
[0028] The present invention has at least the following beneficial effects: The present invention proposes a method and structure for constructing a redistribution layer, wherein first and second redistribution patterns with different heights, materials and surface areas can be arranged on the same redistribution layer by means of secondary sputtering, photolithography and electroplating, and the copper layer and titanium layer are removed stepwise by means of the corrosion resistance of the titanium layer of the titanium / copper seed layer during the wet etching process, thereby avoiding the pollution or appearance abnormality problems that wet etching may cause to the redistribution pattern. Attached Figure Description
[0029] To further illustrate the advantages and other features of the various embodiments of the present invention, a more specific description of the embodiments of the present invention will be presented with reference to the accompanying drawings. It is understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by the same or similar reference numerals for clarity.
[0030] Figure 1 A flowchart illustrating a redistribution layer construction method according to one embodiment of the present invention is shown.
[0031] Figures 2A-2FA schematic diagram illustrating the construction process of a rewiring layer structure in one embodiment of the present invention is shown.
[0032] Figure 3 A schematic diagram of a redistribution layer structure is shown in one embodiment of the present invention. Detailed Implementation
[0033] It should be noted that the components in the various figures may be shown exaggeratedly for illustrative purposes and are not necessarily to scale. In each figure, the same reference numerals are used for components that are identical or have the same function.
[0034] In this invention, unless otherwise specified, "arranged on," "arranged above," and "arranged on" do not exclude the possibility of an intermediate element between them. Furthermore, "arranged on or above" merely indicates the relative positional relationship between two components, and in certain cases, such as when the product orientation is reversed, it can also be converted to "arranged below or under," and vice versa.
[0035] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.
[0036] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.
[0037] It should also be noted that, in the embodiments of the present invention, only a portion of the components or parts may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, necessary components or parts can be added as needed for specific scenarios. Furthermore, unless otherwise stated, features in different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment can replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment will also fall within the scope of disclosure or description of this application.
[0038] It should also be noted that, within the scope of this invention, the terms "same," "equal," and "equal to" do not imply that the two values are absolutely equal, but rather allow for a certain reasonable margin of error. In other words, the terms also encompass "substantially the same," "substantially equal," and "substantially equal to." Similarly, in this invention, the directional terms "perpendicular to," "parallel to," etc., also encompass the meanings of "substantially perpendicular to" and "substantially parallel to."
[0039] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.
[0040] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0041] Figure 1 A flowchart illustrating a redistribution layer construction method according to one embodiment of the present invention is shown. Figure 1 As shown, the method may include the following steps:
[0042] Step 101: Deposit a first titanium / copper seed layer 202 on the substrate 201.
[0043] Step 102: Arrange the first rewiring pattern 203 on the first titanium / copper seed layer 202.
[0044] Step 103: Remove the first titanium / copper seed layer 202 located on the non-patterned area of the substrate 201.
[0045] Step 104: Deposit a second titanium / copper seed layer 204 on the substrate 201 on which the first rewiring pattern 203 is arranged.
[0046] Step 105: Arrange a second rewiring pattern 205 on the second titanium / copper seed layer 204.
[0047] Step 106: Remove the copper layer 2041 of the second titanium / copper seed layer 204 located in the non-graphic area and above the first rewiring pattern 203.
[0048] Step 107: Remove the titanium layer 2042 of the second titanium / copper seed layer 204 located in the non-graphic area and above the first rewiring pattern 203.
[0049] The following describes the redistribution layer construction method in detail with reference to the redistribution layer structure in a specific embodiment.
[0050] Figure 2A - This diagram illustrates the construction process of a rewiring layer structure in one embodiment of the present invention.
[0051] In step 101, as Figure 2A As shown, the substrate 201 can be an integrated circuit wafer (IC wafer) with silicon oxide on its surface. The substrate 201 can be a silicon (Si) substrate, or it can be a substrate of any other material, such as a variety of semiconductor materials, such as germanium (Ge), gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), etc. Alternatively, the substrate can also be made of electrically non-conductive materials, such as glass, plastic, or sapphire wafers.
[0052] The first titanium / copper (Ti / Cu) seed layer 202 can be sputtered onto the substrate 201 using a physical vapor deposition (PVD) method. The titanium layer of the first titanium / copper seed layer 202 is disposed on the side in contact with the substrate 201, and the copper layer of the first titanium / copper seed layer is disposed on the titanium layer. The titanium layer of the first titanium / copper seed layer can serve as an adhesion layer and an anti-diffusion layer during the redistribution layer construction process.
[0053] In step 102, as Figure 2B As shown, the first redistribution pattern 203 can be arranged on the first titanium / copper seed layer 202 by photolithography and electroplating.
[0054] In step 103, as Figure 2C As shown, the first titanium / copper seed layer 202, located in the non-patterned area on the substrate 201, can be removed by resist removal and wet etching. Here, the term "non-patterned area" refers to an area on the substrate where no redistribution pattern is disposed.
[0055] In step 104, as Figure 2D As shown, the second titanium / copper seed layer 204 can be sputtered a second time on the substrate 201 on which the first redistribution pattern 203 is arranged by physical vapor deposition.
[0056] In step 105, as Figure 2E As shown, the second redistribution pattern 205 can be arranged on the second titanium / copper seed layer 204 by photolithography and electroplating, and the second titanium / copper seed layer 204 can be exposed by removing the resist.
[0057] The first rewiring pattern 202 and the second rewiring pattern 205 are arranged on the same wiring layer, and the height, material and surface area of the second rewiring pattern 205 and the first rewiring pattern 203 can be different. This is because when arranging the second rewiring pattern 205, the second rewiring pattern 205 and the first rewiring pattern 203 are isolated from each other by the second titanium / copper seed layer 204 and will not affect each other. For example, the second rewiring pattern 205 can be a copper structure with added tin-silver alloy (SnAg) or other structures.
[0058] In step 106, as Figure 2F As shown, during seed layer etching, the copper layer of the second titanium / copper seed layer 204, which is located in the non-pattern area and above the first rewiring pattern 203, is first removed by wet etching. At this time, the titanium layer of the second titanium / copper seed layer 204 acts as a protective layer to protect the first rewiring pattern 203.
[0059] In step 107, the titanium layer of the second titanium / copper seed layer 204 located in the non-patterned area and above the first redistribution pattern 203 can be removed by wet etching to obtain the desired result. Figure 3 The redistribution layer structure is shown.
[0060] like Figure 3 As shown, the redistribution layer structure may include a substrate 201, a first redistribution pattern 202, and a second redistribution pattern 205, wherein the first redistribution pattern 202 and the second redistribution pattern 205 are connected to the substrate 201 through a first titanium / copper seed layer 202 and a second titanium / copper seed layer 204. The first redistribution pattern 202 and the second redistribution pattern 205 are arranged on the same redistribution layer, and the height, material, and size of the first redistribution pattern 202 and the second redistribution pattern 205 may be different.
[0061] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.
Claims
1. A method for constructing a redistribution layer, characterized in that, Includes the following steps: A first titanium / copper seed layer is disposed on the substrate; Arrange a first rewiring pattern on the first titanium / copper seed layer; Remove the first titanium / copper seed layer located on the non-patterned area of the substrate; A second titanium / copper seed layer is disposed on the substrate on which the first wiring pattern is arranged; A second wiring pattern is arranged on the second titanium / copper seed layer; Remove the copper layer of the second titanium / copper seed layer located in the non-graphic area and above the first rewiring pattern; and Remove the titanium layer of the second titanium / copper seed layer located in the non-graphic area and above the first rewiring pattern. The first and second wiring patterns differ in at least one of the following: height, material, and surface area. The first and second wiring patterns are arranged on the same wiring layer.
2. The rewiring layer construction method according to claim 1, characterized in that, The substrate includes a silicon substrate, a germanium substrate, a gallium nitride substrate, a gallium arsenide substrate, or an indium phosphide substrate.
3. The redistribution layer construction method according to claim 1, characterized in that, The first and second titanium / copper seed layers are deposited on the substrate by physical vapor deposition.
4. The redistribution layer construction method according to claim 1, characterized in that, A first layer of wiring patterns is formed on the first titanium / copper seed layer by photolithography and electroplating, and a second layer of wiring patterns is formed on the second titanium / copper seed layer.
5. The redistribution layer construction method according to claim 1, characterized in that, The first and second titanium / copper seed layers were removed by degumming and wet etching.
6. The redistribution layer construction method according to claim 5, characterized in that, The removal of the second titanium / copper seed layer by wet etching includes: The copper layer of the second titanium / copper seed layer is etched using a first etchant, wherein the titanium layer of the second titanium / copper seed layer is configured such that the first rewiring pattern is isolated from the first etchant; and The titanium layer of the second titanium / copper seed layer is etched by a second etchant.
7. A redistribution layer structure, characterized in that, The redistribution layer structure is constructed using the redistribution layer construction method according to any one of claims 1-6, wherein the redistribution layer structure includes: Substrate; A first wiring pattern, which is connected to the substrate via a first titanium / copper seed layer; and The second wiring pattern is connected to the substrate through a second titanium / copper seed layer, wherein the second wiring pattern and the first wiring pattern are located on the same wiring layer.
8. The redistribution layer structure according to claim 7, characterized in that, The first wiring pattern differs from the second wiring pattern in at least one of the following aspects: height, material, and surface area.
Citation Information
Patent Citations
Manufacture of multilayer printed wiring board
JP1999307943A
Semiconductor package having a variable redistribution layer thickness
US20170170111A1