Integrated circuit device and method of forming the same

Abstract

An integrated circuit device and a method of forming the same are provided. The method includes forming a transistor on a front side of a substrate, forming an inner connection structure on the transistor, depositing a first transition metal layer on the inner connection structure, performing a plasma treatment to transform the first transition metal layer into a first transition metal dichalcogenide layer, forming a dielectric layer on the first transition metal dichalcogenide layer, forming a first gate electrode on the dielectric layer and a first portion of the first transition metal dichalcogenide layer, and forming a first source contact and a first drain contact connected to second and third portions of the first transition metal dichalcogenide layer, respectively, the first portion of the first transition metal dichalcogenide layer being between the second and third portions of the first transition metal dichalcogenide layer.

Description

Technical Field

[0001] This disclosure relates to integrated circuit devices and methods for their fabrication. Background Technology

[0002] The semiconductor industry has experienced rapid growth as the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) continues to improve. In most cases, improvements in integration density stem from the repeated reduction of the smallest feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] According to some embodiments disclosed herein, a method for forming an integrated circuit device is provided. The method includes depositing a first transition metal layer on the front side of a substrate; performing a plasma treatment to transform the first transition metal layer into a first transition metal disulfide layer; forming a dielectric layer on the first transition metal disulfide layer; forming a first gate electrode on the dielectric layer and a first portion of the first transition metal disulfide layer; and forming a first source contact and a first drain contact, respectively connecting a second and a third portion of the first transition metal disulfide layer, wherein the first portion of the first transition metal disulfide layer is located between the second and third portions of the first transition metal disulfide layer.

[0004] According to some embodiments of the present disclosure, a method for forming an integrated circuit device is provided. The method includes forming a non-insulating structure on a front side of a substrate; and forming a conductive structure on the non-insulating structure, wherein forming the conductive structure includes: depositing a transition metal layer on the non-insulating structure; performing a plasma treatment to transform the transition metal layer into a transition metal disulfide layer; and depositing a metal material on the transition metal disulfide layer.

[0005] According to some embodiments disclosed herein, an integrated circuit device includes a substrate, a first transition metal disulfide layer, a dielectric layer, a first gate electrode, a first source contact, and a first drain contact. The first transition metal disulfide layer is located above the substrate, wherein the surface roughness of the first transition metal disulfide layer is greater than 0.5 nm and less than 1 nm. The dielectric layer is above the first transition metal disulfide layer. The first gate electrode is located above the dielectric layer and a first portion of the first transition metal disulfide layer. The first source contact and the first drain contact are respectively connected to a second portion and a third portion of the first transition metal disulfide layer, with the first portion of the first transition metal disulfide layer located between the second and third portions of the first transition metal disulfide layer. Attached Figure Description

[0006] The various features disclosed herein can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In practice, the dimensions of the features may be arbitrarily increased or decreased for clarity of description.

[0007] Figure 1A This is a side view schematic diagram of an apparatus for forming a transition metal dichalcogenide (TMDC) layer according to a partial embodiment of the present disclosure;

[0008] Figure 1B exhibit Figure 1A A three-dimensional view of a part of the equipment;

[0009] Figure 2 This is a flowchart of a method for forming a TMDC layer according to an embodiment of this disclosure;

[0010] Figures 3 to 6A A method for forming a TMDC layer according to a partial embodiment of the present disclosure is shown;

[0011] Figure 6B A single-layer schematic diagram of an example TMDC layer according to a partial example implementation is shown;

[0012] Figure 7A This is a graph showing the relationship between electronic temperature and gas temperature and pressure according to a partial embodiment of this disclosure;

[0013] Figure 7B The temperature of the process chamber of an apparatus for forming a TMDC layer according to a partial embodiment of this disclosure is shown;

[0014] Figure 8A and Figure 8B Raman spectra of a sulfided molybdenum layer and a sulfided tungsten layer according to certain embodiments of this disclosure are shown respectively.

[0015] Figures 9A to 9E Raman spectra of molybdenum layers sulfurized on various substrates and at different operating powers according to some embodiments of the present disclosure are shown.

[0016] Figure 9F Demonstrating operating power and Figure 9E The relationship between the full width at half maximum (FWHM);

[0017] Figures 10A to 10C Raman spectra of molybdenum layers sulfurized on various substrates and at different deposition times according to some embodiments of the present disclosure are shown.

[0018] Figure 11A and Figure 11B X-ray photoelectron spectroscopy (XPS) data of molybdenum (Mo) and sulfur (S) in layers obtained according to certain embodiments of this disclosure are shown respectively.

[0019] Figure 12A and Figure 12B An atomic force microscope (AFM) is used to demonstrate MoS2 layers obtained on various substrates according to certain embodiments of the present disclosure.

[0020] Figure 13A and Figure 13B AFM of a molybdenum layer on a dielectric layer before plasma treatment and a corresponding MoS2 layer on the dielectric layer after plasma treatment are shown respectively according to some embodiments of the present disclosure.

[0021] Figure 14 This is a side view schematic diagram of an apparatus for forming a TMDC layer according to a partial embodiment of the present disclosure;

[0022] Figure 15 This is a side view schematic diagram of an apparatus for forming a TMDC layer according to a partial embodiment of the present disclosure;

[0023] Figure 16 This is a side view schematic diagram of an apparatus for forming a TMDC layer according to a partial embodiment of the present disclosure;

[0024] Figure 17A and Figure 17B This is a flowchart of a method for forming an integrated circuit device according to some embodiments of the present disclosure;

[0025] Figures 18 to 35 A method for forming an integrated circuit device according to a partial embodiment of the present disclosure is illustrated;

[0026] Figure 36 This is a flowchart of a method for forming an integrated circuit device according to some embodiments of the present disclosure;

[0027] Figures 37 to 43 A method for forming an integrated circuit device according to a partial embodiment of the present disclosure is illustrated.

[0028] [Symbol Explanation]

[0029] 100: Equipment

[0030] 110: Process Chamber

[0031] 110I: Air Intake

[0032] 110O: Air outlet

[0033] 110E: Area

[0034] 110T: Temperature range

[0035] 112, 114: Partial

[0036] 120: Plasma reactor

[0037] 122: Power Supply

[0038] 130: Substrate support

[0039] 130T: Groove

[0040] 130W: Width

[0041] 132: Base

[0042] 134: Emphasize the edge

[0043] 140, 140P, 140L, 140G: Containers

[0044] 152, 154: Gas source

[0045] 160, 160P, 160L: Heating device

[0046] 172: Vacuum Pump

[0047] 174: Well

[0048] 180: Controller

[0049] 182: Processor

[0050] 184: Computer-readable media

[0051] 186: Input / Output Interface

[0052] 200, 200P, 200L, 200G: Precursors

[0053] 300: Floor

[0054] 300M: Transition metal atom

[0055] 300X: Chalcogenide atom

[0056] 402: Substrate

[0057] 403: Semiconductor protrusions, fins

[0058] 404: Device

[0059] 404G: Gate structure

[0060] 404GD: Dielectric layer

[0061] 404GM: Metallic layer

[0062] 404SD: Source / Drain Region

[0063] 404SP: Spacer

[0064] 405: Shallow trench isolation area

[0065] 406: Internal Connection Structure

[0066] 406I: Inner Connector Layer

[0067] 406D: Interlayer dielectric layer

[0068] 406M: Conductivity characteristics

[0069] 406E: Etching Stop Layer

[0070] 412: Contact plug

[0071] 420: First metal thin film

[0072] 422: First metal layer

[0073] 422': TMDC layer

[0074] 422SD: Source / Drain Region

[0075] 422C: Passage Area

[0076] 430: Second metal thin film

[0077] 432: Second metal layer

[0078] 432': TMDC layer

[0079] 432SD: ​​Source / Drain Region

[0080] 432C: Passage Area

[0081] 450: Dielectric layer

[0082] 460: Gate electrode layer

[0083] 462, 464: Gate electrodes

[0084] 470a: Conductive filler material

[0085] 470b: Liner

[0086] 472: Contact

[0087] 474: Conductive plug

[0088] 490: Internal connection structure

[0089] 490I: Inner Connector Layer

[0090] 490D: Dielectric layer

[0091] 490M: Conductive material

[0092] 490Ma: Conductive filler material

[0093] 490Mb: Liner

[0094] 490M': Conductivity characteristics

[0095] 490E: Etching Stop Layer

[0096] 510: Metallic film

[0097] 510': TMDC layer

[0098] 510”: Barrier layer

[0099] 520: Conductive filler material

[0100] 520': Conductivity characteristics

[0101] P1: Plasma

[0102] W: Substrate, wafer

[0103] WF: front

[0104] WB: Back

[0105] TM: Metal layer

[0106] TM': TMDC layer

[0107] CS: Gas Channel

[0108] L1: Height

[0109] WW: Width

[0110] V11, V12, V21, V22, V3, V4, V5, V6, V7, V8, V91, V92: Valves

[0111] MFC1, MFC2, MFC3, MFC4, MFC5: Controllers

[0112] PG: Pressure gauge

[0113] X, Y: Direction

[0114] CG: Airflow

[0115] M: Method

[0116] S1, S2, S3, S4: Steps

[0117] P s , P at :pressure

[0118] E 1 2g A 1g Peak

[0119] D EA : distance

[0120] MA: Method

[0121] AS1, AS2, AS3, AS4: Steps

[0122] ILD0, ILD X Interlayer dielectric layer

[0123] GS1, GS2: Gate Structure

[0124] O1, O2, O3, O3', O4: Open

[0125] OT: Groove section

[0126] OV: Through-hole portion

[0127] T1, T2: Transistors

[0128] MB: Method

[0129] BS1, BS2, BS3, BS4, BS5, BS6, BS7: Steps Detailed Implementation

[0130] The following disclosure provides numerous different implementations or embodiments for carrying out various features of the provided subject matter. Specific embodiments of components and configurations are described below to simplify this disclosure. These are, of course, merely embodiments and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various implementations and / or configurations discussed.

[0131] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s) or feature(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive symbols used herein can be interpreted similarly. As used herein, “about,” “approximately,” “roughly,” “essentially,” or “substantially” may mean within 20%, 10%, or 5% of a given value or range. The numerical values ​​given herein are approximate, meaning that the terms “about,” “approximately,” “roughly,” “essentially,” or “substantially” can be inferred even if not explicitly stated otherwise.

[0132] This disclosure relates to a method for forming a large-area transition metal dichalcogenide (TMDC) material. TMDC materials exhibit high channel mobility, high current on / off ratio, and good sub-threshold swing. Exemplary TMDC materials may include MoS2, WS2, etc. In some embodiments, TMDC can serve as a channel layer in a transistor. In some alternative embodiments, TMDC can serve as a barrier layer between a metal feature and a dielectric layer. Developing a method for forming large-area TMDC materials can more easily facilitate the fabrication of integrated circuit (IC) devices incorporating TMDC materials.

[0133] Figure 1AThis is a side view schematic diagram of an apparatus 100 for forming a transition metal dichalcogenide layer according to some embodiments of the present disclosure. In some embodiments, apparatus 100 may be referred to as a plasma-enhanced chemical vapor deposition (PECVD) system. In a further partial embodiment, apparatus 100 may be referred to as a microwave plasma chemical vapor deposition (MPCVD) system. Apparatus 100 includes a process chamber 110, a plasma reactor 120, a substrate support 130, a container 140, gas sources 152 and 154, a heating device 160, a vacuum pump 172, and a controller 180.

[0134] The process chamber 110 may be referred to as a processing tube. The process chamber 110 is made of a material such as quartz, which provides a non-reactive environment that will sustain plasma generation. In addition to quartz, other materials including alumina, glass, etc., can also be used to manufacture the process chamber 110.

[0135] Plasma reactor 120 is associated with power supply 122 to generate plasma P1 within process chamber 110. Power supply 122 may be a microwave source power supply that generates microwaves, where microwaves can refer to electromagnetic waves with frequencies higher than 300 MHz. In some embodiments, microwaves may refer to the ultra-high frequency (UHF) portion of the radio frequency (RF) spectrum, for example, in the range from approximately 2.4 GHz to approximately 2.5 GHz, such as at approximately 2.45 GHz. Since plasma P1 is microwave plasma generated using microwaves, plasma reactor 120 may be referred to as a microwave plasma reactor. For example, plasma reactor 120 may be a cavity, used as a resonator, composed of a metallic structure that confines the electromagnetic field to the microwave region of the spectrum. The metallic structure may be hollow or filled with a dielectric material. Microwaves bounce back and forth between the cavity walls. At the cavity's resonant frequency, they are amplified to form standing waves within the cavity.

[0136] In this embodiment, portion 112 of process chamber 110 is surrounded by plasma reactor 120, while portion 114 of process chamber 110 is not surrounded by plasma reactor 120, wherein portion 114 is in fluid communication with portion 112. With this configuration, the plasma density in portion 112 of process chamber 110 is higher than the plasma density in portion 114 of process chamber 110. In some alternative embodiments, plasma reactor 120 may surround portions 112 and 114 of process chamber 110, such that the plasma density in portion 114 is equal to the plasma density in portion 112.

[0137] A substrate holder 130 is placed in portion 112 of the process chamber 110 and supports the substrate W. The substrate holder 130 can be made of a material such as quartz, which is inactive to plasma P1. Other materials besides quartz, including alumina, glass, etc., can also be used to manufacture the substrate holder 130. In some embodiments, the substrate holder 130 can be a crucible. In this embodiment, the substrate W may include a transition metal layer (not shown) facing the substrate holder 130. For example, the transition metal layer may include Mo, W, Pd, Pt, the like, or combinations thereof.

[0138] In some embodiments, the chalcogenide precursor 200 is stored in a container 140, which is placed in portion 114 of the process chamber 110. The container 140 may be made of a material inert to plasma P1, such as quartz. Other materials besides quartz, including alumina, glass, etc., may also be used to manufacture the container 140. In some embodiments, the container 140 may be a crucible. In this embodiment, the chalcogenide precursor 200 may be stored in solid form. For example, the chalcogenide precursor 200 may be one or more chalcogenide blocks in a solid form with a fixed shape. Chalcogenide flakes may be sulfur (S) flakes, selenium (Se) flakes, tellurium (Te) flakes, the like, or combinations thereof. In some other embodiments, the chalcogenide precursor 200 may be chalcogenide powder in a solid form without a fixed shape. Chalcogenide powder may be S powder, Se powder, Te powder, the like, or combinations thereof. In some alternative embodiments, the chalcogenide precursor 200 may be stored in liquid or gaseous form. For example, the chalcogen precursor 200 may comprise chalcogen liquids, such as C2H6S, SeF4, etc., and / or chalcogen gases, such as H2S, SeF6, CH4S, WF6, etc. These chalcogen powders, liquids, and gases may be stored in a container 140 located within a portion 114 of the process chamber 110 or in other containers outside the portion 114 of the process chamber 110, which will be subsequently... Figures 14 to 16 As shown in the figure. In some alternative embodiments, the chalcogenide precursor 200 may comprise a combination of two or three of the following: chalcogenide solid (bulk or powder), chalcogenide liquid, and chalcogenide gas.

[0139] In this embodiment, the process chamber 110 has an inlet 110I and an outlet 110O, wherein portions 112 and 114 of the process chamber 110 are located between the inlet 110I and the outlet 110O. Portion 114 of the process chamber 110 may be closer to the inlet 110I than portion 112 of the process chamber 110. One or more plasma gas sources 152 and 154 are fluidly connected to the inlet 110I. For example, plasma gas sources 152 and 154 may provide CH4, Ar, and H2. In some embodiments, gas source 152 is an H2 gas source, and gas source 154 is an Ar gas source. Mass flow controllers (MFCs) MFC1 and MFC2, or other suitable flow controllers, may be used to control the flow rate of gas from gas sources 152 and 154 to the process chamber 110. Various valves V11, V12, V21, V22 and V3 can be used to control the gas pressure in the process chamber 110.

[0140] A heating element 160, such as a heating band, may surround a portion 114 of the process chamber 110. The heating element 160 may be connected to a temperature controller. Under the control of the temperature controller, heating of the heating element 160 may melt the sulfide precursor 200 and produce an appropriate amount of gaseous sulfide-containing precursor. For example, in a partial embodiment where the sulfide precursor 200 contains sulfur (whose melting point is approximately 120°C), the temperature of the heating element 160 may be in the range of approximately 120°C to approximately 200°C. If the temperature of the heating element 160 is too low, the sulfur may not melt, and almost no sulfur-containing precursor will be produced. If the temperature of the heating element 160 is too high, the sulfur may melt too quickly, evaporate and be consumed too rapidly, which may result in high costs.

[0141] In some embodiments, vacuum pump 172 is fluidly connected to the outlet 110O of process chamber 110, thereby extracting gas from process chamber 110. A backing trap 174 may be used in the vacuum line from outlet 110O to vacuum pump 172 to prevent pumped gas from flowing back into process chamber 110. In some embodiments, a pressure gauge PG may be used in the vacuum line from outlet 110O to backing trap 174 and vacuum pump 172 to monitor the pressure in process chamber 110. Additional vacuum components may be used appropriately depending on the specific application. Furthermore, valve V4 and one or more vacuum control valves V5 may be used to control the gas pressure in process chamber 110.

[0142] In some embodiments, controller 180 is connected to mass flow controllers MFC1 and MFC2, valves V11, V12, V21, V22, V3, V4, vacuum control valve V5, plasma reactor 120 and power supply 122, temperature controller for heating device 160, and other suitable system components for operating device 100. In some embodiments, fewer or more components may be coupled to controller 180. Controller 180 may include processor 182, computer-readable media 184, and input / output (I / O) interface 186. Processor 182 is used to perform calculations related to controlling at least some of the vacuum pressure, gas flow rate, plasma generation, heating temperature, and other system parameters. Computer-readable media 184 (also referred to as a database or memory) is coupled to processor 182 to store data used by the processor and other system components. Using processor 182, computer-readable media 184, and I / O interface 186, a user can operate the system to form the TMDC layer described above.

[0143] Processor 182 may include special-purpose circuitry, an ASIC, combinational logic, other programmable processors, combinations thereof, etc. Processor 182 can execute instructions and data. For example, processor 182 executes at least a portion of the instructions of the method according to this disclosure in software, firmware, and / or hardware. Computer-readable medium 184 may include a hard disk drive, flash memory, floppy disk drive together with associated removable media, optical disk drive, removable media cartridge, and other similar storage media. Computer-readable medium 184 can store instructions and data executed by processor 182.

[0144] Also refer to Figure 1A and Figure 1B . Figure 1B It shows Figure 1A A perspective view of a portion of the device 100. The substrate support 130 may have a groove 130T facing the plasma reactor 120. In some embodiments, the substrate support 130 has a base 132 and a protruding edge 134 at opposite sidewalls of the base 132, thereby forming the groove 130T. The base 132 and the protruding edge 134 may extend in a direction X along the process chamber 110. For example, the inlet 110I of the process chamber 110 (see reference...) Figure 1B The vent 110O and the exhaust port 110O are located on opposite sides of the process chamber 110 along the X direction. The substrate W (refer to...) Figure 1A The substrate W (refer to) can be placed between the substrate support 130 and the plasma reactor 120 and supported by the protruding edge 134. With the above configuration, the substrate W (refer to) Figure 1A It can cover at least a portion of the 130T trench.

[0145] exist Figure 1B In the middle, as mentioned above, chalcogenide precursor 200 (reference) Figure 1A The gas source 152 is placed in part 114 of the process chamber 110 and surrounded by the heating device 160. When the gas sources 152 and 154 (reference) Figure 1A When the gas flow for forming plasma P1 is provided, the heated chalcogenide precursor 200 can add chalcogenide gas to the gas flow. For example, a gas flow CG containing chalcogenide (represented by a cross-dot pattern) can fill portion 114 of process chamber 110.

[0146] In the illustrated embodiment, the plasma reactor 120 is positioned above the top of the process chamber 110 and spans the lateral sides of the process chamber 110. The plasma reactor 120 may not extend directly below the process chamber 110. With this configuration, the energy received from microwaves at a higher position in the process chamber 110 is greater than the energy received from microwaves at a lower position in the process chamber 110, causing plasma P1 to be generated primarily in the higher portion of the process chamber 110.

[0147] Figure 2 This is a flowchart of a method M for forming a TMDC layer according to a partial embodiment of this disclosure. Figures 3 to 6A This invention illustrates a method for forming a TMDC layer according to a partial embodiment of the present disclosure. Method M may include steps S1 to S4. In step S1, a metal layer is deposited on the front side of a substrate. In step S2, a substrate holder is placed in a process chamber. In step S3, the substrate is placed on the substrate holder such that the front side of the substrate faces the holder, wherein a gas channel is defined between the metal layer and the substrate holder. In step S4, the metal layer is chalcogenized by microwave plasma treatment. It is understood that... Figure 2 Additional steps are provided before, during, and after steps S1 to S4, and some steps described below may be replaced or eliminated in other implementations of the method. The order of operations / processes may be interchanged.

[0148] Reference Figure 2 and Figure 3 Method M begins with step S1, in which a metal layer TM is deposited on the front side WF of the substrate W. In some embodiments, the substrate W is a semiconductor substrate having transistors and interconnect structures. The substrate W is an intermediate structure in the integrated circuit manufacturing process and can be used for subsequent... Figures 17A to 35 Implementation methods or Figures 36 to 43 The substrate described in the embodiments is as follows. The substrate W may include a surface layer on its front side WF. For example, the surface layer of the substrate W may include a dielectric material, a metallic material, a semiconductor material, the like, or a combination thereof.

[0149] A metal layer TM is deposited on the surface of the substrate W. The metal layer TM may contain transition metals such as Mo, W, Pd, Pt, the like, or combinations thereof. The deposition of the metal layer TM may include physical vapor deposition (PVD) (e.g., electron gun evaporation deposition or thermal evaporation deposition), atomic layer deposition (ALD), chemical vapor deposition (CVD), similar methods, or combinations thereof.

[0150] In some embodiments, after the deposition of the metal layer TM, the metal layer TM can optionally be patterned into a patterned metal layer by appropriate photolithography and etching processes. For example, a mask layer (e.g., a silicon nitride layer) is deposited on the metal layer TM, a photoresist layer is coated on the mask layer and patterned by a photolithography process. Subsequently, the patterned photoresist layer is used as an etching mask to pattern the mask layer. Then, the patterned mask layer is used as an etching mask to pattern the metal layer TM. This patterning may include one or more etching processes that etch the material of the metal layer TM at a faster rate than etching the mask layer and etching the surface of the substrate W. After patterning, the portions of the metal layer exposed by the patterned mask layer are etched away by an appropriate etching process, and the portions of the metal layer covered by the patterned mask layer are retained after the etching process.

[0151] Reference Figure 2 and Figure 4 Method M proceeds to step S2, where the substrate support 130 is placed in the process chamber 110. As described above, the substrate support 130 may have a groove 130T facing the plasma reactor 120. In the figures, the plasma reactor 120 is shown above the top of the process chamber 110, and it should be understood that the plasma reactor 120 may span the lateral sides of the process chamber 110, such as... Figure 1B As shown.

[0152] refer to Figure 2 , Figure 5A and Figure 5B . Figure 5B yes Figure 5AA cross-sectional view. Method M proceeds to step S3, in which the substrate W is placed on the substrate support 130 such that the front side WF of the substrate W faces the substrate support 130. The back side WB of the substrate W, opposite the front side WF, may face the plasma reactor 120. In other words, the front side WF of the substrate W faces away from the plasma reactor 120, meaning that the substrate W is placed on the substrate support 130 in an inverted manner. A gas channel CS is defined between the metal layer TM and the substrate support 130 by using the protruding edge 134 supporting the substrate W, which in turn allows the precursor gas to flow through the front side WF of the substrate W and thus react with the metal layer TM to form TMDC on the front side WF of the substrate W. The gap height L1 of the gas channel CS (i.e., the distance between the metal layer TM and the substrate support 130) can be in the range of approximately 100 micrometers to approximately 3 millimeters, or in the range of approximately 100 micrometers to approximately 750 micrometers. If the gap height L1 of the gas channel CS is less than approximately 100 micrometers, insufficient gas may flow through the gas channel CS, which will reduce the rate at which the metal layer TM is chalcogenized into the TMDC layer in subsequent processes. If the gap height L1 of the gas channel CS is greater than approximately 3 millimeters, the placed substrate W may extend beyond the processing tube.

[0153] In some embodiments, the substrate W (reference) Figure 1A The width WW measured along the Y direction is greater than the width 130W measured along the Y direction of the substrate support 130. In the figure, directions X and Y can be parallel to the top surface of the substrate W and orthogonal to each other. With this configuration, the substrate W (reference...) Figure 1A It can be supported by the protruding edge 134 of the substrate support 130 without contacting the base 132 of the substrate support 130.

[0154] refer to Figure 2 and Figure 6A Method M proceeds to step S4, where a chalcogenizing metal layer TM is achieved through microwave plasma processing. In this embodiment, a gas flow CG containing chalcogens is directed through a gas channel CS, and a plasma reactor 120 is used to ionize the gas flow CG to generate plasma P1 around the substrate W in the process chamber 110. In some embodiments, gas sources 152 and 154 (see reference) Figure 1A The gas flow CG is configured to supply a gas flow containing a mixture of Ar and H2 to the process chamber 110. In the portion 114 of the process chamber 110 (reference...), the gas flow CG... Figure 1ASubsequently, the heated chalcogen precursor 200 can add chalcogen gas to the gas stream CG. The plasma reactor 120 receives microwaves from the power supply 122. When the microwave energy is sufficiently high, the microwaves ionize the gas stream CG containing chalcogen gas, thereby generating plasma P1. The metal layer TM on the front side WF of the substrate W reacts with the chalcogens in the plasma P1 to become a TMDC layer TM'. In some embodiments, depending on the chalcogens contained in the gas stream CG, this chalcogenizing process can be called a sulfurizing process, a selenizing process, etc., and this chalcogenizing process, for example, transforms the metal layer TM into a TMDC layer TM'. In the chalcogenizing process, the dopant source fluid can be connected to the gas inlet 110I (see...). Figure 1A ), and some substances are doped in situ into the TMDC layer.

[0155] TMDC is a class of materials with the chemical formula MX2, where M is a transition metal element such as titanium, vanadium, cobalt, nickel, zirconium, molybdenum, uranium, rhodium, palladium, hafnium, tantalum, tungsten, rhenium, iridium, or platinum, and X is a chalcogenide element such as sulfur, selenium, or tellurium. Examples of TMDC include MoS2, WS2, WSe2, MoSe2, MoTe2, WTe2, the like, or combinations thereof. Once formed, the TMDC layer TM' is in a layered structure having one or more two-dimensional layers of the general formula XMX, wherein chalcogenide atoms in two planes are separated by a plane of metal atoms.

[0156] The TMDC layer TM' can be a single layer or can contain multiple single layers, depending on the metal layer TM (see [link to documentation]). Figure 3 The thickness of ). Figure 6B A schematic diagram of a single layer 300 of an example TMDC layer TM' according to a partial example implementation is shown. Figure 6B In the TMDC layer 300, which is a single molecule thick, there are transition metal atoms 300M and chalcogenide atoms 300X. In the middle region of the TMDC layer 300, the transition metal atoms 300M can form a layer, and the chalcogenide atoms 300X can form a first layer on top of the transition metal atoms 300M, and a second layer below the transition metal atoms 300M. The transition metal atoms 300M can be W atoms or Mo atoms, while the chalcogenide atoms 300X can be S atoms, Se atoms, or Te atoms. Figure 6BIn the embodiments, each transition metal atom 300M is bonded (e.g., via covalent bonds) to six chalcogenide atoms 300X, and each chalcogenide atom 300X is bonded (e.g., via covalent bonds) to three transition metal atoms 300M. Throughout the description, the combination of multiple layers of cross-bonded structures (comprising one layer of transition metal atoms 300M and two layers of chalcogenide atoms 300X) is referred to as a monolayer 300 of the TMDC layer TM'.

[0157] In some embodiments, the operating power of the power supply 122 during plasma processing can be in the range of approximately 20W to approximately 100W. If the power is below approximately 20W, plasma formation is difficult. If the power is above approximately 100W, the substrate or the peripheral area of ​​the substrate may be damaged by the plasma.

[0158] In some embodiments, during plasma treatment, gas sources 152 and 154 (see...) Figure 1A The flow rate of the gas stream CG provided ranges from approximately 1 standard cubic centimeter per minute (sccm) to approximately 50 sccm. The gas stream CG can contain a mixture of reactive gases, including H2, Ar, and H2S. If the flow rate of the gas stream CG is below approximately 1 sccm, plasma formation is difficult. If the flow rate of the gas stream CG is greater than approximately 50 sccm, chalcogenide gases (such as H2S) may move too fast to react with the metal film, and the pressure may be too high to form a plasma.

[0159] In some embodiments, during plasma processing, the process pressure of the process chamber 110 is, for example, measured by a pressure gauge PG (reference). Figure 1A Monitoring is conducted in the range of several millitors (mTorr) to hundreds of millitors. For example, the process pressure in process chamber 110 can be approximately 8 × 10⁻⁶ mTorr. -2 Pull up to approximately 9×10 -2 Within the range of Torr. If the pressure is higher than approximately 9 × 10 -2 Torr, with its low ionization efficiency, may not readily form plasma. If the pressure is below approximately 8 × 10⁻⁶... -2 If the voltage of gas decomposition is too high, plasma may not easily form.

[0160] In some implementations, the duration of plasma treatment ranges from approximately 1 minute to approximately 15 minutes. If the duration is less than approximately 1 minute, the sulfidation reaction may be incomplete, which could result in an uneven sulfidated metal layer. If the duration is greater than approximately 15 minutes, prolonged exposure to plasma may cause damage to a rough surface and may unnecessarily increase process time.

[0161] Back Figure 6A In some embodiments disclosed herein, since microwave plasma is reaction-triggered, plasma can be formed at high energy density in the desired region, thereby enabling the transition metal layer TM (reference) to be formed. Figure 3 The substrate W is transformed into a TMDC layer TM', where the substrate W is not heated (e.g., the substrate W is directly heated using a heating device in contact with the substrate W). With this configuration, the TMDC layer TM' is synthesized at a low temperature. For example, the temperature of the process chamber 110 can be controlled below approximately 400°C, which reduces thermal budget. Thermal budget can be referred to as the total amount of heat energy transferred to the wafer during a given high-temperature operation; low thermal budget is required in integrated circuit manufacturing to prevent dopant redistribution. Furthermore, in some embodiments of this disclosure, the TMDC layer TM' is formed without heating the substrate W (e.g., by directly heating the substrate W using a heating device in contact with the substrate W), thereby eliminating the need for processes for heating and cooling the substrate W, which in turn saves processing time.

[0162] Furthermore, by placing the substrate W downwards, plasma P1 impacts the back surface WB of the substrate W. While plasma P1 may bombard the back surface WB, the front surface WF of the substrate W is protected from plasma bombardment. Through this configuration, the TMDC layer TM' on the front surface WF of the substrate W will not be damaged by plasma P1.

[0163] In some further embodiments, a transition metal layer TM of suitable thickness is deposited (see...). Figure 3 ) and etch the transition metal layer TM in the desired pattern (see Figure 3 The resulting TMDC layer TM' can be formed with a suitable thickness and the desired pattern.

[0164] Figure 7A This is a graph showing the relationship between electron temperature (Te) and gas temperature (Tg) versus pressure. Electron temperature (Te) represents the temperature of electrons within the chamber. Gas temperature (Tg) refers to the temperature of ions and neutral atoms within the chamber, and it primarily determines the temperature of the process chamber. This is achieved at pressures far below atmospheric pressure P. at Under pressure, local thermal equilibrium can no longer be maintained. The onset of non-thermal equilibrium can be represented by pressure P. s At high pressure (e.g., above pressure P) s At low pressures (e.g., below pressure P), thermal plasma (or hot plasma) may be generated between Te and Tg. s When Te is much greater than Tg, non-thermal plasma (or cold plasma) is generated.

[0165] In some embodiments disclosed herein, portion 112 of the process chamber 110 for forming the TMDC layer (see [reference]). Figure 1A , Figure 1B and Figure 6A The process chamber 110 is controlled within region 110E. This is because portion 112 of the process chamber 110 (reference) Figure 1A , Figure 1B and Figure 6A The pressure is lower than the pressure P. at Therefore, the gas temperature (Tg) of the gas in portion 112 of process chamber 110 is much lower than the electron temperature (Te) of the gas in portion 112 of process chamber 110. Thus, process chamber 110 can be maintained at a low temperature.

[0166] Figure 7B An apparatus 100 for forming a TMDC layer according to a partial embodiment of this disclosure is shown (see [link]). Figure 1A , Figure 1B and Figure 6A The temperature of the process chamber 110. In some embodiments, various metals with different melting points are disposed in the process chamber 110 to test portion 112 of the process chamber 110 (reference). Figure 1A and 1B The temperature of the process chamber 110 can be determined by examining the melting conditions of these metals. Figure 1A and 1B The temperature of ). For example, by examining the melting conditions of these metals, it can be concluded that part 112 of the process chamber 110 (reference) Figure 1A and 1B The temperature of the process chamber 110 is higher than the melting points of In and Sn, overlaps with the melting point of Pb (e.g., about 328°C), and is lower than the melting point of Zn (e.g., about 420°C). Therefore, the temperature of a portion 112 of the process chamber 110 can be represented as the temperature range 110T in the figure, where the temperature range 110T can range from about 300°C to about 400°C, or from about 328°C to about 420°C.

[0167] Figure 8A and Figure 8B Raman spectra of a sulfided molybdenum layer and a sulfided tungsten layer according to certain embodiments of this disclosure are shown respectively. For example, Raman spectra can be obtained by performing Raman spectroscopy analysis on the layer after plasma treatment. The first characteristic peak E of MX2 is shown. 1 2g Second characteristic peak A 1g The presence of MX2 (e.g., MoS2 and WS2) in the layer can be confirmed, with the prominent peak E. 1 2g and A 1g This corresponds to the in-plane and out-of-plane vibrations of the atom. (Through...) Figure 8A and Figure 8B The Raman spectra shown indicate that the sulfidated molybdenum layer and the sulfidated tungsten layer are considered to be the MoS2 layer and the WS2 layer, respectively.

[0168] exist Figure 8A In the Raman spectrum shown, the first characteristic peak E 1 2g Located at approximately 380 cm -1 Up to approximately 384 cm -1 Within the range, the second characteristic peak A 1g Located at approximately 403 cm -1 Up to approximately 408 cm -1 Within the range. Note that, depending on the number of MoS2 layers, the first characteristic peak E of MoS2... 1 2g Second characteristic peak A 1g The position can vary within the above range. If the number of MoS2 layers decreases, the first characteristic peak E... 1 2g It may shift slightly to the right, and the second characteristic peak A 1g It may shift slightly to the left. First characteristic peak E 1 2g Second characteristic peak A 1g Distance D between EA This can decrease as the number of MoS2 layers decreases. For example, the distance D EA At approximately 19 cm -1 Up to approximately 25cm -1 Within the range, corresponding to 1 to 5 or more MoS2 layers.

[0169] exist Figure 8B In the Raman spectrum shown, the first characteristic peak E 1 2g Located at approximately 349 cm -1 Up to approximately 353 cm -1 The second characteristic peak A 1g Located at approximately 410 cm -1 Up to approximately 413 cm -1 Note that, depending on the number of WS2 layers, the first characteristic peak E of WS2... 1 2g Second characteristic peak A 1g The position can vary within the above range. If the number of WS2 layers decreases, the first characteristic peak E... 1 2g It may shift slightly to the right, and the second characteristic peak A 1g It may shift slightly to the left. The first characteristic peak E 1 2gand the second characteristic peak A 1g Distance D between EA This can decrease as the number of WS2 layers decreases. For example, distance D EA At approximately 60 cm -1 Up to approximately 65cm -1 This corresponds to WS2 layers with 1 to 5 or more layers.

[0170] Figures 9A to 9E Raman spectra of molybdenum layers sulfurized on various substrates and at different operating powers, according to some embodiments of this disclosure, are shown. Figures 9A to 9E In this case, the operating power increased from P#1 to P#5, while the deposition time remained essentially the same. Figures 9A to 9E Raman spectra of molybdenum layers sulfided on SiO2 layers, low-k dielectric layers, high-k dielectric layers, sapphire substrates, and SiO2 layers were displayed. Figures 9A to 9E The Raman spectra shown indicate that the sulfided molybdenum layer on the SiO2 layer, low-k dielectric layer, high-k dielectric layer, and sapphire substrate is a MoS2 layer.

[0171] Figure 9F Demonstrating operating power and Figure 9E Characteristic peak E 1 2g and A 1g The relationship between the full width at half maximum (FWHM) and the characteristic peak E. As the operating power increases, the characteristic peak E... 1 2g and A 1g The FWHM and its error curve decreased. This indicates that higher operating power can lead to more consistent quality in the resulting MoS2 layers.

[0172] Figures 10A to 10C Raman spectra of molybdenum layers sulfurized on various substrates at different deposition times, according to some embodiments of this disclosure, are shown. Figures 10A to 10C In this process, the deposition time was increased from T#1 to T#3, while the operating power remained substantially the same. Figures 10A to 10C Raman spectra of molybdenum layers sulfided on SiO2, low-k dielectric, and high-k dielectric layers are shown respectively. The Raman spectra reveal that the molybdenum layers sulfided on SiO2, low-k dielectric, and high-k dielectric layers are MoS2 layers.

[0173] The figure also shows that a longer deposition time results in a smaller FWHM, which indicates a stronger signal in the resulting MoS2 layer. Therefore, a longer deposition time may lead to a better quality MoS2 layer. Furthermore, a comparison... Figure 10C and Figure 10A and 10B , Figure 10CThe FWHM of the Raman spectrum appears to be greater than Figure 10A and 10B The FWHM of the Raman spectrum. This indicates that the SiO2 layer and the MoS2 layer on the low-k dielectric layer have better film quality than the MoS2 layer on the high-k dielectric layer.

[0174] Figure 11A and Figure 11B X-ray photoelectron spectroscopy (XPS) data of molybdenum (Mo) and sulfur (S) in the sulfided molybdenum layers obtained according to certain embodiments of this disclosure are shown respectively. The binding energy and atomic ratio of the obtained sulfided molybdenum layers were detected by XPS analysis. Figure 11A In the figure, the two peaks of the Mo binding energy correspond to Mo. 4+ 3D 5 / 2 and Mo 4+ 3D 3 / 2 .exist Figure 11B In the figure, the two peaks of the S binding energy correspond to 2p. 3 / 2 and 2p 1 / 2 As shown in the figure. Figure 11A and Figure 11B As shown, the elemental composition ratio of S:Mo is in the range of approximately 1.9:1 to approximately 2.1:1, for example, approximately 2:1. The resulting sulfided molybdenum layer is a MoS2 layer.

[0175] Figure 12A and Figure 12B An atomic force microscope (AFM) image is shown of a MoS2 layer obtained on a high-k dielectric layer and a SiO2 layer according to a partial embodiment of this disclosure. For Figure 12A and Figure 12B The MoS2 layer in the substrate operates at the same power during the plasma processing for forming TMDC. Large-area TMDC layers can be synthesized regardless of the material of the substrate surface. For example... Figure 12A and Figure 12B As shown, in the high-k dielectric layer ( Figure 12A ) and SiO2 layer ( Figure 12BThe MoS2 layer formed on the surface has a very small surface roughness. In this context, surface roughness can be represented by centerline averaged roughness (Ra), which is the average area per unit length deviating from the centerline. In other words, Ra is the arithmetic mean of multiple absolute values ​​on the ordinate of the roughness distribution. Analysis using atomic force microscopy confirmed that the surface roughness (e.g., Ra) of the obtained MoS2 layer is below 1 nanometer. For example, Figure 12A The surface roughness (e.g., Ra) of the shown MoS2 layer can be in the range of about 0.5 nm to about 0.6 nm (e.g., about 0.536 nm), and Figure 12B The surface roughness (e.g., Ra) of the MoS2 layer shown can be in the range of about 0.8 nm to about 0.9 nm (e.g., about 0.889 nm).

[0176] Figure 13A and Figure 13B AFM of a molybdenum layer on a dielectric layer before plasma treatment and a corresponding MoS2 layer on the dielectric layer after plasma treatment, according to certain embodiments of this disclosure, are shown respectively. Figure 13A As shown, prior to plasma treatment, the Mo layer has a very small surface roughness (e.g., Ra), less than 1 nanometer. For example, Figure 13A The surface roughness (e.g., Ra) of the Mo layer shown can be in the range of approximately 0.3 nm to approximately 0.4 nm (e.g., approximately 0.37 nm). After plasma treatment, as... Figure 13B As shown, the MoS2 layer has a very small surface roughness (e.g., Ra), which is less than 1 nanometer. For example, Figure 13B The surface roughness (e.g., Ra) of the MoS2 layers shown can range from approximately 0.6 nm to approximately 0.7 nm (e.g., approximately 0.66 nm). This indicates that plasma treatment has little or no effect on roughness, which has great application potential in back-end processes.

[0177] Figure 14 This is a side view schematic diagram of an apparatus for forming a TMDC layer according to a partial embodiment of this disclosure. This embodiment is similar to... Figure 1AThe embodiment shown differs in that the chalcogenide precursor 200P is supplied to the plasma P1 in powder form. For example, the chalcogenide precursor 200P may contain S, Se, and Te powders. In this embodiment, the chalcogenide precursor 200P is stored outside the process chamber 110. For example, the chalcogenide precursor 200P is stored in a container 140P, which is in fluid communication with gas sources 152 and 154 and is surrounded by a heating device 160P. The heating device 160P can heat and melt the chalcogenide precursor 200P, thereby generating an appropriate amount of gaseous chalcogenide-containing precursor. Therefore, when gas sources 152 and 154 provide a gas flow for forming the plasma P1, the heated chalcogenide precursor 200P can add chalcogenide gas to the gas flow. For example, in one embodiment of sulfur (with a melting point of approximately 120°C) in chalcogenide precursor 200P, the temperature of heating device 160P can be in the range of approximately 120°C to approximately 200°C. If the temperature of heating device 160P is below approximately 120°C, the sulfur may not melt, and almost no chalcogenide gas will be produced. If the temperature of heating device 160P is above approximately 200°C, the sulfur may melt too quickly, and the sulfur will evaporate and be consumed too rapidly, which may result in high costs.

[0178] Mass flow controllers MFC1 and MFC2 can be used to control the flow rate of gas from gas sources 152 and 154 to container 140P, and mass flow controller MFC3 can be used to control the flow rate of sulfide-containing gas from container 140P to process chamber 110. Additional valves V6 and V7 can be used to control the gas flow into and out of container 140P, respectively. Controller 180 can be coupled to mass flow controllers MFC1 to MFC3, valves V11, V12, V21, V22, V3, V4, V6, V7, vacuum control valve V5, plasma reactor 120 and power supply 122, heating device 160P, and other suitable system components for operating equipment 100 (controlling, for example, vacuum pressure, gas flow rate, plasma generation, heating temperature, and at least some of other system parameters). Further details of this embodiment are related to... Figure 1A The implementation method is similar and will not be described in detail here.

[0179] Figure 15 This is a side view schematic diagram of an apparatus for forming a TMDC layer according to a partial embodiment of this disclosure. This embodiment is similar to... Figure 1AThe embodiment shown differs in that the sulfide precursor 200L is supplied to the plasma P1 in liquid form. For example, the sulfide precursor 200L may contain liquid sulfide, such as C2H6S, SeF4, etc. In this embodiment, the sulfide precursor 200L is stored outside the process chamber 110. For example, the sulfide precursor 200L is stored in a container 140L in fluid communication with gas sources 152 and 154. In some embodiments, the container 140L may be surrounded by a heating device 160L. The heating device 160L can heat and evaporate the sulfide precursor 200L, thereby generating an appropriate amount of gaseous sulfide-containing precursor. Therefore, when gas sources 152 and 154 provide a gas flow for forming the plasma P1, the heated sulfide precursor 200L can add sulfide gas to the gas flow. For example, in some embodiments of the chalcogenide precursor 200L containing SeF4, the temperature of the heating device 160L can be in the range of approximately 25°C to approximately 80°C. If the temperature of the heating device 160L is below approximately 25°C, almost no chalcogenide gas is produced. If the temperature of the heating device 160L is above approximately 80°C, sulfur may evaporate and be consumed too quickly, which could result in high costs. In some other embodiments of the chalcogenide precursor 200L containing C2H6S, the heating device 160L can be omitted.

[0180] Mass flow controller MFC4 can be used to control the flow rate of sulfide gas from container 140L to the gas flow provided by gas sources 152 and 154, and to process chamber 110. An additional valve V8 can be used to control the release of sulfide gas from container 140L. Controller 180 can be coupled to mass flow controllers MFC1, MFC2, MFC4, valves V11, V12, V21, V22, V3, V4, V8, vacuum control valve V5, plasma reactor 120 and power supply 122, heating device 160L, and other suitable system components for operating equipment 100 (e.g., controlling vacuum pressure, gas flow rate, plasma generation, heating temperature, and at least some of other system parameters). Further details of this embodiment are related to… Figure 1A The implementation method is similar and will not be described in detail here.

[0181] Figure 16 This is a side view schematic diagram of an apparatus for forming a TMDC layer according to a partial embodiment of this disclosure. This embodiment is similar to... Figure 1AThe embodiment shown differs in that the chalcogenide precursor 200G is supplied to the plasma P1 in gaseous form. For example, the chalcogenide precursor 200G may contain chalcogenide gases such as H₂S, SeF₆, CH₄S, WF₆, etc. In this embodiment, the chalcogenide precursor 200G is stored outside the process chamber 110. For example, the chalcogenide precursor 200G is stored in a container 140G in fluid communication with gas sources 152 and 154. When gas sources 152 and 154 provide a gas flow for forming the plasma P1, the chalcogenide gas (i.e., the chalcogenide precursor 200G) can be added to the gas flow. In this embodiment, since the chalcogenide precursor 200G is stored in gaseous form, no heating device is needed to heat the container 140G and evaporate the chalcogenide precursor 200G.

[0182] The flow rate of chalcogenide precursor 200G from container 140G to the gas flow provided by gas sources 152 and 154, and to process chamber 110, can be controlled using mass flow controller MFC5. Additional valves V91 and V92 can be used to control the release of chalcogenide precursor 200G from container 140G and from mass flow controller MFC5. Controller 180 can be coupled to mass flow controllers MFC1, MFC2, MFC5, valves V11, V12, V21, V22, V3, V4, V91, V92, vacuum control valve V5, plasma reactor 120, and power supply 122, as well as other suitable system components for operating equipment 100 (e.g., controlling vacuum pressure, gas flow rate, plasma generation, heating temperature, and at least some of other system parameters). Further details of this embodiment are consistent with… Figure 1A The implementation method is similar and will not be described in detail here.

[0183] exist Figures 14 to 16 The sulfide gas from sulfide precursors 200L and 200G has higher flowability than the sulfide gas from sulfide precursor 200P. Therefore, containers 140L and 140G storing sulfide precursors 200L and 200G are arranged as gas sources connected in parallel with gas sources 152 and 154. On the other hand, container 140P containing sulfide precursor 200P is connected in series with gas sources 152 and 154.

[0184] Figure 17A and Figure 17B This is a flowchart of a method MA for forming an integrated circuit device according to a partial embodiment of the present disclosure. Figures 18 to 35 A method for forming an integrated circuit device according to a partial embodiment of this disclosure is illustrated. Method MA may include steps AS1 to AS14. It will be understood that... Figure 17A and Figure 17BAdditional steps are provided before, during, and after steps AS1 to AS14. In other embodiments of the method, some steps described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0185] refer to Figure 17A and Figure 18 Method MA begins at step AS1, which provides a substrate having an internal interconnection structure. Figure 18 A cross-sectional view of the intermediate structure of wafer W during integrated circuit manufacturing is shown. Figure 18 In this embodiment, the semiconductor wafer W is an intermediate structure in the integrated circuit manufacturing process, in which transistors and interconnect structures have already been formed. In some embodiments, the semiconductor wafer W may include a substrate 402. The substrate 402 may include, for example, an active layer of doped or undoped silicon bulk or a semiconductor-on-insulator (SOI) substrate. Typically, the SOI substrate includes a layer of semiconductor material, such as silicon, formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is disposed on a substrate, such as a silicon or glass substrate. Alternatively, the substrate 402 may include another elemental semiconductor, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0186] In some embodiments, one or more active and / or passive devices 404 are formed on the substrate 402. Figure 18 (Illustrated as a single transistor). This one or more active and / or passive device 404 may comprise various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, etc. Those skilled in the art will understand that the examples provided above are for illustrative purposes only and are not intended to limit this disclosure in any way. Other circuits may be appropriately formed for a given application.

[0187] In some embodiments, an interconnect structure 406 is formed on one or more active and / or passive devices 404 and substrate 402. The interconnect structure 406 electrically interconnects one or more active and / or passive devices 404 to form a functional circuit within a semiconductor structure. The interconnect structure 406 may include one or more metallization layers. The metallization layers include one or more horizontal interconnects (e.g., wires extending horizontally or laterally in a dielectric layer, respectively) and vertical interconnects (e.g., conductive vias extending vertically in a dielectric layer, respectively). The formation of the interconnect structure 406 may be referred to as a back-end-of-line (BEOL) process.

[0188] Contact plug 412 electrically couples the upper internal connection structure 406 to the lower device 404. In the depicted embodiment, device 404 is a fin-effect transistor (FinFET), which is a three-dimensional MOSFET structure formed in the semiconductor protrusions (referred to as fins) 403 of the fin-like strip. Figure 18 The cross-section shown is taken along the longitudinal axis of the fin in the direction of current flow parallel to the source / drain regions 404SD. The fins 403 can be formed by patterning the substrate 402 using photolithography and etching techniques. For example, spacer image transfer (SIT) patterning techniques can be used. In this method, a sacrificial layer is formed on the substrate and patterned using a suitable photolithography and etching process to form a mandrel. Spacers are formed next to the mandrel using a self-aligned process. The sacrificial layer is then removed by a suitable selective etching process. Each remaining spacer can then be used as a hard mask to pattern the corresponding fin 403 by etching trenches into the substrate 402 using, for example, reactive ion etching (RIE). Figure 18 A single fin 403 is illustrated; the substrate 402 may contain any number of fins. In some other embodiments, the device 404 is a planar transistor or a gate-all-around (GAA) transistor.

[0189] Shallow trench isolation (STI) regions 405 are formed on the opposite sidewalls of fin 403. The shallow trench isolation regions 405 can be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trenches around the fins, and then recessing the upper surface of the dielectric material. The dielectric material of the shallow trench isolation regions 405 can be deposited using high-density plasma chemical vapor deposition (HDP-CVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCVD), spin coating, and / or similar methods or combinations thereof. After deposition, an annealing or curing process can be performed. In some cases, the shallow trench isolation regions 405 may include a liner, such as a thermal oxide liner grown through the silicon oxide surface. The recessing process can be performed using, for example, a planarization process (e.g., chemical mechanical polishing (CMP)) followed by a selective etching process (e.g., wet etching, dry etching, or a combination thereof). The selective etching process can recess the upper surface of the dielectric material in the shallow trench isolation region 405, causing the upper part of the fin 403 to protrude from the surrounding insulating shallow trench isolation region 405. In some cases, the patterned hard mask used to form the fin 403 can also be removed by the planarization process.

[0190] In some embodiments, the gate structure 404G of the FinFET device 404 is a high-k metal gate (HKMG) structure that can be formed using a gate-last process. In the gate-last process, after forming the shallow trench isolation region 405, a sacrificial dummy gate structure (not shown) is formed. The dummy gate structure may include a dummy gate dielectric, a dummy gate electrode, and a hard mask. First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, etc.) may be deposited. Next, a dummy gate material (e.g., amorphous silicon, polycrystalline silicon, etc.) may be deposited on the dummy gate dielectric and then planarized (e.g., through CMP). A hard mask (e.g., silicon nitride, silicon carbide, etc.) may be formed over the dummy gate material. The dummy gate structure is then formed by patterning the hard mask and transferring the pattern to the dummy gate dielectric and dummy gate material using appropriate photolithography and etching techniques. The dummy gate structure can extend along multiple sides of the protruding fins and between the fins onto the surface of the shallow trench isolation region 405. As described in more detail below, Figure 18As shown, the dummy gate structure can be replaced by the HKMG gate structure 404G. Any suitable method can be used to deposit the material used to form the dummy gate structure and the hard mask, such as CVD, PECVD, ALD, plasma-enhanced atomic layer deposition (PEALD), similar methods, thermal oxidation through the semiconductor surface, or combinations thereof.

[0191] exist Figure 18 In this process, source / drain regions 404SD and spacers 404SP, such as a self-aligned dummy gate structure, are formed in device 404. The spacers 404SP can be formed by deposition and anisotropic etching of a spacer dielectric layer performed after the dummy gate patterning is complete. The spacer dielectric layer may comprise one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc., or combinations thereof. The anisotropic etching process removes the spacer dielectric layer on top of the dummy gate structure, leaving the spacers 404SP, which extend laterally along the sidewalls of the dummy gate structure onto a portion of the surface of fin 403.

[0192] The source / drain region 404SD is a semiconductor region in direct contact with the semiconductor fin 403. In some embodiments, the source / drain region 404SD may comprise a heavily doped region and a relatively lightly doped drain extension region, or a lightly-doped drain (LDD) region. The spacer 404SP separates the heavily doped region from the dummy gate structure, and the LDD region can be formed prior to the formation of the spacer 404SP, thus extending below the spacer 404SP, and in some embodiments, further extending into a portion of the semiconductor fin 403 below the dummy gate structure. For example, the LDD region can be formed by implanting dopants (e.g., As, P, B, In, etc.) using an ion implantation process.

[0193] The source / drain region 404SD can include epitaxial growth regions. For example, after forming the LDD region, a spacer 404SP can be formed. Subsequently, heavily doped source and drain regions self-aligned with the spacer 404SP can be formed by first etching fins to create grooves. Then, crystalline semiconductor material is deposited in the grooves using a selective epitaxial growth (SEG) process. This process can fill the grooves and can further extend beyond the original surface of the fin 403 to form a raised source / drain epitaxial structure. The crystalline semiconductor material can be an element (e.g., Si or Ge) or an alloy (e.g., Si). 1-x C x or Si 1-x Ge xSEG processes can use any suitable epitaxial growth method, such as vapor / solid / liquid phase epitaxy (VPE / SPE / LPE), metal-organic chemical vapor deposition (MOCVD), or molecular beam epitaxy (MBE). High doses (e.g., approximately 10...) 14 cm -2 Up to 10 16 cm -2 The dopants can be doped in situ during SEG, or introduced into the heavily doped source and drain regions 404SD via an ion implantation process performed after SEG, or a combination thereof.

[0194] After the source / drain region 404SD is formed, a first interlayer dielectric (ILD) layer (e.g., the lower portion of the interlayer dielectric layer ILD0) is deposited over the source / drain region 404SD. In some embodiments, a contact etch stop layer (CESL) (not shown) of a suitable dielectric material (e.g., silicon nitride, silicon carbide, or combinations thereof) may be deposited before depositing the interlayer dielectric material. A planarization process (e.g., CMP) may be performed to remove excess interlayer dielectric material and any remaining hard masking material from above the dummy gate to form an upper surface in which the upper surface of the dummy gate material is exposed and can be substantially coplanar with the upper surface of the first interlayer dielectric layer. Then, to form the HKMG gate structure 404G, the dummy gate structure may be removed using one or more etching techniques to create grooves between the individual spacers 404SP. Next, a substituted gate dielectric layer 404GD comprising one or more dielectrics is deposited, followed by a substituted gate metal layer 404GM comprising one or more metals to completely fill the trench. Excess portions of the dielectric layer 404GD and metal layer 404GM in the gate structure layer can be removed from the upper surface of the first interlayer dielectric layer using, for example, a CMP process. The resulting structure may include the remaining portions of the dielectric layer 404GD and metal layer 404GM embedded in the HKMG gate layer between the respective spacers 404SPs.

[0195] The gate dielectric layer 404GD comprises, for example, a high-k dielectric material, such as oxides and / or silicates, silicon nitrides, silicon oxides, etc., of metals (e.g., Hf, Al, Zr, La, Mg, Ba, Ti, and other metals), or combinations thereof, or a multilayer structure thereof. In some embodiments, the gate metal layer 404GM may be a multilayer metal gate stack comprising a barrier layer, a work function layer, and a gate fill layer continuously formed on the gate dielectric layer 404GD. Example materials for the barrier layer include TiN, TaN, Ti, Ta, the like, or multilayer combinations thereof. The work function layer may comprise TiN, TaN, Ru, Mo, Al for p-type FETs, and Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr for n-type FETs. Other suitable work function materials, combinations thereof, or multilayer structures may also be used. The gate fill layer filling the remaining portion of the trench may comprise a metal, such as Cu, Al, W, Co, Ru, the like, combinations thereof, or a multilayer structure thereof. Materials used to form the gate structure can be deposited by any suitable method, such as CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), electroless plating, and / or similar methods.

[0196] After forming the HKMG gate structure 404G, a second interlayer dielectric layer is deposited on top of the first interlayer dielectric layer, and these interlayer dielectric layers are combined and referred to as the interlayer dielectric layer ILD0, as shown below. Figure 18As shown. In some embodiments, the insulating material forming the first interlayer dielectric layer and the second interlayer dielectric layer may comprise silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), low-k dielectrics such as fluorosilicate glass (FSG), silicon oxycarbonate (SiOCH), carbon-doped oxide (CDO), flowable oxides or porous oxides (e.g., dry gels / aerogels), or the like or combinations thereof. The dielectric material used to form the first interlayer dielectric layer and the second interlayer dielectric layer can be deposited using any suitable method, such as CVD, PVD, ALD, PEALD, PECVD, SACVD, FCVD, spin coating and / or similar methods or combinations thereof. Conductive contact plugs 412 can be formed in the interlayer dielectric layer ILD0 using photolithography, etching, and deposition techniques. Figure 18 In the embodiment shown, the contact plug 412 is electrically connected to the gate structure 404G and the source / drain region 404SD of the device 404.

[0197] After the contact plug 412 is formed, according to the back-end architecture (BEOL) scheme adopted in the integrated circuit design, an internal interconnect structure 406 comprising multiple internal interconnect layers can be formed, vertically stacked above the contact plug 412 formed in the interlayer dielectric layer ILD0. In the illustrated embodiment, the internal interconnect structure 406 may comprise multiple internal interconnect layers 406I, and each internal interconnect layer 406I may have an interlayer dielectric layer 406D and conductive features (e.g., conductive vias, wires, or combinations thereof) 406M surrounded by the interlayer dielectric layer 406D. In some embodiments, an etch stop layer 406E may be formed between every two adjacent internal interconnect layers 406I. These etch stop layers 406E may comprise a dielectric material different from the interlayer dielectric layer 406D of the internal interconnect structure 406. For example, the etch stop layer 406E may comprise silicon nitride, silicon carbide, silicon oxynitride, silicon carbonoxylate, silicon carbonitride, etc., or combinations thereof. Figure 18 In the illustrated BEOL embodiment, the various interconnect layers have similar characteristics. However, it should be understood that other implementations may use different integration schemes, where the various interconnect layers may use different characteristics. For example, the source / drain contact plug 412, shown as a vertical connector, may extend to form a conductor for lateral current transmission.

[0198] In some embodiments, the interlayer dielectric layer 406D may comprise a low-k dielectric material having a k value, for example, below about 4.0 or even 2.0. For example, the interlayer dielectric layer 406D may be made of, for example, PSG, BPSG, FSG, SiO2. x C y The conductive feature 406M is made of spin-coated glass, spin-coated polymer, silicon oxide, silicon oxynitride, or combinations thereof, and is formed by any suitable method such as spin coating, CVD, PECVD, etc. The conductive feature 406M may comprise conductive materials such as copper, aluminum, tungsten, or combinations thereof. In some embodiments, the conductive feature 406M may further comprise one or more barrier / adhesive layers 406MB to protect the corresponding interlayer dielectric layer 406D from metal diffusion (e.g., copper diffusion) and metal contamination. This one or more barrier / adhesive layers may comprise titanium, titanium nitride, tantalum, tantalum nitride, the like, or combinations thereof.

[0199] refer to Figure 17A and Figure 19 Method MA proceeds to step AS2, where a first metal thin film 420 is deposited on the internal interconnect structure 406. The first metal thin film 420 may contain a transition metal, such as Mo, W, Pd, Pt, the like, or combinations thereof. The deposition of the first metal thin film 420 may include PVD (e.g., electron gun evaporation deposition or thermal evaporation deposition), ALD, CVD, similar methods, or combinations thereof.

[0200] refer to Figure 17A and Figure 20 Method MA proceeds to step AS3, where the first metal thin film 420 is patterned (see reference). Figure 19 To form the first metal layer 422. For example, it is first formed on the first metal thin film 420 (see...). Figure 19 A mask layer is then applied, followed by a patterned mask layer to form a patterned mask. The patterned mask is then used to apply the patterned mask to the first metal film 420 (see [reference]). Figure 19 The etching process is performed. A mask layer acts as an etching mask, thereby protecting the first metal film 420 (see [reference]). Figure 19 The patterned mask layer is patterned into a first metal layer 422. In some embodiments, the patterned mask layer may comprise an organic material, such as a photoresist, and may be formed using a spin coating process, followed by patterning the photoresist using a suitable photolithography technique to achieve a pattern. In some embodiments, the etching process may comprise wet etching, dry etching, or a combination thereof. For this etching process, the top layer of the interconnect structure 406 (e.g., etch stop layer 406ESL) may have a larger surface area than the first metal film 420 (see reference 420). Figure 19 Higher etch resistance, thus protecting the underlying components from being etched.

[0201] refer to Figure 17A and Figure 21In step AS4 of method MA, a second metal thin film 430 is deposited on the internal interconnect structure. The second metal thin film 430 may contain a transition metal, such as Mo, W, Pd, Pt, the like, or a combination thereof. The second metal thin film 430 may contain a material different from the first metal layer 422. The deposition of the second metal thin film 430 may include PVD (e.g., electron gun evaporation deposition or thermal evaporation deposition), ALD, CVD, similar methods, or a combination thereof.

[0202] refer to Figure 17A and Figure 22 Method MA proceeds to step AS5, where the second metal thin film 430 is patterned (see reference). Figure 21 Patterning is performed to form a second metal layer 432. For example, firstly, a second metal thin film 430 (see reference 430) is patterned to form a second metal layer 432. Figure 21 A mask layer is formed on the second metal thin film 430 (reference). The mask layer is then patterned to form a patterned mask. The patterned mask is then used as an etching mask to etch the second metal thin film 430. Figure 21 The etching process layer is used to pattern the second metal film 430 (see [reference]). Figure 21 The first metal layer 422 and the second metal layer 432 are used to form TMDC layers with different compositions in subsequent processing. The materials of the first and second metals depend on the target conductivity type of the resulting transistor. For example, when the first metal layer 422 is Mo, it can be used to form a MoS2 layer, which is suitable as the active region of an n-type FET, using electrons as channel carriers in the MoS2 channel, and when the second metal layer is W, it can be used to form WS2, which is suitable as the active region of a p-type FET, using holes as channel carriers in the WS2. In some embodiments, the patterned mask layer may comprise an organic material, such as a photoresist, and can be formed using a spin coating process, followed by patterning the photoresist using a suitable photolithography technique to give the photoresist a pattern. In some embodiments, the etching process may comprise wet etching, dry etching, or a combination thereof. For this etching process, the top layer of the interconnect structure 406 (e.g., etch stop layer 406ESL) may have a higher density than the second metal film 430 (see reference 430). Figure 21 It provides higher etch resistance, thereby protecting the underlying interconnect structure 406 from etching.

[0203] refer to Figure 17A and Figure 23 Method MA proceeds to step AS6, where plasma treatment is performed to chalcogenize the first and second metal layers 422 and 432 (see...). Figure 22 As shown in the previous figure. Figures 1A to 6AAs shown, the plasma treatment can use microwave plasma P1, which contains chalcogenides brought in by the gas flow CG. Through plasma treatment, the first and second metal layers 422 and 432 (see...) Figure 22 These are transformed into TMDC layers 422' and 432', respectively, which have high channel mobility, high current switching (ON / OFF) ratio, and good subthreshold swing. For example, in the first and second metal layers 422 and 432 (see... Figure 22 In some embodiments of the Mo and W layers, when the gas flow CG contains sulfur, the TMDC layers 422' and 432' formed are the MoS2 layer and the WS2 layer, respectively.

[0204] refer to Figure 17A and Figure 24 In step AS7 of method MA, a dielectric layer 450 is deposited on TMDC layers 422' and 432'. Dielectric layer 450 may contain a suitable dielectric material for electrically isolating TMDC layers 422' and 432' from the subsequently formed gate electrode. In some embodiments, dielectric layer 450 may be referred to as the gate dielectric layer. In some embodiments, dielectric layer 450 contains a high-k dielectric material, such as oxides and / or silicates of metals (e.g., oxides and / or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and other metals), silicon nitride, silicon oxide, the like, or combinations thereof, or a multilayer structure thereof. In some embodiments, dielectric layer 450 may contain a low-k dielectric material, such as PSG, BPSG, FSG, SiOxCy, spin-coated glass, spin-coated polymers, silicon oxide, silicon oxynitride, combinations thereof, etc. In some embodiments, dielectric layer 450 comprises a material similar to the gate dielectric layer 404GD in the transistor device 404 beneath the interconnect structure 406. Dielectric layer 450 can be formed by any suitable method, such as spin coating, CVD, PECVD, etc.

[0205] refer to Figure 17A and Figure 25 Method MA proceeds to step AS8, where a gate electrode layer 460 is deposited on the dielectric layer 450. The gate electrode layer 460 may comprise a suitable conductive material, such as a metal (e.g., W) or polysilicon (poly-Si). In some embodiments, the gate electrode layer 460 comprises a material similar to the gate metal layer 404GM in the device 404 beneath the interconnect structure 406. The gate electrode layer 460 may be deposited using CVD, PVD, sputtering deposition, or other techniques suitable for depositing conductive materials.

[0206] refer to Figure 17B and Figure 26 Method MA proceeds to step AS9, where the gate electrode layer 460 is patterned (see...). Figure 24Gate electrodes 462 and 464 are formed, which are respectively located on TMDC layers 422' and 432'. For example, firstly, on gate electrode layer 460 (see...) Figure 24 A mask layer is formed on the gate electrode layer 460, and then the mask layer is patterned to form a patterned mask. Then, by using the patterned mask layer as an etching mask, the gate electrode layer 460 (see [reference]) is etched. Figure 24 The gate electrode layer 460 is patterned by an etching process (see [reference]). Figure 24 Gate electrodes 462 and 464 are provided. In some embodiments, the patterned mask layer may comprise an organic material, such as a photoresist, and may be formed using a spin-coating process, followed by patterning the photoresist using a suitable photolithography technique. In some embodiments, the etching process may comprise wet etching, dry etching, or a combination thereof. In some embodiments, for the etching process, dielectric layer 450 may have higher etch resistance than gate electrode layer 460 (see [link to relevant documentation]). Figure 24 This protects the underlying internal interconnect structure 406 and TMDC layers 422' and 432' from being etched.

[0207] Through the above steps, a gate structure GS1 (i.e., a combination of gate 462 and a portion of the dielectric layer 450 below it) is formed on the TMDC layer 422', and a gate structure GS2 (i.e., a combination of gate 464 and a portion of the dielectric layer 450 below it) is formed on the TMDC layer 432'.

[0208] In this embodiment, gate structures GS1 and GS2 are formed by patterned deposition of a gate electrode layer and a deposited dielectric layer. In some alternative embodiments, gate structures GS1 and GS2 can be formed using a post-gate process flow. In the post-gate process flow, a sacrificial dummy gate structure (not shown) is formed after the formation of TMDC layers 422' and 423'. The dummy gate structure may include a dummy gate dielectric (e.g., silicon oxide) and a dummy gate electrode (e.g., polysilicon) above the dummy gate dielectric. The dummy gate structure may be replaced by a metal gate structure. Replacement of the dummy gate structure may involve forming gate spacers on opposite sides of the dummy gate structure, etching the dummy gate structure to leave gate trenches between the gate spacers, depositing a gate dielectric layer and a gate electrode layer into the gate trenches, and then performing a planarization process (e.g., CMP). The gate dielectric layer may include a high-k dielectric layer. The gate electrode layer may include a barrier layer, a work function layer, and a fill metal. Example materials for the barrier layer include TiN, TaN, Ti, Ta, the like, or multilayer combinations thereof. The work function layer may comprise TiN, TaN, Ru, Mo, and Al for p-type FETs, and Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr for n-type FETs. The filler metal may comprise metals such as Cu, Al, W, Co, Ru, the like, combinations thereof, or multilayer structures thereof. In the back-gate embodiment, gate structures GS1 and GS2 may comprise materials similar to the gate structure 404G in the device 404 below the interconnect structure 406.

[0209] refer to Figure 17B and Figure 27 Method MA proceeds to step AS10, in which an interlayer dielectric layer (ILD) is deposited on gate electrodes 462 and 464. X In some embodiments, the interlayer dielectric layer (ILD) X It may contain silicon oxide, PSG, BSG, BPSG, USG, low-k dielectrics (e.g., FSG, silicon carbide (SiOCH), carbon-doped oxide (CDO), flowable oxides or porous oxides (e.g., xerogel / aerogel)), or combinations thereof. Interlayer dielectric layer (ILD) X Deposition can be performed using any suitable method, such as CVD, PVD, ALD, PEALD, PECVD, SACVD, FCVD, spin coating, and / or similar methods or combinations thereof.

[0210] refer to Figure 17B and Figure 28 Method MA proceeds to step AS11, where the interlayer dielectric layer ILD is applied. XIn dielectric layer 450, openings O1 and O2 are etched. Opening O1 exposes TMDC layers 422' and 432'. Opening O2 exposes the underlying conductive feature 406M. For example, first in the interlayer dielectric layer ILD... X A mask layer is formed on top, and then the mask layer is patterned to form a patterned mask. The patterned mask layer is used as an etching mask, and then the interlayer dielectric layer (ILD) is etched. X The dielectric layer 450 is etched to form openings O1, O2, or a combination thereof. In some embodiments, the patterned mask layer may comprise an organic material, such as a photoresist, and may be formed using a spin-coating process, followed by patterning the photoresist using a suitable photolithography technique. In some embodiments, the etching process may comprise wet etching, dry etching, or a combination thereof. For this etching process, the TMDC layers 422' and 432' and the etch stop layer 406E may have a higher dielectric density than the interlayer dielectric layer ILD. X It exhibits higher etch resistance and therefore will not be substantially etched by the etching process. After the opening O2 is formed, a substrate removal etching process can be performed to remove a portion of the etch stop layer 406E exposed by the opening O2, thereby exposing the underlying conductive features 406M.

[0211] refer to Figure 17B and Figure 29 Method MA proceeds to step AS12, where a conductive filler material 470a is deposited into the opening O1. The conductive filler material 470a may comprise W, Al, Cu, Ru, Ni, Co, alloys thereof, combinations thereof, etc. Any acceptable deposition technique can be used to deposit the conductive filler material 470a, such as CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, etc., or any combination thereof. In some embodiments, prior to depositing the conductive filler material 470a, a substrate 470b is conformally deposited on the opening O1. The substrate 470b may comprise a barrier metal to reduce the diffusion of conductive material from the contact outwards into the surrounding dielectric material. The substrate 470b may comprise a material different from the conductive filler material 470a. For example, the substrate 470b may comprise TiN, TaN, Ta, or other suitable metals or alloys thereof.

[0212] refer to Figure 17B and Figure 30 Method MA proceeds to step AS13, where a planarization process (e.g., CMP) can be used to transfer the interlayer dielectric layer (ILD) from the substrate. X On the surface, all conductive materials (e.g., liner 470b and conductive filler 470a) are removed. The remaining conductive material forms source / drain contacts 472 in opening O1 and conductive plugs 474 in opening O2. The source / drain contacts 472 extend into the interlayer dielectric layer (ILD). XIt is incorporated within dielectric layer 450 and physically and electrically connected to TMDC layers 422' and 432'. Conductive plug 474 extends into the interlayer dielectric layer (ILD). X It is incorporated in dielectric layer 450 and physically and electrically connected to conductive feature 406M.

[0213] Transistors T1 and T2 are formed through the above steps. Transistor T1 may include a TMDC layer 422', a gate structure GS1, and a source / drain contact 472. Transistor T2 may include a TMDC layer 432', a gate structure GS2, and a source / drain contact 472. In some embodiments, the source / drain contact 472 may be referred to as the source / drain electrode. In some embodiments, the portions of TMDC layers 422' and 432' covered by the source / drain contact 472 may be referred to as source / drain regions 422SD and 432SD, a portion of TMDC layer 422' between the source / drain regions 422SD may be referred to as channel region 422C, and a portion of TMDC layer 432' between the source / drain regions 432SD may be referred to as channel region 432C. In some embodiments, transistor T1 is an n-type transistor, and transistor T2 is a p-type transistor. The difference in conductivity type may depend at least on the difference in composition between TMDC layers 422' and 432'.

[0214] refer to Figure 17B and Figures 31 to 35 Method MA proceeds to step AS14, using a similar process and materials as previously discussed regarding the internal interconnect structure 406, to install the interlayer dielectric layer (ILD). X Above, another interconnect structure 490 is formed. For example, the interconnect structure 490 electrically interconnects one or more transistors T1 and T2, and may further electrically interconnect one or more transistor devices 404 on the substrate 402, for example, by using one or more deep through vias extending from the upper interconnect structure 490 to the lower interconnect structure 406. The interconnect structure 490 may include one or more interconnect layers 490I, and each interconnect layer 490I includes an interlayer dielectric layer 490D and a conductive feature (e.g., a conductive via, a conductive line, or a combination thereof) 490M' ​​surrounded by the interlayer dielectric layer 490D. The interconnect structure 490 may also include an etch stop layer 490E located between two adjacent interconnect layers 490I.

[0215] refer to Figure 31An interlayer dielectric layer 490D is deposited on contact 472 and conductive plug 474. In some embodiments, the interlayer dielectric layer 490D may comprise silicon oxide, PSG, BSG, BPSG, USG, low-k dielectrics (e.g., FSG, silicon carbide (SiOCH), carbon-doped oxide (CDO), flowable oxides or porous oxides (e.g., xerogel / aerogel)), or combinations thereof. The interlayer dielectric layer 490D can be deposited using any suitable method, such as CVD, PVD, ALD, PEALD, PECVD, SACVD, FCVD, spin coating, etc., or combinations thereof. In some embodiments, an etch stop layer 490E is deposited on contact 472 and conductive plug 474 prior to the deposition of the interlayer dielectric layer 490D.

[0216] refer to Figure 32 In the interlayer dielectric layer 490D, an opening O3 is etched. Opening O3 can be a via opening, a trench opening, or a combination thereof. A substrate removal etching process can be performed to remove a portion of the etch stop layer 490E exposed by opening O3. The formed opening O3 can extend through the interlayer dielectric layer and the etch stop layer 490E, exposing some contacts 472 and conductive plugs 474.

[0217] refer to Figure 33 Conductive material 490M is deposited into the opening O3 in the interlayer dielectric layer 490D. Conductive material 490M may comprise conductive filler material 490Ma and a liner 490Mb. Conductive filler material 490Ma may comprise W, Al, Cu, Ru, Ni, Co, alloys thereof, combinations thereof, etc. Any acceptable deposition technique can be used to deposit conductive filler material 490Ma, such as CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, etc., or any combination thereof. Prior to depositing conductive filler material 490Ma, liner 490Mb may be conformally deposited on the opening O3. Liner 490Mb may comprise a barrier metal to reduce the diffusion of conductive material from the contact outwards into the surrounding dielectric material. Liner 490Mb may comprise a material different from conductive filler material 490Ma. For example, liner 490Mb may comprise TiN, TaN, Ta, or other suitable metals or alloys thereof.

[0218] refer to Figure 34A planarization process (e.g., CMP) is performed to remove excess conductive material (e.g., substrate 490Mb and conductive filler 490Ma) from the surface of the interlayer dielectric layer 490D. The remaining conductive material forms conductive features 490M' ​​in the opening O3. Depending on the shape of the opening O3, the conductive features 490M' ​​can be conductive vias, wires, or a combination thereof. Through these steps, an inner interconnect layer 490I comprising the interlayer dielectric layer 490D and the conductive features 490M' ​​is formed.

[0219] refer to Figure 35 ,exist Figure 31 In terms of structure, an upper inner interconnect layer 490I is formed. The formation of the upper inner interconnect layer 490I is similar to... Figures 31 to 34 The process shown. Through these steps, an internal interconnect structure 490 comprising multiple internal interconnect layers 490I is formed. Depending on the shape of the opening O3' etched in the interlayer dielectric layer 490D of the upper internal interconnect layer 490I, the conductive feature 490M' ​​of the upper internal interconnect layer 490I can be a conductive via, a wire, or a combination thereof. For example, in Figure 35 In the process, since the opening O3' in the interlayer dielectric layer 490D etched in the upper inner interconnect layer 490I is a combination of via opening and trench opening, the conductive feature 490M' ​​of the upper inner interconnect layer 490I is a combination of conductive via and wire.

[0220] Figure 36 This is a flowchart of a method MB for forming an integrated circuit device according to a partial embodiment of the present disclosure. Figures 37 to 43 This illustration depicts a method for forming an integrated circuit device according to a partial embodiment of this disclosure. Method MB may include steps BS1 to BS7. It will be understood that... Figure 36 Additional steps are provided before, during, and after steps BS1 to BS7, and some steps described below may be replaced or eliminated for other implementations of the method. The order of operations / processes may be interchanged.

[0221] Reference Figure 36 and Figure 37 The method MB begins with step BS1, which provides a substrate with an internal interconnection structure. Figure 37 A cross-sectional view of the intermediate structure of wafer W during integrated circuit manufacturing is shown. Figure 37In this embodiment, the semiconductor wafer W is an intermediate structure in the integrated circuit manufacturing process, in which transistors and interconnect structures have already been formed. In some embodiments, the semiconductor wafer W may include a substrate 402 and one or more active and / or passive devices 404 formed thereon. An interconnect structure 406 is formed on one or more active and / or passive devices 404 and the substrate 402. The interconnect structure 406 electrically interconnects one or more active and / or passive devices 404 to form functional circuitry within the semiconductor structure. The interconnect structure 406 includes one or more interconnect layers 406I, each interconnect layer 406I including an interlayer dielectric layer 406D and a conductive feature 406M (e.g., a conductive via, a wire, or a combination thereof) 406D surrounded by the interlayer dielectric layer. Other details regarding the interconnect structure 406, devices 404, and substrate 402 have been described above and will not be repeated here.

[0222] Interlayer dielectric layer (ILD) X Deposited above the internal interconnect structure 406. Interlayer dielectric layer (ILD) X The materials may include silicon oxide, PSG, BSG, BPSG, USG, low-k dielectrics (e.g., FSG, silicon carbide (SiOCH), carbon-doped oxide (CDO), flowable oxides, or porous oxides (e.g., degel / aerogel)) or combinations thereof. The dielectric material used to form the first and second interlayer dielectric layers can be deposited using any suitable method, such as CVD, PVD, ALD, PEALD, PECVD, SACVD, FCVD, spin coating, and / or other similar methods or combinations thereof. In some embodiments, the interlayer dielectric layer (ILD) is deposited... X Previously, an etch stop layer 406E was deposited on the inner interconnect layer 406I. The etch stop layer 406E may contain a different layer than the interlayer dielectric layer (ILD). X The dielectric material. For example, the etch stop layer 406E may comprise silicon nitride, silicon carbide, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, or combinations thereof.

[0223] refer to Figure 36 and Figure 38 The method MB proceeds to step BS2, where the interlayer dielectric layer ILD... X In the process, the opening O4 is etched. The etching process can include trench etching and via etching. For example, a trench etching process is first performed to remove the interlayer dielectric (ILD). X This forms part of the trench portion OT, creating the opening O4. Subsequently, a via etching process is performed to remove the interlayer dielectric layer (ILD). X This forms part of the via portion OV, thus creating the opening O4. For the via etching process, the etch stop layer 406E can have a higher dielectric density than the interlayer dielectric layer ILD. XHigher etch resistance, thus protecting the underlying material from etching during the via etching process. A suitable substrate removal process can be performed to remove a portion of the etch stop layer 406E after the via etching process, so that the opening O4 can expose the underlying conductive features 406M.

[0224] refer to Figure 36 and Figure 39 In step BS3 of method MB, a metal thin film 510 is deposited on the interlayer dielectric layer ILD. X It then enters the opening O4. A conformal metal film 510 can be deposited so that the metal film 510 is aligned with the sidewalls of the opening O4, the exposed upper surface of the conductive feature 406M, and the ILD layer. X The upper surface is aligned. The metal thin film 510 may contain transition metals such as Mo, W, Pd, Pt, the like, or combinations thereof. The deposition of the metal thin film 510 may include PVD (e.g., electron gun evaporation deposition or thermal evaporation deposition), ALD, CVD, similar methods, or combinations thereof.

[0225] refer to Figure 36 and Figure 40 Method MB proceeds to step BS4, where plasma treatment is performed to form a chalcogenide metal thin film 510 (see...). Figure 39 As before. Figures 1A to 6A As shown, the plasma treatment can use microwave plasma P1 containing chalcogens brought in by the gas flow CG. Through plasma treatment, the metal thin film 510 is transformed into a TMDC layer 510', which has high channel mobility, high current on / off ratio, and good subthreshold swing. For example, in a partial embodiment where the metal thin film 510 is a Mo layer, the formed TMDC layer 510' is a MoS2 layer.

[0226] Reference Figure 36 and Figure 41 Method MB proceeds to step BS5, where conductive filler material 520 is filled through opening O4. Conductive filler material 520 may comprise W, Al, Cu, Ru, Ni, Co, alloys thereof, combinations thereof, and the like. Any acceptable deposition technique can be used to deposit conductive filler material 520, such as CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating, similar methods, or combinations thereof.

[0227] refer to Figure 36 and Figure 42 The method MB proceeds to step BS6, where a planarization process (e.g., CMP) is performed to extract the interlayer dielectric layer (ILD). X Remove conductive filler material 520 from the upper surface (see Figure 41 ) and TMDC layer 510' (see Figure 41Excess material. Remaining conductive filler material 520 (see...) Figure 41 A conductive feature 520' is formed in opening O3. Depending on the shape of opening O4, the conductive feature 520' can be a conductive via, a wire, or a combination thereof. The remaining TMDC layer 510' (see...) Figure 41 This can be used as a barrier layer 510” to prevent metal diffusion. The barrier layer 510” connects the conductive feature 520’ to the interlayer dielectric layer ILD. X Separated. In this embodiment, the barrier layer 510” also separates the conductive feature 520’ from the conductive feature 406M. In some embodiments, the patternable metal film 510 (see reference) Figure 39 A barrier layer 510" is used to expose the conductive feature 406M, allowing the conductive feature 520' to be in direct contact with the conductive feature 406M. In some embodiments, one of the conductive features 520' and one of the barrier layers 510" may be collectively referred to as conductive features, such as conductive vias, wires, or combinations thereof.

[0228] refer to Figure 36 and Figure 43 Method MB proceeds to step BS7, using a similar process and materials as previously discussed regarding the internal interconnect structure 406, to install the interlayer dielectric layer (ILD). X On top, another internal connection structure 490 is formed. The internal connection structure 490 may include one or more internal connection layers 490I, and each internal connection layer 490I includes a dielectric layer 490D and a conductive feature (e.g., a conductive via, a conductive line, or a combination thereof) 490M' ​​surrounded by the dielectric layer 490D. The internal connection structure 490 may also include an etch stop layer 490E located between two adjacent internal connection layers 490I. Other details of this embodiment are similar to those of the embodiments described above and will not be repeated here.

[0229] Based on the above discussion, it is clear that this disclosure offers advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor are specific advantages required for all embodiments. One advantage is that the TMDC layer is directly synthesized and grown on the substrate using a chalcogenination process in a microwave plasma system. Another advantage is that the TMDC layer is synthesized at low temperatures, thereby reducing heat buildup and offering high application potential in back-end processes. Yet another advantage is that the TMDC layer is located on the side of the substrate away from the plasma reactor, so that plasma treatment has little or no effect on the roughness of the formed TMDC layer.

[0230] According to some embodiments disclosed herein, a method for forming an integrated circuit device is provided. The method includes depositing a first transition metal layer on the front side of a substrate; performing a plasma treatment to transform the first transition metal layer into a first transition metal disulfide layer; forming a dielectric layer on the first transition metal disulfide layer; forming a first gate electrode on the dielectric layer and a first portion of the first transition metal disulfide layer; and forming a first source contact and a first drain contact, respectively connecting a second and a third portion of the first transition metal disulfide layer, wherein the first portion of the first transition metal disulfide layer is located between the second and third portions of the first transition metal disulfide layer.

[0231] In some embodiments, the plasma treatment is performed using a plasma reactor, and during the plasma treatment, the front side of the substrate faces away from the plasma reactor.

[0232] In some embodiments, the plasma treatment is performed when the substrate is supported by a substrate support and the front side of the substrate faces the substrate support.

[0233] In some embodiments, the plasma treatment is performed using a microwave plasma, and the temperature of the substrate is below 400°C.

[0234] In some embodiments, the plasma treatment is carried out using a chalcogenide gas.

[0235] In some embodiments, the method further includes forming a transistor on the front side of the substrate; and forming an interconnect structure on the transistor before depositing the first transition metal layer, wherein the first transition metal layer is deposited such that the first transition metal layer is located on the interconnect structure.

[0236] In some embodiments, prior to the plasma treatment, the first transition metal layer is patterned to expose at least a portion of the front side of the substrate.

[0237] In some embodiments, a patterned second transition metal layer is formed on the substrate, wherein the patterned second transition metal layer contains a transition metal element different from the patterned first transition metal layer, and the plasma treatment further transforms the patterned second transition metal layer into a second transition metal disulfide layer; a second gate electrode, a second source contact, and a second drain contact are formed on the dielectric layer and a first portion of the second transition metal disulfide layer, respectively connecting a second portion and a third portion of the second transition metal disulfide layer, wherein the first portion of the second transition metal disulfide layer is located between the second portion and the third portion of the second transition metal disulfide layer.

[0238] According to some embodiments of the present disclosure, a method for forming an integrated circuit device is provided. The method includes forming a non-insulating structure on a front side of a substrate; and forming a conductive structure on the non-insulating structure, wherein forming the conductive structure includes: depositing a transition metal layer on the non-insulating structure; performing a plasma treatment to transform the transition metal layer into a transition metal disulfide layer; and depositing a metal material on the transition metal disulfide layer.

[0239] In some embodiments, the plasma treatment is performed at a plasma frequency higher than 300 MHz.

[0240] In some embodiments, the plasma treatment is performed using a plasma reactor, and during the plasma treatment, a back side of the substrate faces the plasma reactor.

[0241] In some embodiments, the plasma treatment is performed without directly heating the substrate.

[0242] In some embodiments, the method further includes forming a dielectric layer on the non-insulating structure; and etching an opening in the dielectric layer prior to forming the conductive structure, wherein the formation of the conductive structure results in the conductive structure being formed in the opening in the dielectric layer.

[0243] In some embodiments, forming the conductive structure further includes removing a portion of the transition metal disulfide layer and a portion of the metal material located on an upper surface of the dielectric layer.

[0244] In some embodiments, the formation of the conductive structure is such that the transition metal disulfide layer separates the metal material from the dielectric layer.

[0245] In some embodiments, the formation of the conductive structure is such that the transition metal disulfide layer separates the metal material from the non-insulating structure.

[0246] According to some embodiments disclosed herein, an integrated circuit device includes a substrate, a first transition metal disulfide layer, a dielectric layer, a first gate electrode, a first source contact, and a first drain contact. The first transition metal disulfide layer is located above the substrate, wherein the surface roughness of the first transition metal disulfide layer is greater than 0.5 nm and less than 1 nm. The dielectric layer is above the first transition metal disulfide layer. The first gate electrode is located above the dielectric layer and a first portion of the first transition metal disulfide layer. The first source contact and the first drain contact are respectively connected to a second portion and a third portion of the first transition metal disulfide layer, with the first portion of the first transition metal disulfide layer located between the second and third portions of the first transition metal disulfide layer.

[0247] In some embodiments, the elemental composition ratio of chalcogenide elements to transition metal elements in the first transition metal disulfide layer is in the range of 1.9:1 to 2.1:1.

[0248] In some embodiments, the integrated circuit device further includes a transistor, an interlayer dielectric layer, and a contact plug. The transistor is located on the substrate. The interlayer dielectric layer covers the transistor. The contact plug is located in the interlayer dielectric layer and connects to the transistor, wherein the first transition metal dichalcogenide layer is located on an upper surface of the interlayer dielectric layer and an upper surface of the contact plug.

[0249] In some embodiments, the integrated circuit device further includes a second transition metal disulfide layer, a second gate electrode, a second source contact, and a second drain contact. The second transition metal disulfide layer is located on the substrate, wherein the second transition metal disulfide layer has a chalcogenide element identical to that of the first transition metal disulfide layer and a transition metal element different from that of the first transition metal disulfide layer. The second gate electrode is located on the dielectric layer and a first portion of the second transition metal disulfide layer. The second source contact and a second drain contact are respectively connected to a second portion and a third portion of the second transition metal disulfide layer, with the first portion of the second transition metal disulfide layer located between the second and third portions of the second transition metal disulfide layer.

[0250] The foregoing outlines the features of various embodiments, and those skilled in the art will better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can serve as the basis for designing or modifying other programs or structures to achieve the same objectives and / or benefits mentioned in the embodiments. Those skilled in the art should also understand that these equivalent structures do not exceed the spirit and scope of this disclosure, and various changes, substitutions, and transformations can be made; here, the spirit and scope of this disclosure encompasses these changes, substitutions, and transformations.

Claims

1. A method for forming an integrated circuit device, characterized in that, Include: A first transition metal layer is deposited on one side of a substrate; A plasma treatment is performed to transform the first transition metal layer into a first transition metal disulfide layer. The plasma treatment is performed using a plasma reactor, and during the plasma treatment, the front side of the substrate faces away from the plasma reactor. A dielectric layer is formed on the first transition metal disulfide layer; A first gate electrode is formed on a first portion of the dielectric layer and the first transition metal disulfide layer; as well as A first source contact and a first drain contact are formed, which respectively connect a second portion and a third portion of the first transition metal disulfide layer, wherein the first portion of the first transition metal disulfide layer is located between the second portion and the third portion of the first transition metal disulfide layer.

2. The method as described in claim 1, characterized in that, The first transition metal layer contains molybdenum.

3. The method as described in claim 1, characterized in that, The plasma treatment is performed when the substrate is supported by a substrate support and the front side of the substrate faces the substrate support.

4. The method as described in claim 1, characterized in that, The plasma treatment is performed using a microwave plasma, and the temperature of the substrate is below 400°C.

5. The method as described in claim 1, characterized in that, The plasma treatment is carried out using a chalcogenide gas.

6. The method as described in claim 1, characterized in that, Also includes: A transistor is formed on the front side of the substrate; and Before depositing the first transition metal layer, an internal interconnect structure is formed on the transistor, wherein the first transition metal layer is deposited such that the first transition metal layer is located on the internal interconnect structure.

7. The method as described in claim 1, characterized in that, Also includes: Prior to the plasma treatment, the first transition metal layer is patterned to expose at least a portion of the front side of the substrate.

8. The method of claim 7, further comprising: A patterned second transition metal layer is formed on the substrate, wherein the patterned second transition metal layer contains a transition metal element different from the patterned first transition metal layer, and the plasma treatment further causes the patterned second transition metal layer to become a second transition metal disulfide layer. A second gate electrode is formed on a first portion of the dielectric layer and the second transition metal dichalcogenide layer; and A second source contact and a second drain contact are formed, respectively connecting a second portion and a third portion of the second transition metal disulfide layer, wherein the first portion of the second transition metal disulfide layer is located between the second portion and the third portion of the second transition metal disulfide layer.

9. A method for forming an integrated circuit device, characterized in that, Include: A non-insulating structure is formed on one front side of a substrate; A dielectric layer is formed on this non-insulating structure; An opening is etched into the dielectric layer; as well as After etching the opening, a conductive structure is formed in the opening on the non-insulating structure and in the dielectric layer, wherein forming the conductive structure includes: A transition metal layer is deposited on this non-insulating structure; Perform a plasma treatment to transform the transition metal layer into a transition metal disulfide layer; and A metallic material is deposited on the transition metal disulfide layer.

10. The method as described in claim 9, characterized in that, The plasma treatment was performed at a plasma frequency higher than 300 MHz.

11. The method as described in claim 9, characterized in that, The plasma treatment is performed using a plasma reactor, and during the plasma treatment, one back side of the substrate faces the plasma reactor.

12. The method as described in claim 9, characterized in that, The plasma treatment is performed without directly heating the substrate.

13. The method as described in claim 9, characterized in that, The metal material is in contact with the transition metal disulfide layer.

14. The method as described in claim 9, characterized in that, Forming the conductive structure further includes removing a portion of the transition metal disulfide layer and a portion of the metal material located on an upper surface of the dielectric layer.

15. The method as described in claim 9, characterized in that, The formation of this conductive structure causes the transition metal disulfide layer to separate the metal material from the dielectric layer.

16. The method as described in claim 9, characterized in that, The formation of this conductive structure causes the transition metal disulfide layer to separate the metallic material from the non-insulating structure.

17. An integrated circuit device, characterized in that, Include: One substrate; A first transition metal disulfide layer is located on the substrate, wherein the surface roughness of the first transition metal disulfide layer is greater than 0.5 nm and less than 1 nm; A dielectric layer is located on the first transition metal disulfide layer; A first gate electrode is located on a first portion of the dielectric layer and the first transition metal dichalcogenide layer; and A first source contact and a first drain contact are respectively connected to a second portion and a third portion of the first transition metal disulfide layer. The first portion of the first transition metal disulfide layer is located between the second portion and the third portion of the first transition metal disulfide layer. A bottom surface of the first source contact is lower than a bottom surface of the first gate electrode, and a top surface of the first source contact is higher than a top surface of the first gate electrode.

18. The integrated circuit device as claimed in claim 17, characterized in that, The elemental composition ratio of chalcogenide elements to transition metal elements in the first transition metal disulfide layer is in the range of 1.9:1 to 2.1:

1.

19. The integrated circuit device as claimed in claim 17, characterized in that, Also includes: A transistor is located on the substrate; A dielectric layer covers the transistor; and A contact plug is located in the interlayer dielectric layer and connected to the transistor, wherein the first transition metal dichalcogenide layer is located on an upper surface of the interlayer dielectric layer and an upper surface of the contact plug.

20. The integrated circuit device as claimed in claim 17, characterized in that, Also includes: A second transition metal disulfide layer is located on the substrate, wherein the second transition metal disulfide layer has a chalcogenide element that is the same as that of the first transition metal disulfide layer and a transition metal element that is different from that of the first transition metal disulfide layer; A second gate electrode is located on a first portion of the dielectric layer and the second transition metal dichalcogenide layer; and A second source contact and a second drain contact are respectively connected to a second portion and a third portion of the second transition metal disulfide layer, with the first portion of the second transition metal disulfide layer between the second portion and the third portion of the second transition metal disulfide layer.

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