Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same are provided. Doped wells can be formed with less lateral diffusion and less vertical doping using parallel implantation techniques and angled implantation techniques.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is continuously reducing the minimum feature size and increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to some embodiments disclosed herein, a semiconductor device includes a semiconductor substrate, an isolation layer, a first deep well, a first well, a second well, and a third well. The semiconductor substrate includes one or more fins. The isolation layer is above the semiconductor substrate and extends along multiple sidewalls of the one or more fins. The first deep well is in the semiconductor substrate and below the one or more fins, and is doped with a first dopant having a first conductivity type. The first well is in the semiconductor substrate, with the one or more fins in the first well, and is doped with a second dopant having a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type, and the first well is above the first deep well. The second well is in the semiconductor substrate on a first side of the first well. The third well is located on a second side of the first well in the semiconductor substrate, wherein a first side boundary is aligned with a first sidewall of the one or more fins, and a second side boundary is aligned with a second sidewall of the one or more fins. The first sidewall is the sidewall of the one or more fins closest to the second well, and the second sidewall is the sidewall of the one or more fins closest to the third well. The average concentration of the second dopant in a first region of the semiconductor substrate below the one or more fins and between the first and second side boundaries is 5 x 10⁻⁶. 17 atoms / cm 3 Up to 7x10 17 atoms / cm 3 Within a certain range.

[0005] According to some embodiments of this disclosure, a method of forming a semiconductor device includes: forming a patterned mask over a substrate, wherein the patterned mask has an opening over a first portion of the substrate; implanting a first dopant into the substrate at a first angle using a first ion beam, wherein the first ion beam is in a first plane parallel to one side of the first portion in a plan view, wherein the first plane is perpendicular to a top surface of the substrate, wherein the first ion beam impacts the top surface of the substrate at the first angle relative to a line perpendicular to the top surface of the substrate; and implanting the first dopant at a second angle using a second ion beam. In the substrate, the second ion beam is in a second plane parallel to the side of the first portion in a plan view, the second plane is perpendicular to the top surface of the substrate, the second ion beam strikes the top surface of the substrate at the second angle relative to the line perpendicular to the top surface of the substrate, the first ion beam and the second ion beam are on opposite sides of the line perpendicular to the top surface of the substrate, a first well is formed by implanting with the first ion beam and implanting with the second ion beam; and the substrate is etched to form one or more fins in the first well, wherein a maximum concentration of the first dopant is lower than a bottom of the one or more fins.

[0006] According to some embodiments of this disclosure, a method of forming a semiconductor device includes: forming a first patterned mask over a substrate, wherein the first patterned mask has a first opening above a top surface of a first portion of the substrate; performing a first implantation on the first portion of the substrate with a first dopant, wherein a first ion beam of the first implantation forms a first acute angle with respect to the top surface of the first portion of the substrate, the first ion beam being substantially parallel to a plane perpendicular to the top surface of the substrate, the plane including a longitudinal side of the first portion of the substrate; rotating the substrate 180 degrees after performing the first implantation; and performing a second implantation on the first portion of the substrate with the first dopant, wherein a second ion beam of the second implantation forms a second acute angle with respect to the top surface of the first portion of the substrate, the second ion beam being substantially parallel to the plane perpendicular to the top surface of the substrate, the plane including the longitudinal side of the first portion of the substrate. Attached Figure Description

[0007] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 The illustration shows an example of a nanostructured field-effect transistor (nanoFET) in a three-dimensional view according to some embodiments;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 5C , Figure 6 , Figure 7A , Figure 7B , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 26A , Figure 26B , Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 28C , Figure 29A , Figure 29B , Figure 29C , Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B , Figure 32A , Figure 32B ,and Figure 32C The illustration shows various intermediate stages in the fabrication of nanoFETs according to some embodiments;

[0010] Figure 8A and Figure 8B The figure shows a curve illustrating the relationship between doping concentration and distance.

[0011] [Symbol Explanation]

[0012] 10: Substrate

[0013] 10N: n-type region

[0014] 10P: p-type region

[0015] 12: Masking layer

[0016] 14: Alignment Marks

[0017] 16: Deep n-well area

[0018] 18: Implantation of a mask

[0019] 20: Opening

[0020] 22: Implantation of a mask

[0021] 24: p-type well

[0022] 26: Opening

[0023] 28: Ion Beam

[0024] 30: n-type well

[0025] 31: District

[0026] 32: Doping Concentration Profile

[0027] 33: District

[0028] 34: Implantation of a mask

[0029] 35: District

[0030] 36: Opening

[0031] 37: District

[0032] 38: Passage

[0033] 51A~51C: First semiconductor layer

[0034] 52A~52C: First Nanostructure

[0035] 53A~53C: Second semiconductor layer

[0036] 54A~54C: Second nanostructure

[0037] 55: Nanostructures

[0038] 64: Multi-layer stacking

[0039] 66: Fins

[0040] 68: STI Zone

[0041] 70: Dummy dielectric layer

[0042] 71: Dummy gate dielectric layer

[0043] 72: Dummy gate layer

[0044] 74: Masking layer

[0045] 76: Dummy gate

[0046] 78: Mask

[0047] 80: First spacer layer

[0048] 81: First spacer

[0049] 82: Second spacer layer

[0050] 83: Second spacer

[0051] 86: First Groove

[0052] 88: Sidewall groove

[0053] 90: First internal spacer

[0054] 92: Epitaxial source / drain region

[0055] 92A: First semiconductor material layer

[0056] 92B: Second semiconductor material layer

[0057] 92C: Third semiconductor material layer

[0058] 94: CESL

[0059] 96: First ILD

[0060] 98: Second groove

[0061] 100: Gate dielectric layer

[0062] 102: Gate electrode / gate structure

[0063] 104: Gate mask

[0064] 106: Second ILD

[0065] 108: Third Groove

[0066] 110: Silicide region

[0067] 112: Contact

[0068] 114: Contact

[0069] AA': Cross-section

[0070] BB': Cross-section

[0071] CC': Cross-section

[0072] DD' : line

[0073] D B : distance

[0074] D C : distance

[0075] D T : distance

[0076] EE' : line

[0077] FF' : line

[0078] GG' : line

[0079] HH': Line

[0080] II' : Line

[0081] JJ' : line

[0082] α: First tilt angle

[0083] β: Second tilt angle Detailed Implementation

[0084] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0085] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0086] As discussed in more detail below, embodiments disclosed herein describe dopant implantation processes for forming p-type and / or n-type wells in a substrate, which can be used to form transistors (e.g., nanoFETs, fin field-effect transistors (FinFETs), planar transistors, or the like). The techniques described herein include tilting and twisting or rotating the substrate during the implantation process to modulate the doping concentration profile in the p-type and n-type wells. Embodiments such as those described herein can produce doping concentration profiles characterized by less vertical and lateral dispersion of the dopant, and the dopant depositing at a shallow depth in a small region below the substrate surface. Such doping concentration profiles can provide reduced depletion region clamping in the p-type and n-type wells, resulting in greater resistance along the junction leakage path, thereby reducing junction leakage from the source and drain regions to the substrate (e.g., adjacent wells), which may be ideal for transistors with small critical dimensions of p-type and n-type wells. Embodiments are described below in a specific context, namely, a die containing a nanoFET. However, various embodiments may be adapted to include other types of transistors, such as FinFETs, planar transistors, or the like, in place of nanoFETs or dies combined with nanoFETs.

[0087] Figure 1The illustration shows an example of a nanoFET (e.g., a nanowire FET, a nanosheet FET, or the like) in a three-dimensional view according to some embodiments. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, nanowire, or the like) above fins 66 on a substrate 10 (e.g., a semiconductor substrate), wherein the nanostructure 55 acts as a channel region of the nanoFET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 68 are disposed between adjacent fins 66, which may protrude above and between adjacent isolation regions 68. Deep n-well regions 16 are disposed in the substrate 10. Although the isolation regions 68 are described / illustrated as separate from the substrate 10, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fins 66 is illustrated as a single continuous material like the substrate 10, the bottom portion of the fins 66 and / or the substrate 10 may comprise a single material or multiple materials. In this case, fins 66 refer to the portion extending between adjacent isolation regions 68.

[0088] The gate dielectric layer 100 is above the top surface of the fin 66 and extends along the top surface, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66, on the opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0089] Figure 1 Further illustrations are provided for the reference cross sections used in the following figures. Cross section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. Cross section B-B' is substantially perpendicular to cross section A-A' and substantially parallel to the longitudinal axis of the fin 66 of the nanoFET, and in a direction, for example, between the epitaxial source / drain regions 92 of the nanoFET, within the process variation range. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions of the nanoFET. For clarity, the following figures refer to these reference cross sections.

[0090] Some embodiments discussed herein are presented in the context of nanoFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are considered for use in other devices, such as planar FETs or FinFETs.

[0091] Figures 2 to 32C The illustration shows various intermediate stages in the fabrication of nanoFETs according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 7A , Figure 7B , Figure 9 , Figure 10 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A ,and Figure 32A Illustration Figure 1 The reference cross section A-A' is shown in the figure. Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 21C , Figure 22B , Figure 22D , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B ,and Figure 32B Illustration Figure 1 The reference cross section B-B' is shown in the figure. Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 22C , Figure 23C , Figure 28C , Figure 29C , Figure 30C , Figure 31A , Figure 31B ,and Figure 32C Illustration Figure 1 The reference cross section C-C' shown is illustrated.

[0092] First refer to Figure 2 According to some embodiments, a substrate 10 is shown having a masking layer 12 formed thereon. The substrate 10 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 10 may be a wafer, such as a silicon wafer. Figure 2The following figures illustrate a portion of the wafer to better illustrate features of some embodiments. Similar structures and processes can be applied over a larger portion of the wafer. Typically, the SOI substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 10 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0093] A mask layer 12 is formed over the substrate 10 and patterned to form alignment marks 14. These alignment marks can be used to align the wafer in subsequent processes. According to some embodiments, the mask layer 12 may be formed of silicon oxide, which can be formed by oxidizing a surface layer of the semiconductor substrate 10. In some embodiments, the mask layer 12 may be formed via deposition, for example using atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), or similar methods. The alignment marks 14 may be formed on the substrate 10 and the mask layer 12 by etching using optical lithography. The depth of the alignment marks 14 may be in the range of about 100 nm to about 150 nm (e.g., about 120 nm) below the top surface of the substrate 10, and the width of the alignment marks 14 may be in the range of about 1 µm to about 1.5 µm (e.g., about 1.5 µm). In some embodiments, the mask layer 12 may be removed.

[0094] According to some embodiments, a p-type ion implantation process is performed to lightly dope the substrate. The p-type dopant may include, for example, boron, indium, the like, or combinations thereof. The p-type ion implantation process may include one or more blanket implantation processes and may be performed using energies in the range of about 180 keV to about 240 keV. The p-type implantation process may provide a p-type region in the substrate, which may act as a deep p-type well (not shown separately), spaced from the top surface of the substrate 10 at a distance of about 0.8 µm to about 1.2 µm. The p-type doping concentration may be equal to or less than 1 x 10⁻⁶. 17 cm -3 Such as in approximately 1x10 16 cm -3 To approximately 1x10 17 cm -3Within the range. Annealing can be used to repair implant damage and revitalize implant impurities. Annealing can be performed at temperatures ranging from about 1000°C to about 1100°C (such as about 1050°C) for a duration of about 1 second to about 20 seconds (such as about 10 seconds).

[0095] refer to Figure 3 According to some embodiments, an implantation mask 18 is formed and n-type ion implantation is performed to form a deep n-well region 16. The implantation mask 18 may be formed of a material capable of substantially blocking ions during subsequent implantation processes. In some embodiments, the implantation mask 18 is formed of a photoresist, which is coated and then patterned using optical lithography to form an opening 20. According to some embodiments, the implantation mask 18 may be used to perform one or more n-type ion implantation processes to form the deep n-well region 16.

[0096] Figure 3 The following figures illustrate a portion of the substrate 10 used to form the deep n-well region 16 and a portion of the implantation mask 18 for illustrative purposes. It should be understood that the implantation mask 18 may extend over other portions of the substrate 10 and may include additional openings 20 to form additional deep n-well regions 16 in other portions of the substrate 10. The n-type dopant may include phosphorus, arsenic, antimony, the like, or combinations thereof. n-type ion implantation can be performed using energies in the range of about 600 keV to about 800 keV. The deep n-well region 16 is formed deep within the substrate 10, with the top of the deep n-well region 16 spaced from the top surface of the substrate 10 at a distance of about 0.9 µm to about 1.1 µm. Figure 3 As shown, due to the implantation process, the deep n-well region 16 can extend laterally beyond the lateral edge of the opening 20. The n-type doping concentration can be equal to or less than 1 x 10⁻⁶. 17 cm -3 Such as in approximately 1x10 16 cm -3 To approximately 1x10 17 cm -3 Within the range. For example, in some embodiments, the implant mask 18 can be removed by an acceptable ashing process, and annealing can be used to repair implant damage and activate implant impurities. Annealing can be performed at a temperature in the range of about 1000°C to about 1100°C (such as about 1025°C) for a duration of about 1 second to about 20 seconds (such as about 10 seconds).

[0097] refer to Figure 4According to some embodiments, an implantation mask 22 is formed and a p-type ion implantation process is performed to form a p-type well 24. The p-type well 24 provides an active region in the substrate 10 for fabricating an n-type metal-oxide-semiconductor (NMOS) device, as discussed in more detail below. The implantation mask 22 may be formed of a material capable of substantially blocking ions during subsequent implantation processes. In some embodiments, the implantation mask 22 is formed of a photoresist, which is coated and then patterned using optical lithography to form an opening 26. According to some embodiments, the implantation mask 22 may be used to perform one or more p-type ion implantation processes to form the p-type well 24. For illustrative purposes, Figure 4 The following figures illustrate a portion of substrate 10 and a portion of implantation mask 22, including a p-type well 24. It should be understood that implantation mask 22 may extend over other portions of substrate 10 and may include additional openings 26 to form additional p-type wells 24 in other portions of substrate 10. P-type dopants may include boron, indium, the like, or combinations thereof. P-type ion implantation can be performed using energies in the range of about 2 keV to about 100 keV. Implantation temperatures may range from about -60 °C to about 450 °C. The p-type well 24 may extend to the top surface of substrate 10 and may extend into a deep n-well region 16. Figure 4 As shown, due to diffusion during the implantation process, the p-type well 24 can extend laterally beyond the lateral edge of the opening 26. The p-type doping concentration in the p-type well 24 can be equal to or less than 1 x 10⁻⁶. 20 cm -3 Such as in approximately 1x10 17 cm -3 To approximately 1x10 20 cm -3 Within the range. In some embodiments, the implant mask 22 may be removed, for example, by an acceptable ashing process, and annealing may be used to repair implant damage and activate implant impurities. Annealing may be performed at a temperature in the range of about 1000°C to about 1100°C (such as about 1050°C) for a duration of about 1 second to about 20 seconds (such as about 10 seconds).

[0098] According to some embodiments, the implantation process for forming the p-shaped well 24 may include performing a first implantation, twisting or rotating the substrate 10 180 degrees relative to the ion beam, and performing a second implantation, such as... Figures 5A to 5C As shown, the substrate 10 is depicted as a wafer shape with flat edges, and the masking layer 12 and alignment marks 14 are omitted for illustrative purposes. Figure 5A As shown, the first step of the implantation process involves performing a first implantation while keeping the substrate 10 stationary. Figure 5B As shown, the second step of the implantation process involves twisting or rotating the wafer by 180 degrees, and as... Figure 5C As shown, the third step of the implantation process includes performing a second implantation while keeping the substrate 10 stationary.

[0099] According to some embodiments, the first and second implants may utilize a parallel implantation technique, in which the ion beam 28 is configured substantially parallel to the longitudinal sidewall of the opening 26 in a plan view, such as... Figure 5A and Figure 5C As shown, this is within the range of process variations. Furthermore, Figure 6 A perspective view is provided illustrating the implantation steps for forming a p-shaped well 24 using a parallel implantation technique. For illustrative purposes, Figure 6 A portion of the implantation mask 22 is omitted. When using parallel implantation technology, the ion beam 28 is in a plane that is substantially parallel (within the range of process variations) to a plane perpendicular to the top surface of the substrate 10 and the mask layer 12, including the interface between the longitudinal sidewall of the implantation mask 22 and the top surface of the underlying layer (e.g., the mask layer 12 in this example).

[0100] According to some embodiments, the first and second implants may further utilize tilted implantation techniques. For example... Figure 6 As shown, the implantation of the p-shaped well 24 can be performed with the ion beam 28 at a first tilt angle α relative to a line perpendicular to the top surface of the substrate 10 and the masking layer 12. The first tilt angle α can be in the range of greater than 0° to about 15°, such as about 7°. In other words, the implantation of the p-shaped well 24 can be performed with the ion beam 28 at a second tilt angle β relative to the top surface of the substrate 10 and the masking layer 12. The second tilt angle β can be in the range of about 75° to less than 90°, such as about 83°.

[0101] The embodiments described herein provide a way to reduce Figure 31A The interface leakage in the complete device shown is for p-type well 24 and n-type well 30 (see Figure 7A and Figure 7B The doping concentration profile of the p-type well 24 is determined. In some embodiments, parallel implantation and tilted implantation techniques may be applied alone or in combination to achieve the desired doping concentration profile during well formation. In the case of forming the p-type well 24 as described above, the ion beam 28 is configured substantially parallel (within the process variation range) to the interface between the p-type well 24 and the projected n-type well 30 (e.g., see...). Figure 7A This reduces the amount of ion implantation below the implantation mask 22, thereby reducing the lateral dispersion of p-type dopants toward adjacent regions, such as adjacent projected n-type wells 30. This allows for the formation of narrower p-type wells 24. Configuring the ion beam 28 at a second tilt angle β relative to the top surface of the substrate 10 and the mask layer 12 reduces dopant channeling in the lattice of the substrate 10 and reduces the vertical dispersion of dopants to a greater depth below the top surface of the substrate 10, thus preventing dopant accumulation at a smaller depth below the top surface of the substrate 10.

[0102] Figure 7A The illustrations are based on some embodiments. Figure 4 The doping concentration profile 32 of the p-type well 24 shown is illustrated. The doping concentration profile 32 includes regions A, B, and C, where regions A, B, and C represent relative doping concentration profiles 32 of the p-type well 24 achievable using the described technique. Region C represents a region with a relatively high doping concentration, region B represents a region with a doping concentration lower than region C, and region A represents a region with a doping concentration lower than region B. For illustrative purposes, Figure 7A The diagram illustrates three distinct regions to show the relative concentration and general shape or outline of the doped regions, as well as the dopant stacking and dispersion pattern of dopant concentration profile 32 using the techniques discussed herein. In some embodiments, dopant concentration profile 32 may be illustrated as having more or fewer regions. Regions A, B, and C illustrate that the dopant concentration may extend outward from region C in a gradient. Furthermore, Figure 7A The doping concentration profile 32 shown in the figure has a higher slope in the horizontal direction than in the vertical direction, as illustrated by comparing the widths of regions A and B in the horizontal direction with the widths of regions A and B in the vertical direction. In some embodiments, the p-type doping concentration in region A can be approximately 1.6 x 10⁻⁶. 17 atoms / cm 3 To approximately 2.7x10 17 atoms / cm 3 Within that range, such as approximately 2.2 x 10 17 atoms / cm 3 The p-type doping concentration in region B can be approximately 2.7 x 10⁻⁶. 17 atoms / cm 3 To approximately 7.4x10 17 atoms / cm 3 Within a range, such as approximately 4.5 x 10 17 atoms / cm 3 Furthermore, the p-type doping concentration in region C can be approximately 7.4 x 10⁻⁶. 17 atoms / cm 3 To approximately 1.2 x 10 18 atoms / cm 3 Within a range, such as approximately 1x10 18 atoms / cm 3 .

[0103] Figure 7AFurther illustration shows lines D-D', E-E', and F-F' extending vertically through opening 26, masking layer 12, and p-type well 24. Line D-D' is equidistant from the two sidewalls of opening 26. Lines E-E' and F-F' are aligned with the opposite sidewalls of opening 26 and are parallel to line D-D'. Using techniques discussed herein, such as parallel implantation techniques, the distance from line E-E' (representing the boundary of opening 26) to the outer boundary of the implantation region (represented by doping concentration profile 32) is reduced, thereby limiting the amount of p-type dopant implanted or diffused into adjacent regions (such as adjacent n-type well 30). For example, in some embodiments, arranging the ion implantation beam substantially parallel to the sidewalls of the implantation mask 22 can limit the lateral dimension of the doping concentration profile to below 50 nm from line E-E'.

[0104] Figure 7A The diagram also illustrates region 31, which covers region C. Region 31 is a region with a high doping concentration. As discussed in more detail below, substrate 10 may be etched to form fin 66, and in some embodiments, the depths of region 31 and region C are adjusted such that region 31 and region C remain beneath the fin 66 subsequently formed in the substrate. In some embodiments, region 31 may have approximately 5 x 10 mm. 17 atoms / cm 3 Approximately 7x10 17 atoms / cm 3 Average p-type doping concentration within the range. Figure 7A As illustrated, the parallel implantation and tilted implantation techniques discussed in this paper reduce the vertical and lateral dispersion of p-type dopants, thereby creating p-type dopant accumulation within region 31. References will follow below. Figure 31B Let's discuss the location of section 31 in more detail.

[0105] Figure 7A The diagram also illustrates region 33 located below region 31. In some embodiments, region 33 is located below region 31, within a range of approximately 400 nm to approximately 600 nm below the bottom of region 31, and may have an area of ​​approximately 0.5 x 10⁻⁶. 17 atoms / cm 3 To approximately 1x10 17 atoms / cm 3 The average p-type doping concentration within the range indicates less vertical dispersion of p-type dopants within region 33.

[0106] Figure 7A Further illustration shows that the doping concentration profile 32 exhibits less lateral diffusion and dispersion. For example, region 35 is positioned along the top surface of substrate 10, above the lateral protrusion of doping concentration profile 32, and laterally adjacent to the top region of doping concentration profile 32. Figure 7AAlso illustrated is region 37, located above region 33, below the lateral protrusion of doping concentration profile 32, and laterally adjacent to the bottom region of doping concentration profile 32. Regions 35 and 37 are below implantation mask 22 and have less dopant due to the use of implantation techniques such as those described herein. In some embodiments, the p-type doping concentration in region 35 may be less than 2.7 x 10⁻⁶. 17 atoms / cm 3 This indicates that the p-type dopant is less laterally dispersed towards the projected n-type well 30 at smaller depths. In some embodiments, the p-type doping concentration in region 37 may be less than 1.6 x 10⁻⁶. 17 atoms / cm 3 This indicates that the p-type dopant is less laterally dispersed toward the projected n-type well 30 at greater depths.

[0107] Figure 7B Diagram and Figure 7A The same doping concentration profile 32 of the p-type well 24 shown is used, with reference lines D-D', G-G', H-H', I-I', and J-J' added. Figure 8A and Figure 8B A doping concentration profile is provided along the reference line shown. Line D-D' extends vertically through the center of opening 26, while lines G-G', H-H', I-I', and J-J' are perpendicular to line D-D' at different depths. Line H-H' extends horizontally through the horizontal center of regions A, B, and C of the doping concentration profile 32, while line G-G' extends horizontally through p-type well 24 to a depth approximately midway between line H-H' and the top surface of substrate 10. Line I-I' extends horizontally from the top surface of substrate 10 to a depth 1.5 times the depth of line H-H'. Line J-J' extends horizontally from the top surface of substrate 10 to a depth 1.75 times the depth of line H-H'. For example, in some embodiments, line H-H' is at a depth of about 150 nm to about 250 nm (such as about 200 nm) below the top surface of substrate 10; line G-G' is at a depth of about 75 nm to about 125 nm (such as about 100 nm) from the top surface of substrate 10; line I-I' is at a depth of about 275 nm to about 325 nm (such as about 300 nm) from the top surface of substrate 10; and line J-J' is at a depth of about 330 nm to about 370 nm (such as about 350 nm) from the top surface of substrate 10.

[0108] Figure 8A Display doping concentration as along Figure 7BThe curve shown is a function of the depth of line D-D' below the top surface of substrate 10. In some embodiments, the magnitude of the slope of the concentration profile from line G-G' to line H-H' (where concentration changes with depth) may be greater than the magnitude of the slope from the top surface of substrate 10 to line G-G'. In other words, the first slope of the curve from line G-G' to line H-H' is steeper than the second slope of the curve from the start point of the curve to line G-G'. In some embodiments, the magnitude of the slope from line H-H' to line I-I' may be greater than the magnitude of the slope from line I-I' to line J-J'. In other words, the third slope of the curve from line H-H' to line I-I' is steeper than the fourth slope of the curve from line I-I' to line J-J'. In some embodiments, the peak of the curve is between lines G-G' and I-I', and the slope from the peak is relatively steep, indicating that dopant has accumulated between lines G-G' and I-I'. In some embodiments, the curve shows a relatively sharp drop outside the J-J' line, which also indicates that the dopant has accumulated above the J-J' line.

[0109] Figure 8B Curves A, B, and C are displayed, representing the doping concentration as a function of curves along the curves. Figure 7B The lines G-G', H-H', and J-J' shown are functions of the distance from the left interface between the p-type well 24 and the projected n-type well 30 to the right interface between the p-type well 24 and the projected n-type well 30. In some embodiments, curve A may also represent the doping concentration as a function of the distance along line I-I' from the left interface between the p-type well 24 and the projected n-type well 30 to the right interface between the p-type well 24 and the projected n-type well 30. Figure 8B As shown, curve B, which extends through the horizontal center of the high-concentration region of region C, shows the doping concentration profile increasing to a high, flat peak centered on line D-D'.

[0110] Curves A and C extend to zones 35 and 37 respectively (see...) Figure 7A and Figure 7B The illustration shows a doped profile with relatively few dopants at the side boundaries and a steep slope that increases sharply to a relatively low and flat peak. For reference, Figure 8B Lines E-E' and F-F' are added to indicate the internal locations of regions 35 and 37. The relatively low and flat peak between lines E-E' and F-F' is a result of tilted implantation during the doping of p-type well 24, indicating less vertical dispersion into these individual regions. The steep slope extending from the relatively low and flat peak near lines E-E' and F-F' is a result of parallel implantation during the doping of p-type well 24, indicating less lateral dispersion into these individual regions.

[0111] In some embodiments, between line E-E' and line D-D', the slope of curve B is greater than the slope of curve A and the slope of curve C, and between line D-D' and line F-F', the slope of curve B is greater than the slope of curve A and the slope of curve C. In some embodiments, the highest point of curve B is higher than the highest points of curves A and C, while the highest point of curve A is higher than the highest point of curve C. For example, the highest point of curve A is about 30% to about 40% of the highest point of curve B, while the highest point of curve C is about 20% to about 30% of the highest point of curve B. In some embodiments, the lowest point of curve B is higher than the lowest point of curves A and B, while the lowest point of curve A is approximately the same as the lowest point of curve C. In some embodiments, the lowest point of curve B is approximately the same as or greater than the highest point of curve C. In other words, between line E-E' and line F-F', curve B has a high and sharp peak, while curves A and C have low and flat peaks. This is the result of using tilted implantation technology during doping of p-type well 24, indicating dopant accumulation between line E-E' and line F-F' and at a depth of approximately line H-H'.

[0112] refer to Figure 9 According to some embodiments, implantation mask 22 is removed, and implantation mask 34 is formed, and an n-type ion implantation process is performed to form an n-type well 30. The n-type well 30 provides an active region in the substrate 10 for fabricating a p-type metal-oxide-semiconductor (PMOS) device, as discussed in more detail below. Implantation mask 34 may be formed of a material capable of substantially blocking ions during subsequent implantation processes. In some embodiments, implantation mask 34 is formed of a photoresist, which is coated and then patterned using optical lithography to form an opening 36. One or more n-type ion implantation processes may be performed using implantation mask 34 to form the n-type well 30. In some embodiments, the n-type well 30 may be formed in a similar manner to that described above with reference to forming p-type well 24 to achieve the same or similar doping concentration profile in the n-type well 30 as described above with reference to p-type well 24. For example, the n-type well 30 can be formed by performing a first implantation with an ion beam (which is substantially parallel to the interface between the p-type well 24 and the projected n-type well 30 and at a second tilt angle β relative to the top surface of the substrate 10 and the masking layer 12), twisting or rotating the wafer 180 degrees relative to the ion beam, and performing a second implantation similar to the first implantation. Figure 9The following figures illustrate a portion of a substrate 10 containing two n-wells 30. Further n-wells 30 may be formed in other portions of the substrate 10, but are not shown. The n-type dopant may include phosphorus, arsenic, antimony, the like, or combinations thereof. n-type ion implantation can be performed using energy lower than that required to form the deep n-well region 16, such as in the range of about 5 keV to about 400 keV. The implantation temperature may be in the range of about -60 °C to about 450 °C. The n-wells 30 extend to the top surface of the substrate 10 and may extend into the deep n-well region 16. Figure 9 As shown, due to the implantation process, the n-type well 30 can extend laterally beyond the lateral edge of the opening 36. The n-type doping concentration in the n-type well 30 can be equal to or less than 1 x 10⁻⁶. 20 cm -3 Such as in approximately 1x10 17 cm -3 To approximately 1x10 20 cm -3 Within the range. The implant mask 34 can then be removed, such as through an acceptable ashing process in some embodiments. Afterwards, annealing can be used to repair implant damage and reactivate implant impurities. Annealing can be performed at a temperature in the range of about 1000°C to about 1100°C (e.g., about 1050°C) for a duration of about 1 second to about 20 seconds (e.g., about 10 seconds). For illustrative purposes, Figures 4 to 9 This shows that the p-type well 24 is formed before the n-type well 30 is formed. In some embodiments, the n-type well 30 may be formed before the p-type well 24.

[0113] refer to Figure 10 According to some embodiments, the mask layer 12 is removed by an acceptable etching process. Figure 11 The illustrations are based on some embodiments. Figure 10 A perspective view of a portion of the structure shown. Figure 11 In the structure shown, the top surfaces of the p-type well 24 and the n-type well 30 can be formed into rectangles, and the p-type wells 24 and n-type wells 30 can be alternately arranged adjacent to each other. In some embodiments, the width of the shorter side of the p-type well 24 is in the range of about 90 nm to about 120 nm. In some embodiments, the width of the shorter side of the n-type well 30 is in the range of about 80 nm to about 110 nm.

[0114] like Figure 12 As shown, substrate 10 has an n-type region 10N and a p-type region 10P. The n-type region 10N includes a p-type well 24 and can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nanoFET. The p-type region 10P includes an n-type well 30 and can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nanoFET. For illustrative purposes, Figure 12The illustration shows a p-type well 24 and an adjacent n-type well, and the substrate 10 may include any number of such interfaces. Furthermore, although an n-type region 10N and a p-type region 10P are illustrated, any number of n-type regions 10N and p-type regions 10P may be provided.

[0115] Further in Figure 12 In this embodiment, a multilayer stack 64 is formed above the substrate 10. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as discussed in more detail below, the second semiconductor layers 53 are removed and the first semiconductor layers 51 are patterned to form channel regions for nanoFETs in the p-type region 10P. Furthermore, the first semiconductor layers 51 are removed and the second semiconductor layers 53 are patterned to form channel regions for nanoFETs in the n-type region 10N. However, in some embodiments, the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions for nanoFETs in the n-type region 10N, while the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions for nanoFETs in the p-type region 10P.

[0116] In some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form channel regions of a nano-FET in the n-type region 10N and the p-type region 10P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form non-FET channel regions in the n-type region 10N and the p-type region 10P. In such embodiments, the channel regions in the n-type region 10N and the p-type region 10P may have the same material composition (e.g., silicon, or another semiconductor material) and may be formed simultaneously. Figures 32A to 32C The diagram illustrates a structure resulting from such an embodiment, wherein the channel regions in both the p-type region 10P and the n-type region 10N contain silicon, for example.

[0117] For illustrative purposes, the multilayer stack 64 is illustrated as three layers including each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each of the multilayer stacks 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or similar methods. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for p-type nanoFETs (such as silicon germanium, or the like), while the second semiconductor layer 53 may be formed of a second semiconductor material suitable for n-type nanoFETs (such as silicon, silicon carbon, or the like). For illustrative purposes, the multilayer stack 64 is illustrated as having a bottom semiconductor layer suitable for p-type nanoFETs. In some embodiments, the multilayer stack 64 may be formed such that the bottom layer is a semiconductor layer suitable for n-type nanoFETs. The first semiconductor layer 51 and the second semiconductor layer 53 may be doped in situ or doped using one or more implantation processes.

[0118] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity to each other. Therefore, the first semiconductor layer 51 of the first semiconductor material in the n-type region 10N can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nanoFET. Similarly, the second semiconductor layer 53 of the second semiconductor material in the p-type region 10P can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nanoFET.

[0119] Now for reference Figure 13 According to some embodiments, fins 66 are formed in substrate 10, and nanostructures 55 are formed in multilayer stack 64. The fins 66 protrude from the top surface of substrate 10, and the height of the fins 66 is in the range of about 50 nm to about 70 nm. In some embodiments, the nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 10, respectively, by etching trenches in multilayer stack 64 and substrate 10. As described above, region 31 and / or region C (e.g., a highly doped region) remain in the substrate beneath the fins 66, which can result in high resistance along leakage path 38 from the subsequently formed source / drain region 92, such as... Figure 31AAs shown in the diagram. For example, region 31 and / or region C in p-type well 24 includes a high concentration of p-type dopant, and the high concentration of p-type dopant along leakage path 38 results in high resistance for the subsequently formed n-type source / drain region 92. Similarly, region 31 and / or region C in n-type well 30 includes a high concentration of n-type dopant, and the high concentration of n-type dopant along leakage path 38 results in high resistance for the subsequently formed p-type source / drain region 92.

[0120] The etching process for forming the fins 66 and nanostructures 55 can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar processes, or combinations thereof. The etching can be anisotropic. The nanostructures 55 formed by etching the multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from the first semiconductor layer 51, and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from the second semiconductor layer 53. The first nanostructures 52 and the second nanostructures 54 can be further collectively referred to as nanostructures 55. Figure 13 The diagram shows two fins formed in each of the n-type region 10N and the p-type region 10P. In other embodiments, different numbers of fins may be formed in each region.

[0121] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more optical lithography processes, including dual or multiple patterning processes. Typically, dual or multiple patterning processes combine optical lithography with a self-aligned process, allowing the resulting patterns to have, for example, a smaller pitch than that obtained using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0122] Figure 13 The fins 66 in the n-type region 10N and p-type region 10P are illustrated, and for illustrative purposes, their widths are substantially equal. In some embodiments, the width of the fins 66 in the n-type region 10N may be greater than or less than the width of the fins 66 in the p-type region 10P. Furthermore, although each of the fins 66 and / or nanostructures 55 is illustrated to have a uniform width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each of the fins 66 and / or nanostructures 55 increases continuously in the direction toward the substrate 10. In such embodiments, each of the nanostructures 55 may have different widths and be trapezoidal in shape.

[0123] exist Figure 14 In this embodiment, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 10, the fin 66, and the nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or combinations thereof. Any other insulating material formed by an acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In this embodiment, the formation of the insulating material results in excess insulating material covering the nanostructure 55. Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the top surface of the substrate 10, the fin 66, and the nanostructure 55. Subsequently, a filling material as described above can be formed on top of the lining.

[0124] Next, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or similar methods, may be used. The planarization process exposes the nanostructure 55 so that, after the planarization process is completed, the nanostructure 55 is flush with the top surface of the insulating material.

[0125] Next, the insulating material is recessed to form STI regions 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type region 10N and p-type region 10P protrude from between adjacent STI regions 68. Furthermore, the top surface of the STI region 68 may have a planar, convex, concave (such as dish-shaped), or combination thereof, as shown in the figure. The top surface of the STI region 68 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using acceptable etching processes, such as etching processes selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the material of the fins 66 and nanostructures 55). For example, dilute hydrofluoric acid (dHF) can be used to remove oxides.

[0126] The above is about Figures 12 to 14The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed above the top surface of the substrate 10, and trenches can be etched through the dielectric layer to expose the underlying substrate 10. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structures may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially growing epitaxial structures, the epitaxial growth material may be doped in situ during growth or through one or more implantation processes.

[0127] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting nanostructure 52) and the second semiconductor layer 53 (and the resulting nanostructure 54) are illustrated and discussed herein as containing the same material in the p-type region 10P and the n-type region 10N. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in different orders in the p-type region 10P and the n-type region 10N.

[0128] Further in Figure 14 In this process, suitable wells (not shown separately) can be formed in nanostructure 55. In embodiments with different well types, photoresist or other masks (not shown separately) can be used to achieve different implantation steps for the n-type region 10N and the p-type region 10P. For example, photoresist can be formed over the fin 66, nanostructure 55, and STI region 68 in the n-type region 10N and the p-type region 10P. The photoresist is patterned to expose the p-type region 10P. The photoresist can be formed using a spin-coating technique and can be patterned using acceptable optical lithography. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 10P, and the photoresist can act as a mask to substantially prevent n-type impurities from implanting into the n-type region 10N. The n-type impurity can be phosphorus, arsenic, antimony, or the like implanted in the region, with a concentration ranging from about 1 x 10⁻⁶. 13 atoms / cm 3 To approximately 1x10 14 atoms / cm 3 After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0129] Before or after implantation of the p-type region 10P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 10P and the n-type region 10N. The photoresist is patterned to expose the n-type region 10N. The photoresist can be formed using a spin-coating technique and can be patterned using acceptable optical lithography. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 10N, and the photoresist can act as a mask to substantially prevent p-type impurity implantation into the p-type region 10P. The p-type impurity can be boron, boron fluoride, indium, or the like implanted in the region, with a concentration ranging from approximately 1 x 10⁻⁶. 13 atoms / cm 3 To approximately 1x10 14 atoms / cm 3 After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0130] After implantation of the n-type region 10N and the p-type region 10P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin can be doped in situ during growth, which avoids implantation, although in-situ doping and implantation doping can be used together.

[0131] exist Figure 15 In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a masking layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, such as by CMP. The masking layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polySiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques used to deposit the selected material. The dummy gate layer 72 may be made of other materials that exhibit high etch selectivity for the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 10N and the p-type region 10P. It should be noted that, for illustrative purposes only, the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that it covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0132] Figures 16A to 28C The illustration shows various additional steps in manufacturing the apparatus of the embodiment. Figure 16A and Figure 16B In this process, acceptable optical lithography and etching techniques can be used to pattern the mask layer 74 (see...). Figure 15 The pattern of mask 78 is then transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric layer 71, respectively. The dummy gate 76 covers each channel region of fin 66. The pattern of mask 78 can be used to separate each of the dummy gates 76 from the adjacent dummy gate 76 entities. The dummy gate 76 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the individual fin 66.

[0133] exist Figure 17A and Figure 17B In the middle, the first spacer layer 80 and the second spacer layer 82 are respectively formed in Figure 16A and Figure 16B Above the structure shown. The first spacer layer 80 and the second spacer layer 82 are then patterned to act as spacers for forming self-aligned source / drain regions. Figure 17A and Figure 17B In this configuration, a first spacer layer 80 is formed on the top surface of the STI region 68; on the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and on the sidewalls of the dummy gate 76 and the dummy gate dielectric layer 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like, using techniques such as thermal oxidation or by CVD, ALD, or the like. The second spacer layer 82 may be formed of a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

[0134] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation of lightly doped source / drain (LDD) regions (not shown separately) can be performed. In embodiments with different device types, this is similar to the above. Figure 4The implantation discussed herein involves forming a mask, such as a photoresist, over the n-type region 10N while simultaneously exposing the p-type region 10P. An impurity of an appropriate type (e.g., p-type) can then be implanted into the p-type region 10P within the exposed fin 66 and nanostructure 55. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-type region 10P while simultaneously exposing the n-type region 10N. An impurity of an appropriate type (e.g., n-type) can then be implanted into the n-type region 10N within the exposed fin 66 and nanostructure 55. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The impurity concentration in the lightly doped source / drain regions can be approximately 1 x 10⁻⁶. 15 atoms / cm 3 To approximately 1x10 19 atoms / cm 3 Within a certain range. Annealing can be used to repair implant damage and activate implant impurities.

[0135] exist Figure 18A and Figure 18B In this process, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 serve to self-align the subsequently formed source and drain regions, and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), or the like. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer when the second spacer layer 82 is patterned, and that the second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, an anisotropic etching process can be used to etch the second spacer layer 82, wherein the first spacer layer 80 serves as an etching stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, such as... Figure 18A As shown in the diagram. Subsequently, during the etching of the exposed portion of the first spacer layer 80, the second spacer 83 acts as a mask, thereby forming as shown in the diagram. Figure 18A The first spacer 81 shown.

[0136] like Figure 18A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 18BAs shown, in some embodiments, the second spacer layer 82 may be removed over the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric layer 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric layer 71. In other embodiments, a portion of the second spacer layer 82 may remain over the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric layer 71.

[0137] It should be noted that the above disclosure typically describes the process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., the first spacer 81 may be patterned before the deposition of the second spacer layer 82), additional spacers may be formed and removed, and / or the like. Furthermore, different structures and steps may be used to form n-type and p-type devices.

[0138] exist Figure 19A and Figure 19B In some embodiments, a first groove 86 is formed in the fin 66, the nanostructure 55, and the substrate 10. An epitaxial source / drain region is then formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 10. Figure 19A As shown, the top surface of the STI region 68 may be flush with the bottom surface of the first groove 86. In various embodiments, the fin 66 may be etched such that the bottom surface of the first groove 86 is disposed below the top surface of the STI region 68; or similarly. The first groove 86 may be formed by etching the fin 66, the nanostructure 55, and the substrate 10 using an anisotropic etching process (such as RIE, NBE, or similar). During the etching process for forming the first groove 86, a first spacer 81, a second spacer 83, and a mask 78 shield portions of the fin 66, the nanostructure 55, and the substrate 10. A single etching process or multiple etching processes may be used to etch the individual layers of the nanostructure 55 and / or the fin 66. A timed etching process may be used to terminate the etching of the first groove 86 after the first groove 86 has reached the desired depth.

[0139] exist Figure 20A and Figure 20B In the process, the portions of the sidewalls of the layer formed by the first semiconductor material (e.g., the first nanostructure 52) of the multilayer stack 64 exposed by the first groove 86 are etched to form sidewall grooves 88 in the n-type region 10N, while the portions of the sidewalls of the layer formed by the second semiconductor material (e.g., the second nanostructure 54) of the multilayer stack 64 exposed by the first groove 86 are etched to form sidewall grooves 88 in the p-type region 10P. Although the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall grooves 88 are... Figure 20BThe diagram shows straight sides, but these sidewalls can be concave or convex. Isotropic etching processes (such as wet etching or similar) can be used to etch the sidewalls. A mask (not shown) can be used to protect the p-type region 10P while an etchant selective for the first semiconductor material is used to etch the first nanostructure 52, such that the second nanostructure 54 and the substrate 10 remain relatively unetched compared to the first nanostructure 52 in the n-type region 10N. Similarly, a mask (not shown) can be used to protect the n-type region 10N while an etchant selective for the second semiconductor material is used to etch the second nanostructure 54, such that the first nanostructure 52 and the substrate 10 remain relatively unetched compared to the second nanostructure 54 in the p-type region 10P. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to etch the sidewalls of the first nanostructure 52 in the n-type region 10N, and a wet or dry etching process using hydrogen fluoride, another fluorine-based etchant, or the like can be used to etch the sidewalls of the second nanostructure 54 in the p-type region 10P.

[0140] exist Figures 21A to 21C In the middle, the first internal spacer 90 is formed in the sidewall groove 88. This can be achieved by... Figure 20A and Figure 20B An internal spacer layer (not shown separately) is deposited over the structure shown to form the first internal spacer 90. The first internal spacer 90 can serve as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the recess 86, and the first nanostructure 52 in the n-type region 10N and the second nanostructure 54 in the p-type region 10P will be replaced by the corresponding gate structures.

[0141] The internal spacer layer can be deposited using conformal deposition processes such as CVD, ALD, or similar. The internal spacer layer may comprise materials such as silicon nitride or silicon oxynitride, although any suitable material may be used, such as low-k materials having a k value less than about 3.5. The internal spacer layer can then be anisotropically etched to form a first internal spacer 90. Although the outer walls of the first internal spacer 90 are illustrated to be flush with the sidewalls of the second nanostructure 54 in the n-type region 10N and with the sidewalls of the first nanostructure 52 in the p-type region 10P, the outer walls of the first internal spacer 90 may extend beyond or be recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0142] Furthermore, although the outer wall of the first internal spacer 90 is in Figure 21B The diagram shows a straight line, but the outer wall of the first internal spacer 90 may be concave or convex. As an example, Figure 21C The illustration shows one embodiment where the sidewalls of the first nanostructure 52 in the n-type region 10N are concave, the outer sidewalls of the first internal spacer 90 are concave, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54. Another illustration shows an embodiment where the sidewalls of the second nanostructure 54 in the p-type region 10P are concave, the outer sidewalls of the first internal spacer 90 are concave, and the first internal spacer 90 is recessed from the sidewalls of the first nanostructure 52. The internal spacer layer can be etched using an anisotropic etching process (such as RIE, NBE, or similar). The first internal spacer 90 can be used to prevent the formation of subsequent source / drain regions (such as epitaxial source / drain regions 92, as referred to below). Figures 22A to 22C The aforementioned damage can be caused by subsequent etching processes, such as etching processes used to form gate structures.

[0143] exist Figures 22A to 22C In this configuration, epitaxial source / drain regions 92 are formed in the first groove 86. In some embodiments, the source / drain regions 92 can apply stress to the second nanostructure 54 in the n-type region 10N and the first nanostructure 52 in the p-type region 10P, thereby improving performance. Figure 22B As shown, epitaxial source / drain regions 92 are formed in a first recess 86 such that each dummy gate 76 is disposed between individual adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, while a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the gate subsequently formed in the resulting nanoFET.

[0144] The epitaxial source / drain region 92 in the n-type region 10N (e.g., an NMOS region) can be formed by shielding the p-type region 10P (e.g., a PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the n-type region 10N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material on which tensile strain is applied, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 92 may have a surface rising from an individual upper surface of the nanostructure 55 and may have a facet.

[0145] The epitaxial source / drain region 92 in the p-type region 10P (e.g., a PMOS region) can be formed by shielding the n-type region 10N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the p-type region 10P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanoFET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can comprise a material on which compressive strain is applied, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain region 92 can also have a surface rising from an individual surface of the multilayer stack 64 and can have a facet.

[0146] Epitaxial source / drain regions 92, first nanostructures 52, second nanostructures 54, and / or substrate 10 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have a density of approximately 1 x 10⁻⁶. 19 atoms / cm 3 With approximately 1x10 21 atoms / cm 3 The impurity concentrations between these parameters. The n-type and / or p-type impurities in the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0147] Due to the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 10N and the p-type region 10P, the upper surface of the epitaxial source / drain regions 92 has small planes extending laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, such as Figure 22A As shown, these facets merge adjacent epitaxial source / drain regions 92 of the same nanoFET. In other embodiments, such as Figure 22C As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated. Figure 22A and Figure 22C In the illustrated embodiment, the first spacer 81 may be formed to the top surface of the STI region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewall of the nanostructure 55, further blocking epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 68.

[0148] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different doping concentrations. In some embodiments, the first semiconductor material layer 92A may have a doping concentration lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0149] Figure 22D The illustration shows an embodiment in which the sidewalls of the first nanostructure 52 in the n-type region 10N and the second nanostructure 54 in the p-type region 10P are concave, the outer sidewall of the first internal spacer 90 is concave, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Figure 22D As shown, the epitaxial source / drain region 92 can be formed in contact with the first internal spacer 90 and can extend beyond the sidewall of the second nanostructure 54 in the n-type region 10N and the sidewall of the first nanostructure 52 in the p-type region 10P.

[0150] exist Figures 23A to 23C In the middle, the first interlayer dielectric (ILD) 96 is deposited on... Figure 16A , Figure 22B ,and Figure 22A Above the structure shown ( Figures 17A to 22D The manufacturing process will not change. Figure 16A(See the cross-section shown). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, or plasma-enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), undoped silicon glass (USG), or the like. Other insulating materials may be used, formed by any acceptable process. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, the mask 78, and the first spacer 81. The CESL 94 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having an etch rate different from that of the material covering the first ILD 96.

[0151] exist Figures 24A to 24B In this process, a planarization process, such as CMP, can be performed to align the top surface of the first ILD 96 with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and portions of the first spacer 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are aligned within a range of process variations. Therefore, the top surface of the dummy gate 72 is exposed via the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process aligns the top surface of the first ILD 96 with the top surfaces of the mask 78 and the first spacer 81.

[0152] exist Figure 25A and Figure 25B In one or more etching steps, the dummy gate 76 and the mask 78 (if present) are removed to form a second recess 98. A portion of the dummy gate dielectric layer 71 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric layer 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases (multiples) that selectively etch the dummy gate 76 at a faster rate than etching the first ILD 96 or the first spacer 81. A portion of the nanostructure 55 is exposed and / or overlaid on each second recess 98, which serves as a channel region in the subsequently completed nanoFET. The portion of the nanostructure 55 serving as the channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric layer 71 may be used as an etch stop layer when etching the dummy gate 76. The dummy gate dielectric layer 71 may then be removed after the removal of the dummy gate 76.

[0153] exist Figure 26A and Figure 26B In this embodiment, the first nanostructure 52 in the n-type region 10N and the second nanostructure 54 in the p-type region 10P are removed, extending the second groove 98. The first nanostructure 52 can be removed by forming a mask (not shown) over the p-type region 10P and performing an isotropic etching process (such as wet etching, or the like) using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 10, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 comprises, for example, SiGe, and the second nanostructures 54A-54C comprise, for example, Si or SiC, the first nanostructure 52 in the n-type region 10N can be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0154] The second nanostructure 54 in the p-type region 10P can be removed by forming a mask (not shown) over the n-type region 10N and performing an isotropic etching process (such as wet etching, or the like) using an etchant selective for the material of the second nanostructure 54, while the first nanostructure 52, the substrate 10, and the STI region 68 remain relatively unetched compared to the second nanostructure 54. In embodiments where the second nanostructure 54 comprises, for example, SiGe, and the first nanostructure 52 comprises, for example, Si or SiC, the second nanostructure 54 in the p-type region 10P can be removed using hydrogen fluoride, another fluorine-based etchant, or the like.

[0155] In other embodiments, channel regions in both the n-type region 10N and the p-type region 10P can be formed simultaneously, for example, by removing the first nanostructure 52 from both the n-type region 10N and the p-type region 10P, or by removing the second nanostructure 54 from both the n-type region 10N and the p-type region 10P. In such embodiments, the channel regions of the n-type nanoFET and the p-type nanoFET can have the same material composition, such as silicon, silicon germanium, or the like. Figure 32A , Figure 32B ,and Figure 32C The diagram illustrates a structure resulting from such an embodiment, wherein the channel regions of both the p-type region 10P and the n-type region 10N are provided by a second nanostructure 54 and contain silicon, for example.

[0156] exist Figure 27A and Figure 27BIn the second recess 98, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 10N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 10, and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. In the p-type region 10P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 10, and on the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68.

[0157] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric layer may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 10N and the p-type region 10P. Methods for forming the gate dielectric layer 100 may include molecular-beam deposition (MBD), ALD, PECVD, or the like.

[0158] Gate electrodes 102 are deposited over the gate dielectric layer 100 and fill the remaining portion of the second trench 98. Gate electrodes 102 may comprise metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although in Figure 27A and Figure 27B The diagram shows a single-layer gate electrode 102, but the gate electrode 102 may include any number of liner layers, any number of work function tuning layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited in the n-type region 10N between adjacent layers of the second nanostructure 54 and between the second nanostructure 54A and the substrate 10, and may be deposited in the p-type region 10P between adjacent layers of the first nanostructure 52.

[0159] The formation of the gate dielectric layer 100 in the n-type region 10N and the p-type region 10P can be performed simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0160] After filling the second recess 98, a planarization process, such as CMP, can be performed to remove excess portions of the gate dielectric layer 100 and the material of the gate electrode 102, which are located above the top surface of the first ILD 96. Thus, the remaining material of the gate electrode 102 and the gate dielectric layer 100 forms the replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the “gate structure”.

[0161] exist Figures 28A to 28C In this configuration, the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed to form a groove between the gate structure directly above and the opposing portion of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or the like) is filled into the groove, followed by a planarization process to remove excess dielectric material extending over the first ILD 96. The subsequently formed gate contacts (such as gate contact 114, hereinafter referred to as...) Figure 30A and Figure 30B (Discussion) Penetrates the gate shield 104 to contact the top surface of the recessed gate electrode 102.

[0162] like Figures 28A to 28C As further shown, a second ILD 106 is deposited over the first ILD 96 and the gate mask 104. In some embodiments, the second ILD 106 is a flowable thin film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method such as CVD, PECVD, or the like.

[0163] exist Figures 29A to 29CIn this process, the second ILD 106, the first ILD 96, CESL 94, and the gate mask 104 are etched to form a third groove 108, exposing the surface of the epitaxial source / drain region 92 and / or gate structure. The third groove 108 can be formed by etching using an anisotropic etching process (such as RIE, NBE, or similar). In some embodiments, the third groove 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; it can be etched through the gate mask 104 using a second etching process; and then it can be etched through the CESL 94 using a third etching process. A mask such as a photoresist can be formed and patterned over the second ILD 106 to mask portions of the second ILD 106 from the first and second etching processes. In some embodiments, the etching process may involve over-etching, so that the third groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom portion of the third groove 108 may be flush with the epitaxial source / drain region 92 and / or gate structure (e.g., at the same location, or at the same distance from the substrate) or lower than the epitaxial source / drain region 92 and / or gate structure (e.g., closer to the substrate). Although Figure 29B The third recess 108 is illustrated as exposing the epitaxial source / drain region 92 and gate structure in the same cross-section. However, in various embodiments, the epitaxial source / drain region 92 and gate structure may be exposed in different cross-sections, thereby reducing the risk of short circuits at subsequently formed contacts. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (not shown) (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92 over the exposed portion of the epitaxial source / drain region 92, followed by a thermal annealing process to form the silicide region 110. The unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, it may also be a germanide region or a silicon germanide region (e.g., a region containing both silicide and germanide). In an embodiment, the silicide region 110 contains TiSi and has a thickness between about 2 nm and about 10 nm.

[0164] Next, in Figures 30A to 30CIn this embodiment, contacts 112 and 114 (also referred to as contact sockets) are formed in the third recess 108. Contacts 112 and 114 may each comprise one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to an underlying conductive feature (e.g., the gate structure 102 and / or the silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to the gate structure 102 and may be referred to as a gate contact, while contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. Planarization processes, such as CMP, may be performed to remove excess material from the surface of the second ILD 106.

[0165] Figure 31A Illustration Figure 30C In the same structure shown, another p-type region 10P is to the left of the n-type region 10N; therefore, according to some embodiments, each side of the p-type well 24 has an n-type well 30. According to some embodiments, passage 38 represents, according to some embodiments, two of the passages through the p-type well 24 from the n-type source / drain region 92 in the n-type region 10N to the n-type well 30 in the p-type region 10P where junction leakage can occur. Figure 31A As shown, region 31 is positioned such that path 38 extends through the highly doped portion of region 31. At each of the interfaces between p-type well 24 and n-type well 30, there is a depletion region (not shown). When the device is biased, the two depletion regions can overlap in p-type well 24, potentially causing depletion region clamping in p-type well 24. Depletion region clamping creates a lower resistance path between n-type source / drain region 92 and n-type well 30. As discussed in more detail below, embodiments such as those discussed below reduce depletion region clamping, thereby increasing resistance along path 38 and reducing junction leakage.

[0166] Figure 31B Illustration Figure 31A The p-type well 24 shown in the figure. Figure 7A The doping concentration profile 32 and region 31 shown are also displayed in Figure 31B On the p-type well 24, although a portion of the doping concentration profile 32 is absent due to the formation of fins 66 according to some embodiments. The doping concentration profile 32 can be modulated such that region 31 (including at least a portion of region C) remains below the fins. In some embodiments, such as Figure 31B As shown, region 31 extends laterally between the outer walls of the fins 66 contained in the p-shaped well 24 and has a spacing D between the bottom of the fins 66 and the outer walls of the fins 66. T The top boundary and the distance D between the top boundary and the bottom of the fin 66 B The bottom boundary. DC Represents the center of region C (e.g., such as Figure 7B The line H-H' shown in the diagram), D T With D C The ratio can be in the range of about 0.5 to about 0.6, and D B With D C The ratio can range from about 1.5 to about 1.75. In some embodiments, D T It can be approximately 50 nm to approximately 70 nm, D C It can be approximately 130 nm to approximately 160 nm, and D B The region can be approximately 200 nm to approximately 280 nm. For example, region 31 can extend from approximately 50 nm below the bottom of fin 66 to approximately 280 nm below the bottom of fin 66. The average concentration of dopant in region 31 is approximately 5 x 10⁻⁶. 17 atoms / cm 3 Approximately 7x10 17 atoms / cm 3 Within this range. This reduces the overlap between the two depletion regions mentioned above, thereby reducing depletion region clamping in p-type well 24. This can further lead to an increase in resistance along the path 38, thereby reducing the junction leakage through p-type well 24 from the n-type source / drain region 92 in n-type region 10N to n-type well 30, such as Figure 31A As shown in the figure. In some embodiments, the n-type well 30 also has a doping concentration profile 32, which can lead to a reduction in junction leakage through the n-type well 30 from the p-type source / drain region 92 in the p-type region 10P to the p-type well 24.

[0167] Figures 32A to 32C The figure shows a cross-sectional view of an apparatus according to some alternative embodiments. Figure 32A Illustration Figure 1 The reference cross section A-A' is shown in the figure. Figure 32B Illustration Figure 1 The reference cross section B-B' is shown in the figure. Figure 32C Illustration Figure 1 The reference cross section C-C' is shown in the diagram. Figures 32A to 32C In the middle, similar reference numbers indicate that they are derived from... Figures 30A to 30C Similar components are formed using a similar manufacturing process to their structure. However, in Figures 32A to 32C In this context, the channel regions in the n-type region 10N and the p-type region 10P contain the same material. For example, a second nanostructure 54 containing silicon provides the channel region for the p-type nanoFET in the p-type region 10P and the n-type nanoFET in the n-type region 10N. Figures 32A to 32CThe structure can be formed, for example, by simultaneously removing the first nanostructure 52 from both the p-type region 10P and the n-type region 10N; depositing a gate dielectric layer 100 and a gate electrode 102P (e.g., a gate electrode suitable for a p-type nanoFET) around the second nanostructure 54 in the p-type region 10P; and depositing a gate dielectric layer 100 and a gate electrode 102N (e.g., a gate electrode suitable for an n-type nanoFET) around the second nanostructure 54 in the n-type region 10N. In such embodiments, the material of the epitaxial source / drain region 92 may differ in the n-type region 10N compared to the p-type region 10P, as described above.

[0168] The embodiments offer advantages. For example, by utilizing the techniques described above, such as parallel implantation and tilted implantation, during the implantation process, the doping concentration profile 32 in the p-type well 24 and n-type well 30 can be modulated. The doping concentration profile 32 results in a reduction of the depletion region clamping in the p-type well 24 and n-type well 30. This leads to a reduction in junction leakage from the source / drain region 92 to the substrate 10 in the nanoFET device.

[0169] In an embodiment, the semiconductor device includes a semiconductor substrate including one or more fins; an isolation layer above the semiconductor substrate and along the sidewalls of the one or more fins; a first deep well in the semiconductor substrate below the one or more fins, the first deep well being doped with a first dopant having a first conductivity type; a first well in the semiconductor substrate, wherein one or more fins are in the first well, the first well being doped with a second dopant having a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type, wherein the first well is above the first deep well; a second well on a first side of the first well in the semiconductor substrate; and a third well on a second side of the first well in the semiconductor substrate, wherein the first side boundary is aligned with a first sidewall of the one or more fins, wherein the second side boundary is aligned with a second sidewall of the one or more fins, wherein the first sidewall is the sidewall of the one or more fins closest to the second well, wherein the second sidewall is the sidewall of the one or more fins closest to the third well, wherein the average concentration of the second dopant in a first region of the semiconductor substrate below the one or more fins and between the first side boundary and the second side boundary is 5 x 10⁻⁶. 17 atoms / cm 3 Up to 7x10 17 atoms / cm 3Within the range. In an embodiment, the first region is 50 nm to 280 nm below the bottom of one or more fins. In an embodiment, the second dopant has a first concentration at a first location along a first vertical line, wherein the first vertical line is located midway between the second and third wells in the first well, wherein the first location is at the center of the peak of the second dopant concentration profile along the first vertical line, wherein the second dopant has a second concentration at a second location, wherein the depth of the second location from the top surface of the semiconductor substrate is 1.5 times the depth of the first location, and wherein the second concentration is 30% to 40% of the first concentration. In an embodiment, the second dopant has a first concentration at a first location along a first vertical line, wherein the first vertical line is located midway between the second and third wells in the first well, wherein the first location is at the center of the peak of the second dopant concentration profile along the first vertical line, wherein the second dopant has a third concentration at a third location, wherein the depth of the third location from the top surface of the semiconductor substrate is 1.75 times the depth of the first location, and wherein the third concentration is 20% to 30% of the first concentration. In the embodiment, the first well is a p-type well, and the second and third wells are n-type wells.

[0170] In an embodiment, a method of forming a semiconductor device includes: forming a patterned mask over a substrate, wherein the patterned mask has an opening over a first portion of the substrate; implanting a first dopant into the substrate at a first angle using a first ion beam, wherein the first ion beam is in a first plane parallel to one side of the first portion in the plan view, wherein the first plane is perpendicular to a top surface of the substrate, wherein the first ion beam impinges on the top surface of the substrate at a first angle relative to a line perpendicular to the top surface of the substrate; implanting the first dopant into the substrate at a second angle using a second ion beam, wherein the second ion beam is in a second plane parallel to one side of the first portion in the plan view, wherein the second plane is perpendicular to the top surface of the substrate, wherein the second ion beam impinges on the top surface of the substrate at a second angle relative to a line perpendicular to the top surface of the substrate, wherein the first ion beam and the second ion beam are on opposite sides of a line perpendicular to the top surface of the substrate, wherein implanting with the first ion beam and implanting with the second ion beam form a first well; and etching the substrate to form one or more fins in the first well, wherein the maximum concentration of the first dopant is below the bottom of the one or more fins. In an embodiment, the method further includes rotating the substrate after implantation with a first ion beam and before implantation with a second ion beam. In an embodiment, the magnitude of the first angle is greater than 0 degrees and less than 15 degrees. In an embodiment, the magnitude of the second angle is greater than 0 degrees and less than 15 degrees. In an embodiment, the magnitude of the first angle is equal to the magnitude of the second angle. In an embodiment, after implantation with the second ion beam, the first dopant has a first concentration profile along a vertical line extending through the middle of the first portion, wherein the first concentration profile has a peak, wherein the peak is centered at a first distance below the bottom of one or more fins, wherein the average concentration of the first dopant in the region is 5 x 10⁻⁶.17 atoms / cm 3 Up to 7x10 17 atoms / cm 3 Within the range, the region is laterally defined by the outermost outermost wall of one or more fins in the first well, and vertically defined by an upper boundary and a lower boundary, wherein the upper boundary has a first depth of 0.5 to 0.6 times the first distance, and the lower boundary has a second depth of 1.5 to 1.75 times the first distance. In an embodiment, the maximum concentration of the first dopant is in the range of 130 nm to 160 nm below the bottom of one or more fins.

[0171] In an embodiment, a method of forming a semiconductor device includes: forming a first patterned mask over a substrate, wherein the first patterned mask has a first opening above a top surface of a first portion of the substrate; performing a first implantation on the first portion of the substrate with a first dopant, wherein a first ion beam of the first implantation forms a first acute angle with respect to the top surface of the first portion of the substrate, the first ion beam being substantially parallel to a plane perpendicular to the top surface of the substrate, the plane including a longitudinal side of the first portion of the substrate; rotating the substrate 180 degrees after performing the first implantation; and performing a second implantation on the first portion of the substrate with the first dopant, wherein a second ion beam of the second implantation forms a second acute angle with respect to the top surface of the first portion of the substrate, the second ion beam being substantially parallel to a plane perpendicular to the top surface of the substrate, the plane including a longitudinal side of the first portion of the substrate. In an embodiment, the first dopant is a p-type dopant, wherein performing the first implantation and the second implantation forms a p-type well. In an embodiment, the first dopant is boron. In an embodiment, the first dopant is an n-type dopant, wherein performing the first implantation and the second implantation forms an n-type well. In an embodiment, the first dopant is arsenic or phosphorus. In one embodiment, each of the first acute angle and the second acute angle is in the range of 75° to less than 90°. In another embodiment, the first acute angle and the second acute angle are the same. In yet another embodiment, the substrate is stationary during the first and second implantation.

[0172] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A semiconductor substrate, the semiconductor substrate comprising one or more fins; An isolation layer is provided above the semiconductor substrate and along the multiple sidewalls of the one or more fins; A first deep well, in the semiconductor substrate and below the one or more fins, is doped with a first dopant having a first conductivity type; A first well in the semiconductor substrate, wherein one or more fins are in the first well, the first well is doped with a second dopant having a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type, wherein the first well is above the first deep well; A second well, in the semiconductor substrate on a first side of the first well; and A third well is located on a second side of the first well in the semiconductor substrate, wherein a first side boundary is aligned with a first sidewall of the one or more fins, and a second side boundary is aligned with a second sidewall of the one or more fins. The first sidewall is the sidewall of the one or more fins closest to the second well, and the second sidewall is the sidewall of the one or more fins closest to the third well. The average concentration of the second dopant in a first region of the semiconductor substrate below the one or more fins and between the first side boundary and the second side boundary is 5 x 10⁻⁶. 17 atoms / cm 3 Up to 7x10 17 atoms / cm 3 Within a certain range.

2. The semiconductor device as claimed in claim 1, characterized in that, The first region is located 50 to 280 nanometers below the bottom of one or more fins.

3. The semiconductor device as claimed in claim 1, characterized in that, The second dopant has a first concentration at a first location along a first vertical line, wherein the first vertical line is located midway between the second well and the third well in the first well, wherein the first location is at the center of a peak in a doping concentration profile of the second dopant along the first vertical line, wherein the second dopant has a second concentration at a second location, wherein a depth of the second location from a top surface of the semiconductor substrate is 1.5 times the depth of the first location, and wherein the second concentration is 30% to 40% of the first concentration.

4. The semiconductor device as claimed in claim 1, characterized in that, The second dopant has a first concentration at a first location along a first vertical line, wherein the first vertical line is located midway between the second well and the third well in the first well, wherein the first location is at the center of a peak in a doping concentration profile of the second dopant along the first vertical line, wherein the second dopant has a third concentration at a third location, wherein a depth of the third location from a top surface of the semiconductor substrate is 1.75 times the depth of the first location, and wherein the third concentration is 20% to 30% of the first concentration.

5. The semiconductor device as claimed in claim 1, characterized in that, The first well is a p-type well, while the second and third wells are n-type wells.

6. A method for forming a semiconductor device, characterized in that, The method includes: A patterned mask is formed over a substrate, wherein the patterned mask has an opening over a first portion of the substrate; A first dopant is implanted into the substrate at a first angle using a first ion beam, wherein the first ion beam is in a first plane parallel to one side of the first portion in a plan view, wherein the first plane is perpendicular to a top surface of the substrate, and wherein the first ion beam strikes the top surface of the substrate at the first angle relative to a line perpendicular to the top surface of the substrate. The first dopant is implanted into the substrate at a second angle using a second ion beam, wherein the second ion beam is in a second plane parallel to the side of the first portion in a plan view, wherein the second plane is perpendicular to the top surface of the substrate, wherein the second ion beam strikes the top surface of the substrate at the second angle relative to a line perpendicular to the top surface of the substrate, wherein the first ion beam and the second ion beam are on opposite sides of the line perpendicular to the top surface of the substrate, wherein the implantation with the first ion beam and the implantation with the second ion beam form a first well, and the magnitude of the first angle is equal to the magnitude of the second angle; and The substrate is etched to form one or more fins in the first well, wherein a maximum concentration of the first dopant is below a bottom of the one or more fins.

7. The method as described in claim 6, characterized in that, It further includes rotating the substrate after implantation with the first ion beam and before implantation with the second ion beam.

8. The method as described in claim 6, characterized in that, The value of the first angle is greater than 0 degrees and less than 15 degrees.

9. The method as described in claim 8, characterized in that, The value of the second angle is greater than 0 degrees and less than 15 degrees.

10. The method as described in claim 6, characterized in that, The first dopant is either a p-type dopant or an n-type dopant.

11. The method as described in claim 6, characterized in that, After implantation with the second ion beam, the first dopant has a first concentration profile along a vertical line extending through the middle of the first portion, wherein the first concentration profile has a peak value centered at a first distance below a bottom of the one or more fins, and wherein an average concentration of the first dopant in a region is 5 x 10⁻⁶. 17 atoms / cm 3 Up to 7x10 17 atoms / cm 3 Within a certain range, wherein the area is laterally defined by the outermost walls of the one or more fins in the first well, and is vertically defined by an upper boundary and a lower boundary, wherein the upper boundary has a first depth of 0.5 to 0.6 times the first distance, and wherein the lower boundary has a second depth of 1.5 to 1.75 times the first distance.

12. The method as described in claim 6, characterized in that, The maximum concentration of the first dopant is in the range of 130 nm to 160 nm below the bottom of the one or more fins.

13. A method for forming a semiconductor device, characterized in that, The method includes: A first patterned mask is formed above a substrate, wherein the first patterned mask has a first opening above a top surface of a first portion of the substrate; A first implantation is performed on the first portion of the substrate using a first dopant, wherein a first ion beam of the first implantation forms a first acute angle with respect to the top surface of the first portion of the substrate, and the first ion beam is substantially parallel to a plane perpendicular to the top surface of the substrate, the plane including a longitudinal side of the first portion of the substrate. After the first implantation is performed, the substrate is rotated 180 degrees; and A second implantation is performed on the first portion of the substrate using the first dopant, wherein a second ion beam of the second implantation forms a second acute angle with respect to the top surface of the first portion of the substrate, the second ion beam being substantially parallel to a plane perpendicular to the top surface of the substrate, the plane including the longitudinal side of the first portion of the substrate, and the first acute angle being the same as the second acute angle.

14. The method as described in claim 13, characterized in that, The first dopant is a p-type dopant, wherein the first implantation and the second implantation are performed to form a p-type well.

15. The method as described in claim 14, characterized in that, The first dopant is boron.

16. The method as described in claim 13, characterized in that, The first dopant is an n-type dopant, wherein the first implantation and the second implantation are performed to form an n-type well.

17. The method as described in claim 16, characterized in that, The first dopant is arsenic or phosphorus.

18. The method as described in claim 13, characterized in that, Both the first acute angle and the second acute angle are within the range of 75° to less than 90°.

19. The method as described in claim 13, characterized in that, In the first part, the average concentration of the first dopant is 5 x 10⁻⁶. 17 atoms / cm 3 Up to 7x10 17 atoms / cm 3 Within a certain range.

20. The method as described in claim 13, characterized in that, The substrate is stationary during the first and second implantations.

Images