A stacked conductive pillar interconnect structure and its fabrication method

Abstract

This invention provides a stacked conductive pillar interconnect structure and its fabrication method. The stacked conductive pillar interconnect structure includes: a first dielectric layer to an Nth dielectric layer stacked vertically in sequence; N is an integer greater than or equal to 2; any nth dielectric layer has an nth through-slot; the first conductive pillar to the Nth conductive pillar are stacked vertically and adjacent to each other; any nth conductive pillar is located in the nth through-slot, and any nth conductive pillar includes: an nth stress-blocking layer located on the inner wall surface of the nth through-slot and an nth conductive body located on the nth stress-blocking layer; n is an integer greater than or equal to 1 and less than or equal to N; any kth conductive body and the (k+1)th stress-blocking layer are in contact, and k is an integer greater than or equal to 1 and less than or equal to N-1. The stacked conductive pillar interconnect structure avoids reliability test failures and improves service life.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a stacked conductive pillar interconnect structure and its fabrication method. Background Technology

[0002] In fabricating multilayer redistribution layers (RDLs), to achieve the shortest interconnection between adjacent upper and lower dielectric layers, methods such as... are typically employed. Figure 1 The diagram shows a design where cured polyimide (PI) photoresist coats stacked conductive pillars. (Refer to...) Figure 1 Each redistribution layer preparation process includes: (1) liquid polyimide coating, low-temperature baking to remove solvent from polyimide, exposure, development, and high-temperature baking curing (≥200℃); (2) copper electroplating process. The wiring design of the multilayer redistribution layer is designed according to the signal and power supply requirements between the chip and the substrate. Taking the wiring design of a 3-layer redistribution layer as an example, a high-temperature baking curing process is required when preparing the first, second, and third layers of wiring. During the preparation of the previous layer of wiring, the wiring of the next layer will undergo a heat treatment process from high-temperature baking curing to room temperature. The coefficient of thermal expansion (CTE) of polyimide photoresist is about 60ppm / ℃, while the CTE of copper is 17.5ppm / ℃. The large difference in the coefficient of thermal expansion between polyimide and copper will cause thermal stress during the high-temperature baking curing process. The process of cooling from high temperature to room temperature is also a process of thermal stress release. The thermal stress will be released at the interface of different materials.

[0003] Reference Figure 1 The interfaces between the different materials include: interface 4a between the first stacked conductive pillar 2a and the second stacked conductive pillar 2b; interface 4b between the second stacked conductive pillar 2b and the third stacked conductive pillar 2c; and interface 5 between the first stacked conductive pillar 2a, the second stacked conductive pillar 2b, the third stacked conductive pillar 2c, and the cured polyimide 1. Thermal stress is released at these interfaces during the cooling process from high temperature to room temperature. When the released thermal stress exceeds the modulus of the material itself, cracks will appear in the material. (Refer to...) Figure 2Since the elastic modulus of copper is 119 GPa, while the elastic modulus of cured polyimide (2 GPa-3 GPa) is much lower than that of copper, the inherent elasticity of the polymer material of cured polyimide can absorb most of the thermal stress. Therefore, the cracks caused by thermal stress will preferentially appear in the first crack 3a near interface 4a and the second crack 3b near interface 4b. This will lead to an increase in the impedance of the traces where the first stacked conductive pillar 2a, the second stacked conductive pillar 2b, and the third stacked conductive pillar 2c are located. Moreover, during the reliability test of the packaged product and the long-term service of the product, the cracks will continue to expand, eventually leading to the failure of the packaged product or reducing the service life of the product.

[0004] Therefore, how to avoid reliability test failures and improve service life is an urgent technical problem to be solved. Summary of the Invention

[0005] In view of this, the present invention provides a stacked conductive pillar interconnect structure and its preparation method to solve the problems of reliability test failure and short service life of the stacked conductive pillar interconnect structure in the prior art.

[0006] This invention provides a stacked conductive pillar interconnection structure, comprising: a first dielectric layer to an Nth dielectric layer stacked vertically in sequence; N being an integer greater than or equal to 2; an nth dielectric layer having an nth through-slot; a first conductive pillar to an Nth conductive pillar stacked vertically and adjacent to each other in sequence; an nth conductive pillar located in the nth through-slot, the nth conductive pillar comprising: an nth stress-blocking layer located on the inner wall surface of the nth through-slot and an nth conductive body located on the nth stress-blocking layer; n being an integer greater than or equal to 1 and less than or equal to N; an kth conductive body in contact with the (k+1)th stress-blocking layer, k being an integer greater than or equal to 1 and less than or equal to N-1.

[0007] Optionally, the elastic modulus of any nth stress-blocking layer is greater than the elastic modulus of the nth conductive body.

[0008] Optionally, the material of any nth stress barrier layer includes nickel, tungsten, nickel-based compounds, tungsten-based compounds, or nanotwinned copper.

[0009] Optionally, the material of any nth stress barrier layer includes an organic buffer material doped with several conductive nanoparticles.

[0010] Optionally, a number of conductive nanoparticles in any nth stress barrier layer can form a conductive mesh.

[0011] Optionally, the thickness of the conductive mesh is 0.5μm-5μm.

[0012] Optionally, the conductive mesh includes several grids; in any nth stress barrier layer, the organic buffer material surrounded by the grid has pores; the nth stress barrier layer also has conductive particles filling the pores.

[0013] Optionally, the average particle size of the filling conductive particles is smaller than the average particle size of the conductive nanoparticles.

[0014] Optionally, the conductive particles used for filling include copper-filled particles.

[0015] Optionally, the organic cushioning material may be a conductive adhesive or a polypyrrole-based polymer.

[0016] Optionally, the conductive nanoparticles include one or more combinations of silver nanoparticles, copper nanoparticles, aluminum nanoparticles, and gold nanoparticles.

[0017] Optionally, the average particle size of the conductive nanoparticles is 0.1 μm-5 μm.

[0018] Optionally, any nth conductive pillar may further include an nth nucleus layer located between the nth conductive body and the nth stress barrier layer.

[0019] This invention also provides a method for fabricating a stacked conductive pillar interconnect structure, comprising: forming a first dielectric layer to an Nth dielectric layer stacked vertically in sequence, and a first conductive pillar to an Nth conductive pillar stacked vertically and adjacent to each other in sequence; the step of forming any k conductive pillar, k+1 conductive pillar, k dielectric layer, and k+1 dielectric layer includes: forming a k dielectric layer, wherein a k-th through-groove is formed in the k dielectric layer; forming a k-th conductive pillar in the k-th through-groove; the step of forming a k-th conductive pillar in the k-th through-groove includes: forming a k-th stress-blocking layer on the inner wall surface of the k-th through-groove; and forming a k-th stress-blocking layer on the inner wall surface of the k-th through-groove. The steps of forming a k-th conductive body on a barrier layer; forming a k+1-th dielectric layer on a k-th dielectric layer, forming a k+1-th through-hole in the k+1-th dielectric layer, exposing the k-th conductive body in the k+1-th through-hole; and forming a k+1-th conductive pillar in the k+1-th through-hole include: forming a k+1-th stress barrier layer on the inner wall surface of the k+1-th through-hole, the k+1-th stress barrier layer being in contact with the k-th conductive body; and forming a k+1-th conductive body on the k+1-th stress barrier layer; where k is an integer greater than or equal to 1 and less than or equal to N-1.

[0020] Optionally, the elastic modulus of any nth stress barrier layer is greater than the elastic modulus of the nth conductive body; the process for forming any nth stress barrier layer includes a deposition process.

[0021] Optionally, the step of forming any nth stress barrier layer includes: preparing a conductive paste in which a plurality of conductive nanoparticles are dispersed; spraying the conductive paste onto the inner wall surface of the nth channel; and curing the conductive paste on the inner wall surface of the nth channel to form the nth stress barrier layer, wherein the material of the nth stress barrier layer includes an organic buffer material doped with a plurality of conductive nanoparticles.

[0022] Optionally, during the curing process, several conductive nanoparticles in the conductive slurry agglomerate to form a conductive mesh, which includes several grids.

[0023] Optionally, the conductive paste also contains volatile solvents. During the curing process, the volatile solvents in the conductive paste evaporate, creating voids in the organic buffer material surrounded by the mesh.

[0024] Optionally, the step of forming any nth conductive pillar further includes: depositing an nth nucleus layer on the surface of the nth stress barrier layer before forming the nth conductive body.

[0025] Optionally, it also includes: during the deposition of the nth nucleus layer on the surface of the nth stress barrier layer, forming conductive particles filling the voids.

[0026] Optionally, the process for depositing the nth nucleus layer on the surface of the nth stress barrier layer includes magnetron sputtering.

[0027] The technical solution of the present invention can achieve the following beneficial effects:

[0028] In the stacked conductive pillar interconnect structure provided by this invention, any nth conductive pillar includes: an nth stress barrier layer located on the inner wall surface of the nth through-slot and an nth conductive body located on the nth stress barrier layer. Any kth conductive body is in contact with the (k+1)th stress barrier layer. Even if the stacked conductive pillar interconnect structure experiences thermal stress due to material thermal mismatch between the dielectric layers and the conductive bodies, the nth stress barrier layer can act as a buffer layer for thermal stress. The nth stress barrier layer can absorb thermal stress and reduce crack formation in the nth conductive body. Even if cracks occur near the conductive bodies above or below the stress barrier layer, the strain buffering effect of the stress barrier layer can further alleviate crack propagation during reliability testing and long-term product service, avoiding chip package failure during reliability testing and improving the lifespan of the chip product during long-term service. Attached Figure Description

[0029] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a stacked conductive pillar interconnection structure;

[0031] Figure 2 This is another schematic diagram of a stacked conductive pillar interconnect structure;

[0032] Figure 3 This is a schematic diagram of a stacked conductive pillar interconnection structure according to an embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of the structure of the first conductive pillar in an embodiment of the present invention;

[0034] Figure 5 and Figure 6 This is a schematic diagram of the stacked conductive pillar interconnection structure of the present invention during the fabrication process.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1-Curing polyimide; 2a-First stacked conductive pillar; 2b-Second stacked conductive pillar; 2c-Third stacked conductive pillar; 3a-First crack; 3b-Second crack; 4a-Interface; 4b-Interface; 5-Interface; P1-First dielectric layer; P2-Second dielectric layer; P3-Third dielectric layer; 11-First conductive pillar; 11a-First stress barrier layer; 11b-First nucleus layer; 11c-First conductive body; 11a-1-Conductive mesh; 11a-2-Conductive particles; 12-Second conductive pillar; 12a-Second stress barrier layer; 12b-Second nucleus layer; 12c-Second conductive body; 13-Third conductive pillar; 13a-Third stress barrier layer; 13b-Third nucleus layer; 13c-Third conductive body; S1-First mask layer. Detailed Implementation

[0037] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection between two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0040] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0041] This embodiment provides a stacked conductive pillar interconnection structure, including: a first dielectric layer to an Nth dielectric layer stacked vertically in sequence; N is an integer greater than or equal to 2; any nth dielectric layer has an nth through-slot; the first conductive pillar to the Nth conductive pillar are stacked vertically and adjacent to each other in sequence; any nth conductive pillar is located in the nth through-slot, and any nth conductive pillar includes: an nth stress barrier layer located on the inner wall surface of the nth through-slot and an nth conductive body located on the nth stress barrier layer; n is an integer greater than or equal to 1 and less than or equal to N; any kth conductive body and the (k+1)th stress barrier layer are in contact, and k is an integer greater than or equal to 1 and less than or equal to N-1.

[0042] Any nth conductive pillar includes: an nth stress-blocking layer located on the inner wall surface of the nth through-slot and an nth conductive body located on the nth stress-blocking layer. Any kth conductive body and the (k+1)th stress-blocking layer are in contact. Even if the stacked conductive pillar interconnect structure experiences thermal stress due to material thermal mismatch between the dielectric layers and the conductive bodies, the nth stress-blocking layer can act as a buffer layer for thermal stress. The nth stress-blocking layer can prevent the release of thermal stress in the conductive body and also prevent the expansion of thermal stress into the conductive body, reducing the occurrence of cracks in the nth conductive body. Even if cracks occur near the conductive bodies above or below the stress-blocking layer, the thermal stress buffering effect of the stress-blocking layer can further alleviate crack propagation during reliability testing and long-term product service, avoiding failure of the chip package during reliability testing and improving the lifespan of the chip product during long-term service.

[0043] The material of any nth conductive body includes copper.

[0044] In one embodiment of the present invention, any nth conductive pillar further includes an nth nucleus layer located between the nth conductive body and the nth stress barrier layer, the nth nucleus layer being in contact with both the nth stress barrier layer and the nth conductive body. The nth nucleus layer serves as a seed layer for growing the nth conductive body.

[0045] The material of any nth nucleus layer includes copper.

[0046] It should be noted that in other embodiments, any nth conductive pillar may not include the nth nucleus layer, the nth stress barrier layer, and the nth conductive body in contact.

[0047] In one embodiment of the present invention, the elastic modulus of any nth stress-blocking layer is greater than that of the nth conductive body. Because the elastic modulus of any nth stress-blocking layer is larger, it can better absorb the thermal stress caused by material thermal mismatch, and simultaneously prevent the thermal stress from expanding towards the nth conductive body.

[0048] In one embodiment of the present invention, the material of any nth stress barrier layer includes nickel, tungsten, nickel-based compounds, tungsten-based compounds, or nanotwinned copper.

[0049] The elastic modulus of copper is 119 GPa, and the nth stress barrier layer can be made of nickel with an elastic modulus of 207 GPa or tungsten with an elastic modulus of 344 GPa.

[0050] In one embodiment of the present invention, the material of any nth stress barrier layer includes an organic buffer material doped with a plurality of conductive nanoparticles.

[0051] In one embodiment of the present invention, a plurality of conductive nanoparticles in any nth stress-barrier layer constitute a conductive mesh. The conductive nanoparticles of the conductive mesh are used to aggregate to form electron transport nodes, and the nodes with lower elastic modulus in the conductive mesh are used to release thermal stress.

[0052] In one embodiment of the present invention, the thickness of the conductive mesh is 0.5 μm-5 μm. For example, the thickness of the conductive mesh is 500 nm, 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0053] In one embodiment of the present invention, the conductive mesh includes a plurality of grids; in any nth stress barrier layer, the organic buffer material surrounded by the grids has pores; the nth stress barrier layer also has conductive particles filling the pores. The presence of the pores can absorb some thermal deformation, thus alleviating the cracking problem caused by thermal stress to a certain extent. The conductive particles can compensate for the high volume resistivity caused by the presence of pores, thereby improving the volume conductivity of the nth stress barrier layer.

[0054] In one embodiment of the present invention, the average particle size of the conductive particles is smaller than the average particle size of the conductive nanoparticles. This is because, in order to reduce the impedance of the electrical connection between adjacent conductive pillars stacked on top of each other, the average particle size of the copper atoms in the nucleus layer prepared by magnetron sputtering is in the nanometer range. These copper atoms can be embedded into the pores of the conductive nanoparticles and the organic buffer material surrounded by the mesh, thus synergistically improving the electron transport capability of the stacked conductive pillars with the conductive particles.

[0055] In one embodiment of the present invention, the conductive filler particles include copper filler particles. It should be noted that the conductive filler particles can also be other conductive materials.

[0056] In one embodiment of the present invention, the organic buffer material is a conductive adhesive or a polypyrrole-based polymer.

[0057] In one embodiment of the present invention, the conductive nanoparticles include one or more combinations of silver nanoparticles, copper nanoparticles, aluminum nanoparticles, and gold nanoparticles.

[0058] In one embodiment of the present invention, the average particle size of the conductive nanoparticles is 0.1 μm-5 μm. For example, the average particle size of the conductive nanoparticles is 0.1 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0059] In one embodiment of the present invention, the average particle size of the conductive particles is related to the power of magnetron sputtering. Preferably, the average particle size of the conductive particles is 20nm-200nm. For example, the average particle size of the conductive particles is 20nm, 40nm, 50nm, 60nm, 80nm, 100nm, 120nm, 140nm, 160nm, 180nm, or 200nm.

[0060] Reference Figure 3 In one embodiment of the present invention, the stacked conductive pillar interconnection structure includes a first dielectric layer P1, a second dielectric layer P2, and a third dielectric layer P3 stacked vertically in sequence. The first dielectric layer P1 has a first through-slot, the second dielectric layer P2 has a second through-slot, and the third dielectric layer P3 has a third through-slot. A first conductive pillar 11, a second conductive pillar 12, and a third conductive pillar 13 are stacked vertically and sequentially adjacent to each other. The first conductive pillar 11 is located in the first through-slot, the second conductive pillar 12 is located in the second through-slot, and the third conductive pillar 13 is located in the third through-slot. The first conductive pillar 11 includes a first stress-blocking layer 11a located on the inner wall surface of the first through-slot and a first conductive body 11c located on the first stress-blocking layer 11a. The second conductive pillar 12 includes a second stress-blocking layer 12a located on the inner wall surface of the second through-slot and a second conductive body 12c located on the second stress-blocking layer 12a. The third conductive post 13 includes: a third stress-blocking layer 13a located on the inner wall surface of the third through groove and a third conductive body 13c located on the third stress-blocking layer 13a.

[0061] Reference Figure 3 The first conductive pillar 11 further includes a first crystal nucleus layer 11b located between the first conductive body 11c and the first stress barrier layer 11a; the second conductive pillar 12 further includes a second crystal nucleus layer 12b located between the second conductive body 12c and the second stress barrier layer 12a; and the third conductive pillar 13 further includes a third crystal nucleus layer 13b located between the third conductive body 13c and the third stress barrier layer 13a.

[0062] In one embodiment of the present invention, the materials of the first stress-blocking layer 11a, the second stress-blocking layer 12a, and the third stress-blocking layer 13a are conductive materials with high elastic modulus, such as metallic materials with high elastic modulus. The elastic modulus of the first stress-blocking layer 11a is greater than that of the first conductive body 11c. The elastic modulus of the second stress-blocking layer 12a is greater than that of the second conductive body 12c. The elastic modulus of the third stress-blocking layer 13a is greater than that of the third conductive body 13c. Exemplarily, the material of the first stress-blocking layer 11a includes nickel, tungsten, nickel-based compounds, tungsten-based compounds, or nanotwinned copper. The material of the second stress-blocking layer 12a includes nickel, tungsten, nickel-based compounds, tungsten-based compounds, or nanotwinned copper. The material of the third stress-blocking layer 13a includes nickel, tungsten, nickel-based compounds, tungsten-based compounds, or nanotwinned copper.

[0063] In a specific example of the present invention, the first conductive body 11c, the second conductive body 12c, and the third conductive body 13c are all made of copper with an elastic modulus of 119 GPa; the first stress barrier layer 11a, the second stress barrier layer 12a, and the third stress barrier layer 13a are all made of nickel with an elastic modulus of 207 GPa; or, the first stress barrier layer 11a, the second stress barrier layer 12a, and the third stress barrier layer 13a are all made of tungsten with an elastic modulus of 344 GPa.

[0064] In one embodiment of the present invention, the materials of the first stress-blocking layer 11a, the second stress-blocking layer 12a, and the third stress-blocking layer 13a comprise an organic buffer material doped with a plurality of conductive nanoparticles. In another embodiment of the present invention, the plurality of conductive nanoparticles in the first stress-blocking layer 11a, the second stress-blocking layer 12a, and the third stress-blocking layer 13a constitute a conductive mesh. In one embodiment, the conductive nanoparticles include one or more combinations of silver nanoparticles, copper nanoparticles, aluminum nanoparticles, and gold nanoparticles. In one embodiment, the average particle size of the conductive nanoparticles is 0.1 μm-5 μm. Exemplarily, the average particle size of the conductive nanoparticles is 0.1 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0065] The first stress-blocking layer 11a, the second stress-blocking layer 12a, and the third stress-blocking layer 13a can be made of the same material or different materials.

[0066] The aforementioned conductive mesh is described in detail below, taking the first stress-barrier layer 11a as an example. (Refer to...) Figure 4 The conductive nanoparticles in the first stress barrier layer 11a form a conductive mesh 11a-1 with a thickness of 0.5μm-5μm. For example, the thickness of the conductive mesh 11a-1 is 500nm, 1μm, 2μm, 3μm, 4μm or 5μm.

[0067] In the first stress barrier layer 11a, the organic buffer material surrounded by a conductive mesh 11a-1 composed of several conductive nanoparticles has pores, and the conductive particles 11a-2 are located in the pores.

[0068] In one example, the average particle size of the conductive particles 11a-2 is smaller than the average particle size of the conductive nanoparticles. In one embodiment, the conductive particles 11a-2 comprise copper-filled particles.

[0069] In one embodiment of the present invention, the organic buffering material of the first stress barrier layer 11a, the second stress barrier layer 12a and the third stress barrier layer 13a is a conductive adhesive or a polypyrrole polymer.

[0070] In one embodiment, conductive nano-metal particles are dispersed in the conductive adhesive. The conductive adhesive is a polymeric buffer layer that absorbs thermal stress, which can alleviate crack propagation at the conductive interface caused by the full release of thermal stress.

[0071] This invention also provides a method for fabricating a stacked conductive pillar interconnect structure, comprising: forming a first dielectric layer to an Nth dielectric layer stacked vertically in sequence, and a first conductive pillar to an Nth conductive pillar stacked vertically and adjacent to each other in sequence; the step of forming any k conductive pillar, k+1 conductive pillar, k dielectric layer, and k+1 dielectric layer includes: forming a k dielectric layer, wherein a k-th through-groove is formed in the k dielectric layer; forming a k-th conductive pillar in the k-th through-groove, wherein forming a k-th conductive pillar in the k-th through-groove includes: forming a k-th stress-barrier layer on the inner wall surface of the k-th through-groove; and forming a k-th stress-barrier layer on the inner wall surface of the k-th through-groove. The steps of forming a k-th conductive body on a barrier layer; forming a k+1-th dielectric layer on a k-th dielectric layer, forming a k+1-th through-hole in the k+1-th dielectric layer, exposing the k-th conductive body in the k+1-th through-hole; and forming a k+1-th conductive pillar in the k+1-th through-hole include: forming a k+1-th stress barrier layer on the inner wall surface of the k+1-th through-hole, the k+1-th stress barrier layer being in contact with the k-th conductive body; and forming a k+1-th conductive body on the k+1-th stress barrier layer; where k is an integer greater than or equal to 1 and less than or equal to N-1.

[0072] In one embodiment, the elastic modulus of any nth stress barrier layer is greater than the elastic modulus of the nth conductive body; the process for forming any nth stress barrier layer includes a deposition process.

[0073] In one embodiment, the step of forming an arbitrary nth stress barrier layer includes: preparing a conductive paste in which a plurality of conductive nanoparticles are dispersed; spraying the conductive paste onto the inner wall surface of the nth channel; and curing the conductive paste on the inner wall surface of the nth channel to form the nth stress barrier layer, wherein the material of the nth stress barrier layer includes an organic buffer material doped with a plurality of conductive nanoparticles.

[0074] In one embodiment, during the curing process, several conductive nanoparticles in the conductive slurry agglomerate to form a conductive mesh, which includes several grids.

[0075] In one embodiment, the conductive paste further includes a volatile solvent, which evaporates during the curing process, creating voids in the organic buffer material surrounded by the mesh.

[0076] In one embodiment, the step of forming an arbitrary nth conductive pillar further includes: depositing an nth nucleus layer on the surface of the nth stress barrier layer before forming the nth conductive body.

[0077] In one embodiment, the method further includes forming conductive particles in the voids during the deposition of the nth nucleus layer on the surface of the nth stress barrier layer.

[0078] In one embodiment, the process of depositing the nth nucleus layer on the surface of the nth stress barrier layer includes a magnetron sputtering process.

[0079] The following section details the fabrication method of a stacked conductive pillar interconnection structure, using the formation of a first dielectric layer P1 and a first conductive pillar 11 located therein as an example.

[0080] The method for forming the first dielectric layer P1 and the first conductive pillar 11 located in the first dielectric layer P1 is as follows: Figure 5 and Figure 6 .

[0081] Reference Figure 5 The process involves forming a first dielectric layer P1; forming a patterned photoresist layer on the first dielectric layer P1; etching the first dielectric layer P1 using the photoresist layer as a mask to form a first through-hole in the first dielectric layer P1; and then removing the photoresist layer. The formation of the photoresist layer includes: forming a photoresist film, and sequentially subjecting the photoresist film to low-temperature baking, exposure, development, and curing to form a patterned photoresist layer. (Refer to...) Figure 5 A first stress-blocking layer 11a is formed on the inner wall surface of the first channel and the upper surface of the first dielectric layer P1; a first nucleus layer 11b is formed on the first stress-blocking layer 11a; a patterned first mask layer S1 is formed on the first nucleus layer 11b on the side of the first channel, the first mask layer S1 exposing the first nucleus layer 11b in the first channel; then, referring to Figure 6A first conductive body 11c is formed on the first nucleus layer 11b in the first channel; after the first conductive body 11c is formed, the first mask layer and the first nucleus layer 11b and the first stress barrier layer 11a covered by the first mask layer are removed.

[0082] In one embodiment, the elastic modulus of the first stress barrier layer 11a is greater than the elastic modulus of the first conductive body 11c; the process for forming the first stress barrier layer 11a includes a deposition process.

[0083] The process for forming the first nucleus layer 11b includes deposition processes, such as magnetron sputtering.

[0084] In another embodiment, the step of forming the first stress barrier layer 11a includes: preparing a conductive paste in which a plurality of conductive nanoparticles are dispersed; spraying the conductive paste onto the inner wall surface of the first channel and the upper surface of the first dielectric layer P1; and curing the conductive paste on the inner wall surface of the first channel and the upper surface of the first dielectric layer P1 to form the first stress barrier layer 11a, wherein the material of the first stress barrier layer 11a includes an organic buffer material doped with a plurality of conductive nanoparticles.

[0085] Specifically, in one embodiment, the conductive paste comprises 85wt%-90wt% nano-sized spherical silver powder, 0.12wt%-0.16wt% filler, 2wt%-4wt% resin, 0.1wt%-0.2wt% modifier, 3wt%-5wt% solvent, 0.1wt%-0.2wt% coupling agent, 0.1wt%-0.2wt% dispersant, 0.1wt%-0.2wt% curing agent, 0.1wt%-0.2wt% accelerator, and 0.08wt%-0.16wt% wetting agent. The solvent may be a volatile solvent.

[0086] The conductive paste is sprayed onto the inner wall surface of the first channel and the upper surface of the first dielectric layer P1 using a process including atomization spraying.

[0087] During the curing process of the conductive paste on the inner wall surface of the first channel and the upper surface of the first dielectric layer P1, several conductive nanoparticles in the conductive paste agglomerate to form a conductive mesh, which includes several grids. The conductive paste also contains volatile solvents. During the curing process, the volatile solvents in the conductive paste evaporate, creating voids in the organic buffer material surrounded by the grids.

[0088] During the deposition of the first nucleus layer 11b on the surface of the first stress barrier layer 11a, conductive particles are formed in the voids.

[0089] In other embodiments, the step of forming the first stress barrier layer 11a includes: spraying conductive adhesive onto the inner wall surface of the first channel and the upper surface of the first dielectric layer P1; and curing the conductive adhesive on the inner wall surface of the first channel and the upper surface of the first dielectric layer P1 to form the first stress barrier layer 11a.

[0090] Next, a second dielectric layer is formed on the first dielectric layer, and a second through-channel is formed in the second dielectric layer, exposing the first conductive body; a second conductive pillar is formed in the second through-channel; the step of forming the second conductive pillar in the second through-channel includes: forming a second stress barrier layer on the inner wall surface of the second through-channel and the upper surface of the second dielectric layer; forming a second nucleus layer on the second stress barrier layer; forming a patterned second mask layer on the second nucleus layer on the side of the second through-channel, the second mask layer exposing the second nucleus layer in the second through-channel; then, forming the second conductive body on the second nucleus layer in the second through-channel; after forming the second conductive body, removing the second mask layer and the second nucleus layer and the second stress barrier layer covered by the second mask layer.

[0091] In one embodiment, the elastic modulus of the second stress barrier layer is greater than the elastic modulus of the second conductive body; the process for forming the second stress barrier layer includes a deposition process.

[0092] The process for forming the second nucleus layer includes deposition processes, such as magnetron sputtering.

[0093] In another embodiment, the step of forming the second stress barrier layer includes: preparing a conductive paste in which a plurality of conductive nanoparticles are dispersed; spraying the conductive paste onto the inner wall surface of the second channel and the upper surface of the second dielectric layer; and curing the conductive paste on the inner wall surface of the second channel and the upper surface of the second dielectric layer to form the second stress barrier layer, wherein the material of the second stress barrier layer includes an organic buffer material doped with a plurality of conductive nanoparticles.

[0094] The composition of the conductive paste is as described above.

[0095] The conductive paste is sprayed onto the inner wall surface of the second channel and the upper surface of the second dielectric layer using a process including atomization spraying.

[0096] During the curing process of the conductive paste on the inner wall surface of the second channel and the upper surface of the second dielectric layer, several conductive nanoparticles in the conductive paste agglomerate to form a conductive mesh, which includes several grids. The conductive paste also contains volatile solvents. During the curing process, the volatile solvents in the conductive paste evaporate, creating voids in the organic buffer material surrounded by the grids.

[0097] During the deposition of the second nucleus layer on the surface of the second stress barrier layer, conductive particles are formed in the voids.

[0098] In other embodiments, the step of forming the second stress barrier layer includes: spraying conductive adhesive onto the inner wall surface of the second channel and the upper surface of the second dielectric layer; and curing the conductive adhesive on the inner wall surface of the second channel and the upper surface of the second dielectric layer to form the second stress barrier layer.

[0099] Next, a third dielectric layer is formed on the second dielectric layer, and a third through-channel is formed in the third dielectric layer, exposing the second conductive body; a third conductive pillar is formed in the third through-channel; the step of forming the third conductive pillar in the third through-channel includes: forming a third stress barrier layer on the inner wall surface of the third through-channel and the upper surface of the third dielectric layer; forming a third nucleus layer on the third stress barrier layer; forming a patterned third mask layer on the third nucleus layer on the side of the third through-channel, the third mask layer exposing the third nucleus layer in the third through-channel; then, forming the third conductive body on the third nucleus layer in the third through-channel; after forming the third conductive body, removing the third mask layer and the third nucleus layer and the third stress barrier layer covered by the third mask layer.

[0100] In one embodiment, the elastic modulus of the third stress barrier layer is greater than the elastic modulus of the third conductive body; the process for forming the third stress barrier layer includes a deposition process.

[0101] The process for forming the third nucleus layer includes deposition processes, such as magnetron sputtering.

[0102] In another embodiment, the step of forming the third stress barrier layer includes: preparing a conductive paste in which a plurality of conductive nanoparticles are dispersed; spraying the conductive paste onto the inner wall surface of the third channel and the upper surface of the third dielectric layer; and curing the conductive paste on the inner wall surface of the third channel and the upper surface of the third dielectric layer to form the third stress barrier layer, wherein the material of the third stress barrier layer includes an organic buffer material doped with a plurality of conductive nanoparticles.

[0103] The conductive paste is sprayed onto the inner wall surface of the third channel and the upper surface of the third dielectric layer using a process including atomization spraying.

[0104] During the curing process of the conductive paste on the inner wall surface of the third channel and the upper surface of the third dielectric layer, several conductive nanoparticles in the conductive paste agglomerate to form a conductive mesh, which includes several grids. The conductive paste also contains volatile solvents. During the curing process, the volatile solvents in the conductive paste evaporate, creating voids in the organic buffer material surrounded by the grids.

[0105] During the deposition of the third nucleus layer on the surface of the third stress barrier layer, conductive particles are formed in the voids.

[0106] In other embodiments, the step of forming the third stress barrier layer includes: spraying conductive adhesive onto the inner wall surface of the third channel and the upper surface of the third dielectric layer; and curing the conductive adhesive on the inner wall surface of the third channel and the upper surface of the third dielectric layer to form the third stress barrier layer.

[0107] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A stacked conductive pillar interconnection structure, characterized in that, include: The first dielectric layer to the Nth dielectric layer are stacked vertically in sequence; N is an integer greater than or equal to 2; any nth dielectric layer has an nth through-slot; The first to the Nth conductive pillars are vertically stacked and sequentially adjacent; Any nth conductive post is located in the nth through slot, and any nth conductive post includes: an nth stress barrier layer located on the inner wall surface of the nth through slot and an nth conductive body located on the nth stress barrier layer; n is an integer greater than or equal to 1 and less than or equal to N; any contact between the k-th conductive body and the (k+1)-th stress barrier layer, where k is an integer greater than or equal to 1 and less than or equal to N-1; The elastic modulus of any nth stress-blocking layer is greater than the elastic modulus of the nth conductive body.

2. The stacked conductive pillar interconnection structure according to claim 1, characterized in that, The material of any nth stress barrier layer includes nickel, tungsten, nickel-based compounds, tungsten-based compounds, or nanotwinned copper.

3. The stacked conductive pillar interconnection structure according to claim 1, characterized in that, The material of any nth stress barrier layer includes an organic buffer material doped with several conductive nanoparticles.

4. The stacked conductive pillar interconnection structure according to claim 3, characterized in that, A number of conductive nanoparticles in any nth stress barrier layer constitute a conductive mesh.

5. The stacked conductive pillar interconnection structure according to claim 4, characterized in that, The thickness of the conductive mesh is 0.5μm-5μm.

6. The stacked conductive pillar interconnection structure according to claim 4, characterized in that, The conductive mesh comprises a plurality of grids; in any nth stress barrier layer, the organic buffer material surrounded by the grids has pores; the nth stress barrier layer also has conductive particles filled in the pores; The average particle size of the filling conductive particles is smaller than the average particle size of the conductive nanoparticles.

7. The stacked conductive pillar interconnection structure according to claim 6, characterized in that, The conductive particles being filled include copper particles.

8. The stacked conductive pillar interconnection structure according to claim 3, characterized in that, The organic buffer material is a conductive adhesive or a polypyrrole-based polymer.

9. The stacked conductive pillar interconnection structure according to any one of claims 3 to 8, characterized in that, The conductive nanoparticles include one or more of the following: silver nanoparticles, copper nanoparticles, aluminum nanoparticles, and gold nanoparticles.

10. The stacked conductive pillar interconnection structure according to claim 9, characterized in that, The average particle size of the conductive nanoparticles is 0.1 μm-5 μm.

11. The stacked conductive pillar interconnection structure according to claim 1, characterized in that, Any nth conductive pillar further includes an nth nucleus layer located between the nth conductive body and the nth stress barrier layer.

12. A method for fabricating a stacked conductive pillar interconnect structure, characterized in that, include: Forming a first dielectric layer to an Nth dielectric layer that are vertically stacked in sequence, and a first conductive pillar to an Nth conductive pillar that are vertically stacked and adjacent to each other in sequence; The steps of forming any k-th conductive pillar, k+1-th conductive pillar, k-th dielectric layer, and k+1-th dielectric layer include: forming a k-th dielectric layer, in which a k-th through-groove is formed; forming a k-th conductive pillar in the k-th through-groove; the steps of forming a k-th conductive pillar in the k-th through-groove include: forming a k-th stress-barrier layer on the inner wall surface of the k-th through-groove; forming a k-th conductive body on the k-th stress-barrier layer; forming a k+1-th dielectric layer on the k-th dielectric layer, in which a k+1-th through-groove is formed, the k+1-th through-groove exposing the k-th conductive body; forming a k+1-th conductive pillar in the k+1-th through-groove; the steps of forming a k+1-th conductive pillar in the k+1-th through-groove include: forming a k+1-th stress-barrier layer on the inner wall surface of the k+1-th through-groove, the k+1-th stress-barrier layer being in contact with the k-th conductive body; forming a k+1-th conductive body on the k+1-th stress-barrier layer; where k is an integer greater than or equal to 1 and less than or equal to N-1. The elastic modulus of any nth stress-blocking layer is greater than the elastic modulus of the nth conductive body.

13. The method for fabricating the stacked conductive pillar interconnection structure according to claim 12, characterized in that, The process for forming an arbitrary nth stress barrier layer includes deposition processes.

14. The method for fabricating the stacked conductive pillar interconnection structure according to claim 12, characterized in that, The steps for forming an arbitrary nth stress barrier layer include: preparing a conductive paste in which a plurality of conductive nanoparticles are dispersed; spraying the conductive paste onto the inner wall surface of the nth channel; and curing the conductive paste on the inner wall surface of the nth channel to form the nth stress barrier layer, wherein the material of the nth stress barrier layer includes an organic buffer material doped with a plurality of conductive nanoparticles.

15. The method for fabricating the stacked conductive pillar interconnect structure according to claim 14, characterized in that, During the curing process, several conductive nanoparticles in the conductive slurry agglomerate to form a conductive mesh, which includes several grids.

16. The method for fabricating the stacked conductive pillar interconnect structure according to claim 14, characterized in that, The conductive paste also contains volatile solvents. During the curing process, the volatile solvents in the conductive paste evaporate, creating voids in the organic buffer material surrounded by the mesh.

17. The method for fabricating the stacked conductive pillar interconnection structure according to claim 16, characterized in that, The step of forming an arbitrary nth conductive pillar further includes depositing an nth nucleus layer on the surface of the nth stress barrier layer before forming the nth conductive body.

18. The method for fabricating the stacked conductive pillar interconnect structure according to claim 17, characterized in that, Also includes: During the deposition of the nth nucleus layer on the surface of the nth stress barrier layer, conductive particles are formed in the voids.

19. The method for fabricating the stacked conductive pillar interconnection structure according to claim 17, characterized in that, The process of depositing the nth nucleus layer on the surface of the nth stress barrier layer includes magnetron sputtering.

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