Mim capacitor and method of manufacturing the same

Abstract

The application relates to a MIM capacitor and a preparation method thereof. The MIM capacitor comprises a semiconductor substrate, at least one groove is arranged on the semiconductor substrate, the edge of the groove is in a thorn-shaped protruding structure, the inside of the groove is sequentially filled with a first conductive layer, a dielectric layer, a second conductive layer and a metal filling layer from bottom to top, and the first conductive layer covers all the bottom surfaces of the groove. The application does not have the problem of needing to undergo etching like traditional plane MIM capacitors, does not have the problem of layered bulging caused by stress, and can expand the capacitance according to needs and improve the integration.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a MIM capacitor and its fabrication method. Background Technology

[0002] With the development of very large-scale integrated circuits, the demand for capacitance density per unit area is increasing daily. To create high-precision capacitors while ensuring high-level device performance, MIM (metal-insulator-metal) capacitors are a key approach. Traditional MIM capacitors typically have a sandwich structure, consisting of an upper metal electrode and a lower metal electrode, separated by a thin insulating layer.

[0003] In related technologies, for MIM capacitors, the lateral area of ​​the capacitor is typically increased to improve the capacitor's footprint per unit area. However, due to the size limitations of integrated circuit devices, this technique is increasingly unable to guarantee the high performance required by integrated circuits. As the dielectric layer becomes thinner, and with the presence of etching and annealing steps during processing, delamination and bulging problems are more likely to occur due to stress.

[0004] Therefore, this invention is proposed. Summary of the Invention

[0005] The main objective of this invention is to provide a MIM capacitor and its fabrication method, which does not have the etching problem required by traditional planar MIM capacitors, nor does it generate delamination and bulging problems caused by stress. Furthermore, the capacitance can be expanded as needed to improve integration.

[0006] To achieve the above objectives, the present invention provides the following technical solutions.

[0007] A first aspect of the present invention provides a MIM capacitor comprising:

[0008] Semiconductor substrate;

[0009] The semiconductor substrate has at least one trench, and the edge of the trench has a spiky protrusion structure;

[0010] The trench is filled from bottom to top with a first conductive layer, a dielectric layer, a second conductive layer and a metal filling layer, and the first conductive layer covers all the bottom surfaces of the trench.

[0011] Furthermore, the trench is either a straight line or a broken line.

[0012] Furthermore, the groove has an S-shaped orientation.

[0013] Furthermore, the spines on the spiky protrusions are evenly spaced.

[0014] Furthermore, the trench is either a straight line or a broken line.

[0015] It also includes an electrode contact structure for the first conductive layer and an electrode contact structure for the second conductive layer; the electrode contact structure for the first conductive layer is located at the thorn-like protrusion structure, and the electrode contact structure for the second conductive layer is located on the metal filler layer.

[0016] Furthermore, the first conductive layer and the second conductive layer are each independently made of at least one of Ti or TiN.

[0017] Furthermore, the dielectric layer is made of at least one of HfO2, ZrO2, and composite ceramic materials; the metal filler layer is made of tungsten.

[0018] Furthermore, the thickness of the dielectric layer is 1–2 nm.

[0019] A second aspect of the present invention provides a method for preparing a MIM capacitor, which can be used to prepare the MIM capacitor described above, and includes the following steps:

[0020] Provide semiconductor substrates;

[0021] At least one trench with a spiky protrusion at the edge is etched on the semiconductor substrate;

[0022] The trench is filled from bottom to top with a first conductive layer, a dielectric layer, a second conductive layer, and a metal filler layer, with the first conductive layer covering all the bottom surfaces of the trench.

[0023] Furthermore, after filling the metal filler layer, the method further includes: an electrode contact structure for leading out the first conductive layer at the thorn-like protrusion structure, and an electrode contact structure for leading out the second conductive layer on the metal filler layer.

[0024] Compared with the prior art, the present invention achieves the following technical effects:

[0025] (1) This invention combines a spiky protrusion structure with layers surrounding the trench, which allows for both the array arrangement of capacitors and the electrode contact of the first and second conductive layers without etching the first and second conductive layers, i.e., using the exposed surface at the top of each layer as the contact point; at the same time, the 3D space within the trench expands the capacitor. Since this invention does not require etching, it avoids the problem of delamination caused by stress.

[0026] (2) The present invention can also adjust the direction of the trench to expand capacitors with different parallel connection methods.

[0027] (3) Compared with existing processes, the preparation method of the present invention does not add any extra steps. The spiky protrusion structure can be achieved by existing means such as OPC (Optical Process Modification) or a mask of a specific shape.

[0028] (4) There are no special restrictions on the materials of each layer in the capacitor. Attached Figure Description

[0029] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0030] Figure 1 This is a schematic diagram of an existing MIM capacitor structure;

[0031] Figure 2 A schematic diagram of a capacitor structure provided by the present invention;

[0032] Figure 3 This is a schematic diagram of another capacitor structure provided by the present invention;

[0033] Figure 4 A flowchart of a capacitor manufacturing method provided by the present invention;

[0034] Figure 5-13 The diagram shows the structure obtained in each step of the capacitor fabrication method provided in Embodiment 1 of the present invention. Detailed Implementation

[0035] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0036] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0037] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0038] Existing technical solutions mainly involve forming a sandwich structure, such as Figure 1 As shown, the system includes a substrate 101, an upper metal electrode 104 and a lower metal electrode 102 on the substrate 101. A thin insulating layer 103 separates the upper metal electrode 104 and the lower metal electrode 102, and they are then connected by metal contacts, namely electrode contacts 105a and 105b. Due to increasingly higher integration density, expansion becomes difficult, limiting capacitance to expansion within a 2D plane. Furthermore, the dielectric layer suffers from problems such as stress curling caused by etching.

[0039] This invention transforms 2D structures into 3D structures and, by modifying existing technologies, enables the formation of structures without altering existing processes.

[0040] The two MIM capacitor structures provided by this invention are as follows: Figure 2 and 3 As shown, it includes a semiconductor substrate 201, which can be any substrate known to those skilled in the art for carrying components of a semiconductor integrated circuit, such as, but not limited to, bulk silicon, silicon carbide, germanium, germanium-silicon, gallium arsenide, sapphire, etc. The semiconductor substrate may also contain other optoelectronic structures besides capacitors, such as waveguides, gates, source / drain electrodes, etc., which can be formed before or after the formation of capacitors.

[0041] At least one trench 206 is provided on the semiconductor substrate 201, and the edge of the trench 206 has a spiky protrusion structure 207. The spiky protrusion structure of the present invention refers to a structure containing multiple spikes, that is, the sidewall of the trench 206 is not an arc surface or a plane, but a sidewall containing multiple protruding spikes, and the edge line appears as... when viewed from above. Figure 2 The serrated shape is shown. For ease of understanding, the aforementioned "thorns" can also be called "spikes." These spike-like protrusions serve as electrode contact points. Their combination with the stacked capacitor structure surrounding the trench avoids the delamination and bulging problems caused by etching through the sandwich structure to form contact holes in existing technologies, while also reducing the number of etching passes in the overall process. Furthermore, Figure 2 The illustrated "thorn" has a triangular cross-section, but the invention does not limit the cross-sectional shape of the thorn; it can also be replaced with a circle, ellipse, or other polygons. The "thorns" or "spikes" can be arranged in a regular, equidistant pattern.

[0042] The present invention does not particularly limit the orientation and size of the trench 206, and different degrees of capacitance expansion can be achieved by adjusting the orientation and size. For example, further, the trench is as follows: Figure 2 The indicated straight line or broken line direction, the broken line direction can be as follows: Figure 3 The diagram shows the winding, meandering S-shaped line.

[0043] The trench 206 contains stacked, surrounding capacitor structures, as detailed below. From bottom to top, the trench 206 is filled with a first conductive layer 202, a dielectric layer 203, a second conductive layer 204, and a metal filler layer 205. The first three layers serve as the lower electrode, insulating layer, and upper electrode, respectively. Because the first conductive layer 202, dielectric layer 203, second conductive layer 204, and metal filler layer 205 are stacked in a U-shape, their top surfaces are all exposed. Furthermore, the first conductive layer 202 covers all bottom surfaces of the trench 206. The trench area covered by the first conductive layer 202, dielectric layer 203, second conductive layer 204, and metal filler layer 205 gradually decreases, and the top surfaces are all exposed, allowing electrode contacts to be established without etching. There are no particular restrictions on the materials of each layer in the above capacitor. For example, the first conductive layer 202 and the second conductive layer 204 can each independently use typical materials such as Ti and / or TiN; the dielectric layer 203 can use typical materials such as HfO2, ZrO2, and composite ceramic materials, and can be a single material or a stack of different materials. Since the present invention does not require etching when making electrode contacts, the thickness of the dielectric layer is not affected by etching and can be very thin, for example, 1 to 2 nm; the metal filling layer 205 can be any metal with good conductivity, such as tungsten.

[0044] The electrode contacts can be as follows: the electrode contact structure of the first conductive layer 202 is located at the thorn-like protrusion structure 207, and the electrode contact structure of the second conductive layer 204 is located on the metal filling layer 205.

[0045] The MIM capacitors mentioned above can be used as follows: Figure 4 The method described mainly includes the following steps.

[0046] First, a semiconductor substrate is provided.

[0047] Then, at least one trench with a spiky protrusion at the edge is etched on the semiconductor substrate.

[0048] Next, a first conductive layer is filled into the trench, covering all the bottom surfaces of the trench. The filling method depends on the material of the conductive layer. For example, for metallic materials, sputtering is typically used. For semiconductor materials, selective epitaxy, LPCVD, ALD, RTCVD, or PECVD can be used.

[0049] Then a dielectric layer is filled in. The methods for forming the dielectric layer include, but are not limited to, selective epitaxy, LPCVD, ALD, RTCVD, or PECVD.

[0050] A second conductive layer is filled on top of the dielectric layer, and the method of filling the second conductive layer depends on the material of the conductive layer.

[0051] A metal filler layer is filled on top of the second conductive layer, and optionally planarized.

[0052] The first conductive layer, dielectric layer, second conductive layer, and metal filler layer are arranged in a series of overlapping droplets.

[0053] Finally, the electrode contact structure of the first conductive layer is led out at the spiky protrusion, and the electrode contact structure of the second conductive layer is led out on the metal filler layer. Before leading out the electrode contact structure, it is usually necessary to cover the capacitor structure with a cut-off material, and then only the dielectric material is etched to form contact holes, which are then filled with conductive materials such as metal to form contact plugs.

[0054] The present invention also provides an embodiment for fabricating a capacitor using a silicon substrate as an example.

[0055] Example 1

[0056] The first step involves etching trenches 206 with spiky protrusions 207 onto a silicon semiconductor substrate 201. The top view of the structure is as follows: Figure 5 As shown, the groove 206 can be formed by OPC (Optical Process Modification) or by using a mask that can produce this shape.

[0057] The second step is to fill the trench 206 with the first conductive layer 202, as shown in the top view. Figure 6 As shown ( Figures 6 to 8 The substrate outside the trench was made transparent to clearly show the filling layers inside the trench (i.e., the materials synchronously deposited on the substrate surface outside the trench are not shown). The material can be a Ti / TiN structure to form the lower electrode of the MIM capacitor, with thorn-like protrusions used for contact.

[0058] The third step is to deposit a dielectric layer 203 on the first conductive layer 202, as shown in the top view. Figure 7As shown, the medium can be HfO2, but is not limited to this material. It can also be a multilayer medium, such as ZrO2 or composite ceramic materials. The medium layer is usually very thin, typically 1-2 nm thick.

[0059] Fourth step, the second conductive layer 204 is deposited on the dielectric layer 203, and the structure is shown in top view as follows. Figure 8 As shown, the material of the second conductive layer can be TiN / Ti.

[0060] Step 5: Metal filling and planarization, with the cross-sectional structure along the trench depth direction as follows: Figure 9 As shown, the metal filler layer 205 can be tungsten filler from the previous process. Afterwards, the entire surface is planarized, and the cross-sectional structure along the depth direction of the trench 206 is as follows. Figure 10 As shown, the top view of the structure is as follows Figure 11 As shown.

[0061] The sixth step involves making electrode contacts, including electrode contact structures 208a and 208b. Before the electrodes are led out, the entire assembly is filled with insulating material 209. The top view of the structure is as follows: Figure 12 As shown, the cross-sectional structure along the trench depth direction is as follows: Figure 13 As shown, the number of electrode contacts depends on the situation.

[0062] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A MIM capacitor, characterized in that, include: Semiconductor substrate; The semiconductor substrate has at least one trench, and the edge of the trench has a spiky protrusion structure; The trench is filled from bottom to top with a first conductive layer, a dielectric layer, a second conductive layer and a metal filling layer. The first conductive layer covers all the bottom surfaces of the trench. The trench area covered by the first conductive layer (202), the dielectric layer (203), the second conductive layer (204) and the metal filling layer (205) gradually decreases, and the top surfaces are all exposed, allowing for electrode contact. The thickness of the dielectric layer is 1~2 nm.

2. The MIM capacitor according to claim 1, characterized in that, The trenches can be straight or broken lines.

3. The MIM capacitor according to claim 2, characterized in that, The trench has an S-shaped orientation.

4. The MIM capacitor according to claim 1, characterized in that, The thorns on the thorn-like protrusions are evenly spaced.

5. The MIM capacitor according to claim 1, characterized in that, It also includes an electrode contact structure for the first conductive layer and an electrode contact structure for the second conductive layer; the electrode contact structure for the first conductive layer is located at the thorn-like protrusion structure, and the electrode contact structure for the second conductive layer is located on the metal filler layer.

6. The MIM capacitor according to claim 1, characterized in that, The first conductive layer and the second conductive layer are each independently made of at least one of Ti or TiN.

7. The MIM capacitor according to claim 1 or 6, characterized in that, The dielectric layer is made of at least one of HfO2, ZrO2, and composite ceramic materials; the metal filler layer is made of tungsten.

8. A method for preparing a MIM capacitor as described in claim 1, characterized in that, Includes the following steps: Provide semiconductor substrates; At least one trench with a spiky protrusion at the edge is etched on the semiconductor substrate; The trench is filled from bottom to top with a first conductive layer, a dielectric layer, a second conductive layer, and a metal filler layer, with the first conductive layer covering all the bottom surfaces of the trench.

9. The preparation method according to claim 8, characterized in that, After filling the metal filler layer, the method further includes: leading out an electrode contact structure of the first conductive layer at the spiky protrusion structure, and leading out an electrode contact structure of the second conductive layer on the metal filler layer.

Images