Semiconductor structure and method of forming the same

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a forming method thereof. The semiconductor structure includes: a substrate; a plurality of semiconductor pillars above the substrate, the semiconductor pillars extending along a first direction, the plurality of semiconductor pillars being spaced apart along a second direction and a third direction, the semiconductor pillars having a channel region and a doped region on opposite sides of the channel region; a first support layer on sidewalls of the channel region of the semiconductor pillars arranged along the second direction; a second support layer between adjacent first support layers; and a plurality of word line structures extending along the second direction, at least on two surfaces of the channel region of the plurality of semiconductor pillars arranged along the second direction in the third direction, and on two surfaces of the first support layer and the second support layer in the third direction. Embodiments of the present disclosure at least facilitate ensuring that the word line has better continuity.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] As the integration density of dynamic memory continues to increase, higher requirements are being placed on the arrangement and size of transistors in the dynamic memory array structure.

[0003] Currently, an independent word line structure is usually set on the channel regions of multiple transistors. If the spacing between adjacent transistor channel regions corresponding to the same word line structure is too large, it may cause deformation or even breakage of the word line structure between adjacent transistor channel regions. A word line structure with poor continuity will lead to poor reliability of dynamic memory performance and affect the yield of dynamic memory. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for forming the same, which at least helps to ensure better continuity of word lines.

[0005] This disclosure provides a semiconductor structure, comprising: a substrate; a plurality of semiconductor pillars located above the substrate, the semiconductor pillars extending along a first direction, the plurality of semiconductor pillars being spaced apart along a second direction and a third direction, each semiconductor pillar having a channel region and doped regions located on opposite sides of the channel region; a first support layer located on the sidewalls of the channel regions of the semiconductor pillars arranged along the second direction; a second support layer located between adjacent first support layers; and a plurality of word line structures extending along the second direction, at least located on two surfaces of the channel regions of the plurality of semiconductor pillars arranged along the second direction in the third direction, and also located on two surfaces of the first support layer and the second support layer in the third direction.

[0006] In some embodiments, the first direction and the second direction are both parallel to the substrate surface, the third direction is perpendicular to the substrate surface, the top surface of the first support layer and the top surface of the second support layer are both flush with the top surface of the adjacent semiconductor pillar, and the bottom surface of the first support layer and the second support layer are both flush with the bottom surface of the adjacent semiconductor pillar.

[0007] In some embodiments, an air gap is included between the first support layer and the second support layer.

[0008] In some embodiments, in the second direction, adjacent semiconductor pillars include at least two first support layers and at least two air gaps, each first support layer having the same thickness and each air gap having the same width.

[0009] In some embodiments, a reinforcing layer is provided between the first support layer and the second support layer.

[0010] In some embodiments, in the second direction, at least two first support layers and at least two reinforcing layers are included between adjacent semiconductor pillars, each first support layer having the same thickness and each reinforcing layer having the same thickness.

[0011] In some embodiments, the material of the reinforcing layer is different from the material of the first support and the material of the second support layer.

[0012] In some embodiments, the first support layer and the second support layer are made of the same material.

[0013] In some embodiments, the word line structure includes: a first word line layer, which is located on the top surface of the channel region of the semiconductor pillar, the top surface of the first support layer, and the top surface of the second support layer; and a second word line layer, which is located on the bottom surface of the channel region of the semiconductor pillar, the bottom surface of the first support layer, and the bottom surface of the second support layer; and in a third direction, the first word line layer and the second word line layer have the same thickness.

[0014] In some embodiments, the device further includes a gate dielectric layer located on two third-direction surfaces of the channel region of the semiconductor pillar and between the word line structure and the channel region of the semiconductor pillar.

[0015] In some embodiments, the system further includes an isolation layer located between adjacent word line structures.

[0016] In some embodiments, the device further includes: a dielectric layer located between doped regions of a portion of the semiconductor pillars adjacent to the channel region, and a surface extending along a first direction around the doped regions of the portion of the semiconductor pillars, and the dielectric layer being in contact with both ends of the word line structure in the first direction.

[0017] This disclosure also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of semiconductor pillars located above the substrate, the semiconductor pillars extending along a first direction, the plurality of semiconductor pillars being spaced apart along a second direction and a third direction, each semiconductor pillar having a channel region and doped regions located on opposite sides of the channel region; forming a first support layer located on the sidewalls of the channel regions of the semiconductor pillars arranged along the second direction; forming a second support layer located between adjacent first support layers; and forming a plurality of word line structures extending along the second direction, at least located on two surfaces of the channel regions of the plurality of semiconductor pillars arranged along the second direction in the third direction, and also located on two surfaces of the first support layer and the second support layer in the third direction.

[0018] In some embodiments, forming a semiconductor pillar includes: forming a plurality of semiconductor layers spaced apart in a third direction and an epitaxial layer between the semiconductor layers; patterning the semiconductor layers and the epitaxial layer to form a groove extending along a first direction, with the remaining semiconductor layers serving as the semiconductor pillar.

[0019] In some embodiments, forming the first support layer and the second support layer includes: forming a first support film and a second support film in a groove, the first support film being in contact with a semiconductor pillar and an epitaxial layer on the sidewall of the groove, the second support film being spaced apart from the first support film along a second direction and located between the first support films; forming a sacrificial layer located between the channel regions of a portion of the semiconductor pillars adjacent to the doped region and extending along a first direction around the channel regions of the portion of the semiconductor pillars; removing the sacrificial layer to expose the epitaxial layer between the channel regions of the semiconductor pillars; removing the epitaxial layer between the channel regions of the semiconductor pillars to form an etch hole; removing the first support film and the second support film between the sidewalls of the etch hole, with the remaining first support film serving as the first support layer and the remaining second support film serving as the second support layer.

[0020] In some embodiments, before forming the sacrificial layer, the method further includes: forming a reinforcing film; and removing the reinforcing film between the sidewalls of the etched hole while removing the first and second support films between the sidewalls of the etched hole.

[0021] In some embodiments, the method further includes: removing the reinforcing membrane to form an air gap.

[0022] In some embodiments, prior to removing the sacrificial layer, the method further includes forming a dielectric layer located between doped regions of a portion of the semiconductor pillars adjacent to the sacrificial layer and surrounding a surface of the doped regions of the portion of the semiconductor pillars extending in a first direction.

[0023] The technical solutions provided in this disclosure have at least the following advantages:

[0024] In the above technical solution, multiple semiconductor pillars on the substrate are used to form the semiconductor channels of transistors. The doped regions on both sides of the channel region of the semiconductor pillars are used to form the source and drain of transistors. The word line structure is located on the top and bottom surfaces of the channel region of a row of semiconductor pillars arranged along the second direction. It is used to control the channel region of the row of semiconductor pillars arranged along the second direction based on the control signal. The area between the word line structure on the top surface of the semiconductor pillars and the word line structure on the bottom surface of the semiconductor pillars includes, in addition to the spaced semiconductor pillars, a first support layer and a second support layer between adjacent semiconductor pillars. The first support layer, which is in contact with the sidewall of the channel region of the semiconductor pillars, is used to provide support for the word line structure and to provide isolation protection for the channel region of the semiconductor pillars. The second support layer located between the first support layers is used to strengthen the support force on the word line structure. The first support layer and the second support layer provide support for the word line structure between the top and bottom surfaces of the channel region, which helps to avoid deformation or even breakage of the word line structure between the channel regions of adjacent semiconductor pillars and helps to ensure that the word line structure has better continuity. Attached Figure Description

[0025] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A cross-sectional view of the channel region of a semiconductor structure perpendicular to a first direction, provided in an embodiment of this disclosure;

[0027] Figure 2 A cross-sectional view of a semiconductor structure perpendicular to a second direction, provided in an embodiment of this disclosure;

[0028] Figure 3 A cross-sectional view of the channel region of another semiconductor structure provided in an embodiment of this disclosure, perpendicular to the first direction;

[0029] Figures 4 to 15 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0030] As is known from the background art, if the spacing between adjacent transistor channel regions corresponding to the word line structure is too large, it may lead to poor continuity of the word line structure.

[0031] This disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a substrate and semiconductor pillars. The semiconductor pillars are used to form semiconductor channels for transistors. Doped regions on both sides of the channel region of the semiconductor pillars are used to form the source and drain of the transistors. The structure also includes word line structures located on the top and bottom surfaces of the channel region of a row of semiconductor pillars arranged along a second direction. The word line structures are used to control the channel region of the row of semiconductor pillars arranged along the second direction based on control signals. The area between the word line structures on the top and bottom surfaces of the semiconductor pillars includes, in addition to the spaced semiconductor pillars, a first support layer and a second support layer between adjacent semiconductor pillars. The first support layer, which contacts the sidewall of the channel region of the semiconductor pillars, provides support for the word line structures and provides isolation protection for the channel region of the semiconductor pillars. The second support layer, located between the first support layers, strengthens the support force on the word line structures. The first and second support layers provide support for the word line structures between the top and bottom surfaces of the channel region, which helps to prevent deformation or even breakage of the word line structures between the channel regions of adjacent semiconductor pillars, and helps to ensure better continuity of the word line structures.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] Figure 1 A cross-sectional view of the channel region of a semiconductor structure perpendicular to a first direction, provided in an embodiment of this disclosure; Figure 2 A cross-sectional view of a semiconductor structure perpendicular to a second direction, provided in an embodiment of this disclosure; Figure 3 A cross-sectional view of the channel region of another semiconductor structure provided in an embodiment of this disclosure, perpendicular to a first direction.

[0034] refer to Figure 1 and Figure 2 The semiconductor structure includes: a substrate 100; a plurality of semiconductor pillars 110 located above the substrate 100, the semiconductor pillars 110 extending along a first direction Y, the plurality of semiconductor pillars 110 being arranged at intervals along a second direction X and a third direction Z, the semiconductor pillars 110 having a channel region II and doped regions located on opposite sides of the channel region II.

[0035] The substrate 100 is made of a semiconductor material. In some embodiments, the substrate 100 is a silicon substrate. In other embodiments, the substrate 100 may also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0036] Semiconductor pillar 110 is used to form the semiconductor channel of a transistor. In some embodiments, the material of semiconductor pillar 110 may be the same as the material of substrate 100. In one example, the material of semiconductor pillar 110 may be silicon.

[0037] In some embodiments, the first direction Y and the second direction X can be parallel to the surface of the substrate 100, and the third direction Z can be perpendicular to the surface of the substrate 100. The semiconductor pillars 110 extend in a direction parallel to the surface of the substrate 100 and are spaced apart on the substrate 100. This facilitates the multi-layer stacking of transistors in a direction perpendicular to the surface of the substrate 100, which helps to integrate a larger number of transistors in a limited space, improves the integration density of the semiconductor structure, and achieves smaller integration while ensuring better performance.

[0038] Semiconductor pillar 110 includes a channel region II and doped regions located on both sides of the channel region II. The doped regions include a first doped region I and a second doped region III. The first doped region I, the channel region II, and the second doped region III are sequentially distributed along the extension direction of the semiconductor pillar 110, i.e., the first direction Y. The first doped region I and the second doped region III are used to form the source and drain of the transistor, and the channel region II of the semiconductor pillar 110 is used to form the channel region II of the transistor. In some embodiments, the type of dopant ions in the first doped region I and the second doped region III may be different from the type of dopant ions in the channel region II. Specifically, in one example, the dopant ions in the first doped region I and the second doped region III may be N-type ions, and the dopant ions in the channel region II may be P-type ions. The P-type ions may be at least one of boron ions, indium ions, or gallium ions, and the N-type ions may be at least one of arsenic ions, phosphorus ions, or antimony ions. In another example, the dopant ions in the first doped region I and the second doped region III may be P-type ions, and the dopant ions in the channel region II may be N-type ions. In other embodiments, the type of dopant ions in the doped region may also be the same as the type of dopant ions in the channel region II, that is, the semiconductor pillar 110 may be used to form a junctionless field-effect transistor.

[0039] refer to Figure 1 and Figure 2 The semiconductor structure further includes: a first support layer 120 located on the sidewall of the channel region II of the semiconductor pillars 110 arranged along the second direction X; and a second support layer 130 located between adjacent first support layers 120. A plurality of word line structures 160 extend along the second direction X and are located at least on the two surfaces of the channel region II of the plurality of semiconductor pillars 110 arranged along the second direction X in the third direction, and also on the two surfaces of the first support layer 120 and the second support layer 130 in the third direction. The first support layer 120, which contacts the sidewall of the channel region II of the semiconductor pillar 110, provides support for the word line structure and also provides isolation and protection for the channel region II of the semiconductor pillar 110. The second support layer 130 helps to strengthen the support force on the word line structure 160. The first support layer 120 and the second support layer 130 help to prevent the word line structure 160 from deforming or breaking between adjacent channel regions II of the semiconductor pillar 110, thus ensuring better continuity of the word line structure 160.

[0040] In this embodiment of the present disclosure, a row of semiconductor pillars 110 arranged along the second direction X shares a word line structure 160. The word line structure 160 serves as the gate of a transistor, used to conduct channel region II based on a control signal, thereby enabling carrier transport between the source and drain. The word line structure 160 is made of a conductive material, and in some examples, the material of the word line structure 160 includes at least one of polysilicon, titanium nitride, tungsten, molybdenum, titanium, cobalt, or ruthenium.

[0041] In some embodiments, reference Figure 1 and Figure 2 The word line structure 160 includes: a first word line layer 161, located on the top surface of the channel region II of the semiconductor pillar 110, the top surface of the first support layer 120, and the top surface of the second support layer 130; and a second word line layer 162, located on the bottom surface of the channel region II of the semiconductor pillar 110, the bottom surface of the first support layer 120, and the bottom surface of the second support layer 130. In the third direction Z, the first word line layer 161 and the second word line layer 162 have the same thickness. That is, the word line structure 160 is a double-layer word line structure composed of two conductive layers. This double-layer word line structure can achieve a simpler structure 160 using less word line material while ensuring superior driving capability for the transistors, which is beneficial for reducing the fabrication cost and processing difficulty of the semiconductor structure. Furthermore, the first word line layer 161 and the second word line layer 162, which have the same thickness, ensure that the first word line layer 161 and the second word line layer 162 have the same driving capability for the channel region II of the semiconductor pillar 110, which is beneficial to improving the electrical performance of the semiconductor structure.

[0042] In some implementations, the first letter line layer 161 and the second letter line layer 162 are made of the same material, and the first letter line layer 161 and the second letter line layer 162 are structures formed simultaneously using the same manufacturing process. This helps to reduce the manufacturing difficulty of the first letter line layer 161 and the second letter line layer 162.

[0043] In some embodiments, reference Figure 1 and Figure 2 The semiconductor structure further includes a gate dielectric layer 150, which is located on the two surfaces of the channel region II of the semiconductor pillar 110 in the third direction Z, and between the word line structure 160 and the channel region II of the semiconductor pillar 110. The gate dielectric layer 150 is used to enable the word line structure 160 to drive the source and drain of the transistor to conduct. In some embodiments, the material of the gate dielectric layer 150 can be silicon oxide. The process of forming silicon oxide on the silicon-based semiconductor pillar 110 using thermal oxidation is mature and helps to reduce the fabrication difficulty of the gate dielectric layer 150. In other embodiments, the material of the gate dielectric layer 150 can also be silicon nitride or silicon oxynitride.

[0044] refer to Figure 1 The adjacent semiconductor pillars 110 arranged along the second direction X have a spacing region extending towards the first direction Y. The first support layer 120 and the second support are located in the spacing region between the sidewalls of the channel region II of the semiconductor pillars 110. In this embodiment of the present disclosure, the first support layer 120 includes a second support layer 130. It can be understood that if the spacing distance between the sidewalls of the channel region II of the adjacent semiconductor pillars 110 is large, the first support layer 120 may also include multiple second support layers 130 arranged at intervals in the second direction X.

[0045] In some embodiments, reference Figure 1 The top surfaces of the first support layer 120 and the second support layer 130 are flush with the top surfaces of the adjacent semiconductor pillars 110, and the bottom surfaces of the first support layer 120 and the second support layer 130 are flush with the bottom surfaces of the adjacent semiconductor pillars 110. This ensures that the word line structure 160 extends on a relatively flat plane formed by the semiconductor pillars 110, the first support layer 120, and the second support layer 130, which helps prevent the word line structure 160 from bending and, consequently, from breaking.

[0046] In some embodiments, the first support layer 120 and the second support layer 130 are made of the same material. This allows the first support layer 120 and the second support layer 130 to be fabricated simultaneously using the same process, which helps reduce the fabrication difficulty of the first support layer 120 and the second support layer 130. In one example, the materials of the first support layer 120 and the second support layer 130 can be silicon oxide.

[0047] refer to Figure 3 In some embodiments, an air gap 180 is included between the first support layer 120 and the second support. Air has a low dielectric constant, and providing an air gap 180 helps to reduce the coupling capacitance between the channel regions II of adjacent semiconductor pillars 110, which helps to improve the electrical performance of the semiconductor structure. The air gap 180 also helps to improve the heat dissipation capability of the semiconductor structure.

[0048] refer to Figure 3 In some embodiments, in the second direction X, adjacent semiconductor pillars 110 include at least two first support layers 120 and at least two air gaps 180, with each first support layer 120 having the same thickness and each air gap 180 having the same width. This ensures that the first support layers 120 and second support layers 130 between different semiconductor pillars 110 have the same arrangement, and that the spacing between the sidewalls of the channel region II of the semiconductor pillars 110 is the same. This helps to reduce the arrangement differences between the semiconductor pillars 110 and ensures that the semiconductor structure has better electrical uniformity.

[0049] refer to Figure 1In some embodiments, a reinforcing layer 140 is provided between the first support layer 120 and the second support layer 130. The reinforcing layer 140 can be a dielectric material with strong support. The provision of the reinforcing layer 140 is beneficial to further improve the support capability of the word line structure 160 and ensure that the word line structure 160 in the semiconductor structure has high stability.

[0050] refer to Figure 1 In some embodiments, in the second direction X, adjacent semiconductor pillars 110 include at least two first support layers 120 and at least two reinforcing layers 140, with each second support layer 130 having the same thickness and each reinforcing layer 140 having the same thickness. This ensures that the first support layers 120, second support layers 130, and reinforcing layers 140 between different semiconductor pillars 110 have the same arrangement, and that the spacing between the sidewalls of the channel region II of the semiconductor pillars 110 is the same. This helps to reduce the arrangement differences between the semiconductor pillars 110 and ensures that the semiconductor structure has better electrical uniformity.

[0051] refer to Figure 1 In some embodiments, the material of the reinforcing layer 140 is different from the materials of the first support layer 120 and the second support layer 130. Specifically, a more common dielectric material can be used as the first support layer 120 and the second support, while a material with strong support capacity can be used as the reinforcing layer 140. By balancing the fabrication cost and difficulty of the reinforcing layer 140 with that of the first support layer 120 or the second support layer 130, sufficient support force for the word line structure 160 can be ensured while reducing the processing cost and difficulty of the semiconductor structure. In one example, the material of the reinforcing layer 140 can be silicon nitride.

[0052] refer to Figure 1 or Figure 3 In some embodiments, the semiconductor structure further includes an isolation layer 170 located between adjacent word line structures 160. The isolation layer 170 separates the word line structures 160, which not only protects the word line structures 160 but also helps prevent them from being damaged by impurities in subsequent processes. The isolation layer 170 also provides support for other structures subsequently formed on the word line structures 160, thus improving the stability of the semiconductor structure.

[0053] In some embodiments, the isolation layer 170 is made of silicon oxide, and the fabrication process of silicon oxide is mature, which helps to reduce the processing difficulty of semiconductor structures. In other embodiments, the isolation layer 170 may also be other insulating materials with barrier effects, such as silicon oxynitride.

[0054] refer to Figure 2In some embodiments, the system further includes a dielectric layer 107 located between the doped regions of a portion of the semiconductor pillars 110 adjacent to the channel region II, and extending along a first direction Y around the doped region II of the semiconductor pillars 110. The dielectric layer 107 contacts both ends of the word line structure 160 in the first direction Y. The dielectric layer 107 not only provides support for the semiconductor pillars 110 spaced apart in a third direction Z, but also isolates the sidewalls of the word line structure 160 from other structures, preventing damage to the channel region II and the word line structure 160 during subsequent processing of the doped regions of the semiconductor pillars 110.

[0055] In some embodiments, the dielectric layer 107 may be made of silicon nitride. Silicon nitride has a mature manufacturing process and exhibits good blocking effects against impurity ions or moisture, which is beneficial for providing superior protection to the word line structure 160. In other embodiments, the dielectric layer 107 may also be made of other insulating materials with blocking effects, such as silicon oxynitride.

[0056] In the semiconductor structure provided in the above embodiments, a plurality of semiconductor pillars 110 on the substrate 100 are used to form semiconductor channels of transistors. The doped regions on both sides of the channel region II of the semiconductor pillars 110 are used to form the source and drain of the transistors. The word line structure 160 is located on the top and bottom surfaces of the channel region II of a row of semiconductor pillars 110 arranged along the second direction X, and is used to control the channel region II of the row of semiconductor pillars 110 arranged along the second direction X based on a control signal. The word line structure 160 on the top surface of the semiconductor pillars 110 and the word line structure 160 on the bottom surface of the semiconductor pillars 110 are spaced apart by the semiconductor pillars 110. 0, also includes a first support layer 120 and a second support layer 130 between adjacent semiconductor pillars 110. The first support layer 120, which is in contact with the sidewall of the channel region II of the semiconductor pillar 110, is used to provide support for the word line and to provide isolation protection for the channel region II of the semiconductor pillar 110. The second support layer 130 is used to strengthen the support force on the word line structure 160. The first support layer 120 and the second support layer 130 help to prevent the word line structure 160 from bending or breaking between adjacent semiconductor pillars 110 channel regions II, and help to ensure that the word line structure 160 has better continuity.

[0057] Accordingly, this disclosure also provides a method for forming a semiconductor structure, which can be used to form the semiconductor structure described in the above embodiments. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments can be referred to in the detailed description of the foregoing embodiments, and will not be repeated hereafter.

[0058] Figures 4 to 15 This diagram illustrates the steps of a method for forming a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figures 4 to 15 middle, Figure 7 , Figure 8 as well as Figure 12 This is a cross-sectional view perpendicular to the second direction X; Figures 9 to 11 This is a cross-sectional view of the channel region II of the semiconductor pillar 110, perpendicular to the first direction Y. Figures 13 to 14 This is a cross-sectional view of the semiconductor pillar 110 perpendicular to the third direction Z (for ease of understanding). Figures 13 to 14 The word line structure 160 on the channel region II of the semiconductor pillar 110 is shown.

[0059] refer to Figure 4 The method for forming a semiconductor structure includes providing a substrate. In some embodiments, the substrate 100 may be a silicon substrate. Epitaxial processes based on silicon substrates are relatively mature, which helps to reduce the difficulty of forming semiconductor pillars.

[0060] refer to Figures 4 to 5 Multiple semiconductor pillars 110 are formed, extending along a first direction Y. The semiconductor pillars 110 are spaced apart along a second direction X and a third direction Z. Both the first direction Y and the second direction X are parallel to the surface of the substrate 100, and the third direction Z is perpendicular to the surface of the substrate 100. Each semiconductor pillar 110 has a channel region II and doped regions located on opposite sides of the channel region II. The semiconductor pillars 110 can be used to form the semiconductor channel of a transistor. The channel region II of the semiconductor pillar 110 is used to form the channel region II of the transistor, and the two doped regions of the semiconductor pillar 110 are used to form the source and drain of the transistor, respectively.

[0061] For details, please refer to Figures 4 to 5 In some embodiments, forming the semiconductor pillar 110 includes forming a plurality of semiconductor layers 101 spaced apart in the third direction Z and an epitaxial layer 102 between the semiconductor layers 101. The thickness of the epitaxial layer 102 in the third direction Z is used to define the spacing between adjacent semiconductor pillars 110 spaced apart in the third direction Z. Forming epitaxial layers 102 and semiconductor layers 101 of uniform thickness facilitates the formation of semiconductor pillars 110 with uniform morphology and uniform spacing.

[0062] In some embodiments, the semiconductor layer 101 is made of silicon. Various materials with different properties can be formed on the basis of silicon using epitaxial processes, which facilitates the simple fabrication of the epitaxial layer 102 based on silicon and reduces the manufacturing difficulty of the epitaxial layer 102. In other embodiments, the semiconductor layer 101 can also be other semiconductor channel materials, such as IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide), or ITO (Indium Tin Oxide). When the semiconductor channel is composed of the above materials, it is beneficial to improve the carrier mobility in the semiconductor channel, thereby facilitating the efficient transmission of electrical signals by the semiconductor channel.

[0063] In some embodiments, the epitaxial layer 102 is made of silicon germanide. Under the same etching conditions, silicon germanide and silicon have different etching selectivity ratios. Thus, if silicon is used as the material for the semiconductor pillar 110, selective removal of the epitaxial layer 102 can be achieved more easily when processing the semiconductor pillar 110, thereby exposing the surface of the semiconductor pillar 110. It is understood that in other embodiments, the epitaxial layer 102 may also be made of silicon carbide or other materials with different etching rates compared to silicon.

[0064] In some embodiments, selective epitaxy can be used to form the epitaxial layer 102 and the semiconductor layer 101. By selectively forming the epitaxial layer 102, the thermal expansion coefficients of the epitaxial layer 102, the semiconductor layer 101, and the substrate 100 can be made close and their lattice coefficients matched. This makes the thermal expansion coefficients of adjacent film layers close and their lattice coefficients matched, avoiding stress changes caused by temperature variations and stress mismatches caused by lattice mismatches. This helps to avoid interface misalignment or even film layer cracking caused by stress mismatches between different film layers, and improves the flatness of the semiconductor layer 101, the epitaxial layer 102, and the substrate 100.

[0065] refer to Figure 4 and Figure 5 After forming the semiconductor layer 101 and the epitaxial layer 102, the process includes: patterning the semiconductor layer 101 and the epitaxial layer 102 to form grooves extending along the first direction Y, with the remaining semiconductor layer 101 serving as semiconductor pillars 110. Specifically, a mask layer with an etching window is formed on the top surface of the semiconductor layer 101 away from the substrate 100, and the semiconductor layer 101 and the epitaxial layer 102 exposed by the etching window are removed to form a plurality of grooves extending along the first direction Y and a plurality of spaced semiconductor pillars 110.

[0066] In some embodiments, the process further includes performing a doping process on the semiconductor pillar 110 to form a channel region II, a first doped region I, and a second doped region III of the subsequent semiconductor pillar 110, wherein the first doped region I and the second doped region III are the doped regions on both sides of the channel region II. Specifically, in some embodiments, either ion implantation or thermal diffusion can be used to dope the semiconductor pillar 110. In other embodiments, the semiconductor layer 101 can be doped after the semiconductor layer 101 is formed to form the channel region II, the first doped region I, and the second doped region III of the subsequent semiconductor pillar 110.

[0067] refer to Figures 5 to 10 A first support layer 120 and a second support layer 130 are formed. The first support layer 120 is located on the sidewall of the channel region II of the semiconductor pillars 110 arranged along the second direction X, and the second support layer 130 is located between adjacent first support layers 120. The first support layer 120, which is in contact with the sidewall of the channel region II of the semiconductor pillars 110, provides support for the subsequent word line structure and provides isolation and protection for the channel region II of the semiconductor pillars 110. The second support layer 130 enhances the support force for the word line structure, which helps prevent the word line structure from detaching or even breaking between adjacent semiconductor pillars 110 channel regions II, thus ensuring better continuity of the word line structure.

[0068] refer to Figure 5 In some embodiments, forming the first support layer 120 and the second support layer 130 may include: forming a first support film 103 and a second support film 105 within a groove. The first support film 103 is in contact with the semiconductor pillar 110 and the epitaxial layer 102 on the sidewall of the groove. The second support film 105 is spaced apart from the first support film 103 along a second direction X and is located between the first support films 103. The first support film 103 in contact with the sidewall of the channel region II of the semiconductor pillar 110 is used to form the subsequent first support layer, and the second support film 105 between adjacent sidewalls of the channel regions II of different semiconductor pillars 110 is used to form the subsequent second support layer. Specifically, the first support film 103 and the second support film 105 may be formed using an atomic layer deposition process. In addition to forming the support film within the groove, the first support film 103 and the second support film 105 are also formed on the top surface of the semiconductor pillar 110 away from the substrate 100. Optionally, the second support membrane 105 is formed on the sidewall of the first support membrane 103, or the first support membrane 103 and the second support membrane 105 are arranged at intervals.

[0069] In some embodiments, the process of forming the first support film 103 and the second support film 105 further includes forming a reinforcing film 104. The reinforcing film 104 is located between the first support film 103 and the second support film 105. The reinforcing film 104 between adjacent sidewalls of the channel regions II of the different semiconductor pillars 110 can be used to form the reinforcing layer 140 between the subsequent first support layer 120 and the second support layer 130, or it can be used as a sacrificial film to form an air gap. Specifically, the reinforcing film 104 can be formed using atomic layer deposition after the first support film 103 is formed, and the second support film 105 can be formed after the reinforcing film 104 is formed. Thus, compared to the process of forming the first support film 103 and the second support film 105 and then forming the reinforcing film 104, this method not only avoids filling the gaps between the first support film 103 and the second support film 105 with the reinforcing film 104, thus reducing the difficulty of preparing the reinforcing film 104, but also provides support for the second support film 105. The second support film 105 can be formed directly by filling, which helps to reduce the difficulty of preparing the second support film 105.

[0070] refer to Figure 6 A sacrificial layer 106 is formed, located between the channel regions II of a portion of the semiconductor pillars 110 adjacent to the doped region, and extending along the first direction Y around the channel regions II of the semiconductor pillars 110. The sacrificial layer 106 is used to form subsequent etching windows that expose the epitaxial layer 102 between the channel regions II of the semiconductor pillars 110. Specifically, an etching process can be used to remove a portion of the first support film 103, the second support film 105, and the reinforcing film 104 within the trench to expose the sidewalls of the channel regions II adjacent to the doped region and the epitaxial layer 102 between the channel regions II. The epitaxial layer 102 between the semiconductor pillars 110 is then removed to form a filling hole, and the sacrificial layer 106 is formed in the filling hole. In some embodiments, the sacrificial layer 106 can be a mask layer formed by spin coating.

[0071] In some embodiments, reference Figure 6 The method also includes: forming a dielectric layer 107, which is located between the doped regions of a portion of the semiconductor pillars 110 adjacent to the sacrificial layer 106, and extends along the first direction Y around the doped region II of the portion of the semiconductor pillars 110. The dielectric layer 107 can be used to form a support structure between adjacent semiconductor pillars 110, which helps to ensure that the semiconductor pillars 110 still have relatively reliable structural stability after the epitaxial layer 102 is removed. Specifically, before forming the sacrificial layer 106, filling holes extending to the doped regions of the portion of the semiconductor pillars 110 can be formed. After filling the filling holes with sacrificial material, part of the sacrificial material is removed, and the dielectric layer 107 is formed between the sacrificial materials using a deposition process. The sacrificial material on one side of the dielectric layer 107 serves as the sacrificial layer 106.

[0072] refer to Figures 6 to 7 Remove the sacrificial layer 106 to expose the epitaxial layer 102 between the channel regions II of the semiconductor pillar 110, refer to Figure 8 The epitaxial layer 102 between the channel regions II of the semiconductor pillar 110 is removed to form an etching hole 108. The etching hole 108 is used not only to etch and remove a portion of the first support film 103 and a portion of the second support film 105, but also to expose the top and bottom surfaces of the channel regions II of the semiconductor pillar 110, facilitating the subsequent formation of word line structures on the top and bottom surfaces of the channel regions II of the semiconductor pillar 110. Specifically, refer to... Figure 6 An opening can be formed in a portion of the area between the semiconductor pillars 110 arranged along the second direction X to expose the sidewall of the sacrificial layer 106 in the second direction X, thereby removing the sacrificial layer 106.

[0073] refer to Figure 9 and Figure 10 The first support film 103 and the second support film 105 between the sidewalls of the etched hole 108 are removed, leaving the remaining first support film 103 as the first support layer 120 and the remaining second support film 105 as the second support layer 130. In some embodiments, while removing the first support film 103 and the second support film 105 between the sidewalls of the etched hole 108 in the second direction X, the reinforcing film 104 between the sidewalls of the etched hole 108 is also removed. Here, an etching solution with high selectivity for etching the first support film 103, the second support film 105, and the reinforcing film 104 can be allowed to flow into the etched hole 108 to remove a portion of the first support film 103, the second support film 105, and the reinforcing film 104. This allows only the exposed first support film 103, the second support film 105, and the reinforcing film 104 on the sidewalls of the etched hole 108 to be removed, which helps reduce the fabrication difficulty of the first support layer 120 and the second support layer 130.

[0074] refer to Figure 10 In some embodiments, the remaining reinforcing membrane 104 serves as a reinforcing layer 140 to improve the structural stability of the subsequent word line structure 160 located on the top and bottom surfaces of the first support layer 120 and the second support layer 130.

[0075] refer to Figure 11 The method for forming a semiconductor structure further includes forming a gate dielectric layer 150. Specifically, the gate dielectric layer 150 can be formed on the top and bottom surfaces of the channel region II of the semiconductor pillar 110 using an atomic layer deposition process or a thermal oxidation process. In some embodiments, the top and bottom surfaces of the first support layer 120, the second support layer 130, and the reinforcing layer 140 are also formed with the gate dielectric layer 150.

[0076] refer to Figure 11 and Figure 12Multiple word line structures 160 are formed, extending along the second direction X, and located at least on the top and bottom surfaces of the channel regions II of the multiple semiconductor pillars 110 arranged along the second direction X, and also on the top and bottom surfaces of the first support layer 120 and the second support layer 130. Specifically, conductive layers can be formed on the surface of the gate dielectric layer 150 away from the semiconductor pillars 110 and on the surface of the gate dielectric layer 150 away from the first support layer 120, the second support layer 130 and the reinforcing layer 140. The conductive layer located on the top surface of the channel region II of the semiconductor pillars 110, the top surface of the first support layer 120 and the top surface of the second support layer 130 is the first word line layer 161, and the conductive layer located on the bottom surface of the channel region II of the semiconductor pillars 110, the bottom surface of the first support layer 120 and the bottom surface of the second support layer 130 is the second word line layer 162. The first word line layer 161 and the second word line layer 162 together constitute the word line structure 160.

[0077] In some embodiments, the word line structure 160 may be formed using at least one of physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0078] In some embodiments, reference Figure 1 and Figure 2 After forming the word line structure 160, it also includes: forming an isolation layer 170 between the word line structures 160. The isolation layer 170 is located between adjacent word line structures 160, which not only helps to protect the word line structure 160, but also helps to improve the stability of the semiconductor structure.

[0079] In some embodiments, reference Figure 3 , Figures 13 to 15 This also includes: removing the reinforcing layer 140 to create an air gap 180. For details, please refer to... Figure 13 In some embodiments, an isolation layer 170 is also formed between the sidewalls of the channel region II of the semiconductor pillars 110 arranged along the second direction X in a portion adjacent to the doped region. (See reference...) Figure 14 Before removing the reinforcing layer 140, the process includes: removing the isolation layer 170 and the dielectric layer 107 that are in contact with the sidewalls of the first support layer 120, the second support layer 130 and the reinforcing layer 140 in the first direction Y, so as to expose the sidewalls of the reinforcing layer 140 in the first direction Y; and selectively removing the reinforcing layer 140 between the first support layer 120 and the second support layer 130 using an etching process with high etching selectivity for the reinforcing layer 140.

[0080] In some embodiments, reference Figure 6 Alternatively, before removing the sacrificial layer 106, the reinforcing membrane 104 between the first support membrane 103 and the second support membrane 105 can be removed by utilizing the opening formed by removing the sacrificial layer 106, thereby forming the air gap 180 between the subsequent first support layer 120 and the second support layer 130.

[0081] In some embodiments, after removing the reinforcing layer 140, a dielectric layer 107 is formed to provide support for the semiconductor pillar 110.

[0082] In some embodiments, removing the dielectric layer 107 includes removing only the first support layer 120, the second support layer 130, and the dielectric layer 107 of the reinforcing film 104 in the sidewall extension direction of the first direction Y, while retaining the dielectric layer 107 between the top and bottom surfaces of the semiconductor pillar 110.

[0083] In some embodiments, reference Figure 15 The method for forming the semiconductor structure further includes removing the dielectric layer 107 and other insulating materials between the doped regions of the semiconductor pillar 110 to form a capacitor structure. Therefore, after removing the dielectric layer 107 and other insulating materials between the doped regions of the semiconductor pillar 110, the sidewall of the reinforcing layer 140 on one side in the first direction Y can be exposed, and then the reinforcing layer 140 can be removed. In this way, no additional process steps are required to remove the reinforcing layer 140, which helps to reduce the difficulty of removing the reinforcing layer 140.

[0084] In the semiconductor structure formation method provided in the above embodiments, a first support layer 120 and a second support layer 130 are formed between the channel regions II of the semiconductor pillars 110 arranged in the second direction X. A word line structure 160 is formed at the top and bottom of the channel regions II of the semiconductor pillars 110, the top and bottom of the first support layer 120, and the top and bottom of the second support layer 130. The first support layer 120 and the second support layer 130 provide support for the word line structure 160, avoiding deformation and breakage of the word line structure 160, which is beneficial to forming a word line structure 160 with better continuity and higher structural stability.

[0085] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own variations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A plurality of semiconductor pillars are located above the substrate, the semiconductor pillars extending along a first direction, the plurality of semiconductor pillars being spaced apart along a second direction and a third direction, the semiconductor pillars having a channel region and doped regions located on opposite sides of the channel region; A first support layer is located on the sidewall of the channel region of the semiconductor pillars arranged along the second direction; A second support layer is located between adjacent first support layers; Multiple word line structures, the word line structures extending along the second direction, at least located on the two surfaces of the channel regions of the multiple semiconductor pillars arranged along the second direction on the third direction, and also located on the two surfaces of the first support layer and the second support layer on the third direction.

2. The semiconductor structure according to claim 1, characterized in that, The first direction and the second direction are both parallel to the substrate surface, and the third direction is perpendicular to the substrate surface. The top surface of the first support layer and the top surface of the second support layer are both flush with the top surface of the adjacent semiconductor pillar, and the bottom surface of the first support layer and the second support layer are both flush with the bottom surface of the adjacent semiconductor pillar.

3. The semiconductor structure according to claim 1, characterized in that, An air gap is included between the first support layer and the second support layer.

4. The semiconductor structure according to claim 3, characterized in that, In the second direction, at least two first support layers and at least two air gaps are included between adjacent semiconductor pillars, each of the first support layers having the same thickness and each of the air gaps having the same width.

5. The semiconductor structure according to claim 1, characterized in that, A reinforcing layer is provided between the first support layer and the second support layer.

6. The semiconductor structure according to claim 5, characterized in that, In the second direction, at least two first support layers and at least two reinforcing layers are included between adjacent semiconductor pillars, each of the first support layers having the same thickness and each of the reinforcing layers having the same thickness.

7. The semiconductor structure according to claim 5, characterized in that, The material of the reinforcing layer is different from the material of the first support and the material of the second support layer.

8. The semiconductor structure according to claim 1, characterized in that, The first support layer and the second support layer are made of the same material.

9. The semiconductor structure according to claim 2, characterized in that, The word line structure includes: The first word line layer is located on the top surface of the channel region of the semiconductor pillar, the top surface of the first support layer, and the top surface of the second support layer; The second word line layer is located on the bottom surface of the channel region of the semiconductor pillar, the bottom surface of the first support layer, and the bottom surface of the second support layer; In the third direction, the first word line layer and the second word line layer have the same thickness.

10. The semiconductor structure according to claim 1, characterized in that, Also includes: A gate dielectric layer is located on two surfaces of the channel region of the semiconductor pillar in the third direction and between the word line structure and the channel region of the semiconductor pillar.

11. The semiconductor structure according to claim 1, characterized in that, Also includes: An isolation layer is located between adjacent word line structures.

12. The semiconductor structure according to claim 1, characterized in that, Also includes: A dielectric layer is located between the doped regions of a portion of the semiconductor pillars adjacent to the channel region and extends along the first direction around the doped regions of the portion of the semiconductor pillars, the dielectric layer being in contact with both ends of the word line structure in the first direction.

13. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A plurality of semiconductor pillars are formed above the substrate, the semiconductor pillars extending along a first direction, the plurality of semiconductor pillars being spaced apart along a second direction and a third direction, the semiconductor pillars having a channel region and doped regions located on opposite sides of the channel region; A first support layer is formed, the first support layer being located on the sidewall of the channel region of the semiconductor pillars arranged along the second direction; A second support layer is formed, which is located between adjacent first support layers; Multiple word line structures are formed, the word line structures extending along the second direction and located at least on the two surfaces of the channel regions of the multiple semiconductor pillars arranged along the second direction in the third direction, and also on the two surfaces of the first support layer and the second support layer in the third direction.

14. The method for forming a semiconductor structure according to claim 13, characterized in that, Forming the semiconductor pillar includes: forming a plurality of semiconductor layers spaced apart on the third side and an epitaxial layer between the semiconductor layers; The semiconductor layer and the epitaxial layer are patterned to form a groove extending along the first direction, and the remaining semiconductor layer serves as the semiconductor pillar.

15. The method for forming a semiconductor structure according to claim 14, characterized in that, The formation of the first support layer and the second support layer includes: A first support film and a second support film are formed in the groove. The first support film is in contact with the semiconductor pillar and the epitaxial layer on the sidewall of the groove. The second support film is arranged at intervals with the first support film along the second direction and is located between the first support films. A sacrificial layer is formed between the channel regions of a portion of the semiconductor pillar adjacent to the doped region, and on a surface surrounding the channel regions of a portion of the semiconductor pillar extending in the first direction; Remove the sacrificial layer to expose the epitaxial layer between the channel regions of the semiconductor pillars; Remove the epitaxial layer between the channel regions of the semiconductor pillars to form etched holes; Remove the first support film and the second support film between the sidewalls of the etched hole, leaving the first support film as the first support layer and the second support film as the second support layer.

16. The method for forming a semiconductor structure according to claim 15, characterized in that, Before forming the sacrificial layer, the process further includes: forming a reinforcing film; While removing the first support film and the second support film between the sidewalls of the etched hole, the reinforcing film between the sidewalls of the etched hole is also removed.

17. The method for forming a semiconductor structure according to claim 16, characterized in that, Also includes: Remove the reinforcing membrane to form an air gap.

18. The method for forming a semiconductor structure according to claim 15, characterized in that, The process includes, prior to removing the sacrificial layer: A dielectric layer is formed between the doped regions of a portion of the semiconductor pillar adjacent to the sacrificial layer, and surrounds the surface of the doped regions of the portion of the semiconductor pillar extending in the first direction.

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