Semiconductor structure and method of fabricating the same

Abstract

This disclosure provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate and multiple word lines and multiple sets of word line lead groups disposed on the substrate. The substrate includes a substrate and a dielectric structure located on the substrate. The multiple word lines are located in the dielectric structure and parallel to the substrate. The word lines extend along a first direction and are arranged along a second direction. The multiple sets of word line lead groups are correspondingly disposed with the multiple word lines. Each set of word line lead groups is connected to a preset end of its corresponding word line. Each set of word line lead groups includes multiple word line leads, including a preset lead located above the dielectric structure. The extension direction of the preset lead is parallel to the top surface of the substrate and has a first preset angle with the first direction. In this disclosure, by repeatedly bending the word line leads, the preset lead of the word line leads is located above the dielectric structure, thereby effectively utilizing the space above the capacitor, improving space utilization, and facilitating the realization of a memory with higher storage density.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] With the development of technology, there are more and more capacitor structures used to store data in DRAM (Dynamic Random Access Memory). Correspondingly, there are also more and more leads used to connect the peripheral circuits to the capacitor structures (word lines and bit lines). The leads occupy the space of the capacitor structures, which affects the area where capacitor structures can be formed and is not conducive to improving the storage density of DRAM. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a semiconductor structure and a method for fabricating the same.

[0005] According to a first aspect of this disclosure, a semiconductor structure is provided, comprising:

[0006] A substrate, the substrate comprising a substrate and a dielectric structure located on the substrate;

[0007] Multiple word lines are located in the dielectric structure and parallel to the substrate. The word lines extend along a first direction and are arranged along a second direction. The preset ends of the multiple word lines are stepped in the second direction. The second direction is the thickness direction of the substrate and is perpendicular to the first direction.

[0008] Multiple sets of character line lead groups, the number of character line lead groups being equal to the number of character lines, multiple sets of character line lead groups being configured corresponding to multiple character lines, and each set of character line lead groups being connected to a preset end of the corresponding character line;

[0009] Each word line lead group includes multiple word lines, and the multiple word lines include a preset lead. The preset lead is located above the dielectric structure, and the extension direction of the preset lead is parallel to the top surface of the substrate and has a first preset angle with the first direction.

[0010] In one embodiment, the plurality of word line leads include a first word line lead, a second word line lead, and a third word line lead, wherein the third word line lead is the preset lead;

[0011] Wherein, the first character line lead is connected to the preset end of the character line, and the first character line lead extends along the second direction;

[0012] The first end of the second character line is connected to the first character line, and the second character line extends along a third direction. The third direction has a second preset angle with the first direction, and the third direction is perpendicular to the second direction.

[0013] The third character line lead is connected to the second character line lead, and the extension direction of the third character line lead has the first preset angle with the first direction.

[0014] In one embodiment, in the second direction, the top surfaces of the plurality of first letter leads are flush.

[0015] In one embodiment, the plurality of word line leads further includes a fourth word line lead;

[0016] The fourth lead wire connects the second lead wire and the third lead wire, and the fourth lead wire extends along the second direction.

[0017] In one embodiment, in the third direction, the distances from the connection points of the plurality of fourth word line leads and the plurality of second word line leads to the first end of the second word line lead are not equal.

[0018] In one embodiment, the top surface height of the plurality of second letter leads arranged along the first direction gradually decreases; and / or,

[0019] The lengths of the multiple second-character lines arranged along the first direction gradually decrease in the third direction.

[0020] In one embodiment, the plurality of word line leads include a fifth word line lead, a sixth word line lead, and a seventh word line lead, wherein the seventh word line lead is the preset lead;

[0021] Wherein, the first end of the fifth character line lead is connected to the preset end of the character line, the fifth character line lead extends along a third direction, the third direction is perpendicular to the second direction, and there is a second preset angle between the third direction and the first direction;

[0022] The sixth character line lead is connected to the second end of the fifth character line lead, and the sixth character line lead extends along the second direction;

[0023] The seventh lead wire is connected to the sixth lead wire, and the extension direction of the seventh lead wire has the first preset angle with the first direction.

[0024] In one embodiment, in the third direction, the distance between the second end of the fifth word line lead and the word line is not equal.

[0025] In one embodiment, in the second direction, the top surfaces of the plurality of sixth-line leads are flush.

[0026] In one embodiment, the semiconductor structure further includes:

[0027] Multiple bit lines are located in the dielectric structure and perpendicular to the substrate, and the multiple bit lines are arranged along the first direction;

[0028] Multiple bit line leads are parallel to the substrate, the number of bit line leads is equal to the number of bit lines, and the multiple bit line leads are arranged corresponding to the multiple bit lines;

[0029] In the thickness direction of the substrate, the bit line lead is located between the dielectric structure and the word line lead.

[0030] In one embodiment, the semiconductor structure further includes:

[0031] A transistor is located in the dielectric structure and parallel to the substrate. A first end of the transistor is connected to the bit line. The transistor extends along a third direction, which is perpendicular to the second direction. The third direction has a second preset angle with the first direction.

[0032] A capacitor is located in the dielectric structure and parallel to the substrate, and the capacitor is connected to the second terminal of the transistor.

[0033] According to a second aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0034] A substrate is provided, the substrate comprising a substrate and a dielectric structure disposed on the substrate;

[0035] Multiple word lines are formed, which are located in the dielectric structure and parallel to the substrate. The word lines extend along a first direction and are arranged along a second direction. The preset ends of the multiple word lines are stepped in the second direction, which is the thickness direction of the substrate and is perpendicular to the first direction.

[0036] Multiple sets of word line lead groups are formed, the number of word line lead groups being equal to the number of word lines. The multiple sets of word line lead groups are correspondingly arranged with multiple word lines. Each set of word line lead groups is connected to a preset end of the corresponding word line. Each set of word line lead groups includes multiple word line leads, and the multiple word line leads include a preset lead. The preset lead is located above the dielectric structure, and the extension direction of the preset lead is parallel to the top surface of the substrate and has a first preset angle with the first direction.

[0037] In one embodiment, multiple sets of word line lead groups are formed, including:

[0038] A first character line leader is formed, the first character line leader is connected to the stepped surface of the character line, the first character line leader extends along the second direction, and the top surfaces of multiple first character line leaders are flush.

[0039] A second character line is formed, the first end of the second character line is connected to the top surface of the first character line, the second character line extends along a third direction, the third direction has a second preset angle with the first direction, and the third direction is perpendicular to the second direction;

[0040] A fourth character line is formed, which is connected to the second character line and extends along the second direction;

[0041] A third character line is formed, which serves as the preset lead. The third character line is connected to the fourth character line, and the extension direction of the third character line has the first preset angle with the first direction.

[0042] In one embodiment, multiple sets of word line lead groups are formed, including:

[0043] A fifth character line is formed, the first end of the fifth character line is connected to the stepped surface of the character line, the fifth character line extends along a third direction, the third direction has a second preset angle with the first direction, and the third direction is perpendicular to the second direction;

[0044] A sixth lead wire is formed, which is connected to the second end of the fifth lead wire. The sixth lead wire extends along the second direction, and the top surface of the sixth lead wire is flush with the second direction.

[0045] A seventh-character lead is formed, which is the preset lead. The top surface of the seventh-character lead is connected to the top surface of the sixth-character lead, and the extension direction of the seventh-character lead has the first preset angle with the first direction.

[0046] In one embodiment, forming the fifth letter lead includes:

[0047] A fifth word line lead sacrificial layer is formed, covering the surface of the plurality of word lines, wherein the top surface of the fifth word line lead sacrificial layer is parallel to the top surface of the substrate;

[0048] Remove part of the structure of the fifth word line lead sacrificial layer, and retain the fifth word line lead sacrificial layer in a stepped shape in the second direction, with the stepped surface of the fifth word line lead sacrificial layer exposing part of the top surface of the stepped surface of the word line;

[0049] The fifth word line lead is formed, covering the stepped surface exposed by the word line.

[0050] In one embodiment, a substrate is provided, comprising:

[0051] Provide substrate;

[0052] A stacked structure is formed on the substrate, the stacked structure comprising alternating stacked dielectric layers and sacrificial layers;

[0053] In the stacked structure, a plurality of isolation layers are formed that extend along the second direction and are arranged along the first direction;

[0054] Bit lines are formed between adjacent isolation layers, and the sacrificial layer is removed, leaving the dielectric layer and the isolation layer to form the dielectric structure;

[0055] On the vacancy formed after removing the sacrificial layer, a capacitor via is formed along a third direction, the third direction being perpendicular to the second direction, and the third direction having a second preset angle with the first direction;

[0056] Based on the bit line, a transistor and a capacitor are sequentially formed in the capacitor via, the transistor connecting the bit line and the capacitor, and the capacitor being parallel to the substrate.

[0057] In the semiconductor structure and manufacturing method disclosed herein, by repeatedly bending the word line leads, the preset leads of the word line leads are located above the dielectric structure, thereby effectively utilizing the space above the capacitor, improving space utilization, and facilitating the realization of a memory with higher storage density.

[0058] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0059] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0060] Figure 1 This is a schematic diagram illustrating a semiconductor structure after forming a multilayer structure, according to an exemplary embodiment.

[0061] Figure 2 This is a schematic diagram illustrating a semiconductor structure after the formation of an isolation layer, according to an exemplary embodiment.

[0062] Figure 3 This is a schematic diagram illustrating a semiconductor structure after bit line formation, according to an exemplary embodiment.

[0063] Figure 4 This is a schematic diagram of a semiconductor structure after the sacrificial layer has been removed, according to an exemplary embodiment.

[0064] Figure 5 This is a schematic diagram illustrating a semiconductor structure after the formation of bit line leads, transistors, and capacitors, according to an exemplary embodiment.

[0065] Figure 6 This is a schematic diagram illustrating a semiconductor structure after forming a word line via, according to an exemplary embodiment.

[0066] Figure 7 This is a schematic diagram illustrating the semiconductor structure after the initial word line is formed, according to an exemplary embodiment.

[0067] Figure 8 This is a schematic diagram illustrating the semiconductor structure after word line formation according to an exemplary embodiment.

[0068] Figure 9 This is a schematic diagram illustrating a semiconductor structure after forming a word line lead group, according to an exemplary embodiment.

[0069] Figures 10 to 12 yes Figure 9 The diagram shows a semiconductor structure forming a word line lead group.

[0070] Figure 13 This is a schematic diagram illustrating a semiconductor structure after forming a word line lead group, according to an exemplary embodiment.

[0071] Figures 14 to 19 yes Figure 13 The diagram shows a semiconductor structure forming a word line lead group.

[0072] Figure 20 This is a schematic diagram illustrating a semiconductor structure after forming a word line lead group, according to an exemplary embodiment.

[0073] Figure 21 This is a schematic diagram illustrating a semiconductor structure after forming a word line lead group, according to an exemplary embodiment.

[0074] Figure 22 yes Figure 21 A partial schematic diagram of the semiconductor structure.

[0075] Figure 23 This is a schematic diagram illustrating a semiconductor structure after forming a word line lead group, according to an exemplary embodiment.

[0076] Figure 24 This is a schematic diagram illustrating a semiconductor structure after forming a word line lead group, according to an exemplary embodiment.

[0077] Figure 25 This is a schematic diagram illustrating a semiconductor structure after forming a word line lead group, according to an exemplary embodiment.

[0078] Figure 26 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0079] Figure label:

[0080] 100, Substrate; 110, Base; 120, Dielectric layer; 130, Sacrificial layer; 140, Isolating layer; 150, Capacitor via; 160, Word line via;

[0081] 200, character line;

[0082] 300. Character line leader group; 310. First character line leader; 311. First character line leader sacrificial layer; 320. Second character line leader; 321. Second character line leader sacrificial layer; 330. Fourth character line leader; 331. Fourth character line leader sacrificial layer; 340. Third character line leader; 341. Third character line leader sacrificial layer; 350. Fifth character line leader; 351. Fifth character line leader sacrificial layer; 360. Sixth character line leader; 361. Sixth character line leader sacrificial layer; 370. Seventh character line leader; 371. Seventh character line leader sacrificial layer;

[0083] 400, bit line;

[0084] 500, bit line lead;

[0085] 600, transistor;

[0086] 700. Capacitor. Detailed Implementation

[0087] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0088] With the development of technology, there are more and more capacitor structures used to store data in DRAM (Dynamic Random Access Memory). Correspondingly, there are also more and more leads used to connect the peripheral circuits to the capacitor structures (word lines and bit lines). The leads occupy the space of the capacitor structures, which affects the area where capacitor structures can be formed and is not conducive to improving the storage density of DRAM.

[0089] To address the problems existing in related technologies, this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and multiple word lines and multiple sets of word line lead groups disposed on the substrate. The substrate includes a substrate and a dielectric structure located on the substrate. The multiple word lines are located in the dielectric structure and are parallel to the substrate. The word lines extend along a first direction and are arranged along a second direction. The preset ends of the multiple word lines are stepped in the second direction, which is the thickness direction of the substrate and is perpendicular to the first direction. The number of sets of multiple word line lead groups corresponds to the number of word lines. Each set of word line lead groups includes multiple word line leads, which are correspondingly disposed with the multiple word lines. Each word line lead is connected to the preset end of its corresponding word line. The preset lead in each set of word line lead groups is located above the dielectric structure. The extension direction of the preset lead is parallel to the top surface of the substrate and has a first preset angle with the first direction.

[0090] According to an exemplary embodiment of this disclosure, such as Figure 9 and Figure 13 As shown, and refer to Figure 8 This disclosure provides a semiconductor structure, which includes a substrate 100 and multiple word lines 200 located on the substrate 100, as well as multiple sets of word line lead groups 300 connected to the multiple word lines 200.

[0091] In this embodiment, as Figures 1 to 8 As shown, the substrate 100 includes a substrate 110 and a dielectric structure located on the substrate 110.

[0092] Reference Figures 1 to 8The substrate 110 is used to support the components disposed thereon. The material of the substrate 110 can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide and other III-V compounds.

[0093] Reference Figures 1 to 8 A dielectric structure is disposed on a substrate 110. The dielectric structure may include a plurality of dielectric layers 120 parallel to the substrate 110 and a plurality of isolation layers 140 perpendicular to the substrate 110. The dielectric structure is disposed in a third direction ( Figure 9 The projection of the dielectric layer 120 (in the y-direction shown) is grid-like. The dielectric layer 120 is made of nitrides such as silicon nitride, silicon carbide nitride, or silicon boronitride nitride, and the insulating layer 140 is made of oxides such as silicon oxide.

[0094] Reference Figure 6 The dielectric structure can include bit lines 400, transistors 600, and capacitors 700. Each bit line 400 can be perpendicular to the substrate 110, allowing multiple capacitors 700 to be arranged in a direction perpendicular to the substrate. This enables a single bit line 400 to control multiple capacitors 700. In other words, the capacitors 700 in this embodiment can be parallel to the substrate 110.

[0095] In this embodiment, as Figure 8 As shown, multiple word lines 200 are located in the word line vias 160 of the dielectric structure, and the multiple word lines 200 are parallel to the top surface of the substrate 110. The extension direction of the word lines 200 is defined as a first direction ( Figure 9 The x-direction shown in the figure), the arrangement direction of the multiple character lines 200 is defined as the second direction ( Figure 9 (As shown in the z-direction), the first direction is perpendicular to the second direction. It should be noted that the first direction and the second direction can be approximately perpendicular, for example, an angle of 85° to 95°. The material of the character line 200 includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or combinations of the foregoing materials.

[0096] Reference Figure 8 , Figure 9 and Figure 13 The preset ends of multiple character lines 200 are in the second direction ( Figure 9 As shown in the z-direction, the word lines 200 are arranged in a stepped shape. For example, the length of the multiple word lines 200 arranged along the second direction gradually decreases, so that the top surface of the lower word lines 200 can be exposed. The exposed top surface of each word line 200 can be used to set word line leads, which are used to electrically connect the word lines 200 to the peripheral circuit (not shown).

[0097] It should be noted that multiple character lines can have a stepped shape at the same end, or multiple character lines can have a stepped shape at both ends.

[0098] In this embodiment, as Figure 9 and Figure 13 As shown, one end of the word line lead group 300 is connected to the stepped end of the word line 200, and the other end of the word line lead group 300 is connected to the peripheral circuit (not shown). Multiple word line lead groups 300 are provided, and the number of word line lead groups 300 corresponds to the number of word lines 200, so that the peripheral circuit can independently control each word line 200 through multiple word line lead groups 300.

[0099] Among them, reference Figure 9 and Figure 13 Each word line lead group 300 includes multiple word lines, one of which is a preset lead. These preset leads (the third word line lead 340 and the seventh word line lead 370) are located above the dielectric structure. The extension direction of the preset lead is parallel to the top surface of the substrate 110, and there is a first preset angle between the extension direction of the preset lead and the first direction. This first preset angle can be, for example, 0° to 45°. Typically, the first preset angle is 0° (i.e., the preset lead is parallel to the word line) to facilitate the manufacturing process. By adjusting the orientation of the word line leads, the preset leads in the word line lead group 300 can be located above the dielectric structure, fully utilizing the space above the dielectric structure, improving space utilization, and facilitating higher storage density. It is understood that the preset lead can be the last of the multiple word line leads, allowing it to extend along the first direction and directly connect to the peripheral circuitry.

[0100] It should be noted that the pre-set lead is located above the dielectric structure, meaning that... Figure 9 In the z-direction shown, the height of the preset lead exceeds the top surface of the dielectric structure. Specifically, if the bit lead 500 (refer to...) is formed before the word lead is formed... Figure 7 If the bit line lead 500 is formed after the word line lead is formed, the preset lead can be located above the bit line lead 500 and the dielectric structure.

[0101] In this embodiment of the disclosure, by bending the word line leads multiple times, the preset leads of the word line leads are located above the dielectric structure, thereby effectively utilizing the space above the capacitor, improving space utilization, and facilitating the realization of a memory with higher storage density.

[0102] In one exemplary embodiment, such as Figure 9 and Figure 13 As shown, and refer to Figure 8This disclosure provides a semiconductor structure including a substrate 100, multiple word lines 200, and multiple sets of word line lead groups 300. The substrate 100 includes a base 110 and a dielectric structure located on the substrate 110. The multiple word lines 200 are located in the dielectric structure and parallel to the substrate 110. The word lines 200 extend along a first direction and are arranged along a second direction. The preset ends of the multiple word lines 200 are stepped in the second direction, which is the thickness direction of the substrate 110 and perpendicular to the first direction. The number of word line lead groups 300 corresponds to the number of word lines 200. Each set of word line lead groups 300 includes multiple word line leads, which are correspondingly arranged with the multiple word lines 200. Each word line lead is connected to a preset end of its corresponding word line 200. The preset leads in each group of word line leads 300 are located above the dielectric structure. The extension direction of the preset leads is parallel to the top surface of the substrate 110 and has a first preset angle with the first direction.

[0103] It should be noted that the number of word lines in each group of 300 word lines can be 3, 4, 5, or more, as long as the preset leads among the multiple word lines are formed above the dielectric structure. In practical applications, the number and direction of word lines can be adaptively adjusted according to the specific structure of the semiconductor. For example, more word lines can be added to avoid short circuits in certain structural areas.

[0104] In this embodiment, as Figure 9 As shown, each group of character line leads 300 may include four character line leads (first character line lead 310, second character line lead 320, fourth character line lead 330, and third character line lead 340) as an example. The first character line lead 310 connects to the character line 200 and the second character line lead 320, the second character line lead 320 connects to the first character line lead 310 and the fourth character line lead 330, the fourth character line lead 330 connects to the second character line lead 320 and the third character line lead 340, and the third character line lead 340 serves as a preset lead in this group of character line leads 300.

[0105] Reference Figure 8 and Figure 9 In the second direction ( Figure 9 In the z-direction shown, the lengths of multiple character lines gradually decrease, so that the lower character line 200 can expose part of its top surface, allowing the first character line lead 310 to connect with the exposed top surface of each character line, and the first character line lead 310 along the second direction (as shown in the z-direction). Figure 9 (as shown in the z-direction) extends. In one example, refer to... Figure 9 The top surfaces of multiple first word line leads 310 are flush, and the first word line leads 310 can change the horizontal lead circuit of the horizontal word line 200 from horizontal to vertical.

[0106] Reference Figure 8 and Figure 9 The first end of the second character line lead 320 is connected to the top surface of the first character line lead 310, and the second character line lead 320 is along a third direction ( Figure 9 Extending in the y-direction shown, the third direction and the second direction ( Figure 9 The z-direction shown is perpendicular to the first direction, and the third direction is perpendicular to the first direction. Figure 9 There is a second preset angle between the x-direction shown. This second preset angle can be, for example, 45° to 135°, but is typically 90°. For example, Figure 9 The second preset included angle is shown to be 90°. Figure 20 The second preset included angle is shown to be 45°.

[0107] Reference Figure 9 The fourth character line lead 330 is connected to the second character line lead 320, and the fourth character line lead 330 extends in the second direction. In the third direction, the distance from the connection points of the multiple fourth character line leads and the multiple second character line leads to the first end of the second character line lead is not equal, so that the multiple third character line leads 340 formed based on each fourth character line lead 330 can be arranged along the third direction. By setting the fourth character line lead 330, a height difference exists between the third character line lead 340 and the second character line lead 320 to avoid short circuits caused by contact between the third character line lead 340 and the multiple second character line leads 320.

[0108] Reference Figure 9 The third character line lead 340 (i.e., the preset lead) is connected to the fourth character line lead 330. The extension direction of the third character line lead 340 has a first preset angle with the first direction. The first preset angle has been explained in the previous embodiments and will not be repeated here. The third character line lead 340 is located above the dielectric structure and can be used to directly connect to the peripheral circuit. As can be seen from the above, by setting the first character line lead 310, the second character line lead 320, and the fourth character line lead 330 with different directions, the character line lead undergoes multiple bends, so that the third character line lead 340 can be located above the dielectric structure, making full use of the space above the dielectric structure and improving space utilization.

[0109] In some alternative implementations, the fourth lead wire may not be provided.

[0110] For example, refer to Figure 21 and Figure 22The thickness of the multiple second-character leads is different. In the second direction, the multiple second-character leads are stepped. When the third-character leads 340 are formed on the second-character leads, the height of the multiple third-character leads 340 is also different. Therefore, the multiple third-character leads 340 will not be connected to the multiple second-character leads 320 and short circuit will occur.

[0111] For example, refer to Figures 23 to 25 Multiple second-line leads 320 in third-party direction ( Figure 9 The extension lengths in the y-direction shown are not equal. When the third word line lead 340 is configured to connect to the end of the second word line lead 320, multiple third word line leads 340 can be arranged along a third direction, avoiding short circuits. In one example, refer to... Figure 24 The third letter leader 340 can be on a different plane from the second letter leader 320. See another example. Figure 25 The third character line leader 340 can be on the same plane as the second character line leader 320.

[0112] In this embodiment, a first word line lead extending along a second direction, a second word line lead extending along a third direction, a fourth word line lead extending along the second direction, and a third word line lead forming a first preset angle with the first direction are formed in sequence, thereby placing some word line leads above the dielectric structure, improving the space utilization of the semiconductor structure and facilitating the achievement of higher storage density.

[0113] In one exemplary embodiment, such as Figure 8 , Figure 9 and Figure 13 As shown, this embodiment of the present disclosure provides a semiconductor structure, which includes a substrate 100, multiple word lines 200, and multiple sets of word line lead groups 300. The substrate 100 includes a substrate 110 and a dielectric structure located on the substrate 110. The multiple word lines 200 are located in the dielectric structure and parallel to the substrate 110. The word lines 200 extend along a first direction and are arranged along a second direction. The preset ends of the multiple word lines 200 are stepped in the second direction, which is the thickness direction of the substrate 110 and is perpendicular to the first direction. The number of word line lead groups 300 corresponds to the number of word lines 200. Each set of word line lead groups 300 includes multiple word line leads, which are correspondingly arranged with the multiple word lines 200. Each word line lead is connected to the preset end of its corresponding word line 200. The preset leads in each group of word line leads 300 are located above the dielectric structure. The extension direction of the preset leads is parallel to the top surface of the substrate 110 and has a first preset angle with the first direction.

[0114] In this embodiment, as Figure 13As shown, each group of character line leaders 300 includes three character line leaders (fifth character line leader 350, sixth character line leader 360, and seventh character line leader 370) as an example. The fifth character line leader 350 is connected to the character line 200, and the sixth character line leader 360 connects the fifth character line leader 350 and the seventh character line leader 370.

[0115] Reference Figure 13 The first end of the fifth character line lead 350 is connected to the preset end of the character line 200. The fifth character line lead 350 extends along a third direction, which is perpendicular to the second direction. There is a second preset angle between the third direction and the first direction. The second preset angle can be, for example, 45° to 135°, but is usually 90° to facilitate the manufacturing of the fifth character line lead 350.

[0116] Reference Figure 13 The sixth character line lead 360 is connected to the second end of the fifth character line lead 350, and the sixth character line lead 360 extends along the second direction. It is understood that the function of the sixth character line lead 360 is the same as that of the first character line lead 310, and will not be elaborated further here.

[0117] Reference Figure 13 The seventh character line lead 370 is connected to the sixth character line lead 360. The extension direction of the seventh character line lead 370 has a first preset angle with the first direction. The first preset angle has been explained in the above embodiments and will not be repeated here. The seventh character line lead has the same function as the third character line lead and will not be repeated here.

[0118] In one exemplary embodiment, such as Figure 8 , Figure 9 and Figure 13 As shown, this embodiment of the present disclosure provides a semiconductor structure, which includes a substrate 100, multiple word lines 200, and multiple sets of word line lead groups 300. The substrate 100 includes a substrate 110 and a dielectric structure located on the substrate 110. The multiple word lines 200 are located in the dielectric structure and parallel to the substrate 110. The word lines 200 extend along a first direction and are arranged along a second direction. The preset ends of the multiple word lines 200 are stepped in the second direction, which is the thickness direction of the substrate 110 and is perpendicular to the first direction. The number of word line lead groups 300 corresponds to the number of word lines. Each set of word line lead groups 300 includes multiple word line leads, which are correspondingly arranged with the multiple word lines 200. Each word line lead is connected to a preset end of its corresponding word line 200. The preset leads in each group of word line leads 300 are located above the dielectric structure. The extension direction of the preset leads is parallel to the top surface of the substrate 110 and has a first preset angle with the first direction.

[0119] In this embodiment, as Figures 5 to 8As shown, the semiconductor structure also includes multiple bit lines 400 and multiple bit line leads 500.

[0120] Reference Figures 5 to 8 Multiple bit lines 400 are located in the dielectric structure and perpendicular to the substrate 110, so that each bit line 400 can be in the second direction ( Figure 9 Multiple capacitors 700 are controlled in the z-direction shown in the figure. It should be noted that in this embodiment, the capacitors 700 are horizontal capacitors 700.

[0121] Reference Figures 5 to 8 Bit line lead 500 is connected to bit line 400. Bit line lead 500 is used to connect bit line 400 and peripheral circuits, so that the peripheral circuits can control bit line 400. In turn, by controlling bit line 400 and word line 200, any capacitor 700 can be selected to write data into capacitor 700 or read data from capacitor 700, thereby realizing data reading and writing.

[0122] In one example, refer to Figure 8 , Figure 9 and Figure 13 In the thickness direction of substrate 110 ( Figure 9 (as shown in the z-direction), the bit line lead 500 is located between the dielectric structure and the preset lead of the word line lead.

[0123] In this embodiment, as Figure 5 As shown, the semiconductor structure also includes a transistor 600 and a capacitor 700.

[0124] Reference Figure 5 Transistor 600 is located in a dielectric structure and parallel to substrate 110. Transistor 600 includes a source, a gate, and a drain. A first end of transistor 600 (e.g., the drain of transistor 600) is connected to a bit line. Transistor 600 is located along a third direction ( Figure 9 As shown in the y-direction, the drain, gate, and source of transistor 600 are arranged sequentially along the third direction. Transistor 600 can be, for example, a planar transistor, a fin field-effect transistor, etc.

[0125] Reference Figure 8 The capacitor 700 is located in the dielectric structure and parallel to the substrate 110. The capacitor 700 includes a first electrode layer (not shown) and a second electrode layer (not shown), and a dielectric layer located between the first electrode layer and the second electrode layer. The first electrode layer and the second electrode layer form the two electrode plates of the capacitor. The capacitor 700 is connected to the second end of the transistor 600 (e.g., the source of the transistor 600). For example, the first electrode layer of the capacitor 700 can be connected to the transistor 600, and the second electrode layer of the capacitor 700 can be connected to a capacitor driving circuit (not shown).

[0126] According to exemplary embodiments of this disclosure, such as Figure 26 As shown, this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0127] S100, providing a substrate, the substrate including a substrate and a dielectric structure located on the substrate.

[0128] In this step, refer to Figure 1 The substrate 100 includes a substrate 110 and a dielectric structure located on the substrate 110.

[0129] The material of the substrate 110 has been described in the above embodiments and will not be repeated here.

[0130] The dielectric structure is formed on the substrate 110 and includes a plurality of dielectric layers 120 parallel to the substrate 110 and a plurality of isolation layers 140 perpendicular to the substrate 100. The materials of the dielectric layers 120 and the isolation layers 140 will not be described in detail here.

[0131] Step S100 may specifically include the following steps:

[0132] S110 provides a substrate.

[0133] S120. Forming a stacked structure: A stacked structure is formed on a substrate, the stacked structure comprising alternating stacked dielectric layers and sacrificial layers.

[0134] In this step, refer to Figure 1 A dielectric layer 120 and a sacrificial layer 130 can be alternately formed on a substrate 110 using a deposition process. The alternately stacked dielectric layer 120 and sacrificial layer 130 form a stacked structure. The material of the dielectric layer 120 can be a nitride such as silicon nitride, silicon carbide nitride, or silicon boronitride nitride, and the material of the sacrificial layer 130 can be an oxide such as silicon oxide.

[0135] S130. An isolation layer is formed in the stacked structure, extending in the second direction and arranged in the first direction.

[0136] In this step, refer to Figure 2 Photolithography and etching processes can be used to remove part of the stacked structure to form multiple trenches arranged along the first direction in the stacked structure. Then, deposition or other processes can be used to fill the trenches with an isolation material to form multiple isolation layers 140. The material of the isolation layer 140 can be, for example, an oxide or a nitride.

[0137] S140. Bit lines are formed between adjacent isolation layers, and the sacrificial layer is removed, leaving the dielectric layer and isolation layer to form a dielectric structure.

[0138] In this step, refer to Figure 3The process for forming bit lines can be as follows: First, an etching process can be used to remove part of the stacked structure, forming bit line vias (not shown) between adjacent isolation layers 140. Then, deposition, epitaxial growth, or other processes can be used to form bit lines 400 in the vias. After forming bit lines 400, chemical mechanical polishing can be used to smooth the top surface of bit lines 400, making the top surface of the bit lines flush with the top surface of the dielectric layer 120, which facilitates the formation of bit line leads 500 on the top surface of bit lines 400 in subsequent processes (see reference). Figure 5 ).

[0139] Reference Figure 4 After the bit line 400 is formed, an etching material with a high selectivity to the material of the sacrificial layer 130 can be used to remove the sacrificial layer 130. The etching material has no selectivity or a very low selectivity to the dielectric layer 120 and the isolation layer 140, so that the dielectric layer 120 and the isolation layer 140 can be retained, and the retained dielectric layer 120 and the isolation layer 140 form a dielectric structure.

[0140] Understandably, after the sacrificial layer 130 is removed, multiple vacancies are formed in the dielectric structure, which serve as growth regions for transistor 600 and capacitor 700 in subsequent processes.

[0141] S150. On the vacancy formed after removing the sacrificial layer, a capacitor via is formed along a third direction, the third direction being perpendicular to the second direction, and the third direction having a second preset angle with the first direction.

[0142] In this step, refer to Figure 4 A deposition process can be used to form capacitor 700 and capacitor via 150 in a third direction based on the vacancies of the conductive structure. The sidewalls of capacitor 700 and via 150 are composed of dielectric layer 120 and isolation layer 140.

[0143] S160. Based on the bit line, a transistor and a capacitor are sequentially formed in the capacitor via. The transistor connects the bit line and the capacitor, and the capacitor is parallel to the substrate.

[0144] In this step, refer to Figure 5 An epitaxial growth process can be used to form a transistor 600 connected to a bit line in the capacitor via 150, with the source of transistor 600 connected to the bit line. Next, an epitaxial growth process can be used to form a capacitor 700 connected to the drain of transistor 600 in the capacitor via 150.

[0145] The gate of transistor 600 is used to connect to word lines formed in subsequent processes. Transistor 600 can be turned on or off under the control of word lines.

[0146] S200: Multiple word lines are formed. The multiple word lines are located in the dielectric structure and are parallel to the substrate. The word lines extend along a first direction and are arranged along a second direction. The preset ends of the multiple word lines are stepped in the second direction. The second direction is the thickness direction of the substrate and is perpendicular to the first direction.

[0147] Step S210 may specifically include the following steps:

[0148] S210. Multiple initial word lines are formed in the dielectric structure. The multiple initial word lines are parallel to the substrate and extend along a first direction.

[0149] In this step, refer to Figure 6 A word line via 160 extending along a first direction can be formed in the dielectric layer 120 of the dielectric structure at the location corresponding to the transistor 600 using an etching process. The word line via 160 exposes the gate of the transistor 600.

[0150] Reference Figure 7 After forming the word line via 160, a gate oxide layer (not shown) can be formed on the gate surface of the transistor 600 by means of physical vapor deposition, chemical vapor deposition, atomic layer deposition or epitaxial growth. The material of the gate oxide layer can be, for example, silicon dioxide.

[0151] Reference Figure 7 After the gate oxide layer is formed, multiple initial word lines 200' can be formed in the word line via 160 by means of physical vapor deposition, chemical vapor deposition, atomic layer deposition or epitaxial growth. Each initial word line 200' is connected to the gate of multiple transistors 600 in the first direction.

[0152] S220. Remove part of the structure of the initial character lines so that the preset ends of multiple initial character lines are stepped in the second direction. The retained initial character lines form character lines, and part of the top surface of each character line forms a stepped surface.

[0153] In this step, refer to Figure 8 The initial character lines 200' can be etched back using an etching process, so that the preset ends of multiple initial character lines 200' are stepped in the second direction, and the retained initial character lines 200' form character lines 200.

[0154] S300. Multiple sets of word line lead groups are formed, the number of word line lead groups is equal to the number of word lines, the multiple sets of word line lead groups are correspondingly set with multiple word lines, each set of word line lead groups is connected to a preset end of its corresponding word line, wherein each set of word line lead groups includes multiple word line leads, the multiple word line leads include a preset lead, the preset lead is located above the dielectric structure, the extension direction of the preset lead is parallel to the top surface of the substrate, and has a first preset angle with the first direction.

[0155] In one example, refer to Figures 9 to 12 First, you can form the letter lines extending along the second direction.

[0156] In this example, step S300 may specifically include the following steps:

[0157] S311. Form the first character line leader. The first character line leader is connected to the stepped surface of the character line. The first character line leader extends along the second direction. The top surfaces of multiple first character line leaders are flush.

[0158] In this step, refer to Figure 11 A first word line sacrificial layer 311 can be formed using a deposition process. The first word line sacrificial layer 311 covers the top surface of the word line 200, extends beyond the top surface of the dielectric structure, and is parallel to the top surface of the substrate 110. Next, a deep via structure (not shown) can be formed in the first word line sacrificial layer 311 using an etching process. The deep via structure exposes a portion of the top surface of the stepped surface of each word line 200. Then, a first word line lead 310 can be formed in the deep via structure using a deposition process. The first word line lead 310 is connected to the stepped surface of the word line 200.

[0159] After the first letter lead 310 is formed, chemical mechanical polishing can be used to polish and flatten the top surface of the first letter lead 310 so that the top surfaces of multiple first letter leads 310 are flush.

[0160] S312. A second character line is formed. The first end of the second character line is connected to the top surface of the first character line. The second character line extends along a third direction. The third direction has a second preset angle with the first direction. The third direction is perpendicular to the second direction.

[0161] In this step, refer to Figure 12 A second word line sacrificial layer 321 can be formed on the top surface of the first word line lead 310 and the first word line lead sacrificial layer 311 using a deposition process. The top surface of the second word line lead sacrificial layer 321 is parallel to the top surface of the substrate 110. Next, a portion of the structure of the second word line lead sacrificial layer 321 can be removed using photolithography and etching processes to form a plurality of trenches (not shown) extending in a third direction in the second word line lead sacrificial layer 321. Each trench exposes at least a portion of the top surface of the first word line lead 310. Then, a second word line lead 320 can be formed in each trench using a deposition process.

[0162] After the second letter lead 320 is formed, chemical mechanical polishing can be used to polish and flatten the top surface of the second letter lead 320 so that the top surfaces of multiple second letter leads 320 are flush, so as to avoid short circuits caused by contact between the third letter lead 340 formed in subsequent processes and multiple second letter leads 320.

[0163] S313. A fourth character line lead is formed, which is connected to the second character line lead, and the fourth character line lead extends along the second direction.

[0164] In this step, refer to Figure 12 A fourth word line sacrificial layer 331 can be formed on the top surface of the second word line lead 320 and the second word line lead sacrificial layer 321 using a deposition process. The top surface of the fourth word line lead sacrificial layer 331 is parallel to the top surface of the substrate 110. Next, a portion of the structure of the fourth word line lead sacrificial layer 331 can be removed using photolithography and etching processes to form multiple vias in the fourth word line lead sacrificial layer 331. Each via can expose a portion of the top surface of the second word line lead 320. Then, a fourth word line lead 330 can be formed in each via using a deposition and epitaxial growth process. The fourth word line lead 330 is connected to the second word line lead 320.

[0165] After the fourth letter lead 330 is formed, the top surface of the fourth letter lead 330 can be ground flat.

[0166] S314. A third character line is formed, which serves as a preset line. The third character line is connected to the fourth character line, and the extension direction of the third character line has a first preset angle with the first direction.

[0167] In this step, refer to Figure 12 A third word line sacrificial layer 341 can be formed on the top surface of the fourth word line lead 330 and the fourth word line lead sacrificial layer 331 using a deposition process. The top surface of the third word line lead sacrificial layer 341 is parallel to the top surface of the substrate 110. Next, photolithography and etching processes can be used to remove part of the structure of the third word line lead sacrificial layer 341, forming multiple trenches in the third word line lead sacrificial layer 341. Each trench exposes at least a portion of the top surface of the fourth word line lead 330, and the extension direction of the trench in the third word line lead sacrificial layer 341 has a first predetermined angle with a first direction. Then, deposition, epitaxial growth, and other processes can be used to form the third word line lead 340 in the trenches.

[0168] In the semiconductor structure fabrication method provided in this example, firstly, a first word line lead connected to the word line and extending along a second direction is formed. Next, a second word line lead connected to the first word line lead and extending along a third direction is formed. Then, a fourth word line lead connected to the second word line lead and extending along the second direction is formed. Finally, a third word line lead connected to the fourth word line lead is formed. The third word line lead serves as a preset lead. As can be seen from the above, by bending the word line lead multiple times, the preset lead of the word line lead is located above the dielectric structure, thereby effectively utilizing the space above the capacitor 700, improving space utilization, and facilitating the realization of a memory with higher storage density.

[0169] In another example, refer to Figures 13 to 19 First, you can form the letter lines extending in a third direction.

[0170] In this example, step S300 may specifically include the following steps:

[0171] S321. A fifth character line leader is formed. The first end of the fifth character line leader is connected to the stepped surface of the character line. The fifth character line leader extends along a third direction. The third direction has a second preset angle with the first direction. The third direction is perpendicular to the second direction.

[0172] In this step, refer to Figures 14 to 16 A fifth word line sacrificial layer 351 can be formed using a deposition process. This fifth word line sacrificial layer 351 covers the top surface of the word line 200, and its top surface is parallel to the top surface of the substrate 110. Next, a portion of the structure of the fifth word line sacrificial layer 351 can be removed using photolithography and etching processes. The remaining fifth word line sacrificial layer 351 is stepped in a second direction, exposing a portion of the top surface of the stepped surface of the word line 200. Then, a fifth word line lead 350 can be formed on the exposed stepped surface of the word line using a deposition process, extending along a third direction.

[0173] S322. Form a sixth letter lead, which is connected to the second end of the fifth letter lead. The sixth letter lead extends along the second direction, and the top surface of the sixth letter lead is flush with the second direction.

[0174] In this step, refer to Figure 17 and Figure 18A sixth-word lead sacrificial layer 361 can be formed using a deposition process. This sixth-word lead sacrificial layer 361 covers the top surface of the fifth-word lead sacrificial layer 351 and the fifth-word lead 350, and the top surface of the sixth-word lead sacrificial layer 361 is parallel to the top surface of the substrate 110. Next, a portion of the structure of the sixth-word lead sacrificial layer 361 can be removed using photolithography and etching processes, forming multiple vias in the sixth-word lead sacrificial layer 361. Each via exposes a portion of the top surface of the fifth-word lead 350. Then, a sixth-word lead 360 can be formed in each via using deposition, epitaxial growth, or other processes.

[0175] After the sixth line is formed, the top surface of the sixth line can be ground smooth.

[0176] S323. A seventh-character line is formed. The seventh-character line is a preset line. The top surface of the seventh-character line is connected to the top surface of the sixth-character line. The extension direction of the seventh-character line has a first preset angle with the first direction.

[0177] In this step, refer to Figure 19 A seventh-word lead sacrificial layer 371 can be formed using a deposition process. This seventh-word lead sacrificial layer 371 covers the top surfaces of the sixth-word lead sacrificial layer 361 and the sixth-word lead 360, and the top surface of the seventh-word lead sacrificial layer 371 is parallel to the top surface of the substrate 110. Next, a portion of the structure of the seventh-word lead sacrificial layer 371 can be removed using photolithography and etching processes, forming multiple trenches in the seventh-word lead sacrificial layer 371. Each trench exposes at least a portion of the top surface of the sixth-word lead 360. Then, a seventh-word lead 370 can be formed in each trench using deposition, epitaxial growth, or other processes.

[0178] In the semiconductor structure fabrication method provided in this example, firstly, a fifth word line lead connected to the word line and extending along a third direction is formed. Next, a sixth word line lead connected to the fifth word line lead and extending along a second direction is formed. Then, a seventh word line lead connected to the sixth word line lead and extending along a first direction is formed. The seventh word line serves as a preset lead. As can be seen, by repeatedly bending the word line leads, the preset lead of the word line leads is positioned above the dielectric structure, thereby effectively utilizing the space above the capacitor, improving space utilization, and facilitating the realization of higher storage density memories.

[0179] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0180] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0181] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0182] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0183] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0184] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0185] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor structure, characterized by, include: A substrate, the substrate comprising a substrate and a dielectric structure located on the substrate; Multiple word lines are located in the dielectric structure and parallel to the substrate. The word lines extend along a first direction and are arranged along a second direction. The preset ends of the multiple word lines are stepped in the second direction. The second direction is the thickness direction of the substrate and is perpendicular to the first direction. Multiple sets of character line lead groups, the number of character line lead groups being equal to the number of character lines, multiple sets of character line lead groups being configured corresponding to multiple character lines, and each set of character line lead groups being connected to a preset end of the corresponding character line; Each word line lead group includes multiple word lines, and the multiple word lines include a preset lead. The preset lead is located above the dielectric structure, and the extension direction of the preset lead is parallel to the top surface of the substrate and has a first preset angle with the first direction.

2. The semiconductor structure of claim 1, wherein, The multiple character line leads include a first character line lead, a second character line lead, and a third character line lead, wherein the third character line lead is the preset lead; Wherein, the first character line lead is connected to the preset end of the character line, and the first character line lead extends along the second direction; The first end of the second character line is connected to the first character line, and the second character line extends along a third direction. The third direction has a second preset angle with the first direction, and the third direction is perpendicular to the second direction. The third character line lead is connected to the second character line lead, and the extension direction of the third character line lead has the first preset angle with the first direction.

3. The semiconductor structure of claim 2, wherein, In the second direction, the top surfaces of the multiple first-line leads are flush.

4. The semiconductor structure of claim 2, wherein, The multiple word line leads also include a fourth word line lead; The fourth lead wire connects the second lead wire and the third lead wire, and the fourth lead wire extends along the second direction.

5. The semiconductor structure of claim 4, wherein, In the third direction, the distances from the connection points of the multiple fourth word line leads and the multiple second word line leads to the first end of the second word line lead are not equal.

6. The semiconductor structure of claim 2, wherein, The top surface height of the multiple second-line leaders arranged along the first direction gradually decreases; and / or, The lengths of the multiple second-character lines arranged along the first direction gradually decrease in the third direction.

7. The semiconductor structure of claim 1, wherein, The multiple character line leads include a fifth character line lead, a sixth character line lead, and a seventh character line lead, wherein the seventh character line lead is the preset lead; Wherein, the first end of the fifth character line lead is connected to the preset end of the character line, the fifth character line lead extends along a third direction, the third direction is perpendicular to the second direction, and there is a second preset angle between the third direction and the first direction; The sixth character line lead is connected to the second end of the fifth character line lead, and the sixth character line lead extends along the second direction; The seventh lead wire is connected to the sixth lead wire, and the extension direction of the seventh lead wire has the first preset angle with the first direction.

8. The semiconductor structure of claim 7, wherein, In the third direction, the distance between the second end of the fifth word line lead and the word line is not equal.

9. The semiconductor structure according to claim 7, characterized in that, In the second direction, the top surfaces of the plurality of sixth-line leads are flush.

10. The semiconductor structure according to any one of claims 1-9, characterized in that, The semiconductor structure also includes: Multiple bit lines are located in the dielectric structure and perpendicular to the substrate, and the multiple bit lines are arranged along the first direction; Multiple bit line leads are parallel to the substrate, the number of bit line leads is equal to the number of bit lines, and the multiple bit line leads are arranged corresponding to the multiple bit lines; In the thickness direction of the substrate, the bit line lead is located between the dielectric structure and the word line lead.

11. The semiconductor structure of claim 10, wherein, The semiconductor structure also includes: A transistor is located in the dielectric structure and parallel to the substrate. A first end of the transistor is connected to the bit line. The transistor extends along a third direction, which is perpendicular to the second direction. The third direction has a second preset angle with the first direction. A capacitor is located in the dielectric structure and parallel to the substrate, and the capacitor is connected to the second terminal of the transistor.

12. A method of fabricating a semiconductor structure, the method comprising: include: A substrate is provided, the substrate comprising a substrate and a dielectric structure disposed on the substrate; Multiple word lines are formed, which are located in the dielectric structure and parallel to the substrate. The word lines extend along a first direction and are arranged along a second direction. The preset ends of the multiple word lines are stepped in the second direction, which is the thickness direction of the substrate and is perpendicular to the first direction. Multiple sets of word line lead groups are formed, the number of word line lead groups being equal to the number of word lines. The multiple sets of word line lead groups are correspondingly arranged with multiple word lines. Each set of word line lead groups is connected to a preset end of the corresponding word line. Each set of word line lead groups includes multiple word line leads, and the multiple word line leads include a preset lead. The preset lead is located above the dielectric structure, and the extension direction of the preset lead is parallel to the top surface of the substrate and has a first preset angle with the first direction.

13. The method of fabricating a semiconductor structure of claim 12, wherein, Multiple sets of word line leader groups are formed, including: A first character line leader is formed, the first character line leader is connected to the stepped surface of the character line, the first character line leader extends along the second direction, and the top surfaces of multiple first character line leaders are flush. A second character line is formed, the first end of the second character line is connected to the top surface of the first character line, the second character line extends along a third direction, the third direction has a second preset angle with the first direction, and the third direction is perpendicular to the second direction; A fourth character line is formed, which is connected to the second character line and extends along the second direction; A third character line is formed, which serves as the preset lead. The third character line is connected to the fourth character line, and the extension direction of the third character line has the first preset angle with the first direction.

14. The method of fabricating a semiconductor structure of claim 12, wherein, Multiple sets of word line leader groups are formed, including: A fifth character line is formed, the first end of the fifth character line is connected to the stepped surface of the character line, the fifth character line extends along a third direction, the third direction has a second preset angle with the first direction, and the third direction is perpendicular to the second direction; A sixth lead wire is formed, which is connected to the second end of the fifth lead wire. The sixth lead wire extends along the second direction, and the top surface of the sixth lead wire is flush with the second direction. A seventh-character lead is formed, which is the preset lead. The top surface of the seventh-character lead is connected to the top surface of the sixth-character lead, and the extension direction of the seventh-character lead has the first preset angle with the first direction.

15. The method of fabricating a semiconductor structure of claim 14, wherein, The fifth line leader is formed, including: A fifth word line lead sacrificial layer is formed, covering the surface of the plurality of word lines, wherein the top surface of the fifth word line lead sacrificial layer is parallel to the top surface of the substrate; Remove part of the structure of the fifth word line lead sacrificial layer, and retain the fifth word line lead sacrificial layer in a stepped shape in the second direction, with the stepped surface of the fifth word line lead sacrificial layer exposing part of the top surface of the stepped surface of the word line; The fifth word line lead is formed, covering the stepped surface exposed by the word line.

16. The method of fabricating a semiconductor structure of claim 12, wherein, Provide a substrate, including: Provide substrate; A stacked structure is formed on the substrate, the stacked structure comprising alternating stacked dielectric layers and sacrificial layers; In the stacked structure, a plurality of isolation layers are formed that extend along the second direction and are arranged along the first direction; Bit lines are formed between adjacent isolation layers, and the sacrificial layer is removed, leaving the dielectric layer and the isolation layer to form the dielectric structure; On the vacancy formed after removing the sacrificial layer, a capacitor via is formed along a third direction, the third direction being perpendicular to the second direction, and the third direction having a second preset angle with the first direction; Based on the bit line, a transistor and a capacitor are sequentially formed in the capacitor via, the transistor connecting the bit line and the capacitor, and the capacitor being parallel to the substrate.

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