Array substrate and manufacturing method thereof

Abstract

The application discloses an array substrate and a preparation method thereof. The array substrate comprises a substrate, a first metal layer located on one side of the substrate, the first metal layer comprising a first capacitor plate, a first insulating layer located on a side of the first metal layer away from the substrate, the first insulating layer comprising at least two layers, the first insulating layer comprising a first recess and a first via, the first recess being formed by recessing a surface of the first insulating layer away from the first metal layer, the first via being arranged through the first insulating layer, a normal projection of the first recess on the substrate and a normal projection of the first capacitor plate on the substrate at least partially overlapping, a normal projection of the first via on the substrate and a normal projection of the first capacitor plate on the substrate being arranged in a staggered manner, and a second metal layer located on a side of the first insulating layer away from the first metal layer, the second metal layer comprising a second capacitor plate, at least part of the second capacitor plate being located in the first recess. The application can improve the yield of the array substrate.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and its fabrication method. Background Technology

[0002] With the rapid development of electronic devices, users have increasingly higher requirements for display panels, making the manufacturing and display of electronic device display panels receive more and more attention from the industry.

[0003] The display panel includes an array substrate, which includes a substrate and multiple metal layers disposed on the substrate. Different metal layers include different signal lines, such as gate lines, scan lines, capacitor plates, etc. This makes the fabrication of the array substrate extremely complex, requiring multiple patterning of metal material layers to form various signal lines, which makes it difficult to guarantee the yield of the array substrate. Summary of the Invention

[0004] This application provides an array substrate and a method for fabricating the same, aiming to improve the yield of the array substrate.

[0005] An embodiment of the first aspect of this application provides an array substrate, comprising: a substrate; a first metal layer located on one side of the substrate, the first metal layer including a first capacitor plate; a first insulating layer located on the side of the first metal layer away from the substrate, the first insulating layer comprising at least two layers, the first insulating layer including a first groove and a first via, the first groove being formed by a recess in the surface of the first insulating layer away from the first metal layer, the first via penetrating the first insulating layer, the orthographic projection of the first groove on the substrate at least partially overlapping the orthographic projection of the first capacitor plate on the substrate, the orthographic projection of the first via on the substrate and the orthographic projection of the first capacitor plate on the substrate being misaligned; and a second metal layer located on the side of the first insulating layer away from the first metal layer, the second metal layer including a second capacitor plate, at least a portion of the second capacitor plate being located within the first groove.

[0006] According to an embodiment of the first aspect of this application, the first insulating layer includes at least a first film layer and a second film layer located in the first film layer toward the first metal layer, the first groove is disposed through the first film layer or through a portion of the first film layer, and the first via includes a first segment through the first film layer and a second segment through at least a portion of the second film layer.

[0007] According to any of the foregoing embodiments of the first aspect of this application, it further includes a connecting portion located on the side of the first insulating layer away from the second metal layer, the orthographic projection of the second groove on the substrate and the orthographic projection of the connecting portion on the substrate at least partially overlap, the second metal layer further includes signal lines, at least a portion of the signal lines being electrically connected to the connecting portion via a first via.

[0008] According to any of the foregoing embodiments of the first aspect of this application, the connecting portion is disposed on the first metal layer, and the etching time of the second segment is the same as the etching time of the first groove.

[0009] According to any of the foregoing embodiments of the first aspect of this application, the first groove penetrates the first film layer, and the first film layer and the second film layer have the same thickness and material.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the thickness and material of the first film layer and the second film layer are different, and the first film layer and the second film layer satisfy the following formula (1):

[0011] H1 / V1=H2 / V2 (1)

[0012] Where H1 is the depth of the first groove, V1 represents the etching rate of the first film layer, H2 is the thickness of the second film layer, and V2 represents the etching rate of the second film layer.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the first film layer includes a first sublayer and a second sublayer located on the side of the first sublayer facing the substrate, the first groove penetrates the first sublayer and the second sublayer, and the second film layer, the first sublayer and the second sublayer satisfy the following formula (2):

[0014] H 11 / V 11 +H 12 / V 12 =H2 / V2 (2)

[0015] Among them, H 11 V represents the thickness of the first sublayer. 11 H represents the etching rate of the first sublayer. 12 V represents the thickness of the second sublayer. 12 H2 represents the etching rate of the second sublayer, H2 is the thickness of the second film, and V2 represents the etching rate of the second film.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the first film layer includes a first sublayer and a second sublayer located on the side of the first sublayer facing the substrate, a first groove penetrates the first sublayer, and the bottom wall surface of the first groove is located on the surface of the second sublayer facing away from the second film layer, and the second film layer and the first sublayer satisfy the following formula (3) or (4):

[0017] H 11 / V 11 =H2 / V2 (3)

[0018] H 11 / V 11 =H 12 / V 12+H2 / V2 (4)

[0019] Among them, H 11 V represents the thickness of the first sublayer. 11 H represents the etching rate of the first sublayer. 12 V represents the thickness of the second sublayer. 12 H2 represents the etching rate of the second sublayer, H2 is the thickness of the second film, and V2 represents the etching rate of the second film.

[0020] According to any of the foregoing embodiments of the first aspect of this application, it further includes:

[0021] The first conductive layer is located on the side of the first metal layer facing the substrate, and the connecting portion is disposed on the first conductive layer;

[0022] The second insulating layer is located between the first conductive layer and the first metal layer. The second insulating layer also includes a second via communicating with the first via. The second via is disposed through the second insulating layer, and the orthographic projection of the second via on the substrate and the orthographic projection of the connection portion on the substrate at least partially overlap.

[0023] The etching time for the first groove is equal to the sum of the etching times for the second segment and the second via.

[0024] According to any of the foregoing embodiments of the first aspect of this application, the first film layer includes a first sublayer and a second sublayer located on the side of the first sublayer facing the substrate, and the first groove penetrates the first sublayer and the second sublayer;

[0025] The second film layer, the first sublayer, the second sublayer, and the second insulating layer satisfy the following formula (5):

[0026] H 11 / V 11 +H 12 / V 12 =H2 / V 2+ H3 / V3 (5)

[0027] Among them, H 11 V represents the thickness of the first sublayer. 11 H represents the etching rate of the first sublayer. 12 V represents the thickness of the second sublayer. 12 H2 represents the etching rate of the second sublayer, H3 represents the thickness of the second film layer, V2 represents the etching rate of the second film layer, H3 represents the thickness of the second insulating layer, and V3 represents the etching rate of the second insulating layer.

[0028] According to any of the foregoing embodiments of the first aspect of this application, the first film layer includes a first sublayer and a second sublayer located on the side of the first sublayer facing the substrate, a first groove penetrates the first sublayer, and the bottom of the first groove is located on the second sublayer, and the second film layer, the first sublayer, and the second insulating layer satisfy the following formula (6):

[0029] H 11 / V 11 =H2 / V 2+ H3 / V3 (6)

[0030] Among them, H 11 V represents the thickness of the first sublayer. 11 H2 represents the etching rate of the first sublayer, H2 represents the thickness of the second film layer, V2 represents the etching rate of the second film layer, H3 represents the thickness of the second insulating layer, and V3 represents the etching rate of the second insulating layer.

[0031] According to any of the foregoing embodiments of the first aspect of this application, the first conductive layer is a semiconductor layer, the semiconductor layer further includes a semiconductor portion, and the second insulating layer is an inter-gate insulating layer.

[0032] According to any of the foregoing embodiments of the first aspect of this application, the materials of the first sublayer and the second sublayer are different.

[0033] According to any of the foregoing embodiments of the first aspect of this application, the first sublayer and the second film layer are made of the same material.

[0034] According to any of the foregoing embodiments of the first aspect of this application, the etching rate of the second sublayer is greater than the etching rate of the first sublayer.

[0035] According to any of the foregoing embodiments of the first aspect of this application, the material of the second film layer and the first sublayer includes silicon oxide, and the material of the second sublayer includes silicon nitride; or, the material of the second film layer and the first sublayer includes silicon nitride, and the material of the second sublayer includes silicon oxide.

[0036] According to any of the foregoing embodiments of the first aspect of this application, the thickness of the second film layer is greater than the thickness of the first sublayer.

[0037] An embodiment of the second aspect of this application also provides a method for fabricating an array substrate, comprising:

[0038] A substrate to be etched is provided. The substrate to be etched includes a substrate and a first metal layer and a first insulating layer to be etched are sequentially disposed on one side of the substrate. The first metal layer includes a first capacitor plate. The first insulating layer to be etched has a first groove region and a first via region. The orthographic projection of the first capacitor plate on the substrate and the orthographic projection of the first groove region on the substrate at least partially overlap.

[0039] A photoresist layer is disposed on the surface of the first insulating layer to be etched away from the first metal layer, and the photoresist layer is patterned to form a first etching groove and a second etching groove. The first etching groove is located in the first groove area and is formed by the recess of the photoresist layer away from the surface of the first insulating layer to be etched. The second etching groove is located in the first via area and is disposed through the photoresist layer.

[0040] The substrate to be etched with a photoresist layer is subjected to a first etching process to remove at least a portion of the thickness of the first insulating layer to be etched in the first via area.

[0041] The photoresist layer is thinned so that it penetrates the first etching trench;

[0042] A second etching process is performed on the substrate to be etched with a photoresist layer to form an array substrate including a first insulating layer. The first insulating layer includes a first groove located in a first groove region and a first via located in a first via region. The first groove is formed by a recess in the surface of the first insulating layer away from the first metal layer, and the first via is disposed through the first insulating layer.

[0043] According to an embodiment of the second aspect of this application, the first insulating layer to be etched includes a first film layer and a second film layer located between the first film layer and the first metal layer.

[0044] In the first etching process of the substrate to be etched with a photoresist layer, a first film layer with a thickness of n1*H1 is removed in the first via area, where n1 is a coefficient greater than 0 and less than 1, and H1 is the thickness value of the first film layer.

[0045] In the step of performing a second etching process on the substrate to be etched with a photoresist layer, at least a portion of the first film layer is removed in the first groove region to form a first groove, and the first film layer and the second film layer with a thickness of (1-n1)*H1 are removed in the first via region to form a first via through the first film layer and the second film layer.

[0046] According to any of the foregoing embodiments of the second aspect of this application, the first film layer includes a first sublayer and a second sublayer located on the side of the first sublayer facing the substrate, and the thickness of the first sublayer is n1*H1;

[0047] In the first etching process of the substrate to be etched with a photoresist layer, the first sub-layer is removed in the first via area.

[0048] In the step of performing a second etching process on the substrate to be etched with a photoresist layer, part or all of the first sublayer is removed in the first groove region, or the first sublayer and at least part of the second sublayer are removed in the first groove region to form a first groove; the second sublayer and the second film layer are removed in the first via region to form a first via layer penetrating the first film layer and the second film layer.

[0049] According to any of the foregoing embodiments of the second aspect of this application, the first insulating layer to be etched includes a first film layer and a second film layer located between the first film layer and the first metal layer.

[0050] In the first etching process of the substrate to be etched with a photoresist layer, the first film layer and the second film layer with a thickness of n2*H2 are removed in the first via area, where n2 is a coefficient greater than 0 and less than 1, and H2 is the thickness value of the second film layer.

[0051] In the step of performing a second etching process on the substrate to be etched with a photoresist layer, at least a portion of the first film layer is removed in the first groove region to form a first groove, and a second film layer with a thickness of (1-n2)*H2 is removed in the first via region to form a first via penetrating the first film layer and the second film layer.

[0052] According to any of the foregoing embodiments of the second aspect of this application, the second film layer includes a third sub-layer and a fourth sub-layer located on the side of the third sub-layer facing the substrate, the thickness of the fourth sub-layer being n2*H2.

[0053] In the first etching process of the substrate to be etched with a photoresist layer, the first film layer and the third sub-layer are removed in the first via area.

[0054] In the step of performing a second etching process on the substrate to be etched with a photoresist layer, at least a portion of the first film layer is removed in the first groove region to form a first groove, and a fourth sub-layer is removed in the first via region to form a first via penetrating the first film layer and the second film layer.

[0055] According to any of the foregoing embodiments of the second aspect of this application, the first insulating layer to be etched includes a first film layer and a second film layer located between the first film layer and the first metal layer.

[0056] In the first etching process of the substrate to be etched with a photoresist layer, the first film layer is removed in the first via area.

[0057] In the step of performing a second etching process on the substrate to be etched with a photoresist layer, at least a portion of the first film layer is removed in the first groove region to form a first groove, and a second film layer is removed in the first via region to form a first via penetrating the first film layer and the second film layer.

[0058] According to any of the foregoing embodiments of the second aspect of this application, the first film layer includes a first sublayer and a second sublayer located on the side of the first sublayer facing the substrate.

[0059] According to any of the foregoing embodiments of the second aspect of this application, the substrate to be etched further includes a first conductive layer and a second insulating layer. The first conductive layer is located on the side of the first metal layer facing the substrate, and the first conductive layer is provided with a connection portion located in the first via region. The second insulating layer is located between the first conductive layer and the first metal layer.

[0060] The step of performing a second etching process on the substrate to be etched with a photoresist layer also includes: removing the second insulating layer in the first via region to form a second via penetrating the second insulating layer.

[0061] In the array substrate provided in this application embodiment, the array substrate includes a substrate and a first metal layer, a first insulating layer, and a second metal layer disposed on the substrate. The first metal layer includes a first capacitor electrode, and the second metal layer includes a second capacitor electrode. The first capacitor electrode and the second capacitor electrode can form a capacitor. A first groove is formed on the first insulating layer of the first and second metal layers, and the second capacitor electrode is located in the first groove. By adjusting the size of the first groove, the overlap area of ​​the second capacitor electrode and the first capacitor electrode can be adjusted, thereby adjusting the size of the capacitor. This can improve the fabrication accuracy of the array substrate and thus improve the yield of the array substrate. Attached Figure Description

[0062] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0063] Figure 1 This is a cross-sectional view of an array substrate provided in one embodiment of this application;

[0064] Figure 2 This is a cross-sectional view of an array substrate provided in another embodiment of this application;

[0065] Figure 3 This is a cross-sectional view of an array substrate provided in another embodiment of this application;

[0066] Figure 4 This is a cross-sectional view of an array substrate provided in another embodiment of this application;

[0067] Figure 5 This is a cross-sectional view of an array substrate provided in another embodiment of this application;

[0068] Figure 6 This is a cross-sectional view of an array substrate provided in another embodiment of this application;

[0069] Figure 7 This is a cross-sectional view of an array substrate provided in another embodiment of this application;

[0070] Figure 8 This is a schematic diagram of a method for fabricating an array substrate according to an embodiment of this application;

[0071] Figures 9 to 21 This is a schematic diagram of a method for manufacturing a display panel according to an embodiment of this application.

[0072] Explanation of reference numerals in the attached figures:

[0073] 01. Substrate;

[0074] 02. First metal layer; 210. First capacitor plate;

[0075] 03, First insulating layer; 03a, First film layer; 03a1, First sub-layer; 03a2, Second sub-layer; 03b, Second film layer; 03b1, Third sub-layer; 03b2, Fourth sub-layer; 310, First groove; 320, First via;

[0076] 04. Second metal layer; 410. Second capacitor plate; 420. Signal line;

[0077] 05. Connecting parts;

[0078] 06. First conductive layer;

[0079] 07. Second insulating layer; 710. Second via;

[0080] 08. Photoresist layer; 810. First etching trench; 820. Second etching trench. Detailed Implementation

[0081] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0082] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0083] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0084] This application provides an array substrate and a method for fabricating the same. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the array substrate and its fabrication method.

[0085] This application provides an array substrate that can be used for a display panel, which may be an organic light-emitting diode (OLED) display panel.

[0086] Please see Figure 1 , Figure 1 This is a cross-sectional view of an array substrate provided in one embodiment of this application.

[0087] like Figure 1As shown, an embodiment of the first aspect of this application provides an array substrate, which includes a substrate 01, a first metal layer 02, a first insulating layer 03, and a second metal layer 04. The first metal layer 02 is located on one side of the substrate 01 and includes a first capacitor plate 210. The first insulating layer 03 is located on the side of the first metal layer 02 away from the substrate 01. The first insulating layer 03 includes at least two layers and includes a first groove 310 and a first via 320. The first groove 310 is located on the side of the first insulating layer 03 away from the first metal layer 02. A surface depression is formed, a first via 320 is disposed through the first insulating layer 03, the orthographic projection of the first groove 310 on the substrate 01 overlaps at least partially with the orthographic projection of the first capacitor plate 210 on the substrate 01, and the orthographic projection of the first via 320 on the substrate 01 and the orthographic projection of the first capacitor plate 210 on the substrate 01 are misaligned; the second metal layer 04 is located on the side of the first insulating layer 03 away from the first metal layer 02, the second metal layer 04 includes the second capacitor plate 410, and at least part of the second capacitor plate 410 is located in the first groove 310.

[0088] In the array substrate provided in this application embodiment, the array substrate includes a substrate 01 and a first metal layer 02, a first insulating layer 03, and a second metal layer 04 disposed on the substrate 01. The first metal layer 02 includes a first capacitor electrode 210, and the second metal layer 04 includes a second capacitor electrode 410. The first capacitor electrode 210 and the second capacitor electrode 410 can form a capacitor. A first groove 310 is formed on the first insulating layer 03 of the first metal layer 02 and the second metal layer 04. The second capacitor electrode 410 is located in the first groove 310. By adjusting the size of the first groove 310, the overlap area of ​​the second capacitor electrode 410 and the first capacitor electrode 210 can be adjusted, thereby adjusting the size of the capacitor. This can improve the fabrication accuracy of the array substrate and thus improve the yield of the array substrate.

[0089] The substrate 01 can be made of light-transmitting materials such as glass or polyimide (PI).

[0090] There are various ways to configure the array substrate. In some embodiments, the array substrate 100 may include a semiconductor layer, a first metal layer 02, a second metal layer 04, and a third metal layer stacked on one side of the substrate 01. An insulating layer is disposed between adjacent metal layers. For example, a pixel driving circuit disposed on the array substrate includes a transistor and a storage capacitor C. The transistor includes a semiconductor, a gate, a source, and a drain. The storage capacitor C includes a first capacitor plate 210 and a second capacitor plate 410. As an example, the gate and the first capacitor plate 210 may be located on the first metal layer 02, the second capacitor plate 410 may be located on the second metal layer 04, and the source and drain may be located on the third metal layer.

[0091] There are several ways to make the first insulating layer 03. For some optional embodiments, please refer to... Figure 2 The first insulating layer 03 includes at least a first film layer 03a and a second film layer 03b located in the first film layer 03a toward the first metal layer 02. The first groove 310 is disposed through the first film layer 03a or penetrates a portion of the first film layer 03a. The first via 320 includes a first segment penetrating the first film layer 03a and a second segment penetrating at least a portion of the second film layer 03b.

[0092] In these optional embodiments, the first insulating layer 03 includes a first film layer 03a and a second film layer 03b, a first groove 310 is disposed in the first film layer 03a, and a first via 320 penetrates the first film layer 03a and the second film layer 03b. During the fabrication of the array substrate, the first via 320 can be fabricated in segments. For example, a first segment penetrating the first film layer 03a can be fabricated first, followed by the fabrication of the first groove 310. Simultaneously with the fabrication of the first groove 310, a second segment of the second film layer 03b can be formed at the location of the first segment penetrating the first film layer 03a to form the first via 320. This simplifies the fabrication process of the array substrate and improves the problems of complex fabrication processes and low fabrication efficiency caused by fabricating the first via 320 and the first groove 310 in stages.

[0093] Optionally, the array substrate also includes signal lines 420, such as data lines, scan lines, power lines, voltage reference lines, and connection lines connecting pixel electrodes and driving circuits. These signal lines 420 can be connected through the first via 320.

[0094] For example, in some alternative embodiments, such as Figure 1 or Figure 2 As shown, a connection portion 05 is provided on the side of the first via 320 facing the substrate 01. The signal line 420 is connected to the connection portion 05 through the first via 320 to improve the yield of the signal line 420. The connection portion 05 can be located in the first metal layer 02 or the semiconductor layer.

[0095] In some embodiments, as described above, the array substrate includes a connection portion 05 located on the side of the first insulating layer 03 opposite to the second metal layer 04. The orthographic projection of the first via 320 on the substrate 01 and the orthographic projection of the connection portion 05 on the substrate 01 at least partially overlap. The second metal layer 04 also includes signal lines 420, at least a portion of which are electrically connected to the via of the connection portion 05 through the first via 320. In these optional embodiments, the signal line 420 may include segments located on both sides of the first via 320, and the two segments are interconnected through the connection portion 05, which can improve the yield of the signal line 420.

[0096] In some alternative embodiments, such as Figure 1 or Figure 2 As shown, the connecting part 05 is disposed on the first metal layer 02, and the etching time of the second segment is the same as the etching time of the first groove 310.

[0097] In these optional embodiments, after the first segment of the first via 320 is etched and formed, since the etching time of the second segment is the same as the etching time of the first groove 310, the first groove 310 and the second segment can be etched simultaneously, thereby simplifying the fabrication process of the array substrate. Furthermore, since the connection portion 05 is located in the first metal layer 02, after the second segment is etched, the connection portion 05 can be exposed through the first via 320, allowing the signal line 420 to be interconnected with the connection portion 05 through the first via 320.

[0098] The etching time of the second segment being the same as that of the first groove 310 means that the etching time of the second segment being the same as that of the first groove 310 under the same etching parameters.

[0099] There are several ways to set the first groove 310, for example, as follows: Figure 2 As shown, the first groove 310 can penetrate the first film layer 03a. Specifically, the bottom wall surface of the first groove 310 can be the surface of the second film layer that is away from the substrate.

[0100] In some embodiments, the first film layer 03a and the second film layer 03b have the same thickness and material. Therefore, under the same etching parameters, the etching time of the second segment is the same as the etching time of the first groove 310.

[0101] Alternatively, in other embodiments, the thickness and material of the first film layer 03a and the second film layer 03b are different, and the first film layer 03a and the second film layer 03b satisfy the following formula (1):

[0102] H1 / V1=H2 / V2 (1)

[0103] Wherein, H1 is the depth of the first groove 310, V1 represents the etching rate of the first film layer 03a, H2 is the thickness of the second film layer 03b, and V2 represents the etching rate of the second film layer 03b.

[0104] V1 and V2 represent the etching rates of the first film layer 03a and the second film layer 03b under the same etching parameters.

[0105] In these optional embodiments, the thickness and material of the first film layer 03a and the second film layer 03b are different. Therefore, the etching rates of the first film layer 03a and the second film layer 03b are different under the same etching parameters. When the thickness and etching rate of the first film layer 03a and the second film layer 03b satisfy the above relationship (1), the etching time of the first groove 310 and the second segment is the same, and the first groove 310 and the second segment can be prepared simultaneously in the same process step.

[0106] There are several ways to set the first film layer 03a. For example, the first film layer 03a may include two or more sub-layers, and the first groove 310 may be set through at least one sub-layer.

[0107] In some alternative embodiments, such as Figure 3 As shown, the first film layer 03a includes a first sublayer 03a1 and a second sublayer 03a2 located on the side of the first sublayer 03a1 facing the substrate 01.

[0108] When the first film layer 03a includes a first sub-layer 03a1 and a second sub-layer 03a2, there are multiple ways to configure the first groove 310. For example, please refer to [link / reference]. Figure 3 The first groove 310 penetrates the first sublayer 03a1 and the second sublayer 03a2, and the second film layer 03b, the first sublayer 03a1 and the second sublayer 03a2 satisfy the following formula (2):

[0109] H 11 / V 11 +H 12 / V 12 =H2 / V2 (2)

[0110] Among them, H 11 V represents the thickness of the first sublayer 03a1. 11 H represents the etching rate of the first sublayer 03a1. 12 V represents the thickness of the second sublayer 03a2. 12 H2 represents the etching rate of the second sublayer 03a2, H2 is the thickness of the second film layer 03b, and V2 represents the etching rate of the second film layer 03b.

[0111] V 11 V 12 V2 represents the etching rate of the first sublayer 03a1, the second sublayer 03a2, and the second film layer 03b under the same etching parameters.

[0112] In these optional embodiments, the first film layer 03a includes a two-layer structure of a first sub-layer 03a1 and a second sub-layer 03a2, and the first groove 310 is disposed through the first sub-layer 03a1 and the second sub-layer 03a2. When the thickness and etching rate of the first sub-layer 03a1, the second sub-layer 03a2 and the second film layer 03b satisfy the above relationship (2), the etching time of the first groove 310 and the second segment is the same, and the first groove 310 and the second segment can be prepared simultaneously in the same process step.

[0113] In other embodiments, such as Figure 4 As shown, the first groove 310 penetrates the first sub-layer 03a1, and the bottom of the first groove 310 is located in the second sub-layer 03a2, that is, the bottom wall surface of the first groove 310 is the surface of the second sub-layer 03a2 facing away from the second film layer 03b. Then the second film layer 03b and the first sub-layer 03a1 satisfy the following formula (3):

[0114] H 11 / V 11 =H2 / V2 (3)

[0115] Among them, H 11 V represents the thickness of the first sublayer 03a1. 11 H2 represents the etching rate of the first sublayer 03a1, H2 is the thickness of the second film layer 03b, and V2 represents the etching rate of the second film layer 03b.

[0116] In these optional embodiments, the first groove 310 penetrates only the first sublayer 03a1 and not the second sublayer 03a2. When the second film layer 03b and the first sublayer 03a1 satisfy the above relationship (3), the etching time of the first groove 310 and the second segment is the same, and the first groove 310 and the second segment can be prepared simultaneously in the same process step.

[0117] In some other embodiments, the etching times for the first groove 310 and the second segment may be different; for example, the etching time for the first groove 310 may be longer than the etching time for the second segment. For more details, please refer to... Figure 4 The first groove 310 penetrates the first sub-layer 03a1, and the bottom wall of the first groove 310 is the surface of the second sub-layer 03a2 facing away from the second film layer 03b. The second film layer 03b and the first sub-layer 03a1 can satisfy the following formula (4):

[0118] H11 / V11=H12 / V12+H2 / V2 (4)

[0119] Among them, H 11 V represents the thickness of the first sublayer 03a1. 11 H represents the etching rate of the first sublayer 03a1.12 V represents the thickness of the second sublayer 03a2. 12 H2 represents the etching rate of the second sublayer 03a2, H2 is the thickness of the second film layer 03b, and V2 represents the etching rate of the second film layer 03b.

[0120] It should be noted that the difference between formula (3) and the following formula (4) is:

[0121] If the preparation is carried out according to the following process: firstly, the first sub-layer 03a1 and the second sub-layer 03a2 are penetrated in the first via region where the first via 320 is located, and then the first groove 310 is prepared. At the same time as preparing the first groove 310, the second film layer 03b is penetrated in the first via region to form the first via 320 in the first via region. Then the first film layer 03a and the second film layer 03b need to satisfy formula (3).

[0122] If the preparation is carried out according to the following process: firstly, only the first sub-layer 03a1 is penetrated in the first via region where the first via 320 is located, and then the first groove 310 is prepared. At the same time as preparing the first groove 310, the second sub-layer 03a2 and the second film layer 03b are penetrated in the first via region to form the first via 320. Then the first film layer 03a and the second film layer 03b need to satisfy formula (4).

[0123] In other embodiments, the connecting portion 05 may also be disposed on other film layers. For example, such as Figure 5 As shown, the array substrate further includes a first conductive layer 06 and a second insulating layer 07. The first conductive layer 06 is located on the side of the first metal layer 02 facing the substrate 01, and the connection portion 05 is disposed on the first conductive layer 06. The second insulating layer 07 is located between the first conductive layer 06 and the first metal layer 02. The second insulating layer 07 also includes a second via 710 communicating with the first via 320. The second via 710 is disposed through the second insulating layer 07, and the orthographic projection of the second via 710 on the substrate 01 and the orthographic projection of the connection portion 05 on the substrate 01 at least partially overlap. The etching time of the first groove 310 is equal to the sum of the etching times of the second segment and the second via 710.

[0124] Optionally, the first conductive layer 06 can be the semiconductor layer described above. Alternatively, the first conductive layer 06 can be a new conductive layer of metal material added between the semiconductor layer and the first metal layer 02. Alternatively, the first conductive layer 06 can be a new conductive layer of metal material added between the semiconductor layer and the substrate 01.

[0125] In these alternative embodiments, the connection portion 05 is not located on the first metal layer 02, and a second insulating layer 07 is provided between the connection portion 05 and the second metal layer 04. A second via 710 is provided on the second insulating layer 07, so that the signal line 420 can be connected to the connection portion 05 through the first via 320 and the second via 710.

[0126] Furthermore, the etching time of the first groove 310 is equal to the sum of the etching times of the second segment and the second via 710, so that the first groove 310, the second segment, and the second via 710 can be formed in the same process step, which simplifies the fabrication method of the array substrate.

[0127] There are several ways to set the first membrane layer 03a, such as Figure 6 As shown, the first film layer 03a may include a first sublayer 03a1 and a second sublayer 03a2 located on the side of the first sublayer 03a1 facing the substrate 01.

[0128] When the first film layer 03a includes the first sub-layer 03a1 and the second sub-layer 03a2 mentioned above, the first groove 310 may be configured to penetrate only the first sub-layer 03a1, or the first groove 310 may be configured to penetrate both the first sub-layer 03a1 and the second sub-layer 03a2.

[0129] In some alternative embodiments, such as Figure 6 As shown, the first groove 310 penetrates the first sub-layer 03a1 and the second sub-layer 03a2. The second film layer 03b, the first sub-layer 03a1, the second sub-layer 03a2, and the second insulating layer 07 satisfy the following formula (5):

[0130] H 11 / V 11 +H 12 / V 12 =H2 / V 2+ H3 / V3 (5)

[0131] Among them, H 11 V represents the thickness of the first sublayer 03a1. 11 H represents the etching rate of the first sublayer 03a1. 12 V represents the thickness of the second sublayer 03a2. 12 H2 represents the etching rate of the second sublayer 03a2, H2 represents the thickness of the second film layer 03b, V2 represents the etching rate of the second film layer 03b, H3 represents the thickness of the second insulating layer 07, and V3 represents the etching rate of the second insulating layer 07.

[0132] V 11 V 12V2 and V3 represent the etching rates of the first sublayer 03a1, the second sublayer 03a2, the second film layer 03b, and the second insulating layer 07 under the same etching conditions.

[0133] In these optional embodiments, when the second film layer 03b, the first sub-layer 03a1, the second sub-layer 03a2 and the second insulating layer 07 satisfy the above relationship (5), the first groove 310 and the second segment and the second via 710 can be formed in the same process step, which can simplify the preparation method of the array substrate.

[0134] In other embodiments, such as Figure 7 As shown, the first groove 310 penetrates the first sub-layer 03a1, and the bottom of the first groove 310 is the surface of the second sub-layer 03a2 facing away from the second film layer 03b. The second film layer 03b, the first sub-layer 03a1, and the second insulating layer 07 satisfy the following formula (6):

[0135] H 11 / V 11 =H2 / V 2+ H3 / V3 (6)

[0136] Among them, H 11 V represents the thickness of the first sublayer 03a1. 11 H2 represents the etching rate of the first sublayer 03a1, H2 represents the thickness of the second film layer 03b, V2 represents the etching rate of the second film layer 03b, H3 represents the thickness of the second insulating layer 07, and V3 represents the etching rate of the second insulating layer 07.

[0137] In these optional embodiments, when the second film layer 03b, the first sublayer 03a1, and the second insulating layer 07 satisfy the above relationship (6), the first groove 310 and the second segment and the second via 710 can be formed in the same process step, which can simplify the preparation method of the array substrate.

[0138] When the first conductive layer 06 is a semiconductor layer, the second insulating layer 07 can be an inter-gate insulating layer.

[0139] In any of the above embodiments, there are multiple ways to set the materials of the first sub-layer 03a1 and the second sub-layer 03a2. For example, the materials of the first sub-layer 03a1 and the second sub-layer 03a2 may be different. Therefore, when the first groove 310 penetrates the first sub-layer 03a1 but does not penetrate the second sub-layer 03a2, during the fabrication of the array substrate, by setting different etching parameters, the first sub-layer 03a1 can be etched and the etching effect on the second sub-layer 03a2 can be reduced.

[0140] Optionally, the first sub-layer 03a1 and the second film layer 03b are made of the same material, so that under the same etching parameters, the etching time between the first sub-layer 03a1 and the second film layer 03b can be the same, which facilitates the fabrication of the array substrate.

[0141] Optionally, the etching rate of the second sub-layer 03a2 is greater than the etching rate of the first sub-layer 03a1. In these optional embodiments, when etching the first sub-layer 03a1 to form the first groove 310, the second sub-layer 03a2 and the second insulating layer 07 need to be etched to form the second via 710. The etching rate of the second sub-layer 03a2 is greater than the etching rate of the first sub-layer 03a1, therefore the etching time of the second sub-layer 03a2 is shorter. When the first sub-layer 03a1 is etched simultaneously to form the first groove 310, and the second sub-layer 03a2 and the second insulating layer 07 are etched simultaneously to form the second segment and the second via 710, after the second sub-layer 03a2 is etched, the first sub-layer 03a1 has not yet been etched, so the first sub-layer 03a1 and the second insulating layer 07 can continue to be etched, ultimately forming the first groove 310, the second via 710, and the second segment simultaneously.

[0142] There are various ways to set the materials of the first film layer 03a and the second film layer 03b. For example, the materials of the second film layer 03b and the first sub-layer 03a1 include silicon oxide, and the materials of the second sub-layer 03a2 include silicon nitride. Alternatively, the materials of the second film layer 03b and the first sub-layer 03a1 include silicon nitride, and the materials of the second sub-layer 03a2 include silicon oxide.

[0143] In these optional embodiments, the first sub-layer 03a1 and the second sub-layer 03a2 are made of different materials, and the first sub-layer 03a1 and the second sub-layer 03a2 can be etched in stages by setting etching parameters. The second film layer 03b is made of the same material as the first sub-layer 03a1, and the materials of the second film layer 03b and the first sub-layer 03a1 can be etched in the same step to form the second segment of the first groove 310 and the first via 320.

[0144] In some embodiments, the thickness of the second film layer 03b is greater than the thickness of the first sublayer 03a1.

[0145] Please see Figure 8 , Figure 8 This is a schematic flowchart of a method for fabricating an array substrate according to a second aspect embodiment of this application.

[0146] like Figure 8 As shown, a second aspect of this application also provides a method for fabricating an array substrate, which can be any of the array substrates described in the above embodiments. Figure 8 As shown, the method for fabricating the array substrate includes:

[0147] Step S01: As Figure 9 As shown, a substrate to be etched is provided. The substrate to be etched includes a substrate 01 and a first metal layer 02 and a first insulating layer to be etched are sequentially disposed on one side of the substrate 01. The first metal layer 02 includes a first capacitor plate 210. The first insulating layer to be etched has a first groove region and a first via region. The orthographic projection of the first capacitor plate 210 on the substrate 01 and the orthographic projection of the first groove region on the substrate 01 at least partially overlap.

[0148] Step S02: As Figure 10 As shown, a photoresist layer 08 is provided on the surface of the first insulating layer to be etched away from the first metal layer 02, and the photoresist layer 08 is patterned to form a first etching groove 810 and a second etching groove 820. The first etching groove 810 is located in the first groove area and is formed by the recess of the photoresist layer 08 away from the surface of the first insulating layer to be etched. The second etching groove 820 is located in the first via area and is provided through the photoresist layer 08.

[0149] Step S03: As Figure 11 As shown, a first etching process is performed on the substrate to be etched with a photoresist layer 08 to remove at least a portion of the thickness of the first insulating layer to be etched in the first via region.

[0150] Step S04: As Figure 12 As shown, the photoresist layer 08 is thinned so that the first etching trench 810 penetrates the photoresist layer 08.

[0151] Step S05: As Figure 13 As shown, a second etching process is performed on the substrate to be etched with a photoresist layer 08 to form an array substrate including a first insulating layer 03. The first insulating layer 03 includes a first groove 310 located in the first groove region and a first via 320 located in the first via region. The first groove 310 is formed by the recess of the first insulating layer 03 away from the surface of the first metal layer 02, and the first via 320 is disposed through the first insulating layer 03.

[0152] In the array substrate fabrication method provided in this application embodiment, firstly, in step S02, a photoresist layer 08 is deposited on the surface of the first substrate to be etched. Then, the photoresist is patterned so that at least a portion of the thickness of the first insulating layer to be etched can be removed in the first via region during the subsequent first etching process step S03. Then, in step S04, the photoresist undergoes a second process, namely, a thinning process. After thinning, the photoresist thickness decreases, allowing the first etching trench 810 to penetrate the photoresist layer 08. Next, in step S05, a second etching process is performed. During the second etching process, a first groove 310 is formed at the first etching trench 810, and a first via 320 is formed at the second etching trench 820. Therefore, the etching process of the first groove 310 and the first via 320 only requires one photoresist coating process, eliminating the need for repeated coating and cleaning to remove the photoresist layer 08, which simplifies the array substrate fabrication process and improves the fabrication efficiency of the array substrate.

[0153] Furthermore, as described above, the array substrate prepared by the above preparation method can have the second capacitor plate 410 disposed at the first groove 310. By controlling the position of the first groove 310, the effective overlap area of ​​the second capacitor plate 410 and the first capacitor plate 210 can be adjusted, thereby changing the capacitance parameters and improving the yield of the array substrate.

[0154] In some alternative embodiments, such as Figure 14 As shown, for example, the first insulating layer to be etched includes a first film layer 03a and a second film layer 03b located on the first film layer 03a facing the first metal layer 02. Therefore, in step S03, during the first etching process of the substrate to be etched, the first film layer 03a with a thickness of n1*H1 can be removed in the first via region, where n1 is a coefficient greater than 0 and less than 1, and H1 is the thickness value of the first film layer 03a. For example... Figure 15 As shown, in step S05, when performing a second etching process on the substrate to be etched, at least a portion of the first film layer 03a is removed in the first groove region to form a first groove 310, and the first film layer 03a and the second film layer 03b with a thickness of (1-n1)*H1 are removed in the first via region to form a first via 320 penetrating the first film layer 03a and the second film layer 03b.

[0155] In these alternative embodiments, the first film layer 03a with a thickness of n1*H1 is first removed, and the first groove 310 and the first film layer 03a and the second film layer 03b with a thickness of (1-n1)*H1 are formed in the second etching process, that is, the first groove 310 and the first via 320 are formed, which can simplify the fabrication process of the array substrate and improve the fabrication efficiency of the array substrate.

[0156] As described above, and please refer to Figure 16The first film layer 03a may include a first sub-layer 03a1 and a second sub-layer 03a2 located on the side of the first sub-layer 03a1 facing the substrate 01, wherein the thickness of the first sub-layer 03a1 is n1*H1; as Figure 16 As shown, in step S03, during the first etching process of the substrate to be etched, the first sub-layer 03a1 is removed to form the first segment of the first via 320. Figure 17 As shown, in step S05, during the second etching process of the substrate to be etched, part or all of the first sub-layer 03a1 is removed in the first groove region, or the first sub-layer 03a1 and at least part of the second sub-layer 03a2 are removed in the first groove region to form a first groove 310; the second sub-layer 03a2 and the second film layer 03b are removed in the first via region to form a first via 320 penetrating the first film layer 03a and the second film layer 03b. That is, the first groove 310 and the second segment are formed simultaneously in step S05, and the second segment and the first segment form the first via 320. The first groove 310 and the second segment can be fabricated in the same process step, which can simplify the fabrication process of the array substrate and improve the fabrication efficiency of the array substrate.

[0157] In some other alternative embodiments, such as Figure 18 As shown, when the first insulating layer to be etched includes a first film layer 03a and a second film layer 03b located between the first film layer 03a and the first metal layer 02, in step S03, the first film layer 03a and the second film layer 03b with a thickness of n2*H2 are removed in the first via region, where n2 is a coefficient greater than 0 and less than 1, and H2 is the thickness value of the second film layer 03b. In step S05, the second etching process of the substrate to be etched is performed, at least a portion of the first film layer 03a is removed in the first groove region to form a first groove 310, and the second film layer 03b with a thickness of (1-n2)*H2 is removed in the first via region to form a first via 320 penetrating the first film layer 03a and the second film layer 03b.

[0158] In these alternative embodiments, in step S03, the first film layer 03a and part of the second film layer 03b can be completely removed in the first via region, and in step S05, the first film layer 03a can be removed in the first groove region to form a first groove 310, and the remaining part of the second film layer 03b can be removed in the first via region to form a second via 710.

[0159] Optionally, the second film layer 03b includes a third sublayer 03b1 and a fourth sublayer 03b2 located on the side of the third sublayer 03b1 facing the substrate 01, and the thickness of the fourth sublayer 03b2 is n2*H2.

[0160] like Figure 19As shown, in step S03, during the first etching process of the substrate to be etched, the first film layer 03a and the third sub-layer 03b1 are removed in the first via region. In step S05, during the second etching process of the substrate to be etched, at least a portion of the first film layer 03a is removed in the first groove region to form a first groove 310, and the fourth sub-layer 03b2 is removed in the first via region to form a first via 320 penetrating the first film layer 03a and the second film layer 03b.

[0161] When the second film layer 03b includes a third sub-layer 03b1 and a fourth sub-layer 03b2, the first film layer 03a and the third sub-layer 03b1 can be removed in the first via region in step S03. In step S04, the fourth sub-layer 03b2 is removed from the first via 320 to form the first via 320.

[0162] In some alternative embodiments, such as Figure 20 As shown, when the first insulating layer to be etched includes a first film layer 03a and a second film layer 03b located in the first film layer 03a facing the first metal layer 02, the first film layer 03a can also be removed in the first via region in step S03. In step S05, at least a portion of the first film layer 03a can be removed in the first groove region to form a first groove 310, and the second film layer 03b can be removed in the first via region to form a first via 320 penetrating the first film layer 03a and the second film layer 03b.

[0163] In these optional embodiments, the first segment and the second segment of the first via 320 are formed in steps S03 and S05, respectively, and the first groove 310 is prepared simultaneously when the second segment is formed in step S05, which can simplify the fabrication process of the array substrate and improve the fabrication efficiency of the array substrate.

[0164] In these alternative embodiments, the first film layer 03a may also include the first sublayer described above and a second sublayer 03a2 located on the side of the first sublayer 03a1 facing the substrate 01.

[0165] Optionally, as described above, the array substrate further includes a connection portion 05, such as... Figures 9 to 20 As shown, when the connecting part 05 is located in the first metal layer 02, in step S05, a first groove 310 is formed in the first groove area, and the remaining part of the first insulating layer to be etched is removed in the first via area to form a first via 320, so that the connecting part 05 can be exposed through the first via 320. Subsequently, when metal material is deposited on the first insulating layer to be etched to form a second metal layer 04, at least part of the metal material can fall into the first via 320 and connect with the connecting part 05.

[0166] In other embodiments, such as Figure 21As shown, when the array substrate includes the aforementioned first conductive layer 06 and second insulating layer 07, the first conductive layer 06 is located on the side of the first metal layer 02 facing the substrate 01, the first conductive layer 06 has a connection portion 05 located in the first via region, and the second insulating layer 07 is located between the first conductive layer 06 and the first metal layer 02, step S05 further includes: removing the second insulating layer 07 in the first via region to form a second via 710 penetrating the second insulating layer 07, so that the connection portion 05 can be exposed through the first via 320 and the second via 710. This facilitates the interconnection between the signal line 420 and the connection portion 05.

[0167] The embodiments described above are not exhaustive, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that, include: Substrate; A first metal layer is located on one side of the substrate, and the first metal layer includes a first capacitor plate and a connecting portion; A first insulating layer is located on the side of the first metal layer facing away from the substrate. The first insulating layer comprises at least two layers. The first insulating layer includes a first groove and a first via. The first groove is formed by a recess in the surface of the first insulating layer facing away from the first metal layer. The first via penetrates the first insulating layer. The orthographic projection of the first groove on the substrate at least partially overlaps with the orthographic projection of the first capacitor plate on the substrate. The orthographic projection of the first via on the substrate and the orthographic projection of the first capacitor plate on the substrate are misaligned. The first insulating layer includes at least a first film layer and a second film layer located on the first film layer facing the first metal layer. The first groove penetrates the first film layer or partially penetrates the first film layer. The first via includes a first segment penetrating the first film layer and a second segment penetrating at least partially the second film layer. The orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the connecting portion on the substrate. A second metal layer is located on the side of the first insulating layer opposite to the first metal layer. The second metal layer includes a second capacitor plate and signal lines. At least a portion of the second capacitor plate is located within the first groove, and at least a portion of the signal lines are electrically connected to the connection via through the first via. The etching time of the second segment is the same as the etching time of the first groove. The first groove penetrates the first film layer, and the first film layer and the second film layer satisfy the following formula (1): H1 / V1=H2 / V2(1) Wherein, H1 is the depth of the first groove, V1 represents the etching rate of the first film layer, H2 is the thickness of the second film layer, and V2 represents the etching rate of the second film layer; The first film layer includes a first sublayer and a second sublayer located on the side of the first sublayer facing the substrate. The first groove extends through the first sublayer, and the bottom wall of the first groove is the surface of the second sublayer facing away from the second film layer. The materials of the second film layer and the first sublayer include silicon oxide, and the material of the second sublayer includes silicon nitride.

2. The array substrate according to claim 1, characterized in that, The second film layer and the first sublayer satisfy the following formula (3) or (4): H 11 / V 11 =H2 / V2(3) H 11 / V 11 = H 12 / V 12 +H2 / V2(4) Among them, H 11 V represents the thickness of the first sublayer. 11 H represents the etching rate of the first sub-layer. 12 V represents the thickness of the second sublayer. 12 H2 represents the etching rate of the second sublayer, H2 is the thickness of the second film layer, and V2 represents the etching rate of the second film layer.

3. An array substrate, characterized in that, include: Substrate; A first metal layer is located on one side of the substrate, and the first metal layer includes a first capacitor plate; A first insulating layer is located on the side of the first metal layer facing away from the substrate. The first insulating layer comprises at least two layers. The first insulating layer includes a first groove and a first via. The first groove is formed by a recess in the surface of the first insulating layer facing away from the first metal layer. The first via penetrates the first insulating layer. The orthographic projection of the first groove on the substrate at least partially overlaps with the orthographic projection of the first capacitor plate on the substrate. The orthographic projection of the first via on the substrate and the orthographic projection of the first capacitor plate on the substrate are misaligned. The first insulating layer includes at least a first film layer and a second film layer located on the first film layer facing the first metal layer. The first via includes a first segment penetrating the first film layer and a second segment penetrating at least a portion of the second film layer. The second metal layer is located on the side of the first insulating layer opposite to the first metal layer, and the second metal layer includes a second capacitor plate. A first conductive layer is located on the side of the first metal layer facing the substrate, and a connection portion is disposed on the first conductive layer. The orthographic projection of the first via on the substrate and the orthographic projection of the connection portion on the substrate at least partially overlap. A second insulating layer is located between the first conductive layer and the first metal layer. The second insulating layer further includes a second via communicating with the first via. The second via is disposed through the second insulating layer, and the orthographic projection of the second via on the substrate and the orthographic projection of the connection portion on the substrate at least partially overlap. The second metal layer further includes signal lines, at least a portion of which are electrically connected to the connection via through the first via and the second via. The etching time of the first groove is equal to the sum of the etching times of the second segment and the second via. The first film layer includes a first sublayer and a second sublayer located on the side of the first sublayer facing the substrate. The first groove penetrates the first sublayer, and the bottom wall of the first groove is located in the second sublayer. The thickness of the second film layer is greater than the thickness of the first sublayer. The etching rate of the second sublayer is greater than the etching rate of the first sublayer. The second film layer, the first sublayer, and the second insulating layer satisfy the following formula (6): H 11 / V 11 =H2 / V 2+ H3 / V3 (6) Among them, H 11 V represents the thickness of the first sublayer. 11 H2 represents the etching rate of the first sublayer, H2 represents the thickness of the second film layer, V2 represents the etching rate of the second film layer, H3 represents the thickness of the second insulating layer, and V3 represents the etching rate of the second insulating layer.

4. The array substrate according to claim 3, characterized in that, The first conductive layer is a semiconductor layer, and the semiconductor layer further includes a semiconductor portion; the second insulating layer is an inter-gate insulating layer.

5. The array substrate according to claim 3 or 4, characterized in that, The first sublayer and the second sublayer are made of different materials.

6. The array substrate according to claim 5, characterized in that, The first sublayer and the second film layer are made of the same material.

7. The array substrate according to claim 5, characterized in that, The etching rate of the second sublayer is greater than that of the first sublayer.

8. The array substrate according to claim 5, characterized in that, The materials of the second film layer and the first sublayer include silicon oxide, and the material of the second sublayer includes silicon nitride; or, the materials of the second film layer and the first sublayer include silicon nitride, and the material of the second sublayer includes silicon oxide.

9. The array substrate according to claim 5, characterized in that, The thickness of the second film layer is greater than the thickness of the first sublayer.

10. A method for fabricating an array substrate, characterized in that, include: A substrate to be etched is provided, the substrate to be etched includes a substrate and a first metal layer and a first insulating layer to be etched sequentially disposed on one side of the substrate. The first metal layer includes a first capacitor plate. The first insulating layer to be etched has a first groove region and a first via region. The orthographic projection of the first capacitor plate on the substrate and the orthographic projection of the first groove region on the substrate at least partially overlap. A photoresist layer is disposed on the surface of the first insulating layer to be etched away from the first metal layer, and the photoresist layer is patterned to form a first etching groove and a second etching groove. The first etching groove is located in the first groove area and is formed by the recess of the photoresist layer away from the first insulating layer to be etched. The second etching groove is located in the first via area and is disposed through the photoresist layer. The substrate to be etched with the photoresist layer is subjected to a first etching process to remove at least a portion of the thickness of the first insulating layer to be etched in the first via region. The photoresist layer is thinned so that it penetrates the first etching trench; A second etching process is performed on the substrate to be etched, with the photoresist layer, to form an array substrate including a first insulating layer. The first insulating layer includes a first groove located in the first groove region and a first via located in the first via region. The first groove is formed by a recess in the surface of the first insulating layer away from the first metal layer, and the first via penetrates the first insulating layer. The first insulating layer to be etched includes a first film layer and a second film layer located on the first film layer facing the first metal layer. In the first etching process of the substrate to be etched with the photoresist layer, a first film layer with a thickness of n1*H1 is removed in the first via area, where n1 is a coefficient greater than 0 and less than 1, and H1 is the thickness value of the first film layer. In the step of performing a second etching process on the substrate to be etched with the photoresist layer, at least a portion of the first film layer is removed in the first groove region to form the first groove, and a first film layer and a second film layer with a thickness of (1-n1)*H1 are removed in the first via region to form the first via through the first film layer and the second film layer.

11. The method according to claim 10, characterized in that, The first film layer includes a first sublayer and a second sublayer located on the side of the first sublayer facing the substrate, and the thickness of the first sublayer is n1*H1; In the step of performing the first etching process on the substrate to be etched with the photoresist layer, the first sub-layer is removed in the first via area; In the step of performing a second etching process on the substrate to be etched with the photoresist layer, part or all of the first sublayer is removed in the first groove region, or the first sublayer and at least part of the second sublayer are removed in the first groove region to form the first groove; the second sublayer and the second film layer are removed in the first via region to form the first via layer penetrating the first film layer and the second film layer.

12. The method according to claim 10, characterized in that, The substrate to be etched further includes a first conductive layer and a second insulating layer. The first conductive layer is located on the side of the first metal layer facing the substrate, and the first conductive layer has a connection portion located in the first via region. The second insulating layer is located between the first conductive layer and the first metal layer. The step of performing a second etching process on the substrate to be etched with the photoresist layer further includes: removing the second insulating layer in the first via region to form a second via penetrating the second insulating layer.

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