Semiconductor device and method of forming the same and integrated circuit structure

Abstract

A semiconductor device, its formation method, and integrated circuit structure are disclosed. The semiconductor device includes a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The plurality of 2D semiconductor nanostructures extend over a substrate in a first direction and are disposed in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the plurality of 2D semiconductor nanostructures. The source region and the drain region are located on opposite sides of the gate structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to transistors having two-dimensional semiconductor materials. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements on the substrate.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] In some embodiments, a semiconductor device includes a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The plurality of 2D semiconductor nanostructures extend over a substrate in a first direction and are arranged in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the plurality of 2D semiconductor nanostructures. The source region and the drain region are located on opposite sides of the gate structure.

[0005] In some embodiments, an IC structure includes an n-type field-effect transistor (NFET) and a p-type field-effect transistor (PFET). The NFET and PFET are located above a substrate. The NFET includes a plurality of NFET semiconductor nanostructures arranged spaced above each other, an NFET gate structure surrounding each of the plurality of NFET semiconductor nanostructures, and n-type source / drain regions on opposite sides of the NFET gate structure. The PFET includes a plurality of PFET semiconductor nanostructures disposed spaced above each other, a PFET gate structure surrounding each of the plurality of PFET semiconductor nanostructures, and p-type source / drain regions on opposite sides of the PFET gate structure. The plurality of n-type source / drain regions are formed of a metal having a band-edge work function adjacent to a conduction band of a 2D semiconductor material of the plurality of NFET semiconductor nanostructures.

[0006] In some embodiments, a method of forming a semiconductor device includes: forming a fin over a substrate, the fin including alternately stacked sacrificial semiconductor layers and 2D semiconductor layers; forming a dummy gate structure over the fin and forming a gate spacer on either side of the dummy gate structure; removing the dummy gate structure to form a gate trench over the fin; removing first portions of the plurality of sacrificial semiconductor layers in the gate trench such that the 2D semiconductor layers are suspended in the gate trench; and after removing the plurality of first portions of the plurality of sacrificial semiconductor layers, forming a gate structure surrounding the plurality of 2D semiconductor layers. Attached Figure Description

[0007] The features disclosed herein are best understood when read in conjunction with the accompanying drawings from the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of explanation.

[0008] Figure 1A , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 8C , Figure 9B , Figure 10B , Figure 11B and Figure 12B This is a cross-sectional view of an intermediate stage in the manufacture of a GAA apparatus according to some embodiments of the present disclosure, wherein each of the cross-sectional views is a cross-sectional view obtained by combining a first cross-section along the current direction between the source / drain regions of an n-type transistor and a cross-sectional view obtained by a second cross-section along the current direction between the source / drain regions of a p-type transistor.

[0009] Figure 1B The figure shows a schematic diagram of a single layer of an exemplary TMD according to some embodiments of the present disclosure;

[0010] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A This is a perspective view of an intermediate stage in a manufacturing apparatus for GAA according to some embodiments of the present disclosure;

[0011] Figure 9C and Figure 10CThis is a cross-sectional view of an intermediate stage in the manufacture of a GAA apparatus according to some embodiments of the present disclosure, wherein each of the cross-sectional views is a combination of a cross-sectional view obtainable from a third section along the longitudinal axis of the gate structure of an n-type transistor and a cross-sectional view obtainable from a fourth section along the longitudinal axis of the gate structure of a p-type transistor.

[0012] Figure 11C The illustration shows an example energy band diagram of a Schottky contact for an NFET having a TMD nanosheet, according to some embodiments of this disclosure.

[0013] Figure 12C The illustration shows an example energy band diagram of a Schottky contact for a PFET having TM nanosheets according to some embodiments of this disclosure.

[0014] Figure 13 This is a cross-sectional view of a GAA device according to some embodiments of this disclosure;

[0015] Figure 14 This is a cross-sectional view of a GAA device according to some embodiments of the present disclosure.

[0016] [Symbol Explanation]

[0017] 100: Substrate

[0018] 100N: n-type device area

[0019] 100P: p-type device area

[0020] 102: Etching stop layer

[0021] 110: Multi-layer stacking

[0022] 112: Sacrificial Semiconductor Layer

[0023] 112A~112C: Sacrificial semiconductor layer

[0024] 114: First dielectric layer

[0025] 114A~114C: First dielectric layer

[0026] 116: 2D semiconductor layer

[0027] 116A~116C: 2D semiconductor layer

[0028] 117: Single layer

[0029] 117M: Transition metal atom

[0030] 117X: Chalcogenide atom

[0031] 118: Second dielectric layer

[0032] 118A~118C: Second dielectric layer

[0033] 120: Fins

[0034] 122: Sacrificial Semiconductor Layer

[0035] 122A~122C: Sacrificial Semiconductor Nanosheets

[0036] 124: First Dielectric Nanosheet

[0037] 124A~124C: First dielectric nanosheet

[0038] 126: 2D semiconductor nanosheets

[0039] 126A~126C: 2D semiconductor nanosheets

[0040] 128: Second dielectric nanosheet

[0041] 128A~128C: Second dielectric nanosheet

[0042] 130: Dummy gate structure

[0043] 140: Gate spacer

[0044] 152: First source / drain cap layer

[0045] 154: Second source / drain cap layer

[0046] 160: Gate trench

[0047] 170: Internal spacers

[0048] 180: Interface Layer

[0049] 182: Gate dielectric layer

[0050] 190: Replacement gate structure

[0051] 192: Work function metal layer

[0052] 194: Filler metal

[0053] 200: Gate hard mask

[0054] 210: n-type metal source region

[0055] 210N: n-type metal source / drain region

[0056] 210P: p-type metal source / drain region

[0057] 212N: Protruding part

[0058] 212P: Highlighted Section

[0059] 216: 2D semiconductor nanosheets

[0060] 1262: Source / Drain Extension Region

[0061] 1264: Passage Area

[0062] P1: Photoresist layer

[0063] D1: First horizontal direction

[0064] D2: Second horizontal direction

[0065] D3: vertical direction

[0066] e: electron

[0067] h: Electric hole Detailed Implementation

[0068] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely exemplary and not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the disclosure in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0069] Additionally, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein are interpreted accordingly. As used herein, “approximately,” “about,” “roughly,” or “generally” may mean within 20%, 10%, or 5% of a given value or range. The quantities given herein are approximate values, thus meaning that the terms “approximately,” “about,” “roughly,” or “generally” can be inferred unless explicitly stated. However, those skilled in the art will recognize that the values ​​or ranges described throughout the description are merely exemplary and may decrease as integrated circuits shrink.

[0070] Gate-all-around (GAA) transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more optical lithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine optical lithography and self-alignment processes to allow patterns to be generated that have, for example, smaller spacing compared to patterns otherwise obtainable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0071] This disclosure is generally related to integrated circuit (IC) structures and methods of forming such ICs, and more specifically to the fabrication of gate-all-around (GAA) transistors formed using two-dimensional (2D) semiconductor materials as their channels. It should also be noted that this disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include transistors with gate structures formed on at least two sides of a channel region. Such multi-gate devices may include p-type metal-oxide-semiconductor (MOS) devices and / or n-type MOS devices. Specific examples may be presented and, due to their fin-like structure, are referred to herein as FinFETs. Furthermore, embodiments of multi-gate transistors presented herein are of one type and are referred to herein as gate-all-around (GAA) devices. GAA devices include any device having gate structures or portions thereof formed on four sides of a channel region (e.g., surrounding a portion of the channel region). Devices presented herein also include embodiments having channel regions configured as nanosheet channels, nanowire channels, and / or other suitable channel configurations. The embodiments presented herein are of devices that may have one or more channel regions (e.g., nanosheets) associated with a single continuous gate structure. However, those skilled in the art will recognize that the teachings can be applied to a single channel (e.g., a single nanosheet) or any number of channels. Those skilled in the art will recognize other examples of semiconductor devices that may benefit from the state of this disclosure.

[0072] As the fin width in fin field-effect transistors (FinFETs) decreases, variations in channel width can lead to mobility losses. GAA transistors, such as nanosheet transistors, are being investigated as alternatives to fin FETs. In GAA transistors, the transistor gate is fabricated around multiple channels (e.g., nanosheet channels or nanowire channels), such that each channel is surrounded or encapsulated by the gate. Such transistors offer the advantage of improved electrostatic control of the channels by the gate, which also reduces leakage current. GAA channels are typically formed from silicon (Si). However, reducing the thickness of Si channels results in increased defective channel interfaces, leading to a degradation in channel mobility. Therefore, this disclosure provides GAA transistors formed using 2D semiconductor materials as channels in various embodiments. An advantageous feature of 2D semiconductor materials is their width, ranging from approximately 50 to 1000 cm⁻¹. 2High electron mobility in the range of / V-seconds or even higher. It should be understood that silicon can exhibit significantly degraded mobility when formed at low thicknesses comparable to the thickness of a 2D semiconductor film (e.g., about 3 nm or less). Therefore, the 2D semiconductor channel thickness is reduced compared to the case where silicon has a lower impact on carrier mobility, which in turn achieves satisfactory GAA channel mobility at channel thicknesses of only a few nanometers (e.g., less than 3 nm).

[0073] Figures 1A to 12C The figures illustrate perspective and cross-sectional views of intermediate stages in forming an IC structure having a multi-gate device according to some embodiments of the present disclosure. As used herein, the term "multi-gate device" describes a device (e.g., a semiconductor transistor) having at least one gate material disposed on multiple sides of at least one channel of the device. In some examples, a multi-gate device may be referred to as a GAA device or a nanosheet device having gate material disposed on at least four sides of at least one channel of the device. The channel region may be referred to as a "nanowire," which, as used herein, includes channel regions having various geometries (e.g., cylindrical, rod-shaped) and various sizes.

[0074] Figure 1A , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 8C , Figure 9B , Figure 10B , Figure 11B and Figure 12B This is a cross-sectional view of an intermediate stage in the manufacture of a GAA device according to some embodiments of this disclosure, wherein each of the cross-sectional views combines a first section along the current direction between the source / drain regions of the n-type transistor (e.g., Figure 3A A cross-sectional view obtained from section X1-X1 in the middle and a second cross-section along the current direction between the source / drain regions of the p-type transistor (e.g., Figure 3A The cross-sectional view obtained from section X2-X2 in the middle. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A This is a perspective view of an intermediate stage in a manufacturing apparatus for GAA according to some embodiments of the present disclosure. Figure 9C and Figure 10CThis is a cross-sectional view of an intermediate stage in the manufacturing apparatus for a GAA according to some embodiments of this disclosure, wherein each of the cross-sectional views is combined from a third cross-section (e.g., Figure 3A The cross-sectional view that can be obtained from the section Y1-Y1 in the middle and from the fourth section (e.g., Figure 3A The cross-sectional view obtained by the cross-section Y2-Y2 in the figure, the third cross-section is along the longitudinal direction of the gate structure of the n-type transistor and is in the direction perpendicular to the current direction between the source and drain regions of the n-type transistor, and the fourth cross-section is along the longitudinal direction of the gate structure of the p-type transistor and is in the direction perpendicular to the current direction between the source and drain regions of the N-type transistor.

[0075] exist Figure 1A In this embodiment, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., by p-type or n-type dopant) or undoped. The substrate 100 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0076] The substrate 100 has an n-type device region 100N and a p-type device region 100P. The n-type device region 100N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type GAA FET; and the p-type device region 100P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type GAA FET. The n-type device region 100N can be physically separated from the p-type device region 100P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type device region 100N and the p-type device region 100P. Although one n-type device region 100N and one p-type device region 100P are illustrated, any number of n-type device regions 100N and p-type device regions 100P can be provided.

[0077] In addition, Figure 1AIn this process, an etch stop layer 102 is formed on a substrate 100, and then a multilayer stack 110 is formed on the substrate 100. In some embodiments, the etch stop layer 102 may be formed from silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials using techniques such as thermal oxidation, or deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The etch stop layer 102 serves to protect the substrate 100 from subsequent etch steps, such as etch steps in dummy gate formation and / or etch steps in source / drain region formation. In some embodiments, for example, the etch stop layer 102 has a thickness ranging from about 10 nm to about 100 nm.

[0078] Once the etch stop layer 102 has been formed, the multilayer stack 110 is then formed on top of it. The multilayer stack 110 includes alternating layers of the following: sacrificial semiconductor layers 112A to 112C (collectively referred to as sacrificial semiconductor layer 112), first dielectric layers 114A to 114C (collectively referred to as first dielectric layer 114), 2D semiconductor layers 116A to 116C (collectively referred to as 2D semiconductor layer 116), and second dielectric layers 118A to 118C (collectively referred to as second dielectric layer 118). For illustrative purposes and as discussed in more detail below, the sacrificial semiconductor layer 112 will be removed, and the 2D semiconductor layer 116 will be patterned to form channel regions for the GAA FET in both the n-type device region 100N and the p-type device region 100P.

[0079] Schematic, the multilayer stack 110 is illustrated as three layers including each of a sacrificial semiconductor layer 112, a first dielectric layer 114, a 2D semiconductor layer 116, and a second dielectric layer 118. In some embodiments, the multilayer stack 110 may include any number of sacrificial semiconductor layers 112, first dielectric layers 114, 2D semiconductor layers 116, and second dielectric layers 118. Each of the sacrificial semiconductor layers 112 in the multilayer stack 110 is an undoped polysilicon layer. Each of the sacrificial semiconductor layers contains any suitable thickness. In this embodiment, each of the sacrificial semiconductor layers 112 contains a thickness in the range of about 16 nm to about 20 nm. Each of the sacrificial semiconductor layers 112 may use silane (SiH4), ethylene alkyl (Si2H6), acrylane (Si3H8), or dichlorosilane (SiH2C). 12The silicon source gas is deposited by techniques such as physical vapor deposition (PVD), CVD, sputtering deposition, or other methods. In some embodiments, the sacrificial semiconductor layer 112 may comprise polycrystalline silicon having carbon-hydrogen bonds (e.g., CH3) formed by a precursor gas (e.g., dichlorosilane containing carbon and hydrogen). The carbon-hydrogen bonds can reduce the etch resistance of the sacrificial semiconductor layer 112 and thus increase the etch rate of the sacrificial semiconductor layer 112 in subsequent etch steps after its removal.

[0080] After each of the sacrificial semiconductor layers 112 is deposited, a first dielectric layer 114 is then deposited on each of the sacrificial semiconductor layers 112. In some embodiments, the sacrificial dielectric layer 114 may be an oxide, such as silicon oxide (SiO2), a high-k metal oxide (e.g., Al2O3), a nitride (e.g., SiN), silicon oxynitride (SiON), the like, or a combination thereof, and may be formed by furnace oxidation, CVD, ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other dielectric materials formed by any acceptable process may be used. In some embodiments, an RCA cleaning process (e.g., using hydrogen peroxide, ammonium hydroxide, and water (H2O2 + NH4OH + H2O)) is performed on each of the sacrificial semiconductor layers 112 as needed before the material for depositing the first dielectric layer 114.

[0081] After each of the first dielectric layers 114 is deposited, a 2D semiconductor layer 116 is then formed on each of the first dielectric layers 114. 2D semiconductor materials typically exist as a stack of several thick layers, forming strong bonds with weak interlayer van der Waals forces, allowing the layers to be mechanically or chemically exfoliated into individual atomic thin layers. 2D semiconductor materials are promising candidates for channel, source, and drain materials in transistors. Examples of 2D semiconductor materials include transition metal dichalcogenides (TMDs), graphene, layered III–VI group chalcogenides, hexagonal boron nitride (h-BN), black phosphorus, or the like. In some embodiments, the 2D semiconductor may comprise one or more layers and may have a thickness in the range of about 0.5 to 100 nm. A less layered 2D semiconductor has the advantage of a thickness in the range of about 50 to 1000 cm⁻¹. 2 High electron mobility values ​​in the range of / V-second or even higher. It should be understood that bulk silicon can have significantly degraded mobility when cut to a low thickness (e.g., about 3 nm) comparable to the thickness of a 2D material film.

[0082] In some embodiments, each of the 2D semiconductor layers 116 is a transition metal dichalcogenide (TMD) having the formula MX2, where M is a transition metal element such as titanium, vanadium, cobalt, nickel, zirconium, molybdenum, technetium, rhodium, palladium, hafnium, tantalum, tungsten, rhenium, iridium, platinum, and X is a chalcogenide such as sulfur, selenium, or tellurium. Examples of dichalcogenide materials suitable for use in the 2D semiconductor layer 202 include WS2, MoS2, WSe2, MoSe2, MoTe2, WTe2, similar materials, or combinations thereof. However, any suitable transition metal dichalcogenide material may be used alternatively. Once formed, the transition metal dichalcogenide material is a layered structure of multiple two-dimensional layers having the general formula XMX, wherein the chalcogenide atoms in the two planes are separated by the metal atom planes.

[0083] Each of the 2D semiconductor layers 116 may be a single layer or may include several single layers. Figure 1B The figure shows a schematic diagram of a single layer 117 of an exemplary TMD according to some exemplary embodiments of this disclosure. Figure 1B In this TMD material layer, one molecule thick, comprises transition metal atoms 117M and chalcogenide atoms 117X. The transition metal atoms 117M can form a layer in the middle region of the one-molecule-thick TMD material layer, and the chalcogenide atoms 117X can form a first layer above the layer of transition metal atoms 117M, and a second layer underlying the layer of transition metal atoms 117M. The transition metal atoms 117M can be W or Mo atoms, while the chalcogenide atoms 117X can be S, Se, or Te atoms. X in Figure 1B In this example, each of the transition metal atoms 117M is bonded (e.g., by covalent bonds) to six chalcogenide atoms 117X, and each of the chalcogenide atoms 117X is bonded (e.g., by covalent bonds) to three transition metal atoms 117M. Throughout the description, the illustrated cross-linked layers comprising one layer of transition metal atoms 117M and two layers of chalcogenide atoms 117X are collectively referred to as a monolayer 117 of the TMD.

[0084] In some embodiments, the 2D semiconductor layer 116 is formed from WS2 using an inductively-coupled-plasma (ICP) CVD process with WF6 and H2S as precursors. For example, the WS2 layer 116 can be deposited on individual dielectric layers 114 (e.g., SiO2) at a temperature between about 600°C and about 700°C (e.g., about 550°C) using a sulfur-containing gas (e.g., H2S gas) and a plasma generated from a tungsten-containing gas (e.g., WF6). In some embodiments, the WS2 layer 116 can be deposited to have a thickness in the range of about 0.5 nm to about 10 nm (e.g., about 2 nm). Process conditions are controlled to achieve the desired total amount of monolayer 117 in the WS2 layer. In some embodiments, a plasma treatment using a fluorine-based plasma can be performed on each of the first dielectric layers 114 prior to the deposition of the 2D semiconductor layer 116 to facilitate subsequent 2D semiconductor material deposition.

[0085] In some other embodiments, each of the 2D semiconductor layers 116 is formed using an exfoliation and tapering method. For example, the 2D semiconductor layer can be grown on another crystalline substrate using a suitable deposition technique, and then transferred onto the first dielectric layer 114. For example, the 2D semiconductor layer grown on the crystalline substrate can be covered with a protective film (e.g., PMMA) and thermal release tape, and then the 2D semiconductor layer is mechanically or chemically peeled off from the crystalline substrate and then transferred onto the first dielectric layer 114. The thermal release tape can then be removed, for example, by baking, causing the thermal release tape to lose its adhesiveness. The protective film can then be removed by etching or decomposition. After the protective film is removed, the 2D semiconductor layer 116 remains on the first dielectric layer 114 and is ready for deposition on the second dielectric layer 118.

[0086] After each of the 2D semiconductor layers 116 is deposited, a second dielectric layer 118 is then deposited on each of the 2D semiconductor layers 116. In some embodiments, the second dielectric layer 118 may be an oxide, such as silicon oxide (SiO2), a high-k metal oxide (e.g., Al2O3), a nitride (e.g., SiN), silicon oxynitride (SiON), the like, or combinations thereof, and may be formed by CVD, ALD, the like, or combinations thereof. Other dielectric materials formed by any acceptable process may be used. In some embodiments, the second dielectric layer 118 has the same material as the first dielectric layer 114. In some embodiments, the first dielectric layer 114 and the second dielectric layer 118 have different materials. Because 2D semiconductor materials have lower bonding strength compared to dielectric materials such as oxides and / or nitrides, the 2D semiconductor material is used in subsequent channel release steps (e.g., when the first dielectric layer 114 and the second dielectric layer 118 are neglected). Figure 6A and Figure 6B (As illustrated in the figure) During this period, it may be more susceptible to damage and / or oxidation. Therefore, the first dielectric layer 114 and the second dielectric layer 118 can function to protect the 2D semiconductor layer 116 from unwanted damage and / or oxidation during the channel release step.

[0087] The sacrificial semiconductor layer 112 has high etch selectivity with respect to the 2D semiconductor layer 116 and dielectric layers 114, 118. Therefore, the sacrificial semiconductor layer 112 can be removed without significantly etching the 2D semiconductor layer 116, thereby allowing the 2D semiconductor layer 116 to serve as the channel region for both n-type and p-type GAA FETs.

[0088] See now Figure 2A and Figure 2BAccording to some embodiments, fins 120 are formed in the multilayer stack 110 by etching trenches in the multilayer stack 110. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or similar combinations thereof. The etch stop layer 102 exhibits higher etch resistance to the etching process compared to the bottommost sacrificial semiconductor layer 112A, and therefore exhibits a lower etch rate compared to the overlying sacrificial semiconductor layer 112A. In this way, the etch stop layer 102 can act as a detectable etch end point, and thus the etching process can terminate at the etch stop layer 102. The etching can be anisotropic. The fins 120 formed by etching the multilayer stack 110 further define sacrificial semiconductor nanosheets 122A to 122C (collectively referred to as sacrificial semiconductor layer 122) from sacrificial semiconductor layer 112, first dielectric nanosheets 124A to 124C (collectively referred to as first dielectric nanosheets 124) from first dielectric layer 114, 2D semiconductor nanosheets 126A-C (collectively referred to as 2D semiconductor nanosheets 126) from 2D semiconductor layer 116, and second dielectric nanosheets 128A to 128C (collectively referred to as second dielectric nanosheets 128) from second dielectric layer 118. In some embodiments, the nanosheets are interchangeably referred to as nanostructures.

[0089] The fin 120 can be patterned by any suitable method. For example, the fin 120 can be patterned using one or more optical lithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine optical lithography and self-alignment processes to allow patterns to be generated that have, for example, smaller spacing compared to patterns otherwise obtainable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 120.

[0090] Figures 2A to 2BFor illustrative purposes, the fins 120 in the n-type device region 100N and the p-type device region 100P are shown to have substantially equal widths. In some embodiments, the width of the fins 120 in the n-type device region 100N may be larger or smaller than that in the p-type device region 100P. Furthermore, although each of the fins 120 is illustrated to always have a consistent width, in other embodiments, the fins 120 may have tapered sidewalls such that the width of each of the fins 120 continuously increases in the direction toward the substrate 100. In such embodiments, each of the nanostructures 122 to 128 may have different widths and be trapezoidal in shape.

[0091] exist Figure 3A and Figure 3B In this embodiment, a dummy gate structure 130 is formed over fins 120 in n-type device regions 100N and p-type device regions 100P. Material for the dummy gate structure 130 may be deposited over fins 120 and subsequently planarized, for example, by CMP. The material for the dummy gate structure 130 may be conductive or non-conductive and may be selected from the group consisting of amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, metal nitrides, metal silicides, metal oxides, and metals. The material for the dummy gate structure 130 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. In some embodiments, a dummy gate dielectric layer is deposited on fins 120 prior to the deposition of the dummy gate material. In some embodiments, the dummy gate structure 130 is doped polycrystalline silicon having n-type or p-type dopant. Because the dummy gate structure 130 is doped polysilicon and the sacrificial semiconductor layer 122 is undoped polysilicon, the dummy gate structure 130 can have different etch selectivity and therefore different etch rates in the subsequent dummy gate removal step.

[0092] Subsequently, the material of the dummy gate structure 130 (and, where present, the dummy gate dielectric) is patterned using acceptable optical lithography and etching techniques to form a discrete dummy gate structure 130. The etch stop layer 102 exhibits higher etch resistance to the etching process compared to the dummy gate structure 130, and therefore exhibits a lower etch rate compared to the dummy gate structure 130. In this way, the etch stop layer 102 can serve as a detectable etch end point, and thus the etching process can be terminated at the etch stop layer 102. The dummy gate structure 130 covers individual channel regions of the fin 120. The dummy gate structure 130 may also have a longitudinal direction generally perpendicular to the longitudinal direction of the individual fin 120.

[0093] Figure 3A and Figure 3B The diagram also illustrates the formation of the gate spacer 140. In some embodiments, a spacer material layer is deposited on a substrate. The spacer material layer may be a conformal layer subsequently etched back to form the gate sidewall spacer 140. In the illustrated embodiment, the spacer material layer is conformally disposed on the top and sidewalls of the dummy gate structure 130. The spacer material layer may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. The spacer material layer may be formed by depositing the dielectric material onto the gate structure 130 using processes such as CVD, subatmospheric CVD (SACVD), flow CVD, ALD, PVD, or other suitable processes. An isotropic etching is then performed on the deposited spacer material layer to expose several portions of the fin 120 not covered by the dummy gate structure 130 (e.g., in the source / drain regions of the fin 120). The portion of the spacer material layer directly above the dummy gate structure 130 can be completely removed by this anisotropic etching process. For simplicity, several portions of the spacer material layer on the sidewalls of the dummy gate structure 130 may remain, thereby forming the gate sidewall spacer designated as gate spacer 140.

[0094] exist Figure 4A and Figure 4BIn this configuration, a first source / drain cap layer 152 is formed above the source / drain region of the fin 120, and a second source / drain cap layer 154 is subsequently formed above the first source / drain cap layer 152. The first source / drain cap layer 152 and the second source / drain cap layer 154 comprise dielectric materials deposited using CVD, flow CVD, ALD, or other suitable processes, such as silicon oxide, silicon nitride, silicon oxynitride, SiCN, silicon oxycarbide, or other suitable dielectric materials. An etching process is then performed to etch back the second source / drain cap layer 154 below the top surface of the dummy gate structure 130. In some embodiments, the gate spacer 140 is also etched back by this etching step to become below the dummy gate structure 130. In some embodiments, the second source / drain cap layer 154 is formed of a material different from that of the first source / drain cap layer 152 to provide etch selectivity. In some embodiments, the second source / drain cap layer 154 is formed of the same material as the gate spacer 140. For example, both the gate spacer 140 and the second source / drain cap layer 154 are nitride-based materials (e.g., SiN, SiON, or similar), and the first source / drain cap layer 152 is an oxide material (e.g., SiO2, Al2O3, or similar).

[0095] exist Figure 5A and Figure 5B In this process, the dummy gate structure 130 (and, where present, the dummy gate dielectric) is removed in one or more etching steps, such that a gate trench 160 is formed between corresponding gate spacers 140. In some embodiments, the dummy gate structure 130 is removed by anisotropic dry or wet etching processes. For example, the etching process may include a dry etching process using reactive gases that selectively etch the dummy gate structure 130 at a rate faster than that of the gate spacers 140, the second source / drain cap layer 154, and the second dielectric nanosheet 128. Furthermore, the directionality of the anisotropic etching is controlled to allow a significant etching rate in the vertical direction but no or negligible etching rate in the lateral or horizontal directions. In this way, the dummy gate removal etching step may not result in loss or negligible loss of the sacrificial semiconductor nanosheet 122, the 2D semiconductor nanosheet 126, and the first dielectric sheet 124 and the second dielectric nanosheet 128. Furthermore, in some embodiments, the sacrificial semiconductor layer 122 exhibits etch selectivity with respect to the dummy gate structure 130 because the dummy gate structure 130 is doped polysilicon, while the sacrificial semiconductor 122 is undoped polysilicon. This etch selectivity further aids in keeping the polycrystalline nanosheet 122 intact during the dummy gate removal step.

[0096] Each gate trench 160 exposes and / or covers a portion of a 2D semiconductor nanosheet 126, which serves as a channel region for subsequent completion of the GAA-FET. The 2D semiconductor nanosheets 126 serving as channel regions are disposed between adjacent pairs of first source / drain cap layers 152. In some embodiments, the etch stop layer 102 has higher etch resistance than the dummy gate structure 130, and therefore exhibits a lower etch rate than the dummy gate structure 130. In this way, the etch stop layer 102 can serve as a detectable etch end point, and therefore the etch process can be terminated at the etch stop layer 102.

[0097] exist Figure 6A and Figure 6B In this process, several portions of the sacrificial semiconductor nanosheet 122 in the gate trench 160 are removed using an etchant by an isotropic etching process such as wet etching or similar, where the etchant is selective for the material of the sacrificial semiconductor nanosheet 122. In contrast, the sacrificial semiconductor nanosheet 122 in the gate trench 160 is removed using a selective etching process, thus forming a space (also called a sheet-to-sheet space) between the 2D semiconductor nanosheets 126. This selective etching process etches the sacrificial semiconductor nanosheet 122 at a faster etch rate than etching the first dielectric nanosheet 124, the second dielectric nanosheet 128, and the 2D semiconductor nanosheet 126. This step can be referred to as a channel release process. During this temporary processing step, the space between the 2D semiconductor nanosheets 126 can be filled with an ambient gas (e.g., air, nitrogen, etc.). In some embodiments where the sacrificial semiconductor nanosheet 122 is polycrystalline silicon, the sacrificial semiconductor nanosheet 122 can be removed using a selective wet etching process that uses a hydroxide-containing solution (e.g., ammonium hydroxide), deionized water, and / or other suitable solutions as etchants that attack polycrystalline silicon and hardly attack other materials, such as dielectric nanosheets 124, 128, and / or 2D semiconductor structure nanosheets 126.

[0098] The 2D semiconductor material of the 2D semiconductor nanosheet 126 has a lower bonding force than the dielectric materials of the first dielectric nanosheet 124 and the second dielectric nanosheet 128. Therefore, the 2D semiconductor nanosheet 126 may be more susceptible to damage and / or oxidation in the absence of the first dielectric nanosheet 124 and the second interface nanosheet 128. However, because the first dielectric nanosheet 124 and the second dielectric nanosheet 128 are formed before the channel release step to encapsulate the 2D semiconductor nanosheet 126, the first dielectric nanosheet 124 and the second dielectric nanosheet 128 can protect the 2D semiconductor nanosheet 126 from unwanted damage and / or oxidation during the channel release step, which improves the yield of the GAA device.

[0099] exist Figure 7A and Figure 7B In this configuration, the internal spacer 170 is formed by oxidizing several portions of the sacrificial semiconductor nanosheet 122 exposed in the gate trench 160. Therefore, when the sacrificial semiconductor layer 122 is polysilicon, the internal spacer 170 is a silicon oxide formed by oxidizing polysilicon. In some embodiments, the sacrificial semiconductor nanosheet 122 is oxidized using a selective oxidation process that oxidizes the polysilicon of the sacrificial semiconductor nanosheet 122 at a faster rate than oxidizing the 2D semiconductor material of the 2D semiconductor nanosheet 126. Therefore, the selective oxidation process oxidizes the exposed portions of the sacrificial semiconductor nanosheet 122 while producing no oxidation or negligible oxidation in the 2D semiconductor nanosheet 126. Thus, the selective oxidation process has no or negligible impact on the yield of the GAA device. Furthermore, the internal spacer fabrication steps in a general-purpose GAA device involve selectively etching a SiGe layer to form a recess on the end face of the SiGe, depositing a dielectric layer in the recess of the SiGe layer, and then etching the dielectric layer to expose the Si channel layer. Compared to such complex manufacturing steps, the internal spacers 170 disclosed herein can be formed using a single oxidation step without additional etching and deposition steps, which simplifies the formation of internal spacers.

[0100] exist Figure 8A and Figure 8B In some embodiments of this disclosure, portions of the first dielectric nanosheet 124 and the second dielectric nanosheet 128 exposed in the gate trench 160 are removed by one or more selective etching processes to expose the 2D semiconductor nanosheet 126, and the gate dielectric layer 182 is then conformally deposited in the gate trench 160 in both the n-type device region 100N and the p-type device region 100P. It should be understood that 2D semiconductor materials typically do not have dangling bonds, and therefore it will be challenging to deposit dielectric material onto the dangling 2D semiconductor nanosheet 126 in the absence of dangling bonds on the surface of the 2D material. However, it should be understood that as the etchant removed from dielectric nanosheets 124 and 128 comes into contact with 2D semiconductor nanosheet 126, more dangling bonds are generated on the top and bottom surfaces of each 2D semiconductor nanosheet 126, and thus more nucleation sites are available for absorption and nucleation of the dielectric material. This situation further facilitates the deposition of dielectric material on the top and bottom surfaces of each 2D semiconductor nanosheet 126.

[0101] In some embodiments, the interface layer 180 is formed around each 2D semiconductor nanosheet 126 before the gate dielectric layer 182 is globally deposited over the n-type device region 100N and the p-type device region 100P. In some embodiments, the interface layer comprises an oxide material (e.g., SiO2, HfO2, WO3).x The interface layer 180 is a transition metal oxide formed using techniques such as thermal oxidation, chemical oxidation, or deposited by CVD, ALD, or the like, including, for example, tungsten oxide (WO3), molybdenum oxide (MoO), or other suitable transition metal oxide materials. In some embodiments, the interface layer 180 is a transition metal oxide formed using techniques such as thermal oxidation, chemical oxidation, or deposited by CVD, ALD, or the like, including, for example, tungsten oxide (WO3), molybdenum oxide (MoO), or other suitable transition metal oxide materials.

[0102] In some embodiments where the interface layer 180 is formed using an oxide, the surface layer of the TMD material of the 2D semiconductor nanosheet 126 is oxidized to form the interface layer 180. In this case, the interface layer 180 has the same transition metal composition as the 2D semiconductor nanosheet 126, such as tungsten or molybdenum. For example, when the 2D semiconductor nanosheet 126 is WS2, the interface layer 180 may be tungsten oxide (WO3). In some embodiments where the interface layer 180 is formed by oxidation, the interface layer 180 is regionalized to the surface of the 2D semiconductor nanosheet 126 and may not extend to dielectric surfaces, such as the surfaces of the gate spacer 140, the internal spacer 170, the second source / drain cap layer 154, and the etch stop layer 102. Instead, because the gate dielectric layer 182 is formed using a deposition technique, the gate dielectric layer 182 can be deposited on all exposed surfaces (including the interfaces 180, gate spacer 140, internal spacer 170, the second source / drain cap layer 154, and the etch stop layer 102), such as... Figure 8B As illustrated in the diagram. It should be understood that although the gate dielectric layer 182 is... Figure 8B The cross-sectional view fully covers all exposed surfaces in both the n-type device region 100N and the p-type device region 100P, but for simplicity and clarity, in Figure 8A The 3D diagram shows only the area around the 2D semiconductor nanosheet.

[0103] In some embodiments, the gate dielectric layer 182 includes one or more high-k dielectric layers. As used and described herein, the high-k gate dielectric includes dielectric materials having a high dielectric constant (about 3.9 to 4.0) greater than that of thermally oxidized silicon. The high-k dielectric material of the gate dielectric layer 182 may, by way of example and without limitation, include hafnium oxide (HfO2), hafnium oxysilicide (HfSiO), hafnium oxysilicide (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (La2O3), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum oxysilicide (LaSiO), aluminum oxysilicide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxynitride (SiON), and combinations thereof.

[0104] In some embodiments, the gate dielectric layer 182 in the n-type device region 100N may have a different material composition than that in the p-type device region 100P in order to meet the threshold voltage (Vt) targets of the n-type GAA device and the p-type GAA device. For example, the gate dielectric layer 182 in the n-type device region 100N may include more or less high-k dielectric film compared to the film in the p-type device region 100P. Such a difference in gate dielectric constant can be achieved by sequentially depositing a first high-k dielectric film and a second high-k dielectric film over the n-type device region 100N and the p-type device region 100P, and then removing a portion of the second high-k dielectric film from the n-type device region 100N or the p-type device region 100P using appropriate optical lithography and etching techniques.

[0105] Figure 8C This is an enlarged view illustrating some other embodiments of the present disclosure relating to the fabrication of the gate dielectric layer 182. Figure 8C In this configuration, several portions of the first dielectric nanosheet 124 and the second dielectric nanosheet 128 remain on the surface of the 2D semiconductor nanosheet 126 within the gate trench 160, rather than as... Figure 8B The interface layer 180 is used instead of the gate trench 160. The remaining dielectric nanosheets 124 and 128 in the gate trench 160 provide the benefit of depositing the gate dielectric layer 182 because depositing dielectric material on the 2D semiconductor nanosheets 126 is challenging due to the absence of dangling bonds on the 2D semiconductor surface. In some embodiments, as illustrated in Figure 8CThe structure can be achieved, for example, by thinning the dielectric nanosheets 124 and 128 in the gate trench 160 of both the n-type device region 100N and the p-type device region 100P, and then conformally depositing the gate dielectric layer 182 in the gate trench 160 of both the n-type device region 100N and the p-type device region 100P. This thinning operation is performed by etching (rather than completely removing the dielectric nanosheets 124 and 128 from the gate trench 160).

[0106] exist Figures 9A to 9C In this process, the gate replacement structure 190 is formed to fill the gate trench 160 in the n-type device region 100N and the p-type device region 100P. In some embodiments, such as Figure 9B As illustrated, one or more work function metal layers 192 are deposited on the gate dielectric layer 182 in the n-type device region 100N and the p-type device region 100P, followed by the deposition of fill metal 194 on the one or more work function metal layers 192 to fill the remaining portion of the gate trench 160 in the n-type device region 100N and the p-type device region 100P. CMP is then performed on the fill metal 194 until the gate spacer 140 and the second source / drain cap layer 154 are exposed, resulting in the fill metal 194, one or more work function metal layers 192, gate dielectric layer 182, gate spacer 140, and second source / drain cap layer 154 having generally flush top surfaces. Each replacement gate structure 190 includes an interface layer 180 surrounding a 2D semiconductor nanosheet 126, a gate dielectric layer 182 surrounding each of the interface layers 180, one or more work function metal layers 192 surrounding the gate dielectric layer 182, and a fill metal 194 surrounding one of the multiple work function metal layers 192.

[0107] In some embodiments, if the difference in gate dielectric composition achieves a satisfactory critical voltage target for both the n-type and p-type devices, the number of work function metal layers 192 in the n-type device region 100N is the same as the number of work function metal layers 192 in the p-type device region 100P. In some other embodiments, the number of work function metal layers 192 in the n-type device region 100N may be greater than or less than the number of work function metal layers 192 in the p-type device region 100P to further assist in critical voltage adjustment. Gate stacks with different numbers of work function metal layers 192 can be fabricated using suitable deposition, lithography, and etching processes. For example, the first and second work function metal layers are entirely over the n-type device region 100N and the p-type device region 100P, and then a portion of the second work function metal layer is removed from the n-type device region 100N or the p-type device region 100P using suitable lithography and etching techniques.

[0108] One or more work function metal layers 192 may include one or more work function metals to provide a suitable work function for a high-k / metal gate (KHMG) structure. For an n-type GAA FET, one or more work function metal layers 192 may include one or more n-type work function metals (N metals), which have a work function lower than the intermediate gap work function of the 2D semiconductor material (e.g., TMD) of the 2D semiconductor nanosheet 126, which is located between the valence band and conduction band of the 2D semiconductor material. Examples of n-type work function metals include, but are not limited to, nickel (Ni), titanium (Ti), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminum compounds, and / or other suitable materials. On the other hand, for a p-type GAA FET, one or more work function metal layers 192 may include one or more p-type work function metals (N metals), in which case they have a work function higher than that of the intermediate gap work function of the 2D semiconductor material (e.g., TMD) of the 2D semiconductor nanosheet 126. P-type work function metals may exemplify, but are not limited to, palladium (Pd), platinum (Pt), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), cobalt (Co), conductive metal oxides, and / or other suitable materials.

[0109] In some embodiments, the filler metal 194 may exemplify, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN or other suitable materials.

[0110] exist Figures 10A to 10CIn this process, one or more etching processes are performed to replace the gate structure 190 with etchback, thereby creating a recess above the etched gate structure 190 and between the gate spacers 140. If the replaced gate structure 190 is a high-k / metal gate (HKMG) structure, this step may be referred to as a metal gate etchback (MGEB) step. The one or more etching steps performed in the MGEB step are more selective for the materials of the HKMG structure 190 than the gate spacers 140 and the second source / drain cap layer 154, and therefore the etching rate of the HKMG structure 190 is faster than the etching rate of the gate spacers 140 and the second source / drain cap layer 154. Therefore, one or more etching processes result in the top surfaces of the gate dielectric layer 182, the work function metal layer 192, and the fill metal 194 being lower than the top surfaces of the gate spacers 140 and the second source / drain cap layer 154. One or more etching processes used in the MGEB step include dry etching, wet etching, atomic layer etching (ALE), plasma etching, other etch-back techniques, or combinations thereof. In some embodiments, one or more etching processes selective for high-k gate dielectric materials, work function metals, and filler metals may be, for example, plasma etching processes using one or more etchants such as fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6) and / or chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3).

[0111] Next, in Figures 10A to 10CIn this configuration, a gate hard mask 200 is formed on top of the etch-back replacement gate structure 190. In some embodiments, if the replacement gate structure 190 is an HKMG structure, the gate hard mask 200 may be referred to as a metal gate hard mask (MGHM). The replacement gate hard mask 200 includes SiN, SiC, SiCN, SiON, SiCON, combinations thereof, or similar materials. The gate hard mask 200 can be formed by: depositing a cap material layer over the entire n-type device region 100N and p-type device region 100P until the recess above the etch-back gate structure 190 is overfilled; followed by a CMP process to remove excess cap material outside the recess while leaving a cap material layer in the recess to serve as the gate hard mask 200. In some embodiments, the gate hard mask 200, gate spacer 140, and internal spacer 170 are formed of materials that exhibit high etch selectivity with respect to the source / drain caps 152, 154, the sacrificial semiconductor nanosheet 122, the 2D semiconductor nanosheet 126, and the dielectric nanosheets 124, 128. Therefore, the gate hard mask 200, gate spacer 140, and internal spacer 170 collectively protect the gate structure 190 from subsequent etching steps in the source / drain processing.

[0112] exist Figure 11A and Figure 11B In this process, after forming the gate hard mask 200, a photoresist layer P1 is then formed over both the n-type device region 100N and the p-type device region 100P and subsequently patterned to expose the n-type device region 100N but not the p-type device region 100P. In some embodiments, the photoresist layer P1 is an organic material formed using a spin-coating process, followed by patterning the organic material using a suitable optical lithography technique to expose the n-type device region 100N. For example, the photoresist material is irradiated (exposed) and developed to remove several portions of the photoresist material. More specifically, a photomask or master photomask (not shown) may be placed over the photoresist material, which may then be exposed to a radiation beam, which may be ultraviolet (UV) or an excimer laser, such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser. Exposure of the photoresist material can be performed, for example, using immersion lithography or extreme ultraviolet (EUV) light to increase resolution and reduce the minimum achievable pitch. Baking or curing operations can be performed to harden the exposed photoresist material, and a developer can be used to remove the exposed or unexposed portions of the photoresist material, depending on whether a positive or negative resist is used.

[0113] After the patterned photoresist layer P1 is formed, the first source / drain cap layer 152 and the second source / drain cap layer 154, dielectric nanosheets 124 and 128, and sacrificial semiconductor nanosheet 122 in the n-type device region 100N are removed by one or more selective etching processes. These etching processes etch the source / drain cap layers 152 and 154, dielectric nanosheets 124 and 128, and sacrificial semiconductor nanosheet 122 at a faster etching rate than the etching rate of the 2D semiconductor nanosheet 126. Therefore, in the n-type device region 100N, once the source / drain cap layers 152 and 154, dielectric nanosheets 124 and 128, and sacrificial semiconductor nanosheet 122 are removed, the source / drain extension region 1262 of the 2D semiconductor nanosheet 126 extending outside the gate structure 190 becomes exposed. In some embodiments, in the n-type device region 100N, the source / drain extension region 1262 of the 2D semiconductor nanosheet 126 remains substantially intact at least due to etching selectivity during one or more etching processes, and the channel region 1264 of the 2D semiconductor nanosheet 126 also remains substantially intact because it is protected at least by the gate structure 190.

[0114] After the source / drain caps 152, 154, dielectric nanosheets 124, 128, and sacrificial semiconductor nanosheet 122 are removed from the n-type device region 100N, an n-type metal source region 210 and an n-type drain region 210N are formed, thereby surrounding each of the source and drain extension regions 1262 of the 2D semiconductor nanosheet 126 in the n-type device region 100N. In some embodiments, the source and drain regions are collectively referred to as source / drain regions or S / D regions. The n-type metal source / drain region 210N includes a suitable metal for forming a Schottky contact with the 2D semiconductor material of the 2D semiconductor nanosheet 126, which is advantageous for reducing source / drain resistance. Furthermore, the n-type metal source / drain region 210N contacts at least four sides of the drain / drain extension region 1262 of the 2D semiconductor nanosheet 126, thus further reducing source / drain resistance.

[0115] In some embodiments, the n-type metal source / drain region 210N is formed of a metal having a band-edge work function close to the valence band of a 2D semiconductor material (e.g., TMD), such as Figure 11C The diagram in the image shows... Figure 11C The figure illustrates an exemplary energy band diagram of a Schottky contact for an NFET with TMD nanosheets according to some embodiments of this disclosure. When the gate voltage exceeds a critical voltage, the metal, having a work function near the band edge of the conduction band of the 2D semiconductor material, allows electrons (in...) Figure 11CThe material (labeled "e") flows laterally between the n-type source / drain region 210N and the 2D semiconductor nanosheet 126. Therefore, the resulting transistor has an n-type GAA FET. In some embodiments where the 2D semiconductor material is a TMD, the metal having a band edge work function close to the conduction band of the TMD, exemplarily and non-limitingly, includes nickel (Ni), titanium (Ti), or other suitable metals having a lower work function compared to the intermediate band gap work function of the TMD.

[0116] In some embodiments, the entire 2D semiconductor nanosheet 126 (i.e., including the source / drain extension region 1262 and the channel region 1264) is undoped because undoped 2D semiconductor material (e.g., TMD) has both holes and electrons ready to act as carriers. The dominant carrier type of the GAA FET depends on the metal of the source / drain region. For example, as previously discussed, when the metal source / drain region 210N is formed of a metal having a band-edge function close to the conduction band of the 2D semiconductor material, the dominant carrier type of the undoped 2D semiconductor nanosheet 126 of the GAA FET will be electrons.

[0117] In some embodiments, the n-type metal source / drain region 210N can be formed by depositing a metal with a work function at the edge of the valence band close to the 2D semiconductor nanosheet 126 using a suitable deposition technique (e.g., CVD, PVD, ALD, or similar) to surround each of the 2D semiconductor nanosheets 126, followed by performing a CMP process on the metal layer at least until the gate hard mask 200 and the gate spacer 140 are exposed. In some embodiments, the CMP process uses a paste that grinds the n-type metal source / drain region 210N at a removal rate faster than the removal rate at which it grinds the gate hard mask 200 and the gate spacer 140. As a result, once the CMP process stops, the n-type source / drain region 210N can have a top surface lower than the top surface of the gate hard mask 200 and the gate spacer 140, such as Figure 11A and Figure 11B As illustrated in the figure. In some embodiments, the photoresist layer P1 is removed after the fabrication of the n-type source / drain region 210N is completed. The photoresist layer P1 can be removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed such that the temperature of the photoresist layer P1 is increased until the photoresist P1 experiences thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, can be used.

[0118] exist Figure 12A and Figure 12BIn the process, after photoresist layer P1 is removed from p-type device region 100P, another patterned photoresist layer (not shown) is formed to cover n-type device region 100N and expose p-type device region 100P using a suitable optical lithography technique as previously described with respect to photoresist layer P1. Next, source / drain cap layers 152, 154, dielectric nanosheets 124, 128, and sacrificial semiconductor nanosheet 122 in p-type device region 100P are removed using one or more selective etching processes, thereby exposing the source / drain extension region 1262 of 2D semiconductor nanosheet 126 in p-type device region 100P. In some embodiments, in the p-type device region 100P, the source / drain extension region 1262 of the 2D semiconductor nanosheet 126 remains substantially intact at least due to etch selectivity during the removal of the source / drain cap layers 152, 154, sacrificing the semiconductor nanosheet 122 and dielectric nanosheets 124, 128, and the channel region 1264 of the 2D semiconductor nanosheet 126 also remains substantially intact because the channel region 1264 is protected at least by the gate structure 190.

[0119] After the source / drain caps 152, 154, dielectric nanosheets 124, 128, and sacrificial semiconductor nanosheet 122 are removed from the p-type device region 100P, a p-type metal source / drain region 210P is formed, thereby surrounding each of the source and / or drain extension regions 1262 of the 2D semiconductor nanosheet 126 in the p-type device region 100P. The p-type metal source / drain region 210P includes a suitable metal for forming a Schottky contact with the 2D semiconductor material of the 2D semiconductor nanosheet 126. Furthermore, the p-type metal source / drain region 210P contacts at least four sides of the drain / drain extension region 1262 of the 2D semiconductor nanosheet 126, which is advantageous for reducing source / drain resistance.

[0120] In some embodiments, the p-type metal source / drain region 210P is formed of a metal having a band-edge work function close to the valence band of a 2D semiconductor material (e.g., TMD), such as Figure 12C As shown in Figure 12C The illustration shows an exemplary band structure of a Schottky contact for a PFET with a TMD nanosheet according to some embodiments of this disclosure. When the gate voltage exceeds a critical voltage, a metal having a band-edge work function close to the valence band of the 2D semiconductor material allows holes (labeled "h") to flow laterally between the p-type metal source / drain region 210P and the 2D semiconductor nanosheet 126. Therefore, the resulting transistor has a p-type GAA FET. In some embodiments where the 2D semiconductor material is a TMD, the metal having a band-edge work function close to the valence band of the TMD, illustratively and non-limitingly, includes palladium (Pd), platinum (Pt), or other suitable metals having a higher work function than the intermediate bandgap work function of the TMD.

[0121] In some embodiments, the entire 2D semiconductor nanosheet 126 in the p-type device region 100P (i.e., including the source / drain extension region 1262 and the channel region 1264) is undoped because undoped 2D semiconductor material (e.g., TMD) has both holes and electrons ready to act as carriers. The dominant carrier type of the GAA FET depends on the metal of the source / drain region. For example, as previously described, when the metal source / drain region 210P is formed of a metal having a band edge work function close to the valence band of the 2D semiconductor material, the dominant carrier type of the undoped 2D semiconductor nanosheet 126 of the GAA FET will be holes.

[0122] In some embodiments, the p-type metal source / drain region 210P can be formed by depositing a metal layer with an edge work function close to the valence band of the 2D semiconductor nanosheet 126 to surround each of the 2D semiconductor nanosheets 126 in the p-type device region 100P using a suitable deposition technique (e.g., CVD, PVD, ALD, or similar) followed by performing a CMP process on the metal layer at least until the gate hard mask 200 and the gate spacer 140 are exposed. In some embodiments, the CMP process uses a paste that grinds the p-type metal source / drain region 210P at a removal rate faster than the removal rate at which it grinds the gate hard mask 200 and the gate spacer 140. Thus, once the CMP process is terminated, the p-type source / drain region 210P may have a top surface lower than the top surface of the gate hard mask 200 and the gate spacer 140, such as Figure 12A and Figure 12B As illustrated in the figure. In some embodiments, the photoresist layer covering the n-type device region 100N is removed after the fabrication of the p-type metal source / drain region 210P is completed.

[0123] In some embodiments, because the n-type metal source / drain region 210N is formed of a metal having a band-edge work function close to the conduction band of the 2D semiconductor nanosheet 126 and the p-type source / drain region 210P is formed of a metal having a band-edge work function close to the valence band of the 2D semiconductor nanosheet 126, the metal of the n-type metal source / drain region 210N has a lower work function than the metal of the p-type metal source / drain region 210P. In some embodiments where the 2D semiconductor nanosheet 126 is formed of a TMD having a band gap greater than about 1 eV, 2 eV, or more, the work function difference between the metal of the n-type source / drain region 210N and the metal of the p-type source / drain region 210P may be about 1 eV or more.

[0124] In such Figures 11A to 12CIn some embodiments illustrated, the n-type metal source / drain region 210N is formed prior to the formation of the p-type metal source / drain region 210P. However, the reverse order of source / drain formation is also possible. For example, in some other embodiments, the p-type metal source / drain region 210P is formed prior to the formation of the n-type metal source / drain region 210N.

[0125] According to some embodiments disclosed herein, such as Figures 12A to 12B In the resulting GAA FET illustrated herein, each 2D semiconductor nanosheet 126 has a channel length (i.e., the length of channel region 1264) measured in a first horizontal direction D1 (illustrated in the first horizontal direction D1) ranging from about 5 nm to about 50 nm (e.g., about 14 nm). In some embodiments, each internal spacer 170 has a thickness measured in the first horizontal direction D1 in the range of about 0.5 nm to about 20 nm (e.g., about 5 nm). In some embodiments, each of the n-type source / drain region 210N and the p-type source / drain region 210P has a width measured in the first horizontal direction D1 in the range of about 10 nm to about 20 nm (e.g., about 12 nm). In some embodiments, each interface layer 180 has a thickness in the range of about 0.1 nm to about 1 nm (e.g., 0.5 nm). In some embodiments, each gate dielectric layer 182 has a thickness in the range of about 1 nm to about 10 nm. In some embodiments, each gate dielectric layer includes a first high-k dielectric layer having a thickness in the range of about 1 nm to about 3 nm (e.g., about 2 nm), and a second high-k dielectric layer (also referred to as a high-k cap layer) having a thickness in the range of about 2 nm to about 4 nm (e.g., about 3 nm). In some embodiments, each 2D semiconductor nanosheet has a channel width (i.e., the width of channel region 1264) measured in a second horizontal direction D2 in the range of about 20 nm to about 30 nm (e.g., about 26 nm), and a channel height measured in a vertical direction D3 in the range of about 0.5 nm to about 10 nm (e.g., about 2 nm), wherein the channel height depends on the total number of mono-layers of the 2D semiconductor material. In some embodiments, the vertical spacing between adjacent 2D semiconductor nanosheets 126 is in the range of about 10 nm to about 20 nm (e.g., about 14 nm). In some embodiments, the etch stop layer 102 has a thickness in the range of 10 nm to about 100 nm.

[0126] Figure 13 This is a cross-sectional view of a GAA device according to some embodiments of this disclosure. The GAA device is similar to... Figures 12A to 12BThe GAA devices illustrated herein, except that the 2D semiconductor nanosheet 126 terminates before reaching beyond the internal spacer 170. In some embodiments, for an n-type GAA device, the 2D semiconductor nanosheet 126 in the n-type device region 100N (e.g., Figures 12A to 12B The source / drain extension region 1262 (illustrated in the figure) can be removed by etching prior to the formation of the n-type metal source / drain region 210N. This etching can be controlled such that the resulting 2D semiconductor nanosheet 126 has end surfaces that are aligned with the outer surfaces of the remaining portions of the dielectric nanosheets 124, 128, the outer surface of the internal spacer 170, and the outer surface of the gate spacer 140. Once the n-type metal source / drain region 210N is formed, the n-type metal source / drain region 210N forms Schottky contacts with the end surfaces of the 2D semiconductor nanosheet 126. Similarly, for a p-type GAA device, the source / drain extension region 1262 of the 2D semiconductor nanosheet 126 in the p-type device region 100P can be removed by etching prior to the formation of the p-type metal source / drain region 210P. This etching can be controlled so that the resulting 2D semiconductor nanosheets 126 in the p-type device region 100P have end surfaces that are aligned with the outer surfaces of the remaining portions of the dielectric nanosheets 124, 128, the outer surfaces of the internal spacers 170 and the gate spacers 140. Once the p-type metal source / drain region 210P is formed, the p-type metal source / drain region 210P forms Schottky contacts with the end surfaces of the 2D semiconductor nanosheets 126.

[0127] Figure 14 This is a cross-sectional view of a GAA device according to some embodiments of the present disclosure. The GAA device is similar to that illustrated in the figure. Figures 12A to 12B The GAA devices illustrated in the figure are characterized by the lateral recess of the end surface of the 2D semiconductor nanosheet 126. In some embodiments, for an n-type GAA device, the 2D semiconductor nanosheet 126 in the n-type device region 100N (e.g., Figures 12A to 12BThe source / drain extension region 1262 (illustrated in the figure) can be removed by etching prior to the formation of the n-type metal source / drain region 210N. This etching can be controlled to further laterally recess the 2D semiconductor nanosheet 126, resulting in an end surface that is recessed from the outer surface of the remaining portions of the dielectric nanosheets 124, 128, the outer surface of the internal spacer 170, and the outer surface of the gate spacer 140. Once the n-type metal source / drain region 210N is formed, it has a protrusion 212N extending laterally between the remaining portions of the dielectric nanosheets 124, 128, and forming a Schottky contact with the recessed end surface of the 2D semiconductor nanosheet 126. Similarly, for a p-type GAA device, the source / drain extension region 1262 of the 2D semiconductor nanosheet 126 in the p-type device region 100P can be removed by etching prior to the formation of the p-type metal source / drain region 210P. This etching can be controlled to laterally recess the 2D semiconductor nanosheet 126, such that the resulting 2D semiconductor nanosheet 126 in the p-type device region 100P has end surfaces that are recessed from the outer surfaces of the remaining portions of the dielectric nanosheets 124, 128, the outer surface of the internal spacer 170, and the outer surface of the gate spacer 140. Once the p-type metal source / drain region 210P is formed, the p-type metal source / drain region 210P has a protrusion 212P extending laterally between the remaining portions of the dielectric nanosheets 124, 128, and forming a Schottky contact with the recessed end surfaces of the 2D semiconductor nanosheet 126.

[0128] Based on the foregoing discussion, it is evident that this disclosure offers advantages in various embodiments. However, it should be understood that other embodiments may offer additional advantages, and not all advantages need to be disclosed herein, nor is any specific advantage claimed for all embodiments. One advantage is that the thickness of the 2D semiconductor nanosheets can be reduced with little or no impact on channel mobility compared to silicon, achieving satisfactory GAA channel mobility with reduced channel thickness. Another advantage is that the metal source / drain regions are formed from suitable metals for forming Schottky contacts with the 2D semiconductor nanosheets, which is advantageous for reducing source / drain resistance. Yet another advantage is that the internal spacers are formed by oxidizing sacrificial semiconductor layers, which are alternately configured with the 2D semiconductor nanosheets, further simplifying the internal spacer fabrication process.

[0129] In some embodiments, an apparatus includes a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The 2D semiconductor nanostructures extend over a substrate in a first direction and are arranged in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the 2D semiconductor nanostructures. The source region and the drain region are located on opposite sides of the gate structure. In some embodiments, the 2D semiconductor nanostructures are formed of a transition metal dichalcogenide (TMD) material. In some embodiments, each of the 2D semiconductor nanostructures is further surrounded by the source region and the drain region. In some embodiments, the source region is formed of metal. In some embodiments, the metal of the source region has a band-edge work function adjacent to a conduction band of a 2D semiconductor material of the 2D semiconductor nanostructures. In some embodiments, the metal of the source region has a band-edge work function adjacent to a valence band of a 2D semiconductor material of the 2D semiconductor nanostructures. In some embodiments, the apparatus further includes a first gate spacer separating the source region from the gate structure and a second gate spacer separating the drain region from the gate structure. In some embodiments, the 2D semiconductor nanostructures have opposing ends aligned with an outermost wall of the first gate spacer and an outermost wall of the second gate spacer, respectively. In some embodiments, each of the 2D semiconductor nanostructures has a first end positioned laterally rearward from an outermost wall of the first gate spacer and a second end positioned laterally rearward from an outermost wall of the second gate spacer. In some embodiments, the source region has a plurality of source protrusions directly below the first gate spacer, and the drain region has a plurality of drain protrusions directly below the second gate spacer. In some embodiments, the device further includes a plurality of internal spacers alternately arranged with the plurality of 2D semiconductor nanostructures. The gate structure is at least partially separated from the source and drain regions by the plurality of internal spacers, and the plurality of internal spacers are formed of silicon oxide. In some embodiments, the gate structure includes a plurality of interface layers surrounding the plurality of 2D semiconductor nanostructures, wherein the plurality of interface layers are formed of transition metal oxide. In some embodiments, the device further includes an etch stop layer separating the gate structure from the substrate.

[0130] In some embodiments, an IC structure includes an n-type field-effect transistor (NFET) and a p-type field-effect transistor (PFET). The NFET and PFET are located above a substrate. The NFET includes a plurality of NFET semiconductor nanostructures arranged spaced above each other, an NFET gate structure surrounding each of the NFET semiconductor nanostructures, and n-type source / drain regions on opposite sides of the NFET gate structure. The PFET includes a plurality of PFET semiconductor nanostructures arranged spaced above each other, a PFET gate structure surrounding each of the PFET semiconductor nanostructures, and p-type source / drain regions on opposite sides of the PFET gate structure. The n-type source / drain regions are formed of a metal having a band-edge work function adjacent to a conduction band of a 2D semiconductor material of the NFET semiconductor nanostructures. In some embodiments, the p-type source / drain regions are formed of a metal having a band-edge work function adjacent to a valence band of a 2D semiconductor material of the PFET semiconductor nanostructures. In some embodiments, the 2D semiconductor material of the NFET semiconductor nanostructures is a transition metal dichalcogenide (TMD) material. In some embodiments, the PFET semiconductor nanostructures are formed from the same 2D semiconductor material as the NFET semiconductor nanostructures.

[0131] In some embodiments, a method includes: forming a fin over a substrate, the fin including alternately stacked sacrificial semiconductor layers and 2D semiconductor layers; forming a dummy gate structure over the fin, and forming gate spacers on either side of the dummy gate structure; removing the dummy gate structure to form a gate trench over the fin; removing first portions of the sacrificial semiconductor layers in the gate trench such that the 2D semiconductor layers are suspended in the gate trench; and forming a gate structure around the 2D semiconductor layers after removing the first portions of the sacrificial semiconductor layers. In some embodiments, the fin further includes dielectric layers respectively inserted in adjacent portions of the sacrificial semiconductor layers and the 2D semiconductor layers, and the dielectric layers are retained on the top and bottom surfaces of the 2D semiconductor layers after removing the first portions of the sacrificial semiconductor layers. In some embodiments, the method further includes oxidizing second portions of the sacrificial semiconductor layers to form internal spacers after removing the first portions of the sacrificial semiconductor layers. In some embodiments, the method further includes removing the unoxidized portions of the sacrificial semiconductor layers after oxidizing the second portions of the sacrificial semiconductor layers; and forming metal source / drain regions in the regions where the unoxidized portions of the sacrificial semiconductor layers reside after removing the unoxidized portions of the sacrificial semiconductor layers.

[0132] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: Multiple two-dimensional semiconductor nanostructures extend over a substrate in a first direction and are arranged in a second direction substantially perpendicular to the first direction; A gate structure that surrounds each of the plurality of two-dimensional semiconductor nanostructures; and A source region and a drain region are respectively located on opposite sides of the gate structure, wherein the source region or the drain region is formed of a metal having a band edge work function that is close to a conduction band of a two-dimensional semiconductor material of the plurality of two-dimensional semiconductor nanostructures.

2. The semiconductor device as claimed in claim 1, characterized in that, The multiple two-dimensional semiconductor nanostructures are formed from a transition metal dichalcogenide material.

3. The semiconductor device as claimed in claim 1, characterized in that, Each of the plurality of two-dimensional semiconductor nanostructures is further surrounded by the source region and the drain region.

4. The semiconductor device as claimed in claim 1, characterized in that, The metal in the source region or the drain region contains nickel (Ni).

5. The semiconductor device as claimed in claim 1, characterized in that, The metal in the source region or the drain region contains titanium (Ti).

6. The semiconductor device as claimed in claim 1, characterized in that, Each of the plurality of two-dimensional semiconductor nanostructures further includes a source / drain extension region, and the metal of the source region or the drain region is in contact with at least four sides of the source / drain extension region.

7. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A first gate spacer separates the source region from the gate structure; and A second gate spacer separates the drain region from the gate structure. The plurality of two-dimensional semiconductor nanostructures have opposite ends, which are respectively aligned with an outermost wall of the first gate spacer and an outermost wall of the second gate spacer.

8. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A first gate spacer separates the source region from the gate structure; and A second gate spacer separates the drain region from the gate structure, and each of the plurality of two-dimensional semiconductor nanostructures has a first end that is laterally recessed from an outermost wall of the first gate spacer and a second end that is laterally recessed from an outermost wall of the second gate spacer.

9. The semiconductor device as claimed in claim 8, characterized in that, The source region has a plurality of source protrusions directly below the first gate spacer, and the drain region has a plurality of drain protrusions directly below the second gate spacer.

10. The semiconductor device as claimed in claim 1, characterized in that, Further includes: Multiple internal spacers are alternately arranged with multiple two-dimensional semiconductor nanostructures, and the gate structure is at least partially separated from the source region and the drain region by the multiple internal spacers.

11. The semiconductor device as claimed in claim 1, characterized in that, The gate structure includes multiple interface layers that respectively surround the plurality of two-dimensional semiconductor nanostructures.

12. The semiconductor device as claimed in claim 1, characterized in that, Further includes: An etch stop layer separates the gate structure from the substrate.

13. An integrated circuit (IC) structure, characterized in that, Include: An n-type field-effect transistor (NFET) is provided on a substrate. The n-type field-effect transistor includes a plurality of n-type field-effect transistor semiconductor nanostructures arranged above each other in a spaced manner, an n-type field-effect transistor gate structure surrounding each of the plurality of n-type field-effect transistor semiconductor nanostructures, and n-type source / drain regions on opposite sides of the n-type field-effect transistor gate structure. and A p-type field-effect transistor (PFET) on the substrate includes a plurality of p-type field-effect transistor semiconductor nanostructures arranged above each other in a spaced-above manner, a p-type field-effect transistor gate structure surrounding each of the plurality of p-type field-effect transistor semiconductor nanostructures, and p-type source / drain regions on opposite sides of the p-type field-effect transistor gate structure. The plurality of n-type source / drain regions are formed of a metal having a band edge work function that is close to a conduction band of a two-dimensional semiconductor material of the plurality of n-type field-effect transistor semiconductor nanostructures.

14. The integrated circuit structure as described in claim 13, characterized in that, The plurality of p-type source / drain regions are formed of a metal having a band edge work function that is close to the valence band of a two-dimensional semiconductor material of the plurality of p-type field-effect transistor semiconductor nanostructures.

15. The integrated circuit structure as described in claim 13, characterized in that, The two-dimensional semiconductor material of the plurality of n-type field-effect transistor semiconductor nanostructures is a transition metal dichalcogenide (TMD) material.

16. The integrated circuit structure as described in claim 13, characterized in that, The plurality of p-type field-effect transistor semiconductor nanostructures are formed from the same two-dimensional semiconductor material as the plurality of n-type field-effect transistor semiconductor nanostructures.

17. A method for forming a semiconductor device, characterized in that, Include: A fin is formed above a substrate. The fin includes a plurality of alternately stacked sacrificial semiconductor layers and a plurality of two-dimensional semiconductor nanostructures. The plurality of two-dimensional semiconductor nanostructures extend above the substrate in a first direction and are arranged in a second direction substantially perpendicular to the first direction. The fin also includes a plurality of dielectric layers, each of which is inserted into an adjacent pair of the plurality of sacrificial semiconductor layers and the plurality of two-dimensional semiconductor nanostructures. A dummy gate structure is formed above the fin, and a gate spacer is formed on either side of the dummy gate structure; Remove the dummy gate structure to form a gate trench above the fin; Remove a plurality of first portions of the plurality of sacrificial semiconductor layers in the gate trench, such that the plurality of two-dimensional semiconductor nanostructures are suspended in the gate trench, wherein the plurality of dielectric layers remain on the top and bottom surfaces of the plurality of two-dimensional semiconductor nanostructures after the removal of the plurality of first portions of the plurality of sacrificial semiconductor layers; After removing the plurality of first portions of the plurality of sacrificial semiconductor layers, a gate structure is formed around each of the plurality of two-dimensional semiconductor nanostructures; and A source region and a drain region are formed on opposite sides of the gate structure, wherein the source region or the drain region is formed of a metal having a band edge work function that is close to a conduction band of a two-dimensional semiconductor material of the plurality of two-dimensional semiconductor nanostructures.

18. The method for forming a semiconductor device as claimed in claim 17, characterized in that, The two-dimensional semiconductor material of the plurality of two-dimensional semiconductor nanostructures is a transition metal dichalcogenide (TMD) material.

19. The method for forming a semiconductor device as claimed in claim 17, characterized in that, Also includes: After removing the plurality of first portions of the plurality of sacrificial semiconductor layers, the plurality of second portions of the plurality of sacrificial semiconductor layers are oxidized to form a plurality of internal spacers.

20. The method for forming a semiconductor device as claimed in claim 19, characterized in that, Also includes: After oxidizing the plurality of second portions of the plurality of sacrificial semiconductor layers, the plurality of unoxidized portions of the plurality of sacrificial semiconductor layers are removed; and After removing the plurality of unoxidized portions of the plurality of sacrificial semiconductor layers, a metal source / drain region is formed in the region where the plurality of unoxidized portions of the plurality of sacrificial semiconductor layers are located.

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