Differential mode start-up circuit for fully differential gain amplifier

Abstract

The application relates to a differential-mode starting circuit of a full-differential gain amplifier, which comprises an additional input pair of a fifth PMOS transistor M5 and a sixth PMOS transistor M6 added to the feedback input pair of a second PMOS transistor M2 and a third PMOS transistor M3, the gate of the fifth PMOS transistor M5 is connected with a differential input positive terminal inp, the gate of the sixth PMOS transistor M6 is connected with a differential input negative terminal inn, the common source of the fifth PMOS transistor M5 and the sixth PMOS transistor M6 is connected with the common source of the second PMOS transistor M2 and the third PMOS transistor M3 through a fourth PMOS transistor M4 which is a control switch controlled by a vc signal, the vc signal is generated by a common-mode comparison circuit in a common-mode starting circuit, and the full-differential gain amplifier with the common-mode starting circuit can keep the current balance between the signal input pair and the feedback input pair during the common-mode starting process, so that the circuit is prevented from being stabilized in an undesired state with the highest output terminal and the lowest output terminal due to some nodes being pulled to the limit state.

Description

Technical Field

[0001] This invention relates to differential-mode startup technology for fully differential gain amplifiers, particularly a differential-mode startup circuit for a fully differential gain amplifier. By adding an additional input pair consisting of PMOS transistors M5 and M6 to the feedback input pair composed of PMOS transistors M2 (2nd) and M3 (3rd), with the gate of M5 connected to the positive differential input terminal inp and the gate of M6 connected to the negative differential input terminal inn, the common source terminals of M5 and M6 are connected to the common source terminals of M2 and M3 via PMOS transistor M4 (4th), which acts as a control switch controlled by the VC signal. The VC signal is generated by the common-mode comparator circuit in the common-mode startup circuit. This allows the current of the signal input pair and the feedback input pair to remain balanced during common-mode startup of the fully differential gain amplifier structure with the common-mode startup circuit, avoiding the undesirable state where the circuit stabilizes at the highest output and the lowest output due to certain nodes being pulled to their limits. Background Technology

[0002] Fully differential gain amplifiers typically include a common-mode startup circuit. This circuit usually connects a pair of input transistors in parallel with the feedback input transistor. The control signal is the result of comparing the output common-mode output with the reference output common-mode output. The purpose is to provide a current path to the tail current source of the feedback input transistor even when the initial output common-mode is abnormal and the feedback input transistor is operating in the cutoff or subthreshold region, allowing the op-amp to establish itself to a normal operating state. However, this type of fully differential gain amplifier with a common-mode startup circuit still suffers from differential-mode startup problems; the circuit may stabilize in a state where one output is highest and the other lowest. For the structure of a fully differential gain amplifier with a common-mode startup circuit, please refer to [reference needed]. Figure 1 and Figure 3 Furthermore, the circuit within the dashed box is modified by removing PMOS transistor M4 (number 4), leaving only the additional input pair consisting of PMOS transistors M5 (number 5) and M6 (number 6). This additional input pair is connected in parallel with the feedback input pair consisting of PMOS transistors M2 (number 2) and M3 (number 3). The gates of M5 and M6 are both connected to the control voltage terminal vc, instead of this... Figure 1 In the context of "M5's gate is connected to the differential input positive terminal inp, and M6's gate is connected to the differential input negative terminal inn", VC is generated by the common-mode comparator circuit in the common-mode startup circuit. One implementation method is... Figure 3which is the comparison result between the output common mode 1 / 2(vfbp+vfbn) and the reference common mode vcmo. The principle of the common-mode start-up circuit of the fully differential gain amplifier is as follows: when the output common mode is very high, that is, op, on, or vfbp and vfbn are both very high, and M2 and M3 are cut off or in the subthreshold region, 1 / 2(vfbp+vfbn) is compared with vcmo to output a relatively low vc, so that the current IS1 of Mbp1 controlled by vbp1 can flow through the additional input pair M5 and M6, preventing the circuit from remaining in a state where the Mbp1 current is very small and vfbn and vfbp are very high. However, this circuit still has a differential-mode start-up problem: the additional input pair M5 and M6 equally divide IS1, so that the current I3=I4, while the distribution of IS0 by the input pair M0 and M1 is related to the differential mode of the input signal. When vcmo is biased below 1 / 2vdd and the differential mode of the input signal is also relatively large, the circuit will stabilize in a non-ideal operating state where one end of the output is at the highest level and the other end is at the lowest level. For example, when the differential mode of the input signal is large enough to make I0 much larger than I1, there is I0+I4+ID1>IS3, I1+I3+ID1<IS3, the x point is pulled to the power supply, and the y point is pulled to the ground. At this time, op is pulled to the ground, and on is pulled to the power supply. Since the output common mode is 1 / 2vdd, vc is still a low voltage, M5 and M6 are turned on, while M2 and M3 controlled by vfbp and vfbn cannot compete with M5 and M6 and cannot change the state of the circuit at this time, so the circuit will always remain in a state where one output end is at the highest level and the other end is at the lowest level. Contents of the Invention

[0003] Aiming at the defects or deficiencies existing in the prior art, the present invention provides a differential-mode start-up circuit for a fully differential gain amplifier. An additional input pair composed of the No. 5 PMOS transistor M5 and the No. 6 PMOS transistor M6 is added to the feedback input pair composed of the No. 2 PMOS transistor M2 and the No. 3 PMOS transistor M3. The gate of M5 is connected to the differential input positive terminal inp, the gate of M6 is connected to the differential input negative terminal inn, the common source terminal of M5 and M6 is connected to the common source terminal of M2 and M3 through the No. 4 PMOS transistor M4 which serves as a control switch controlled by the vc signal. The vc signal is generated by the common-mode comparison circuit in the common-mode start-up circuit, which can make the structure of the fully differential gain amplifier with the common-mode start-up circuit keep the current balance between the signal input pair and the feedback input pair during the common-mode start-up process, and avoid the circuit from stabilizing in an undesired state where one end of the output is at the highest level and the other end is at the lowest level due to some nodes being pulled to the limit state.

[0004] The technical solution of the present invention is as follows:

[0005] A differential-mode start-up circuit for a fully differential gain amplifier is characterized by adding an additional input pair consisting of a fifth PMOS transistor M5 and a sixth PMOS transistor M6 to the feedback input pair consisting of a second PMOS transistor M2 and a third PMOS transistor M3. The gate of M5 is connected to the positive differential input terminal inp, and the gate of M6 is connected to the negative differential input terminal inn. The common source terminals of M5 and M6 are connected to the common source terminals of M2 and M3 through a fourth PMOS transistor M4, which acts as a control switch controlled by a VC signal. The VC signal is generated by a common-mode comparator circuit in the common-mode start-up circuit.

[0006] The sources of transistors M2, M3, and M4 are all connected to the drain of the second biased PMOS transistor Mbp1. The source of Mbp1 is connected to the power supply voltage terminal, and the gate of Mbp1 is connected to the first positive bias terminal vbp1. The gate of M2 is connected to the positive terminal of the differential output feedback vfbp, and the gate of M3 is connected to the negative terminal of the differential output feedback vfbn. The gate of M4 is connected to the control voltage terminal vc, and the drain of M4 is connected to the common source terminal of M5 and M6. The drains of M2 and M5 are both connected to the drain of the fourth NMOS transistor MN3. The gate of MN3 is interconnected with the gate of the third NMOS transistor MN2 and then connected to the first negative bias terminal vbn. 1. Both MN3 and MN2 have their sources grounded. Both M3 and M6 have their drains connected to the drain of MN2. The drain of MN2 is connected to the drain of PMOS transistor M0 (number 0). The drain of MN3 is connected to the drain of PMOS transistor M1 (number 1). Both M0 and M1 have their sources connected to the drain of the first biased PMOS transistor Mbp0. The source of Mbp0 is connected to the power supply voltage terminal. The gate of Mbp0 is connected to the first positive bias terminal vbp1. The gate of M0 is connected to the positive differential input terminal inp. The gate of M0 is connected to the negative differential input terminal inn. The drain of MN2 is node x, and the drain of MN3 is node y.

[0007] Node x is connected to the source of the first NMOS transistor MN0, and node y is connected to the source of the second NMOS transistor MN1. The gates of MN0 and MN1 are interconnected and then connected to the second negative bias terminal vbn2. The drain of MN1 is interconnected with the gate of the seventh NMOS transistor MN6 and then connected to the drain of MN6 through the 12th capacitor C12. The drain of MN0 is interconnected with the gate of the lower NMOS transistor and then connected to the positive output terminal op through the 22nd capacitor C22. The drain of the lower NMOS transistor is connected to the positive output terminal op. The sources of MN6 and the lower NMOS transistor are both grounded, and the positive output... Terminal OP is connected to the positive terminal of the differential output feedback, VFBP, through a 1 / 50 conversion circuit. The positive output terminal OP is connected to the drain of the upper PMOS transistor. The drain of MN6 and the drain of the seventh PMOS transistor, MP6, are interconnected to form the negative output terminal ON. The negative output terminal ON is connected to the negative terminal of the differential output feedback, VFBN, through a 1 / 50 conversion circuit. The sources of MP6 and the upper PMOS transistor are both connected to the power supply voltage. The gate of MP6 is connected to the negative output terminal ON through the 11th capacitor, C11. The gate of the upper PMOS transistor is connected to the positive output terminal OP through the 21st capacitor, C21.

[0008] The drain of MN0 is connected to the drain of the fifth PMOS transistor MP4 and the source of the fifth NMOS transistor MN4. The source of MP4 and the drain of MN4 are interconnected and then connected to the gate of MP7. The drain of MN1 is connected to the drain of the sixth PMOS transistor MP5 and the source of the sixth NMOS transistor MN5. The source of MP5 and the drain of MN5 are interconnected and then connected to the gate of MP6. The gates of MP4 and MN5 are both connected to the third positive bias terminal vbp3. The gates of MN4 and MP5 are interconnected and then connected to the third negative bias terminal vbn3.

[0009] The gate of the upper PMOS transistor is connected to the drain of the third PMOS transistor MP2. The source of MP2 is connected to the drain of the first PMOS transistor MP0. The source of MP0 is connected to the power supply voltage terminal. The gate of MP6 is connected to the drain of the fourth PMOS transistor MP3. The source of MP3 is connected to the drain of the second PMOS transistor MP1. The source of MP1 is connected to the power supply voltage terminal. The gates of MP2 and MP3 are interconnected and then connected to the second positive bias terminal vbp2. The gates of MP0 and MP1 are interconnected and then connected to the output terminal CMFB of the common-mode feedback amplifier. The negative input terminal of the common-mode feedback amplifier is connected to the output common-mode terminal (vfbp+vfbn) / 2. The positive input terminal of the common-mode feedback amplifier is connected to the reference output common-mode voltage terminal vcmo.

[0010] Let IS0 be the current flowing through Mbp0, IS1 be the current flowing through Mbp1, ID1 be the current flowing through MP0 and MP1, I0 be the current flowing through M0, I1 be the current flowing through M1, IS3 be the current flowing through MN2 and MN3, I3 be the current flowing out of the drain interconnect node of M2 and M5, and I4 be the current flowing out of the drain interconnect node of M3 and M6. When I0>I1, I3>I4, I0+I4+ID1≈IS3, I1+I3+ID1≈IS3, and points x and y will not be pulled to the limit state. At this time, the common-mode feedback loop will adjust the CMFB voltage until vcmo = 1 / 2(vfbn+vfbp). At this time, vc is very high, and M4 is turned off. In this process, inp-inn = vfbp-vfbn is established.

[0011] The common-mode comparator circuit in the common-mode startup circuit includes an amplifier input pair composed of PMOS transistors M7 (7th) and M8 (8th). The gate of M7 is connected to the output common-mode terminal (vfbp+vfbn) / 2, and the gate of M8 is connected to the reference output common-mode voltage terminal vcmo. The sources of both M7 and M8 are connected to the drain of PMOS transistor M6 (6th). The source of M6 is connected to the power supply voltage terminal, and the gate of M6 is connected to the first positive bias terminal vbp1. The drain of M8 is grounded. The drain of M8 is connected to the drain and gate of NMOS transistor M9 (number 9). The source of M9 is grounded. The gate of M9 is connected to the gate of NMOS transistor M10 (number 10). The source of M10 is grounded. The drain of M10, the drain of PMOS transistor M11 (number 11), and the drain and gate of PMOS transistor M12 (number 12) are interconnected to form the control voltage terminal vc. The sources of M11 and M12 are both connected to the power supply voltage terminal. The gate of M11 is connected to the first positive bias terminal vbp1.

[0012] The technical effects of this invention are as follows: This invention provides a differential mode start-up circuit for a fully differential gain amplifier, from... Figure 2 The simulation results show that during the common-mode startup process, the currents of the signal input pair and the feedback input pair remain balanced, avoiding the circuit stabilizing in the undesirable state where the output is at its highest and the feedback input is at its lowest due to certain nodes being pulled to their limits. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a differential mode start-up circuit structure for implementing the fully differential gain amplifier of the present invention.

[0014] Figure 2 yes Figure 1 A schematic diagram of the simulation results of the circuit's operating state. Figure 2 The horizontal axis represents time, and the vertical axis, from bottom to top, represents voltage V (mV), V (V), V (V), I (uA). Figure 2 The first descending and rising curve from bottom to top is the "vfbp-vfbn" waveform; the second straight line is the "inp-inn" waveform; the third descending and flattening line is the "vc" waveform; the fourth straight line is the "vcmo" waveform; the fifth descending and lowering line is the "(vfbp+vfbn) / 2" waveform; the sixth descending and flattening line at a lower position is the "I3" waveform; and the seventh descending and flattening line at a higher position is the "I4" waveform.

[0015] Figure 3 yes Figure 1 A schematic diagram of the common-mode comparator circuit in the common-mode startup circuit involved in the "vc" signal.

[0016] The reference numerals in the attached diagram are listed below: M0~M6 - PMOS transistors numbered 0 to 6 ( Figure 1M0 and M1 form a differential input pair, M2 and M3 form a feedback input pair, M5 and M6 within the dashed box form an additional input pair, and M4 is a control switch controlled by the VC signal. Figure 3 (Generated by the circuit in the middle); M6~M8 - PMOS transistors No. 6 to No. 8 ( Figure 3 In the amplifier configuration, M6's gate is connected to the first positive bias terminal vbp1, and M7 and M8 form the amplifier input pair; M10 - NMOS transistors 9 to 10; M11 to M12 - PMOS transistors 11 to 12; Mbp0 to Mbp1 - first bias PMOS transistors to second bias PMOS transistors; MP0 to MP6 - first PMOS transistors to seventh PMOS transistors; MN0 to MN6 - first NMOS transistors to seventh NMOS transistors; C11 to C12 - capacitors 11 to 12; C21 to C22 - capacitors 21 to 22; inp - differential input positive terminal; inn - differential input negative terminal; vfbp - differential output feedback positive terminal; vfbn - differential output feedback negative terminal; vc - Control voltage terminal; vcmo - Reference output common-mode voltage terminal; (vfbp+vfbn) / 2 - Differential output related terminal or output common-mode terminal; vbp1~vbp3 - First to third positive bias terminals; vbn1~vbn3 - First to third negative bias terminals; CMFB - Common-mode feedback amplifier output terminal; op - Node op or positive output terminal; on - Node on or negative output terminal; x - Node x; y - Node y; ISO - First current; IS1 - Second current (tail current of feedback input pair transistors M2 and M3); ID1 - Third current; IS3 - Fourth current; I0~I1 - Current number 0 to current number 1; I3~I4 - Current number 3 to current number 4; 1 / 50-1 / 50 conversion circuit. Detailed Implementation

[0017] The following is in conjunction with the attached diagram ( Figures 1-3 The invention will be described in the following sections and examples.

[0018] Figure 1 This is a schematic diagram of a differential mode start-up circuit structure for implementing the fully differential gain amplifier of the present invention. Figure 2 yes Figure 1 A schematic diagram of the simulation results of the circuit's operating state. Figure 3 yes Figure 1 A schematic diagram of the common-mode comparator circuit in the common-mode startup circuit involved in the "vc" signal. (Reference) Figures 1 to 3As shown, a differential mode startup circuit for a fully differential gain amplifier is characterized by adding an additional input pair consisting of a fifth PMOS transistor M5 and a sixth PMOS transistor M6 to the feedback input pair consisting of a second PMOS transistor M2 and a third PMOS transistor M3. The gate of M5 is connected to the positive differential input terminal inp, and the gate of M6 is connected to the negative differential input terminal inn. The common source terminals of M5 and M6 are connected to the common source terminals of M2 and M3 through a fourth PMOS transistor M4, which acts as a control switch controlled by a VC signal. The VC signal is generated by the common mode startup circuit. The sources of transistors M2, M3, and M4 are all connected to the drain of the second biased PMOS transistor Mbp1. The source of Mbp1 is connected to the power supply voltage terminal, and the gate of Mbp1 is connected to the first positive bias terminal vbp1. The gate of M2 is connected to the positive terminal of the differential output feedback vfbp, and the gate of M3 is connected to the negative terminal of the differential output feedback vfbn. The gate of M4 is connected to the control voltage terminal vc, and the drain of M4 is connected to the common source terminal of M5 and M6. The drains of M2 and M5 are both connected to the drain of the fourth NMOS transistor MN3. The gate of MN3 is interconnected with the gate of the third NMOS transistor MN2 and then connected to the first negative bias terminal vbn. 1. Both MN3 and MN2 have their sources grounded. Both M3 and M6 have their drains connected to the drain of MN2. The drain of MN2 is connected to the drain of PMOS transistor M0 (number 0). The drain of MN3 is connected to the drain of PMOS transistor M1 (number 1). Both M0 and M1 have their sources connected to the drain of the first biased PMOS transistor Mbp0. The source of Mbp0 is connected to the power supply voltage terminal. The gate of Mbp0 is connected to the first positive bias terminal vbp1. The gate of M0 is connected to the positive differential input terminal inp. The gate of M0 is connected to the negative differential input terminal inn. The drain of MN2 is node x, and the drain of MN3 is node y.

[0019] Node x is connected to the source of the first NMOS transistor MN0, and node y is connected to the source of the second NMOS transistor MN1. The gates of MN0 and MN1 are interconnected and then connected to the second negative bias terminal vbn2. The drain of MN1 is interconnected with the gate of the seventh NMOS transistor MN6 and then connected to the drain of MN6 through the 12th capacitor C12. The drain of MN0 is interconnected with the gate of the lower NMOS transistor and then connected to the positive output terminal op through the 22nd capacitor C22. The drain of the lower NMOS transistor is connected to the positive output terminal op. The sources of MN6 and the lower NMOS transistor are both grounded, and the positive output... Terminal OP is connected to the positive terminal of the differential output feedback, VFBP, through a 1 / 50 conversion circuit. The positive output terminal OP is connected to the drain of the upper PMOS transistor. The drain of MN6 and the drain of the seventh PMOS transistor, MP6, are interconnected to form the negative output terminal ON. The negative output terminal ON is connected to the negative terminal of the differential output feedback, VFBN, through a 1 / 50 conversion circuit. The sources of MP6 and the upper PMOS transistor are both connected to the power supply voltage. The gate of MP6 is connected to the negative output terminal ON through the 11th capacitor, C11. The gate of the upper PMOS transistor is connected to the positive output terminal OP through the 21st capacitor, C21. The drain of MN0 is connected to the drain of the fifth PMOS transistor MP4 and the source of the fifth NMOS transistor MN4. The source of MP4 and the drain of MN4 are interconnected and then connected to the gate of MP7. The drain of MN1 is connected to the drain of the sixth PMOS transistor MP5 and the source of the sixth NMOS transistor MN5. The source of MP5 and the drain of MN5 are interconnected and then connected to the gate of MP6. The gates of MP4 and MN5 are both connected to the third positive bias terminal vbp3. The gates of MN4 and MP5 are interconnected and then connected to the third negative bias terminal vbn3.

[0020] The gate of the upper PMOS transistor is connected to the drain of the third PMOS transistor MP2. The source of MP2 is connected to the drain of the first PMOS transistor MP0. The source of MP0 is connected to the power supply voltage terminal. The gate of MP6 is connected to the drain of the fourth PMOS transistor MP3. The source of MP3 is connected to the drain of the second PMOS transistor MP1. The source of MP1 is connected to the power supply voltage terminal. The gates of MP2 and MP3 are interconnected and then connected to the second positive bias terminal vbp2. The gates of MP0 and MP1 are interconnected and then connected to the output terminal CMFB of the common-mode feedback amplifier. The negative input terminal of the common-mode feedback amplifier is connected to the output common-mode terminal (vfbp+vfbn) / 2. The positive input terminal of the common-mode feedback amplifier is connected to the reference output common-mode voltage terminal vcmo. Let IS0 be the current flowing through Mbp0, IS1 be the current flowing through Mbp1, ID1 be the current flowing through MP0 and MP1, I0 be the current flowing through M0, I1 be the current flowing through M1, IS3 be the current flowing through MN2 and MN3, I3 be the current flowing out of the drain interconnect node of M2 and M5, and I4 be the current flowing out of the drain interconnect node of M3 and M6. When I0>I1, I3>I4, I0+I4+ID1≈IS3, I1+I3+ID1≈IS3, and points x and y will not be pulled to the limit state. At this time, the common-mode feedback loop will adjust the CMFB voltage until vcmo = 1 / 2(vfbn+vfbp). At this time, vc is very high, and M4 is turned off. In this process, inp-inn = vfbp-vfbn is established. The common-mode startup circuit is a VC signal generation circuit, including an amplifier input pair composed of PMOS transistor M7 (7th) and PMOS transistor M8 (8th). The gate of M7 is connected to the output common-mode terminal (VFBP+VFBN) / 2, and the gate of M8 is connected to the reference output common-mode voltage terminal VCM0. The sources of both M7 and M8 are connected to the drain of PMOS transistor M6 (6th). The source of M6 is connected to the power supply voltage terminal, and the gate of M6 is connected to the first positive bias terminal VBP1. The drain of M8 is grounded. The drain of M8 is connected to the drain and gate of NMOS transistor M9 (number 9). The source of M9 is grounded. The gate of M9 is connected to the gate of NMOS transistor M10 (number 10). The source of M10 is grounded. The drain of M10, the drain of PMOS transistor M11 (number 11), and the drain and gate of PMOS transistor M12 (number 12) are interconnected to form the control voltage terminal vc. The sources of M11 and M12 are both connected to the power supply voltage terminal. The gate of M11 is connected to the first positive bias terminal vbp1.

[0021] The differential-mode startup circuit of this invention addresses the problem in fully differential gain amplifiers with common-mode startup circuits where differential-mode startup may cause the circuit to stabilize in an undesirable state where one output is highest and the other lowest. Figure 1 A pair of input transistors M5 and M6 have been added within the dashed box. They are controlled by differential inputs inp and inn. The control signal vc generated by the original common-mode start-up circuit controls switch M4.

[0022] When the initial common-mode output is high, VC is turned on. Since M5 and M6 also distribute current, when I0 > I1, I3 > I4, I0 + I4 + ID1 ≈ IS3, I1 + I3 + ID1 ≈ IS3. Points x and y will not be pulled to their limits. At this time, the common-mode feedback loop will adjust the CMFB voltage until vcmo = 1 / 2(vfbn + vfbp). At this point, VC is very high, M4 is turned off, and the circuit is established as inp - inn = vfbp - vfbn during this process. Therefore, this invention provides a differential-mode startup circuit solution for a fully differential gain amplifier structure with a common-mode startup circuit. Structurally, a pair of input transistors controlled by the input signal is added, so that the current of the signal input pair and the feedback input pair remains balanced during the common-mode startup process, avoiding the circuit stabilizing in an undesirable state where one end of the output is the highest and the other end is the lowest due to certain nodes being pulled to their limits. Figure 2 The simulation results prove this effect. Figure 3 The "vc" signal generation circuit uses the common-mode comparison circuit in the common-mode startup circuit of the fully differential gain amplifier.

[0023] It should be noted that the above embodiments only describe the case of a fully differential gain amplifier with a PMOS pair as input. For a conventional fully differential gain amplifier, an NMOS pair can also be used as input. Based on a similar principle, those skilled in the art can also configure a differential-mode startup circuit for a fully differential gain amplifier with an NMOS pair as input to help the fully differential gain amplifier with a common-mode startup circuit avoid the undesirable state of the circuit stabilizing at one output end being the highest and the other end being the lowest during the common-mode startup process, which is caused by certain nodes being pulled to their limits.

[0024] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A differential-mode start-up circuit for a fully differential gain amplifier, characterized in that, This includes adding an additional input pair consisting of PMOS transistors M5 and M6 to the feedback input pair consisting of PMOS transistors M2 (2nd) and M3 (3rd). The gate of M5 is connected to the positive differential input terminal inp, and the gate of M6 is connected to the negative differential input terminal inn. The common source terminals of M5 and M6 are connected to the common source terminals of M2 and M3 through PMOS transistor M4 (4th), which acts as a control switch controlled by the VC signal. The VC signal is generated by the common-mode comparator circuit in the common-mode startup circuit.

2. A differential-mode start-up circuit for a fully differential gain amplifier according to claim 1, characterized in that, The sources of transistors M2, M3, and M4 are all connected to the drain of the second biased PMOS transistor Mbp1. The source of Mbp1 is connected to the power supply voltage terminal, and the gate of Mbp1 is connected to the first positive bias terminal vbp1. The gate of M2 is connected to the positive terminal of the differential output feedback vfbp, and the gate of M3 is connected to the negative terminal of the differential output feedback vfbn. The gate of M4 is connected to the control voltage terminal vc, and the drain of M4 is connected to the common source terminal of M5 and M6. The drains of M2 and M5 are both connected to the drain of the fourth NMOS transistor MN3. The gate of MN3 is interconnected with the gate of the third NMOS transistor MN2 and then connected to the first negative bias terminal vbn.

1. Both MN3 and MN2 have their sources grounded. Both M3 and M6 have their drains connected to the drain of MN2. The drain of MN2 is connected to the drain of PMOS transistor M0 (number 0). The drain of MN3 is connected to the drain of PMOS transistor M1 (number 1). Both M0 and M1 have their sources connected to the drain of the first biased PMOS transistor Mbp0. The source of Mbp0 is connected to the power supply voltage terminal. The gate of Mbp0 is connected to the first positive bias terminal vbp1. The gate of M0 is connected to the positive differential input terminal inp. The gate of M1 is connected to the negative differential input terminal inn. The drain of MN2 is node x, and the drain of MN3 is node y.

3. A differential-mode start-up circuit for a fully differential gain amplifier according to claim 2, characterized in that, Node x is connected to the source of the first NMOS transistor MN0, and node y is connected to the source of the second NMOS transistor MN1. The gates of MN0 and MN1 are interconnected and then connected to the second negative bias terminal vbn2. The drain of MN1 is interconnected with the gate of the seventh NMOS transistor MN6 and then connected to the drain of MN6 through the 12th capacitor C12. The drain of MN0 is interconnected with the gate of the lower NMOS transistor and then connected to the positive output terminal op through the 22nd capacitor C22. The drain of the lower NMOS transistor is connected to the positive output terminal op. The sources of MN6 and the lower NMOS transistor are both grounded, and the positive output... Terminal OP is connected to the positive terminal of the differential output feedback, VFBP, through a 1 / 50 conversion circuit. The positive output terminal OP is connected to the drain of the upper PMOS transistor. The drain of MN6 and the drain of the seventh PMOS transistor, MP6, are interconnected to form the negative output terminal ON. The negative output terminal ON is connected to the negative terminal of the differential output feedback, VFBN, through a 1 / 50 conversion circuit. The sources of MP6 and the upper PMOS transistor are both connected to the power supply voltage. The gate of MP6 is connected to the negative output terminal ON through the 11th capacitor, C11. The gate of the upper PMOS transistor is connected to the positive output terminal OP through the 21st capacitor, C21.

4. A differential-mode start-up circuit for a fully differential gain amplifier according to claim 3, characterized in that, The drain of MN0 is connected to the drain of the fifth PMOS transistor MP4 and the source of the fifth NMOS transistor MN4. The source of MP4 and the drain of MN4 are interconnected and then connected to the gate of the PMOS transistor. The drain of MN1 is connected to the drain of the sixth PMOS transistor MP5 and the source of the sixth NMOS transistor MN5. The source of MP5 and the drain of MN5 are interconnected and then connected to the gate of MP6. The gates of MP4 and MN5 are both connected to the third positive bias terminal vbp3. The gates of MN4 and MP5 are interconnected and then connected to the third negative bias terminal vbn3.

5. A differential-mode start-up circuit for a fully differential gain amplifier according to claim 4, characterized in that, The gate of the upper PMOS transistor is connected to the drain of the third PMOS transistor MP2. The source of MP2 is connected to the drain of the first PMOS transistor MP0. The source of MP0 is connected to the power supply voltage terminal. The gate of MP6 is connected to the drain of the fourth PMOS transistor MP3. The source of MP3 is connected to the drain of the second PMOS transistor MP1. The source of MP1 is connected to the power supply voltage terminal. The gates of MP2 and MP3 are interconnected and then connected to the second positive bias terminal vbp2. The gates of MP0 and MP1 are interconnected and then connected to the output terminal CMFB of the common-mode feedback amplifier. The negative input terminal of the common-mode feedback amplifier is connected to the output common-mode terminal (vfbp + vfbn) / 2. The positive input terminal of the common-mode feedback amplifier is connected to the reference output common-mode voltage terminal vcmo.

6. A differential-mode start-up circuit for a fully differential gain amplifier according to claim 5, characterized in that, ... The current flowing through Mbp0 is IS0, the current flowing through Mbp1 is IS1, the current flowing through MP0 and MP1 is ID1, the current flowing through M0 is I0, the current flowing through M1 is I1, the current flowing through MN2 and MN3 is IS3, the current flowing out of the drain interconnect node of M2 and M5 is I3, and the current flowing out of the drain interconnect node of M3 and M6 is I4. When I0>I1, I3>I4, I0+I4+ID1≈IS3, I1+I3+ID1≈IS3, and points x and y will not be pulled to the limit state. At this time, the common-mode feedback loop will adjust the CMFB voltage until vcmo=1 / 2(vfbn+vfbp). At this time, vc is very high, and M4 is turned off. In this process, inp-inn=vfbp-vfbn is established.

7. A differential-mode start-up circuit for a fully differential gain amplifier according to claim 6, characterized in that, The common-mode comparator circuit in the common-mode startup circuit includes an amplifier input pair composed of PMOS transistor M7 (7th) and PMOS transistor M8 (8th), with the gate of M7 connected to the output common-mode terminal (vfbp+). vfbn) / 2, the gate of M8 is connected to the reference output common-mode voltage terminal vcmo, the sources of M7 and M8 are both connected to the drain of the 6th PMOS transistor M6, the source of M6 is connected to the power supply voltage terminal, the gate of M6 is connected to the first positive bias terminal vbp1, the drain of M7 is grounded, the drain of M8 is connected to the drain and gate of the 9th NMOS transistor M9 respectively, the source of M9 is grounded, the gate of M9 is connected to the gate of the 10th NMOS transistor M10, the source of M10 is grounded, the drain of M10, the drain of the 11th PMOS transistor M11, the drain and gate of the 12th PMOS transistor M12 are interconnected to form the control voltage terminal vc, the sources of M11 and M12 are both connected to the power supply voltage terminal, and the gate of M11 is connected to the first positive bias terminal vbp1.

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