Segmented single slope analog-to-digital conversion method and apparatus, single slope ADC and storage medium

Abstract

This application discloses a segmented single-slope analog-to-digital conversion method, apparatus, single-slope ADC, and storage medium. The method includes acquiring multiple current coarse-adjustment decision reference values ​​for quantizing the target analog input signal during a coarse-adjustment decision stage. Each current coarse-adjustment decision reference value is a reference value corresponding to the original coarse-adjustment decision reference value, obtained by shifting the original coarse-adjustment decision reference value downwards based on the time delay data of the target ADC comparator. The target analog input signal is then subjected to a first quantization process in the coarse-adjustment decision stage based on the multiple current coarse-adjustment decision reference values ​​to obtain a target decision sub-interval, thereby performing analog-to-digital conversion on the target analog input signal. This application adjusts the original coarse-adjustment decision reference value downwards based on the comparator's time delay data during the coarse-adjustment decision stage, leaving redundancy for the comparator and avoiding coding dead zones and duplicate codes at the boundaries between sub-intervals during quantization. This optimizes the linearity of the ADC and improves its reliability.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a segmented single-slope analog-to-digital conversion method, apparatus, single-slope ADC, and storage medium. Background Technology

[0002] A single-slope ADC (Analog-to-Digital Converter) typically includes a comparator, a ramp generator, a counter, and a storage unit. Its working principle is to compare the input analog voltage signal with a single-slope signal, convert the input voltage information into time information, and then convert the time information into digital code, thereby realizing the conversion of analog signals into digital signals.

[0003] Because the conversion time of ordinary single-slope ADCs is relatively long, a segmented single-slope ADC is proposed based on the single-slope ADC. Before quantizing the input analog voltage signal using a single-slope signal, the full scale is first divided into several sub-intervals. After determining the sub-interval to which the input analog voltage signal belongs, the input analog voltage signal is then quantized using a single-slope signal within that sub-interval, converting the input analog voltage signal into the corresponding digital code.

[0004] However, in practical applications, the comparators in ADCs usually have a time delay. That is, when the digital code that theoretically corresponds to the input analog voltage signal arrives, the comparator does not flip due to the time delay, but flips with a delay. This will lead to coding dead zones and duplicate codes at the boundaries between sub-intervals during quantization. Summary of the Invention

[0005] This application provides a segmented single-slope analog-to-digital conversion method, apparatus, single-slope ADC, and storage medium, aiming to solve the problem in the prior art that due to the time delay of the comparator, there are coding dead zones and duplicate codes at the boundaries between sub-intervals during quantization.

[0006] In a first aspect, this application provides a piecewise single-slope modular conversion method, which includes:

[0007] Multiple current coarse adjustment decision reference values ​​are obtained for quantizing the target analog input signal in the coarse adjustment decision stage. The multiple current coarse adjustment decision reference values ​​are obtained by shifting the multiple original coarse adjustment decision reference values ​​downward based on the time delay data of the comparator in the target ADC, and each original coarse adjustment decision reference value corresponds to one-to-one with each original coarse adjustment decision reference value. Every two adjacent current coarse adjustment decision reference values ​​constitute a decision sub-interval in the coarse adjustment decision stage.

[0008] Based on multiple existing coarse adjustment decision benchmarks, the target analog input signal is subjected to the first quantization process in the coarse adjustment decision stage to obtain the target decision sub-interval corresponding to the target analog input signal, so as to perform analog-to-digital conversion on the target analog input signal within the target decision sub-interval.

[0009] In one possible implementation of this application, before obtaining multiple current coarse adjustment decision reference values ​​for quantizing the target analog input signal in the coarse adjustment decision stage, the method includes:

[0010] The downward offset is obtained based on the time delay data of the comparator in the target ADC and the preset redundancy; the redundancy is greater than or equal to the time delay data.

[0011] Based on the downward offset, multiple original coarse adjustment decision benchmark values ​​are respectively offset downward to obtain multiple corresponding current coarse adjustment decision benchmark values.

[0012] In one possible implementation of this application, before obtaining multiple current coarse adjustment decision reference values ​​for quantizing the target analog input signal in the coarse adjustment decision stage, the method includes:

[0013] Based on the conversion range of the target ADC and the preset number of coarse adjustment intervals, multiple reference voltage values ​​are obtained; the number of multiple reference voltage values ​​matches the number of coarse adjustment intervals.

[0014] Based on the maximum conversion voltage of the target ADC and multiple reference voltage values, multiple original coarse adjustment decision benchmark values ​​are obtained.

[0015] In one possible implementation of this application, multiple reference voltage values ​​are obtained based on the conversion range of the target ADC and the preset number of coarse adjustment intervals, including:

[0016] The voltage difference is obtained by dividing the conversion range of the target ADC equally according to the number of coarse adjustment intervals;

[0017] Based on the preset initial reference voltage value and voltage difference, multiple reference voltage values ​​that form an arithmetic sequence are obtained.

[0018] In one possible implementation of this application, the target analog input signal is subjected to a first quantization process in the coarse adjustment decision stage based on multiple existing coarse adjustment decision benchmarks to obtain the target decision sub-interval corresponding to the target analog input signal, including:

[0019] Multiple coarse adjustment decision benchmark values ​​are compared with the target analog input signal in ascending order of size.

[0020] When the first coarse adjustment decision benchmark value among multiple coarse adjustment decision benchmark values ​​is greater than the target analog input signal, the first coarse adjustment decision benchmark value is recorded.

[0021] Based on the first current coarse adjustment judgment benchmark value, the current coarse adjustment judgment benchmark value that is adjacent to the first current coarse adjustment judgment benchmark value and is smaller than the first current coarse adjustment judgment benchmark value is determined as the second current coarse adjustment judgment benchmark value.

[0022] Based on the first and second coarse adjustment decision benchmark values, the target decision sub-interval corresponding to the target analog input signal is obtained.

[0023] In one possible implementation of this application, the target analog input signal is subjected to a first quantization process in the coarse adjustment decision stage based on multiple existing coarse adjustment decision benchmark values ​​to obtain the target decision sub-interval corresponding to the target analog input signal. Then, the method includes:

[0024] Within the target decision sub-interval, the target analog input signal undergoes a second quantization process in the fine-tuning decision stage to obtain the digital signal corresponding to the target analog input signal.

[0025] In one possible implementation of this application, within the target decision sub-interval, the target analog input signal undergoes a second quantization process in the fine-tuning decision stage to obtain the digital signal corresponding to the target analog input signal, including:

[0026] Based on the second original coarse adjustment decision reference value corresponding to the second current coarse adjustment decision reference value, the preset downward redundancy data, and the performance parameters of the target ADC, the ramp signal of the target ADC is obtained; the second current coarse adjustment decision reference value is the minimum value of the target decision sub-interval, and the ramp signal increases with the increase of the counter value of the target ADC;

[0027] The control count value starts counting from the initial value of the ramp signal;

[0028] When the ramp signal is greater than the target analog input signal, the count value of the record counter is used as the digital signal corresponding to the target analog input signal.

[0029] In one possible implementation of this application, the ramp signal of the target ADC is obtained based on the second original coarse adjustment decision reference value corresponding to the second current coarse adjustment decision reference value, preset downward redundancy data, and the performance parameters of the target ADC, including:

[0030] The initial value of the ramp signal is obtained based on the second original coarse adjustment decision benchmark value and the downward redundancy data;

[0031] Based on the performance parameters of the target ADC, the growth amplitude of the ramp signal as the count value increases is obtained.

[0032] Secondly, this application also provides a segmented single-slope analog-to-digital converter, which includes:

[0033] The acquisition module is used to acquire multiple current coarse adjustment decision reference values ​​for quantizing the target analog input signal during the coarse adjustment decision stage. The multiple current coarse adjustment decision reference values ​​are obtained by shifting multiple original coarse adjustment decision reference values ​​downward based on the time delay data of the comparator in the target ADC, and each original coarse adjustment decision reference value corresponds to one-to-one with each original coarse adjustment decision reference value. Every two adjacent current coarse adjustment decision reference values ​​constitute a decision sub-interval in the coarse adjustment decision stage.

[0034] The coarse adjustment decision module is used to perform the first quantization process of the target analog input signal in the coarse adjustment decision stage based on multiple existing coarse adjustment decision benchmark values, to obtain the target decision sub-interval corresponding to the target analog input signal, so as to perform analog-to-digital conversion on the target analog input signal within the target decision sub-interval.

[0035] Thirdly, this application also provides a single-slope ADC, which includes a memory and a processor. The memory is used to store a computer program, and when the computer program is executed by the processor, it is used to implement the segmented single-slope analog-to-digital conversion method in the first aspect or any possible implementation of the first aspect.

[0036] Fourthly, this application also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the steps of the piecewise single-slope analog-to-digital conversion method in the first aspect or any possible implementation of the first aspect.

[0037] From the above, it can be concluded that this application has the following beneficial effects:

[0038] In this application, the coarse adjustment decision reference value used in the coarse adjustment decision of the target analog input signal is based on the comparator's time delay data. After adjusting the original coarse adjustment decision reference value downward, multiple current coarse adjustment decision reference values ​​are obtained, each corresponding to one of the original coarse adjustment decision reference values. The target analog input signal is then subjected to the first quantization process in the coarse adjustment decision stage using these multiple current coarse adjustment decision reference values ​​to obtain the target decision sub-interval corresponding to the target analog input signal. Then, the target analog input signal is subjected to subsequent analog-to-digital conversion within the target decision sub-interval. Since the original coarse adjustment decision reference value is adjusted downward based on the comparator's time delay data in the coarse adjustment decision stage, it is equivalent to leaving redundancy for the comparator in the coarse adjustment decision stage. Therefore, the problem of coding dead zone and duplicate codes at the boundary between sub-intervals during quantization due to the comparator's time delay is avoided, ensuring the correctness of the conversion result of the target analog input signal, thereby optimizing the linearity of the ADC and improving the reliability of the ADC. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in the description of this application will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0040] Figure 1 This is a flowchart illustrating a segmented single-slope analog-to-digital conversion method provided in an embodiment of this application.

[0041] Figure 2 This is a schematic diagram of the structure of an existing conventional ADC;

[0042] Figure 3 yes Figure 2 The diagram shown is a schematic of an analog-to-digital conversion of a typical ADC.

[0043] Figure 4 This is a schematic diagram of an existing piecewise single-slope ADC.

[0044] Figure 5 yes Figure 4 The diagram shows an analog-to-digital conversion schematic of a piecewise single-slope ADC.

[0045] Figure 6 This is a schematic diagram showing the correspondence between a single-slope signal and a digital signal in an ideal segmented single-slope ADC.

[0046] Figure 7 This is a schematic diagram showing the correspondence between a single-slope signal and a digital signal in a segmented single-slope ADC with downward redundant bits configured.

[0047] Figure 8 It is based on Figure 7 The diagram shows an analog-to-digital converter (ADC) performing an analog-to-digital conversion on a ramp voltage.

[0048] Figure 9 This is a schematic diagram of an analog-to-digital conversion (ADC) performed according to the segmented single-slope ADC method provided in the embodiments of this application.

[0049] Figure 10 This is a schematic diagram of a segmented single-slope analog-to-digital converter provided in the embodiments of this application;

[0050] Figure 11 This is a schematic diagram of a single-slope ADC provided in the embodiments of this application. Detailed Implementation

[0051] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0052] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0053] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0054] Before introducing the segmented single-slope analog-to-digital conversion method, apparatus, single-slope ADC and storage medium of this application, the existing ADC unit will be described first.

[0055] Please see Figure 2 , Figure 2This is a schematic diagram of a typical existing ADC. The ADC includes a comparator, a ramp generator, a counter, and a storage unit. Its working principle is as follows: the counter updates the count value based on a preset frequency and step size. At the same time, the amplitude of the single ramp signal output by the ramp generator increases as the count value of the counter increases. The comparator compares the target analog input signal Vin with the single ramp signal output by the ramp generator. When the amplitude of the single ramp signal is greater than the amplitude of the target analog input signal Vin, the comparator flips, and the storage unit synchronously records the count value at this time to obtain the digital signal Dout, thereby realizing the conversion of the target analog input signal Vin into the digital signal Dout.

[0056] For example, assuming the ADC is a 10-bit ADC, its accuracy is 1 / 2. 10 Convert the maximum value n=2 10 Assuming the voltage range of the ramp generator is 0V-0.8V, then the least significant bit (LSB) of this ADC is 0.8V / 2. 10 =781.25uV, which means that when the counter value increases once, the voltage amplitude of the single ramp signal of the ramp generator increases by 781.25uV.

[0057] like Figure 3 As shown, Figure 3 yes Figure 2 The diagram shows a typical analog-to-digital conversion (ADC). Assuming the target analog input signal Vin = 796.1mV, when the counter starts counting from 0, and the counter value reaches 1020, the corresponding single-slope signal voltage amplitude is 781.25uV * 1020 = 796.875mV, which just exceeds the target analog input signal Vin. At this point, the comparator's output signal flips, and the storage unit synchronously records the counter value. Therefore, the digital signal Dout = 1020, thus achieving quantization between the target analog input signal 796.1mV and the digital signal 1020.

[0058] However, since a 10-bit ADC requires 1024 counts to complete one conversion, the conversion time is relatively long. Therefore, a segmented single-slope ADC was developed, such as... Figure 4 As shown, Figure 4This is a schematic diagram of an existing segmented single-slope ADC. This segmented single-slope ADC adds a reference voltage generator, multiple gating switches, and a logic controller to the basic ADC. Before quantizing the target analog input signal (Vinp-Vinn) using the single-slope signal of the ramp generator, it first divides the full scale of the ADC into multiple sub-intervals, then performs coarse adjustment to determine which sub-interval the target analog input signal belongs to, and then performs fine adjustment to finally quantize the target analog input signal using the small single-slope signal within that sub-interval.

[0059] Assuming the full scale of this segmented single-slope ADC is divided into 8 sub-intervals, and this segmented single-slope ADC is also a 10-bit ADC, then for each sub-interval, the counter only needs to count 1024 / 8 = 128 times to complete the quantization.

[0060] Please see Figure 5 , Figure 5 yes Figure 4 The diagram shown illustrates an analog-to-digital conversion of a piecewise single-slope ADC. It assumes the full-scale range of this piecewise single-slope ADC is 0V-0.8V, and the number of sub-intervals, k, is 2. 3 =8, then the counter for each sub-interval counts 2 times. 10-3 =2 7 =128. Meanwhile, it is assumed that the multiple reference voltages generated by the reference voltage generator are vref_0 = 0V, vref_1 = 0.1V, ..., vref_7 = 0.7V.

[0061] In the coarse-tuning decision stage, the voltage amplitude of the single-ramp signal from the ramp generator is ramp = 0.8V. The differences between this single-ramp signal's voltage amplitude and each reference voltage are ramp-vref_0 = 0.8V, ramp-vref_1 = 0.7V, ..., ramp-vref_7 = 0.1V, respectively. The logic controller controls the closing of each selector switch, iterating through each reference voltage. When the difference between the voltage amplitude of the single-ramp signal from the ramp generator and the reference voltage is greater than the target analog input signal (Vinp-Vinn), the comparator's output signal flips. The closed selector switch and the reference voltage of the reference voltage generator are recorded at this time, thus obtaining the sub-interval range to which the target analog input signal (Vinp-Vinn) belongs. Figure 5 As shown, when c=1, the difference between the voltage amplitude ramp of the single ramp signal of the corresponding ramp generator and the reference voltage vref_1 is greater than the target analog input signal (Vinp-Vinn), and the output signal of the comparator flips. At this time, the gating switch associated with the reference voltage vref_1 is closed.

[0062] Then, in the fine-tuning decision stage, the voltage amplitude ramp of the single ramp signal from the ramp generator is no longer 0.8V, but a ramp signal rising from 0.7V to 0.8V. This ramp signal rises as the counter count increases. Within the sub-interval determined in the coarse-tuning decision stage, the counter counts from 896 to 1024. Since vref_1 = 0.1V, the sub-interval determined in the coarse-tuning decision stage is (ramp-vref_2, ramp-vref_1). That is, the small single ramp signal in the fine-tuning decision stage is a ramp rising from 0.6V to 0.7V. When the voltage amplitude ramp-vref of this small single ramp signal exceeds the target analog input signal (Vinp-Vinn), the comparator output signal flips, and the storage unit synchronously records the counter count value f, which is located between 896 and 1024. The final digital signal Dout = fc * 2 q .

[0063] Therefore, the voltage amplitude of the single-ramp signal from the ramp generator is crucial for determining the final quantization result. Figure 6 As shown, Figure 6 This is a schematic diagram illustrating the correspondence between a single-slope signal and a digital signal in an ideal segmented single-slope ADC. However, in practical applications, the reference voltage generated by the reference voltage generator has an offset and cannot be completely accurate. This leads to dead zones and duplicate codes at the boundaries between sub-intervals during quantization. Therefore, as... Figure 7 As shown, Figure 7 This is a schematic diagram showing the correspondence between a single-slope signal and a digital signal in a segmented single-slope ADC with downward redundant bits. In the prior art, the problem of quantization dead zone and duplicate codes at the boundary between sub-intervals caused by the offset of the reference voltage is overcome by introducing downward redundant bits into the single-slope signal.

[0064] Please see Figure 8 , Figure 8 It is based on Figure 7 The diagram shows an analog-to-digital converter (ADC) for a single-ramp signal. Assume the target analog input signal is 696.09375mV (=0.7V-781.25uV*5). During the coarse-adjustment stage, this target analog input signal is first determined to fall within the sub-interval [768, 896]. The correct digital output value corresponding to this target analog input signal should be 891. However, when the small single-ramp signal ramp-vref rises from 704 to 891, due to the comparator's delay, the comparator, which should have flipped, does not flip at this point. If the comparator's delay is 5 clock counts, the comparator will eventually flip when the count value reaches 896, meaning the digital signal corresponding to the target analog input signal 696.09375mV is 896.

[0065] In this way, within the sub-interval [768, 896], all target analog input signals with digital output values ​​greater than 891 will be quantized to the maximum quantization value of this sub-interval, i.e., 896, thus forming a 5 LSB-wide duplicate code interval between 891 and 896. Furthermore, if the target analog input signal is slightly larger than 0.7V by less than 1 LSB, due to the comparator delay, the analog input value that should correspond to the digital output value 897 will be quantized to 902, resulting in no target analog input value that can correspond to the digital output values ​​897 to 901, thus forming a 5 LSB-wide dead zone.

[0066] In view of the above problems, this application provides a segmented single-slope analog-to-digital conversion method, device, single-slope ADC and storage medium, which will be described in detail below.

[0067] First, this application provides a segmented single-slope analog-to-digital conversion method. The execution subject of this segmented single-slope analog-to-digital conversion method can be a segmented single-slope analog-to-digital conversion device, or a server device or physical host that integrates the segmented single-slope analog-to-digital conversion device.

[0068] This piecewise single-slope analog-to-digital conversion method can be applied to piecewise single-slope ADCs to control the ADC to quantize the target analog input signal and obtain the corresponding digital signal. The piecewise single-slope analog-to-digital conversion method includes:

[0069] Multiple current coarse adjustment decision reference values ​​are obtained for quantizing the target analog input signal in the coarse adjustment decision stage. The multiple current coarse adjustment decision reference values ​​are obtained by shifting the multiple original coarse adjustment decision reference values ​​downward based on the time delay data of the comparator in the target ADC, and each original coarse adjustment decision reference value corresponds to one-to-one with each original coarse adjustment decision reference value. Every two adjacent current coarse adjustment decision reference values ​​constitute a decision sub-interval in the coarse adjustment decision stage.

[0070] Based on multiple existing coarse adjustment decision benchmarks, the target analog input signal is subjected to the first quantization process in the coarse adjustment decision stage to obtain the target decision sub-interval corresponding to the target analog input signal, so as to perform analog-to-digital conversion on the target analog input signal within the target decision sub-interval.

[0071] like Figure 1 As shown, Figure 1 This is a flowchart illustrating a segmented single-slope analog-to-digital conversion method provided in an embodiment of this application. It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here. This segmented single-slope analog-to-digital conversion method may include the following multiple steps.

[0072] Step S101: Obtain multiple current coarse adjustment decision reference values ​​for quantizing the target analog input signal in the coarse adjustment decision stage; the multiple current coarse adjustment decision reference values ​​are obtained by shifting multiple original coarse adjustment decision reference values ​​downward based on the time delay data of the comparator in the target ADC, and each original coarse adjustment decision reference value corresponds to one-to-one; every two adjacent current coarse adjustment decision reference values ​​constitute a decision sub-interval in the coarse adjustment decision stage.

[0073] Understandably, for a piecewise single-slope ADC, the process of quantizing the input analog quantity can be divided into a coarse adjustment decision process and a fine adjustment decision process. For the coarse adjustment decision process, a sub-interval of coarse adjustment decision can be formed by two adjacent original coarse adjustment decision reference values ​​among multiple original coarse adjustment decision reference values, and the difference between two adjacent original coarse adjustment decision reference values ​​is equal. In other words, multiple original coarse adjustment decision reference values ​​can form an arithmetic sequence.

[0074] In this embodiment, the multiple current coarse adjustment decision benchmark values ​​are obtained by shifting the multiple original coarse adjustment decision benchmark values ​​downward according to the time delay data of the comparator in the target ADC. That is, each original coarse adjustment decision benchmark value is reduced accordingly according to the time delay data of the comparator in the target ADC, so as to obtain the current coarse adjustment decision benchmark value that corresponds one-to-one with each original coarse adjustment decision benchmark value.

[0075] It can be understood that the current coarse adjustment decision benchmark value is obtained by subtracting the time delay data of the comparator in the target ADC from the corresponding original coarse adjustment decision benchmark value. Since two adjacent original coarse adjustment decision benchmark values ​​can form a sub-interval of coarse adjustment decision, after the original coarse adjustment decision benchmark value is shifted downward, two adjacent current coarse adjustment decision benchmark values ​​can also form a new decision sub-interval in the coarse adjustment decision stage. The size of the range of this decision sub-interval is the same as that of the atomic interval, but the values ​​at both ends are smaller than those of the atomic interval, and the smaller amount is the time delay data of the comparator in the target ADC.

[0076] Because the decision sub-interval formed by two adjacent current coarse adjustment decision reference values ​​in the coarse adjustment decision stage is generally shifted downwards compared to the corresponding sub-interval formed by two adjacent original coarse adjustment decision reference values, for some target analog input signals, especially target analog input signals near the boundary between sub-intervals, the target analog input signal that would originally be decided to the original first sub-interval in the coarse adjustment decision stage may be decided to the second decision sub-interval. Here, the second decision sub-interval is the sub-interval corresponding to the original second sub-interval, which is adjacent to the original first sub-interval and smaller than the original first sub-interval.

[0077] Step S102: Perform the first quantization process of the coarse adjustment decision stage on the target analog input signal according to multiple current coarse adjustment decision reference values ​​to obtain the target decision sub-interval corresponding to the target analog input signal, so as to perform analog-to-digital conversion on the target analog input signal within the target decision sub-interval.

[0078] In this embodiment, after determining multiple current coarse adjustment decision reference values ​​in step S101, each decision sub-interval in the coarse adjustment decision stage can be determined. The target analog input signal can then be compared with the endpoint values ​​of each decision sub-interval. When the endpoint value of a certain decision sub-interval, i.e., a current coarse adjustment decision reference value, is greater than the target analog input signal, the comparator's output signal flips. At this point, the decision sub-interval can be determined as the target decision sub-interval corresponding to the target analog input signal. After determining the target decision sub-interval corresponding to the target analog input signal, a small single-slope signal can be used within this target decision sub-interval to perform fine adjustment decision on the target analog input signal. When the small single-slope signal exceeds the target analog input signal, the comparator's output signal flips. At this point, the digital signal corresponding to the target analog input signal can be determined based on the counter value of the target ADC.

[0079] In this embodiment, the coarse adjustment decision reference value used in the coarse adjustment decision of the target analog input signal is based on the comparator's time delay data. After adjusting the original coarse adjustment decision reference value downward, multiple current coarse adjustment decision reference values ​​are obtained, each corresponding to one of the original coarse adjustment decision reference values. The target analog input signal is then subjected to the first quantization process in the coarse adjustment decision stage using these multiple current coarse adjustment decision reference values ​​to obtain the target decision sub-interval corresponding to the target analog input signal. Then, the target analog input signal is subjected to subsequent analog-to-digital conversion within the target decision sub-interval. Since the original coarse adjustment decision reference value is adjusted downward based on the comparator's time delay data in the coarse adjustment decision stage, it is equivalent to leaving redundancy for the comparator in the coarse adjustment decision stage. Therefore, it can avoid the problem of coding dead zones and duplicate codes at the boundaries between sub-intervals during quantization due to the comparator's time delay, ensuring the correctness of the conversion result of the target analog input signal, thereby optimizing the linearity of the ADC and improving the reliability of the ADC.

[0080] Next, continue with Figure 1 The steps shown are explained in detail, as well as the specific implementation methods that may be used in practical applications.

[0081] In some embodiments of this application, before obtaining multiple current coarse adjustment decision reference values ​​for quantizing the target analog input signal during the coarse adjustment decision stage, the method may further include:

[0082] The downward offset is obtained based on the time delay data of the comparator in the target ADC and the preset redundancy; the redundancy is greater than or equal to the time delay data.

[0083] Based on the downward offset, multiple original coarse adjustment decision benchmark values ​​are respectively offset downward to obtain multiple corresponding current coarse adjustment decision benchmark values.

[0084] Understandably, the time delay data of the comparator in the target ADC can be determined based on multiple experiments or past experience. The time delay data of the comparator may be different for different ADCs. For example, the time delay data may be 2 LSB, 5 LSB, 7 LSB, etc. Understandably, the specific value of the time delay data can be determined according to the actual application scenario, and no specific limitation is made here.

[0085] In this embodiment of the application, in order to avoid comparator delay caused by other interference, a redundancy is pre-configured for the time delay data of the comparator in the target ADC based on the time delay data of the comparator in the target ADC. That is, the downward offset of the original coarse adjustment decision reference value is the sum of the time delay data of the comparator in the target ADC and the preset redundancy.

[0086] To ensure sufficient redundancy for the comparator during the coarse-tuning decision stage, in this embodiment, the redundancy is set to be greater than or equal to the time delay data. When the redundancy is greater than the time delay data, the specific value of the redundancy can be selected according to actual needs and application scenarios. For example, if the time delay data is 2 LSBs, the redundancy can be set to any value such as 2 LSBs, 3 LSBs, or 5 LSBs.

[0087] For example, if the time delay data of the comparator in the target ADC is 5 LEB and the redundancy is set to 10 LSB, then the downward offset Δx is 15 LSB.

[0088] like Figure 9 As shown, Figure 9 This is a schematic diagram of analog-to-digital conversion (ADC) performed according to the segmented single-slope ADC method provided in the embodiments of this application. If the time delay data of the comparator in the target ADC is 5 LEB and the redundancy is set to 5 LSB, then the downward offset Δx is 10 LSB. The original coarse adjustment decision reference value is shifted downward based on this downward offset, meaning the original coarse adjustment decision reference value is shifted downward from ramp-vref to ramp-vref-Δx. For example... Figure 9The original coarse adjustment decision reference value is 0.8V. The current coarse adjustment decision reference value obtained by shifting it downward is the dashed line below the original coarse adjustment decision reference value, which is 0.8V-Δx. If the target ADC is a 10-bit ADC, the analog quantity corresponding to the downward shift Δx is 781.25uV*10=7.8125mV. Similarly, by shifting the original coarse adjustment decision reference value downward by Δx for each original coarse adjustment decision reference value, the corresponding current coarse adjustment decision reference value can be obtained.

[0089] In some embodiments of this application, before obtaining multiple current coarse adjustment decision reference values ​​for quantizing the target analog input signal during the coarse adjustment decision stage, the method may further include:

[0090] Based on the conversion range of the target ADC and the preset number of coarse adjustment intervals, multiple reference voltage values ​​are obtained; the number of multiple reference voltage values ​​matches the number of coarse adjustment intervals.

[0091] Based on the maximum conversion voltage of the target ADC and multiple reference voltage values, multiple original coarse adjustment decision benchmark values ​​are obtained.

[0092] In this embodiment of the application, the conversion range of the target ADC is determined based on the minimum and maximum conversion values ​​of the target ADC. For example, if the minimum conversion value of the target ADC is 0V and the maximum conversion value of the target ADC is 0.8V, then its corresponding conversion range is 0.8V. If the minimum conversion value of the target ADC is 0.5V and the maximum conversion value of the target ADC is 2.5V, then its corresponding conversion range is 2V.

[0093] Understandably, the number of coarse tone intervals can be selected according to the actual application scenario. The value of the number of coarse tone intervals can be any value greater than or equal to 2. Understandably, the larger the value of the number of coarse tone intervals, the smaller the count value of the counter in each coarse tone interval.

[0094] In one specific implementation, the conversion range of the target ADC can be evenly divided according to the number of coarse adjustment intervals to obtain the voltage difference; then, based on the preset initial reference voltage value and the voltage difference, multiple reference voltage values ​​forming an arithmetic sequence can be obtained.

[0095] For example, if the target ADC has a conversion range of 0.8V and the number of coarse adjustment intervals is 8, then the voltage difference obtained by dividing the target ADC's conversion range equally among the number of coarse adjustment intervals is 0.1V. Here, this voltage difference can be understood as the size of each coarse adjustment interval, which is also the voltage difference between two adjacent reference voltage values.

[0096] Assuming the initial reference voltage value in this embodiment is 0V, eight reference voltage values ​​can be determined based on this initial reference voltage value and the voltage difference. Since the difference between these eight reference voltage values ​​is a voltage difference, the difference between any two adjacent reference voltage values ​​is equal, meaning the eight reference voltage values ​​form an arithmetic sequence. In this embodiment, the eight reference voltage values, from smallest to largest, are vref_0 = 0V, vref_1 = 0.1V, vref_2 = 0.2V, ..., vref_7 = 0.7V.

[0097] It is understood that the multiple reference voltage values ​​in the embodiments of this application may be multiple reference voltage values ​​obtained by the logic control unit traversing each gating switch connected to the reference voltage generator.

[0098] After determining each reference voltage value, multiple original coarse adjustment decision benchmark values ​​can be obtained based on the maximum conversion voltage of the target ADC and multiple reference voltage values. For example, if the maximum conversion voltage of the target ADC is ramp, then the original coarse adjustment decision benchmark values ​​can be ramp-vref_7 = 0.1V, ..., ramp-vref_2 = 0.6V, ramp-vref_1 = 0.7V, ramp-vref_0 = 0.8V.

[0099] In some embodiments of this application, the first quantization process of the coarse adjustment decision stage is performed on the target analog input signal based on multiple current coarse adjustment decision benchmark values ​​to obtain the target decision sub-interval corresponding to the target analog input signal, which may further include:

[0100] Multiple coarse adjustment decision benchmark values ​​are compared with the target analog input signal in ascending order of size.

[0101] When the first coarse adjustment decision benchmark value among multiple coarse adjustment decision benchmark values ​​is greater than the target analog input signal, the first coarse adjustment decision benchmark value is recorded.

[0102] Based on the first current coarse adjustment judgment benchmark value, the current coarse adjustment judgment benchmark value that is adjacent to the first current coarse adjustment judgment benchmark value and is smaller than the first current coarse adjustment judgment benchmark value is determined as the second current coarse adjustment judgment benchmark value.

[0103] Based on the first and second coarse adjustment decision benchmark values, the target decision sub-interval corresponding to the target analog input signal is obtained.

[0104] In this embodiment, after shifting the original coarse adjustment decision reference value downward to obtain the corresponding current coarse adjustment decision reference value, the current coarse adjustment decision reference value can be compared with the target analog input signal. If the current coarse adjustment decision reference value is less than or equal to the target analog input signal, the current coarse adjustment decision reference value that is adjacent to the current coarse adjustment decision reference value and is greater than the current coarse adjustment decision reference value is compared with the target analog input signal until the first coarse adjustment decision reference value is greater than the target analog input signal. At the same time, the output signal of the comparator flips, and the currently connected gating switch and the first coarse adjustment decision reference value are recorded. The target decision sub-interval corresponding to the target analog input signal is determined based on the first coarse adjustment decision reference value and the adjacent coarse adjustment decision reference value that is less than it, i.e., the second coarse adjustment decision reference value. It can be understood that the second coarse adjustment decision reference value is the minimum value of the target decision sub-interval, i.e., the small endpoint value, and the first coarse adjustment decision reference value is the maximum value of the target decision sub-interval, i.e., the large endpoint value.

[0105] According to the description in the foregoing embodiment, after the original coarse adjustment decision reference value is shifted downward by the downward offset Δx, the original coarse adjustment decision reference value is shifted downward from ramp-vref to ramp-vref-Δx. Therefore, the current coarse adjustment decision reference value can be ramp-vref_7-Δx = 0.1V-Δx, ..., ramp-vref_2-Δx = 0.6V-Δx, ramp-vref_1-Δx = 0.7V-Δx, ramp-vref_0-Δx = 0.8V-Δx. If the target analog input signal is 696.09375mV, since:

[0106] 0.7V-7.8125mV=692.1875mV<696.09375mV<0.8V-7.8125mV=792.1875mV. Therefore, the target analog input signal 696.09375mV is slightly greater than 0.7V-Δx and less than 0.8V-Δx. Thus, its corresponding target decision sub-interval is [896, 1024].

[0107] In some embodiments of this application, the target analog input signal is subjected to a first quantization process in the coarse adjustment decision stage based on multiple current coarse adjustment decision benchmark values ​​to obtain the target decision sub-interval corresponding to the target analog input signal. The method may then further include:

[0108] Within the target decision sub-interval, the target analog input signal undergoes a second quantization process in the fine-tuning decision stage to obtain the digital signal corresponding to the target analog input signal.

[0109] Specifically, within the target decision sub-interval, the target analog input signal undergoes a second quantization process in the fine-tuning decision stage to obtain the digital signal corresponding to the target analog input signal, which may further include:

[0110] Based on the second original coarse adjustment decision reference value corresponding to the second current coarse adjustment decision reference value, the preset downward redundancy data, and the performance parameters of the target ADC, the ramp signal of the target ADC is obtained; the second current coarse adjustment decision reference value is the minimum value of the target decision sub-interval, and the ramp signal increases with the increase of the counter value of the target ADC;

[0111] The control count value starts counting from the initial value of the ramp signal;

[0112] When the ramp signal is greater than the target analog input signal, the count value of the record counter is used as the digital signal corresponding to the target analog input signal.

[0113] In this embodiment of the application, the ramp signal used for fine-tuning decision, namely the small single ramp signal, is the same as the signal before the downward offset processing. That is, the ramp signal is still based on the second original coarse-tuning decision reference value corresponding to the second current coarse-tuning decision reference value, and rises as the counter count value increases.

[0114] Specifically, to avoid coding dead zones and duplicate codes caused by deviations in the reference voltage, in this embodiment, downward redundant data is pre-set for the ramp signal. Based on the second original coarse adjustment decision reference value, the second original coarse adjustment decision reference value is offset downward according to the downward redundant data to obtain the initial value of the ramp signal. Then, based on the performance parameters of the target ADC, such as accuracy and conversion range, the growth amplitude of the ramp signal as the count value increases is calculated. Thus, when the counter value increases each time, the ramp signal can synchronously increase the corresponding growth amplitude in response to the synchronization clock.

[0115] In this embodiment, after the counter starts counting from the initial value of the ramp signal, when the ramp signal is less than or equal to the target analog input signal, the counter increases by a preset step size, and the voltage amplitude of the ramp signal increases synchronously based on its growth amplitude. When the ramp signal is greater than the target analog input signal, the current counter value is recorded, and the current counter value is used as the digital signal corresponding to the target analog input signal to realize the quantization of the target analog input signal.

[0116] For example, for a 10-bit ADC with a conversion range of 0V-0.8V, its increment is 0.8V / 2. 10 =781.25uV, which means that when the counter value increases once, the voltage amplitude of the ramp signal increases by 781.25uV.

[0117] Please continue reading. Figure 9 If the target analog input signal is 696.09375mV, after shifting the original coarse adjustment decision reference value downwards, Figure 9 The multiple dashed lines in the text represent the current coarse adjustment judgment benchmark values, based on... Figure 9 As can be seen, the target analog input signal 696.09375mV, based on the method of this application embodiment, will be judged to the sub-interval [0.7-Δx, 0.8-Δx], i.e. [896, 1024], in the coarse adjustment decision stage. In the fine adjustment decision stage, due to the existence of the downward redundant bit, when the ramp signal ramp-vref increases from 0.65V (corresponding to digital value 832) to 0.8V (corresponding to digital value 1024), when the counter count reaches 891, the ramp signal ramp-vref is greater than the target analog input signal 696.09375mV, and the comparator output signal flips. At the same time, because the comparator has a delay of 5 LSBs, the final digital signal corresponding to the target analog input signal 696.09375mV is 896. Furthermore, if the target analog input signal is slightly greater than 696.09375mV, when quantizing the target analog input signal greater than 696.09375mV, it will be converted into the corresponding digital signal such as 897, 898, 899, etc., according to the actual situation, and the problem of multiple analog signals near the boundary of sub-intervals being encoded into the same digital signal will not occur, thus solving the problem of code duplication in the existing technology.

[0118] When the target analog input signal is slightly less than 0.7V-Δx, i.e., 0.7V-7.8125mV = 692.1875mV, the digital value corresponding to the target analog input signal 692.1875mV should be 896-10 = 886. Due to the downward shift of the original coarse adjustment decision benchmark value, the target analog input signal slightly less than 692.1875mV will be decided to the next sub-interval, i.e., the [768, 896] sub-interval. At this time, the target analog input signal is also the maximum value quantized in the [768, 896] sub-interval. Because if the target analog input signal exceeds 692.1875mV, it will be decided to the [896, 1024] sub-interval. Therefore, at this time, the fine adjustment... During the adjustment decision phase, the ramp signal ramp-vref rises from 0.55V (corresponding to digital value 704) to 0.7V (corresponding to digital value 896). When the ramp signal ramp-vref is greater than the target analog input signal 692.1875mV, the comparator output signal flips. Since the comparator has a delay of 5 LSBs, the final corresponding digital signal is 886+5=891. Furthermore, since the downward offset of the original coarse adjustment decision reference value is the sum of the time delay data of the comparator in the target ADC and the preset redundancy, such as 10 LSBs in this example, the counter value has not yet saturated, thus avoiding the problem of encoding dead zone.

[0119] As can be seen from the description of the segmented single-slope analog-to-digital conversion method of this application in the above embodiments, the method of this application adjusts the original coarse adjustment decision benchmark value downward according to the time delay data of the comparator in the coarse adjustment decision stage, which is equivalent to leaving redundancy for the comparator in the coarse adjustment decision stage. Therefore, it can avoid the problem of coding dead zone and duplicate code at the junction of sub-intervals during quantization due to the time delay of the comparator, ensuring the correctness of the conversion result of the target analog input signal, thereby optimizing the linearity of the ADC and improving the reliability of the ADC.

[0120] Based on the segmented single-slope analog-to-digital conversion method, this application also provides a segmented single-slope analog-to-digital conversion device 1000, such as... Figure 10 As shown, the segmented single-slope analog-to-digital converter 1000 may include:

[0121] The acquisition module 1100 is used to acquire multiple current coarse adjustment decision reference values ​​for quantizing the target analog input signal in the coarse adjustment decision stage. The multiple current coarse adjustment decision reference values ​​are obtained by shifting multiple original coarse adjustment decision reference values ​​downward based on the time delay data of the comparator in the target ADC, and each original coarse adjustment decision reference value corresponds to one-to-one with each original coarse adjustment decision reference value. Every two adjacent current coarse adjustment decision reference values ​​constitute a decision sub-interval in the coarse adjustment decision stage.

[0122] The coarse adjustment decision module 1200 is used to perform the first quantization process of the target analog input signal in the coarse adjustment decision stage according to multiple existing coarse adjustment decision reference values, to obtain the target decision sub-interval corresponding to the target analog input signal, so as to perform analog-to-digital conversion on the target analog input signal within the target decision sub-interval.

[0123] In this embodiment, the coarse adjustment decision module 1200 uses the comparator's time delay data to perform coarse adjustment decision on the target analog input signal. After adjusting the original coarse adjustment decision reference value downward, multiple current coarse adjustment decision reference values ​​are obtained, each corresponding to one of the original coarse adjustment decision reference values. The coarse adjustment decision module 1200 then uses these multiple current coarse adjustment decision reference values ​​to perform the first quantization process of the coarse adjustment decision stage on the target analog input signal, obtaining the target decision sub-interval corresponding to the target analog input signal. Then, the target analog input signal is subsequently converted to digital within the target decision sub-interval. Since the original coarse adjustment decision reference value is adjusted downward according to the comparator's time delay data in the coarse adjustment decision stage, it is equivalent to leaving redundancy for the comparator in the coarse adjustment decision stage. Therefore, it avoids the problem of coding dead zones and duplicate codes at the boundaries between sub-intervals during quantization due to the comparator's time delay, ensuring the correctness of the conversion result of the target analog input signal, thereby optimizing the linearity of the ADC and improving the reliability of the ADC.

[0124] In some embodiments of this application, the segmented single-slope analog-to-digital converter 1000 may further include a downward offset module 1500. Before the acquisition module 1100 acquires multiple current coarse adjustment decision reference values ​​for quantizing the target analog input signal in the coarse adjustment decision stage, the downward offset module 1500 may specifically be used for:

[0125] The downward offset is obtained based on the time delay data of the comparator in the target ADC and the preset redundancy; the redundancy is greater than or equal to the time delay data.

[0126] Based on the downward offset, multiple original coarse adjustment decision benchmark values ​​are respectively offset downward to obtain multiple corresponding current coarse adjustment decision benchmark values.

[0127] In some embodiments of this application, the segmented single-slope analog-to-digital converter 1000 may further include a reference value acquisition module 1400. The acquisition module 1100 acquires multiple coarse adjustment decision reference values ​​for quantizing the target analog input signal during the coarse adjustment decision stage. Specifically, the reference value acquisition module 1400 may be used for:

[0128] Based on the conversion range of the target ADC and the preset number of coarse adjustment intervals, multiple reference voltage values ​​are obtained; the number of multiple reference voltage values ​​matches the number of coarse adjustment intervals.

[0129] Based on the maximum conversion voltage of the target ADC and multiple reference voltage values, multiple original coarse adjustment decision benchmark values ​​are obtained.

[0130] In some embodiments of this application, the reference value acquisition module 1400 may also be used for:

[0131] The voltage difference is obtained by dividing the conversion range of the target ADC equally according to the number of coarse adjustment intervals;

[0132] Based on the preset initial reference voltage value and voltage difference, multiple reference voltage values ​​that form an arithmetic sequence are obtained.

[0133] In some embodiments of this application, the coarse adjustment decision module 1200 can specifically be used for:

[0134] Multiple coarse adjustment decision benchmark values ​​are compared with the target analog input signal in ascending order of size.

[0135] When the first coarse adjustment decision benchmark value among multiple coarse adjustment decision benchmark values ​​is greater than the target analog input signal, the first coarse adjustment decision benchmark value is recorded.

[0136] Based on the first current coarse adjustment judgment benchmark value, the current coarse adjustment judgment benchmark value that is adjacent to the first current coarse adjustment judgment benchmark value and is smaller than the first current coarse adjustment judgment benchmark value is determined as the second current coarse adjustment judgment benchmark value.

[0137] Based on the first and second coarse adjustment decision benchmark values, the target decision sub-interval corresponding to the target analog input signal is obtained.

[0138] In some embodiments of this application, the segmented single-slope analog-to-digital converter 1000 may further include a fine-tuning decision module 1300. After the coarse-tuning decision module 1200 performs a first quantization process on the target analog input signal according to the plurality of current coarse-tuning decision reference values ​​to obtain the target decision sub-interval corresponding to the target analog input signal, the fine-tuning decision module 1300 may specifically be used for:

[0139] Within the target decision sub-interval, the target analog input signal undergoes a second quantization process in the fine-tuning decision stage to obtain the digital signal corresponding to the target analog input signal.

[0140] In some embodiments of this application, the fine-tuning decision module 1300 can specifically be used for:

[0141] Based on the second original coarse adjustment decision reference value corresponding to the second current coarse adjustment decision reference value, the preset downward redundancy data, and the performance parameters of the target ADC, the ramp signal of the target ADC is obtained; the second current coarse adjustment decision reference value is the minimum value of the target decision sub-interval, and the ramp signal increases with the increase of the counter value of the target ADC;

[0142] The control count value starts counting from the initial value of the ramp signal;

[0143] When the ramp signal is greater than the target analog input signal, the count value of the record counter is used as the digital signal corresponding to the target analog input signal.

[0144] In some embodiments of this application, the fine-tuning decision module 1300 can also be used for:

[0145] The initial value of the ramp signal is obtained based on the second original coarse adjustment decision benchmark value and the downward redundancy data;

[0146] Based on the performance parameters of the target ADC, the growth amplitude of the ramp signal as the count value increases is obtained.

[0147] It should be noted that the contents of the acquisition module 1100, coarse adjustment decision module 1200, fine adjustment decision module 1300, reference value acquisition module 1400, and downward offset module 1500 in this application correspond one-to-one with the above. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the segmented single-slope analog-to-digital converter and its corresponding modules and units described above can be referred to as follows: Figures 1 to 9 The specific details of the segmented single-slope analog-to-digital conversion method corresponding to any embodiment will not be repeated here.

[0148] To better implement the segmented single-slope analog-to-digital conversion method of this application, this application also provides a single-slope ADC, which includes a memory 1002 and a processor 1001. The memory 1002 is used to store a computer program, which, when executed by the processor 1001, is used to implement the following functions:

[0149] Multiple current coarse adjustment decision reference values ​​are obtained for quantizing the target analog input signal in the coarse adjustment decision stage. The multiple current coarse adjustment decision reference values ​​are obtained by shifting the multiple original coarse adjustment decision reference values ​​downward based on the time delay data of the comparator in the target ADC, and each original coarse adjustment decision reference value corresponds to one-to-one with each original coarse adjustment decision reference value. Every two adjacent current coarse adjustment decision reference values ​​constitute a decision sub-interval in the coarse adjustment decision stage.

[0150] Based on multiple existing coarse adjustment decision benchmarks, the target analog input signal is subjected to the first quantization process in the coarse adjustment decision stage to obtain the target decision sub-interval corresponding to the target analog input signal, so as to perform analog-to-digital conversion on the target analog input signal within the target decision sub-interval.

[0151] like Figure 11 As shown, it illustrates a structural schematic of the single-slope ADC involved in this application, specifically:

[0152] The single-slope ADC may include components such as a processor 1001 with one or more processing cores, a memory 1002 with one or more computer-readable storage media, a power supply 1003, and an input unit 1004. Those skilled in the art will understand that... Figure 11 The structure shown does not constitute a limitation on a single-slope ADC. A single-slope ADC may also include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein:

[0153] The processor 1001 is the control center of the single-slope ADC. It connects various parts of the device via various interfaces and lines, and performs various functions and processes data by running or executing software programs and / or unit modules stored in the memory 1002, and by calling data stored in the memory 1002, thereby providing overall monitoring of the single-slope ADC. Optionally, the processor 1001 may include one or more processing cores; the processor 1001 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor. Preferably, the processor 1001 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and application programs, and the modem processor mainly handles wireless communication. It is understandable that the aforementioned modem processor may not be integrated into processor 1001.

[0154] The memory 1002 can be used to store software programs and modules. The processor 1001 executes various functional applications and data processing by running the software programs and modules stored in the memory 1002. The memory 1002 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, application programs required for at least one function, etc.; the data storage area may store data created based on the use of a single-slope ADC, etc. In addition, the memory 1002 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 1002 may also include a memory controller to provide the processor 1001 with access to the memory 1002.

[0155] The single-slope ADC may also include a power supply 1003 to power the various components. Preferably, the power supply 1003 can be logically connected to the processor 1001 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system. The power supply 1003 may also include one or more DC or AC power supplies, recharging systems, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components.

[0156] The single-slope ADC may also include an input unit 1004 and an output unit 1005. The input unit 1004 can be used to receive input digital or character information, and to generate keyboard, mouse, joystick, optical or trackball signal inputs related to user settings and function control.

[0157] Although not shown, the single-slope ADC may also include a display unit, etc., which will not be described in detail here. Specifically, in this application, the processor 1001 in the single-slope ADC loads the executable files corresponding to the processes of one or more application programs into the memory 1002 according to the following instructions, and the processor 1001 runs the application programs stored in the memory 1002 to realize various functions, as follows:

[0158] Multiple current coarse adjustment decision reference values ​​are obtained for quantizing the target analog input signal in the coarse adjustment decision stage. The multiple current coarse adjustment decision reference values ​​are obtained by shifting the multiple original coarse adjustment decision reference values ​​downward based on the time delay data of the comparator in the target ADC, and each original coarse adjustment decision reference value corresponds to one-to-one with each original coarse adjustment decision reference value. Every two adjacent current coarse adjustment decision reference values ​​constitute a decision sub-interval in the coarse adjustment decision stage.

[0159] Based on multiple existing coarse adjustment decision benchmarks, the target analog input signal is subjected to the first quantization process in the coarse adjustment decision stage to obtain the target decision sub-interval corresponding to the target analog input signal, so as to perform analog-to-digital conversion on the target analog input signal within the target decision sub-interval.

[0160] Those skilled in the art will understand that all or part of the steps in the various methods described above can be accomplished by instructions, or by controlling related hardware with instructions, which can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0161] Therefore, this application provides a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc. Computer instructions are stored thereon, which are loaded by a processor to execute the steps in any of the segmented single-slope analog-to-digital conversion methods provided in this application. For example, when the computer instructions are executed by the processor, they perform the following functions:

[0162] Multiple current coarse adjustment decision reference values ​​are obtained in the coarse adjustment decision stage for quantizing the target analog input signal. The multiple current coarse adjustment decision reference values ​​are obtained by shifting multiple original coarse adjustment decision reference values ​​downward based on the time delay data of the comparator in the target ADC, and each of the multiple current coarse adjustment decision reference values ​​corresponds to each original coarse adjustment decision reference value. Every two adjacent current coarse adjustment decision reference values ​​constitute a decision sub-interval in the coarse adjustment decision stage.

[0163] Based on multiple existing coarse adjustment decision benchmarks, the target analog input signal is subjected to the first quantization process in the coarse adjustment decision stage to obtain the target decision sub-interval corresponding to the target analog input signal, so as to perform analog-to-digital conversion on the target analog input signal within the target decision sub-interval.

[0164] The computer instructions stored in the computer-readable storage medium can execute the present application as follows. Figure 1 Corresponding to the steps in the segmented single-slope analog-to-digital conversion method in any embodiment, the present application can be implemented as described above. Figure 1 For details on the beneficial effects that the segmented single-slope analog-to-digital conversion method can achieve in any embodiment, please refer to the preceding description, which will not be repeated here.

[0165] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed descriptions of other embodiments above, which will not be repeated here.

[0166] In practice, each of the above units or structures can be implemented as an independent entity or can be arbitrarily combined to be implemented as the same or several entities. For specific implementation of each of the above units or structures, please refer to the previous embodiments, which will not be repeated here.

[0167] The above provides a detailed description of the segmented single-slope analog-to-digital conversion method, apparatus, single-slope ADC, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The above description is only for the purpose of helping to understand the method and its core ideas. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A segmented single-slope analog-to-digital conversion method, characterized by, The method includes: Multiple current coarse adjustment decision reference values ​​are obtained for quantizing the target analog input signal in the coarse adjustment decision stage. The multiple current coarse adjustment decision reference values ​​are obtained by shifting multiple original coarse adjustment decision reference values ​​downward based on the time delay data of the comparator in the target ADC, and each original coarse adjustment decision reference value corresponds to one-to-one with each original coarse adjustment decision reference value. Every two adjacent current coarse adjustment decision reference values ​​constitute a decision sub-interval in the coarse adjustment decision stage. The target analog input signal is subjected to a first quantization process in the coarse adjustment decision stage based on the plurality of current coarse adjustment decision reference values ​​to obtain the target decision sub-interval corresponding to the target analog input signal, so as to perform analog-to-digital conversion on the target analog input signal within the target decision sub-interval.

2. The method according to claim 1, characterized in that, Prior to the acquisition of the coarse adjustment decision stage, which quantizes multiple current coarse adjustment decision reference values ​​of the target analog input signal, the method includes: The downward offset is obtained based on the time delay data of the comparator in the target ADC and a preset redundancy amount; the redundancy amount is greater than or equal to the time delay data. The multiple original coarse adjustment decision benchmark values ​​are respectively offset downward according to the downward offset amount to obtain the corresponding multiple current coarse adjustment decision benchmark values.

3. The method according to claim 1, characterized in that, Prior to the acquisition of the coarse adjustment decision stage, which quantizes multiple current coarse adjustment decision reference values ​​of the target analog input signal, the method includes: Based on the conversion range of the target ADC and the preset number of coarse adjustment intervals, multiple reference voltage values ​​are obtained; the number of the multiple reference voltage values ​​matches the number of coarse adjustment intervals. The plurality of original coarse adjustment decision reference values ​​are obtained based on the maximum conversion voltage of the target ADC and the plurality of reference voltage values.

4. The method according to claim 3, characterized in that, The process involves obtaining multiple reference voltage values ​​based on the conversion range of the target ADC and the preset number of coarse adjustment intervals, including: The voltage difference is obtained by dividing the conversion range of the target ADC equally according to the number of coarse adjustment intervals. Based on the preset initial reference voltage value and the voltage difference, the plurality of reference voltage values ​​that form an arithmetic sequence are obtained.

5. The method according to claim 1, characterized in that, The first quantization process of performing coarse adjustment decision stage on the target analog input signal based on the plurality of current coarse adjustment decision benchmark values ​​to obtain the target decision sub-interval corresponding to the target analog input signal includes: The plurality of coarse adjustment decision benchmark values ​​are compared with the target analog input signal in ascending order of size; When the first coarse adjustment decision benchmark value among the plurality of coarse adjustment decision benchmark values ​​is greater than the target analog input signal, the first coarse adjustment decision benchmark value is recorded. Based on the first current coarse adjustment decision benchmark value, the current coarse adjustment decision benchmark value that is adjacent to the first current coarse adjustment decision benchmark value and is smaller than the first current coarse adjustment decision benchmark value is determined as the second current coarse adjustment decision benchmark value. Based on the first coarse adjustment decision benchmark value and the second coarse adjustment decision benchmark value, the target decision sub-interval corresponding to the target analog input signal is obtained.

6. The method according to claim 1, characterized in that, The method involves performing a first quantization process on the target analog input signal based on the plurality of current coarse adjustment decision benchmarks to obtain the target decision sub-interval corresponding to the target analog input signal. Afterwards, the method includes: Based on the second original coarse adjustment decision reference value corresponding to the second current coarse adjustment decision reference value, the preset downward redundancy data, and the performance parameters of the target ADC, the ramp signal of the target ADC is obtained; the second current coarse adjustment decision reference value is the minimum value of the target decision sub-interval, and the ramp signal increases with the increase of the counter value of the target ADC; The count value is controlled to start counting from the initial value of the ramp signal; When the ramp signal is greater than the target analog input signal, the count value of the counter is recorded as the digital signal corresponding to the target analog input signal.

7. The method according to claim 6, characterized in that, The step of obtaining the ramp signal of the target ADC based on the second original coarse adjustment decision benchmark value corresponding to the second current coarse adjustment decision benchmark value, preset downward redundancy data, and the performance parameters of the target ADC includes: The initial value of the ramp signal is obtained based on the second original coarse adjustment decision benchmark value and the downward redundancy data; Based on the performance parameters of the target ADC, the growth amplitude of the ramp signal as the count value increases is obtained.

8. A segmented single-slope analog-to-digital converter, characterized in that, The device includes: The acquisition module is used to acquire multiple current coarse adjustment decision reference values ​​for quantizing the target analog input signal during the coarse adjustment decision stage. The multiple current coarse adjustment decision reference values ​​are obtained by shifting multiple original coarse adjustment decision reference values ​​downward based on the time delay data of the comparator in the target ADC, and each original coarse adjustment decision reference value corresponds to one-to-one with each original coarse adjustment decision reference value. Every two adjacent current coarse adjustment decision reference values ​​constitute a decision sub-interval in the coarse adjustment decision stage. The coarse adjustment decision module is used to perform a first quantization process on the target analog input signal based on the plurality of existing coarse adjustment decision reference values ​​to obtain the target decision sub-interval corresponding to the target analog input signal, so as to perform analog-to-digital conversion on the target analog input signal within the target decision sub-interval.

9. A single-slope ADC, characterized in that, It includes a memory and a processor, the memory being used to store a computer program, which, when executed by the processor, is used to implement the segmented single-slope analog-to-digital conversion method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the steps of the segmented single-slope analog-to-digital conversion method according to any one of claims 1-7.

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