Layout of photonic integrated circuits using a fixed grid of coordinates

Abstract

Embodiments relate to placement of photonic integrated circuits using a fixed grid of coordinates. In some embodiments, a method includes receiving a request to place a first photonic component within a layout of a photonic integrated circuit. The positioning of the component within the layout is represented in a design database using a grid having fixed coordinates. The method also includes calculating, by a processor, a precise coordinate and a snapped coordinate for the positioning of the first photonic component. The snapped coordinate has a precision that is consistent with the fixed grid of coordinates, and the precise coordinate has a higher precision than the snapped coordinate. The method also includes representing the positioning of the first photonic component in the design database using both the precise coordinate and the snapped coordinate.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 011,554, “Method for Generating Masks for Photonic Devices,” filed April 17, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to the physical layout of photonic integrated circuits. Such a layout can be used to generate photolithographic masks for the fabrication of photonic devices. Background Technology

[0004] A photonic integrated circuit (PIC) is a device that integrates multiple photonic components onto a single device and processes information signals in the form of light waves. PICs are designed and manufactured using tools and processes based on those used in the semiconductor electronics industry. For example, design flows similar to those used for designing electronic integrated circuits can be used to design photonic integrated circuits. The software tools for physical placement of the device and for generating masks used in manufacturing can also be similar to those used in the electronics industry. Semiconductor processes used to manufacture electronic devices can be used for or are suitable for manufacturing photonic devices.

[0005] In many cases, photonic integrated circuits can combine photonics and electronics on the same device. For example, some functions can be performed by photonics, while others can be performed by electronics. Devices such as lasers and other types of optical transmitters can be used to convert signals from electrical to optical forms, while devices such as sensors and other types of optical receivers can be used to convert signals from optical to electrical forms. Electrical signals can also be used to control photonic devices, such as electro-optic modulators and optical amplifiers. Summary of the Invention

[0006] The embodiments relate to the layout of photonic integrated circuits using a fixed coordinate grid. In some embodiments, a method includes receiving a request to place a first photonic component within the layout of the photonic integrated circuit. The positioning of the component within the layout is represented in a design database using a grid with fixed coordinates. The method also includes having a processor calculate precise coordinates and snap coordinates for the positioning of the first photonic component. The snap coordinates have the same accuracy as the fixed coordinate grid, and the precise coordinates have higher accuracy than the snap coordinates. The method further includes using both the precise coordinates and the snap coordinates to represent the positioning of the first photonic component in the design database.

[0007] In some embodiments, the request to place the first photonic component includes a request to align a first optical port of the first photonic component with a second optical port of a previously placed second photonic component in the layout. The precise coordinates for positioning the first photonic component are calculated based on precise coordinates representing the positioning of the second photonic component.

[0008] In some embodiments, a system includes a memory storing instructions and a processor. The processor is coupled to the memory and executes the instructions. When executed, the instructions cause the processor to use precise coordinates and snap coordinates to position photonic components within the layout of a photonic integrated circuit. Other aspects include components, devices, systems, improvements, methods, processes, applications, computer-readable media, and other technologies related to any of the foregoing. Attached Figure Description

[0009] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings illustrating embodiments of the present disclosure. The drawings are provided to give knowledge and understanding of embodiments of the present disclosure, but are not intended to limit the scope of the disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0010] Figure 1 A block diagram of a layout creation system 100 for designing a photonic integrated circuit (PIC) according to some embodiments of the present disclosure is depicted.

[0011] Figure 2A Screenshots depicting the physical layout of a photonic integrated circuit according to some embodiments of the present disclosure.

[0012] Figure 2B Screenshots depicting the physical layout of a photonic integrated circuit with rotating components according to some embodiments of the present disclosure.

[0013] Figure 2C Screenshots depicting the physical layout of a photonic integrated circuit with a curved shape according to some embodiments of the present disclosure.

[0014] Figure 2D Screenshots depicting the physical layout of a photonic integrated circuit according to some embodiments of the present disclosure.

[0015] Figure 2E Some embodiments according to this disclosure are depicted. Figure 2D A close-up view of the interconnects of photonic integrated circuits.

[0016] Figure 3A A diagram depicting the rotational and snapping shapes of components according to some embodiments of the present disclosure is provided.

[0017] Figure 3B The image depicts locations near the precise port position and capture point position according to some embodiments of this disclosure. Figure 3A A magnified view of the component.

[0018] Figure 4 A diagram depicts the shape of connection components having undesirable overlap according to some embodiments of the present disclosure.

[0019] Figure 5 A diagram depicting the rotational shape of components according to some embodiments of the present disclosure.

[0020] Figure 6 The use of precise coordinates in some embodiments of this disclosure is depicted. Figure 5 Rotational shape connection Figure 3A A diagram of a rotated shape.

[0021] Figure 7 The use of snap coordinates in some embodiments of this disclosure is depicted. Figure 5 The rotation of the shape capture shape connection Figure 3A A graph that captures the shape.

[0022] Figure 8 A flowchart depicts a process for generating a layout of a photonic integrated circuit according to some embodiments of the present disclosure.

[0023] Figure 9 Flowcharts depict various processes used during the design and manufacture of photonic integrated circuits according to some embodiments of the present disclosure.

[0024] Figure 10 An abstract diagram of an example computer system in which embodiments of the present disclosure may operate is depicted. Detailed Implementation

[0025] This disclosure relates to the layout of photonic integrated circuits using a fixed coordinate grid. In photonic integrated circuits (also known as integrated optical circuits), various photonic components are integrated onto a substrate. These photonic components can be active or passive. Examples of photonic components include straight and curved waveguides, power dividers, optical amplifiers, optical modulators, filters, lasers, and detectors. Photonic integrated circuits are fabricated using semiconductor manufacturing techniques such as photolithography, etching, and deposition. Examples of photonic integrated circuits include different types of lasers, receivers, modulators (e.g., Mach-Zehnder modulators), and passive devices. For example, material systems used in photonic integrated circuits include indium phosphide, gallium arsenide, silicon, and silicon dioxide. Operating wavelengths typically include visible and near-infrared light.

[0026] Photonic integrated circuits can also combine photonic components with electronic components. As photonic integrated circuits become increasingly complex and contain more electronic devices, layout tools used for the physical layout of electronic devices can be used or are suitable for laying out these photonic integrated circuits.

[0027] However, existing layout design tools for electronic devices are typically based on a grid with fixed coordinates at a certain predefined interval. Components are placed in the layout to snap to the grid's position. For example, the layout of many electronic components consists of rectangles at certain locations. The corners of the rectangles are forced to be at allowed fixed coordinates, and cannot be located in the middle between fixed coordinates. Furthermore, rectangles can only be rotated in 90-degree increments or mirrored on the x-axis or y-axis, but cannot be rotated at arbitrary angles.

[0028] This can lead to placement issues in photonic components. The optical ports of a photonic component are typically the facets of a waveguide, and they must be precisely adjacent to the optical ports of adjacent photonic components to effectively couple optical signals from one component to the next. It is also not uncommon for photonic components to be rotated at arbitrary angles. Therefore, the position of an optical port may not fall on a fixed coordinate grid, but the placement tool can snap its position to the nearest grid coordinate. If adjacent optical ports are subsequently aligned with this snapped position (which is not the actual position), this can introduce overlaps, gaps, or bumps, potentially reducing coupling between components during manufacturing and causing DRC (Design Rule Check) failures that such placement errors can introduce.

[0029] On one hand, when a request to place a photonic component within the layout of a photonic integrated circuit is received, the component's positioning is represented by two sets of coordinates, referred to as precise coordinates and snap coordinates. Precise coordinates are more accurate, while snap coordinates are consistent with a fixed coordinate grid. For example, precise coordinates can be defined as positions between fixed coordinates on the grid. Precise coordinates provide additional precision used in the layout of photonic components, such as for the alignment of optical ports. Snap coordinates, based on a fixed grid, maintain compatibility with layout tools or design databases.

[0030] This allows existing layout tools and techniques to be more easily applied to photonic components in addition to electronic components. It also reduces overall memory usage and data storage requirements because no precise coordinates are used for any components in the layout. The positioning of electronic components can continue to be specified solely by snap coordinates.

[0031] Figure 1A block diagram depicts a layout creation system 100 for designing photonic integrated circuits (PICs). System 100 includes a layout design tool 102, a curve layout engine 104, and a design database 106. The layout design tool 102 provides a design environment for defining the physical layout of the photonic integrated circuit. The layout design tool 102 provides a display of the physical layout for designing and editing. The layout design tool 102 can also provide simulation management and analysis. The curve layout engine 104 provides component placement and verification for components within the layout. In some embodiments, the layout design tool 102 supports the physical layout of electronic devices utilizing a grid with fixed coordinates at a predefined spacing. The layout of the photonic integrated circuit is not limited to photonic components and may include electrical circuitry connected to the photonic components.

[0032] Design database 106 stores the layout of photonic integrated circuits, including information about the components in the layout. The photonic components in the layout have positions within the layout represented in design database 106 using precise coordinates and snap coordinates. For example, optical ports or other points of components in the design database can be represented using precise coordinates used to define the positioning of the components. Snap coordinates have the same precision as the fixed coordinate grid of the layout design tool 102. Precise coordinates have higher precision than snap coordinates and are used to facilitate the interconnection of components in the layout.

[0033] In some embodiments, the precise coordinates are at least 1000 times more precise than the snap coordinates. For example, if the fixed coordinates and snap coordinates of the mesh use integer values, the precise coordinates can use three or more decimal digits. In some embodiments, the precision of the precise coordinates is sufficient to avoid any discontinuities, bumps, or overlaps at facets between components in the vast majority of cases, thereby completely eliminating alignment loss and avoiding DRC errors.

[0034] The layout design tool 102 uses a fixed coordinate grid to provide the layout display. Component positioning refers to the component's position (e.g., x, y coordinates) and rotation. Each component can be represented as a shape defined by multiple points, the position of each point defined by snap coordinates consistent with the fixed coordinate grid. The layout design tool 102 may not allow component points to lie outside the fixed coordinate grid (e.g., by making the points have higher precision than the fixed coordinate grid). Therefore, the use of a fixed coordinate grid imposes limitations on how components are placed in the display layout of the layout design tool 102.

[0035] Figure 2AA screenshot depicting the physical layout of a photonic integrated circuit is shown. The photonic components are as follows: I0: beam splitter, I1: bent waveguide, I2: electro-optic modulator (applies an electrical signal to change the optical path length through the component), I3: straight waveguide, I4: bent waveguide, I5: optical combiner, I6: straight waveguide. These components are connected to form a Mach-Zehnder modulator. The electro-optic modulator I2 modulates the relative phase of the optical paths through the two arms. Therefore, the optical signals from the two arms interfere constructively or destructively at the combiner I5. Figure 2A In the example, electro-optic modulator I2 is an active element and includes an optical port for optical signals and an electrical port for electrical control signals. All other elements are passive. Transition components I7 and I8 bridge different types of optical ports / waveguides. Components I1 to I7 do not rotate relative to a fixed coordinate grid.

[0036] Figure 2B A screenshot depicting the physical layout of a photonic integrated circuit with rotating components. The components are composed of... Figure 2A The orientation of the components is represented by a shape rotated by a rotation angle θ. In this example, the rotation angle θ is defined relative to the x-axis of a fixed coordinate grid that includes the x and y axes. Figure 2B An enlarged view of the boundary 210 between the ports of components I0 and I1 is shown. Because the components are rotated, their ports may not be on the fixed grid. This can lead to port misalignment. Although Figure 2B The components shown are all rotated by the same angle θ, but different components within the layout can include different rotation angles. The angle θ for each component can be various values ​​and is not necessarily a multiple of 90 degrees.

[0037] Figure 2C A screenshot depicting the physical layout of a photonic integrated circuit including components with curved shapes is shown. The curved waveguide I1 has two internal curves 202 and 203 and a straight section 204, which is rotated at an angle θ relative to a fixed coordinate grid. These types of structures can be represented by polygons rotated at arbitrary angles. The resulting coordinates may not be on the fixed grid, which could lead to misalignment or other layout inaccuracies.

[0038] Figure 2D A screenshot depicting the physical layout of a photonic integrated circuit. The photonic integrated circuit is a Benes switch that includes interconnect components. One of the interconnects is located at region 212. Figure 2E Depicting including Figure 2DA close-up view of the interconnect region 212 of the photonic integrated circuit. To compensate for slight misalignment of components 214 and 216, two components 218 and 220 (e.g., optical connectors, such as waveguides) connecting components 214 and 216 include arcs. These arcs can be represented by polygons rotated at arbitrary angles. The resulting coordinates may not be on a fixed grid, which may lead to misalignment or other layout inaccuracies.

[0039] To place a component in a layout, the layout design tool 102 requests the component's positioning from the curve layout engine 104. In response, the curve layout engine 104 generates a snap coordinate positioning for the component that aligns with the fixed coordinate grid of the layout design tool 102. The layout design tool 102 then displays the component in the layout based on the fixed coordinate grid. The requested component may include a building block request or a connector request.

[0040] Building block requests are used to place new components within a layout or change the positioning of existing components within a layout. The specification of a building block request can indicate which component to place, as well as the component's parameter values. Parameter values ​​can include values ​​that define the component's desired positioning. For example, parameter values ​​can define the component's position and rotation angle. This position can be defined by the component's desired optical port position.

[0041] The curve layout engine 104 calculates the precise coordinates and snap coordinates of the components. To calculate the precise coordinates of the components' points, the curve layout engine 104 operates in "full precision" mode. That is, the curve layout engine 104 works with a higher precision than the fixed coordinate grid. The curve layout engine 104 can generate shapes with precise coordinates based on a mathematical curve description. The shape can be initially generated by the curve layout engine 104 using error specifications for the mathematical curve description (e.g., to meet technical error tolerances). The points of the shape can include points along the edges of the shape. Some points along the edges can be optical ports. Depending on the desired position and rotation of the component (which may be an angle that is not a multiple of 90 degrees), the precise coordinates of some or all points of the component may not be on the fixed coordinate grid.

[0042] To calculate the snap coordinates of components that are consistent with a fixed coordinate grid, the curve layout engine 104 can snap each precise coordinate of a point of the shape to the corresponding fixed coordinates of the grid. Knowing the grid settings of the layout design tool 102, which includes the fixed coordinates, the curve layout engine 104 uses iterative snap rounding to calculate the snap coordinates, where the original point segments are replaced by polygon chains, and each point is at least 1 / 2 unit away from any non-incident edge.

[0043] In response to a building block request, the curve layout engine 104 returns snap coordinates for component positioning to the layout design tool 102, which then uses these snap coordinates to display the component in the layout. The curve layout engine 104 also returns precise coordinates for component positioning to the layout design tool 102, which may include, but are not necessarily limited to, precise coordinates of the optical port. The layout design tool 102 may store the precise coordinates and snap coordinates of the component in the design database 106, or the curve layout engine 104 may directly store the precise coordinates and snap coordinates in the design database 106.

[0044] A connector request is used to place components in the layout that will connect to previously placed components. Here, the optical ports of the component to be placed are aligned with the optical ports of previously placed components in the layout and serve as anchor points for the connection. The curve layout engine 104 calculates the precise coordinates and snap coordinates of the components in response to the connector request.

[0045] To calculate the precise coordinates of the component to be placed, the Curve Layout Engine 104 uses the precise coordinates of previously placed components. The precise coordinates of previously placed components can be received from the layout design tool 102 (e.g., in conjunction with the request specification) or retrieved by the Curve Layout Engine 104 from the design database 106.

[0046] The curve layout engine 104 calculates the precise coordinates of the optical ports of the component to be placed based on the component's parameter values ​​and the precise coordinates of the optical ports of previously placed components. These precise coordinates ensure that the optical ports are aligned and connected to each other. Based on the alignment of the optical ports, the component to be placed is rotated such that the edge including the optical port of the component to be placed is adjacent to the edge of the optical port of the previously placed component. The precise coordinates define the positioning of the component, resulting in the edge of the component being adjacent to the precise coordinates of the edge of the previously placed component, without overlap or gaps.

[0047] The Curve Layout Engine 104 uses precise coordinates to calculate the snap coordinates of the component to be placed, which are consistent with a fixed coordinate grid, such as by snapping the precise coordinates of the points of the shape to the fixed coordinate grid.

[0048] In response to a connector request, the curve layout engine 104 returns snap coordinates for component positioning to the layout design tool 102, which then uses these snap coordinates to display the component in the layout. Based on the snap coordinates, in the layout displayed by the layout design tool 102, the edges of the optical ports of the component are adjacent to the edges of the optical ports of previously placed components without overlap or gaps. The curve layout engine 104 provides the layout design tool 102 with the component positioning, represented using both precise coordinates and snap coordinates, for storage in the design database 106, or the curve layout engine 104 may store both precise coordinates and snap coordinates in the design database 106. The precise coordinates of the optical ports can be used for subsequent connector requests to connect other components.

[0049] Figure 3A A diagram depicts the rotation shape 300 and snap shape 310 of a component. The component can be represented in a layout by parametric cells (PCells) and the parameters of the parametric cells. The positioning of the rotation shape 300 in the layout is defined by the precise coordinates of the component, and the positioning of the snap shape 310 is defined by the snap coordinates of the component. In response to a request (e.g., a block request) received from the layout design tool 102, the curve layout engine 104 generates the rotation shape 300 based on parameter values ​​including the optical port position and the rotation angle θ. By rotating the shape 300 by the angle θ, the resulting specified port position 301 has precise coordinates that may not be on a fixed coordinate system of the grid in the layout design tool 102.

[0050] If precise coordinates are not used, layout errors can occur because components are connected to each other in different (e.g., arbitrary) orientations. One type of error occurs when the edges of the snapped shape are not aligned with or coincide with the optical port positions of previously placed components specified in the connector request by the layout design tool 102. When the curve layout engine 104 snaps to a shape that has been rotated at an angle that is not a multiple of 90 degrees, the edges of the snapped shape are likely to be inconsistent with the specified port positions of previously placed components.

[0051] Snap shape 310 is an example of the result when the curve layout engine 104 snaps the rotated shape 300 to the grid of the layout design tool 102. The specified precise port position 301 of the rotated shape 300 (as defined by precise coordinates) is offset to the snap port position 311 of the snapped shape 310 (as defined by snap coordinates). Similarly, the edge position 302 of the rotated shape 300 (as defined by precise coordinates of the edge points) is snapped to the snap edge position 312 of the snapped shape 310 (as defined by snap coordinates of the edge points).

[0052] Figure 3BA diagram depicting a magnified region 315 of the component near the precise port position 301 and the capture point position 311 is shown. An offset vector 325 is defined between the precise port position 301 and the capture point position 311.

[0053] In response to the request specification, the Curve Layout Engine 104 returns the snap shape 310 along with the snap port position 311 to the Layout Design Tool 102. If precise coordinates are not used here, the snap port position 311 reported to the Layout Design Tool 102 does not correspond to the precise port position 301 of the rotated shape 300. When the Layout Design Tool 102 edits the layout of a shape, adjoins instances of the shape together, or updates the optical connectors associated with the shape, the request sent by the Layout Design Tool 102 to the Curve Layout Engine 104 will only specify a snap port position 311 that does not correspond to the precise port position 301. Because the Layout Design Tool 102 uses the snap port position 311 as the anchor position for other shapes connected to the rotated shape 300, gaps or overlaps between adjacent shapes may exist due to the difference between the snap port position 311 and the precise port position 301, as defined by the offset vector 325.

[0054] For example, such as Figure 4 As shown, the layout design tool 102 transmits a connector request to the curve layout engine 104, specifying a second shape 400 of a component (e.g., an optical connector, such as a waveguide) to be optically connected and adjacent to the rotation shape 300. The request includes parameter values ​​defining the second shape 400, including a capture port position 311 of the optical port of the rotation shape 300 to be connected to the second shape 400. This capture port position 311 in the request does not correspond to the precise port position 301. The curve layout engine 104 generates the second shape 400 in response to the received request, wherein the second shape 400 has a precise port position 401 aligned with the capture port position 311. As a result, the precise edge position 402 of the second shape 400 undesirably overlaps with the precise edge position 302 of the rotation shape 300. When the second shape 400 is captured by the grid, the capture edge position of the second shape 400 fails to be adjacent to the capture edge position 311 of the capture shape 310, and the capture port position of the second shape 400 is not aligned with the capture port position 311 of the capture shape 310.

[0055] Therefore, the precise port position 301 is stored (e.g., in the design database 106) to ensure that the layout design tool 102 does not lose information about the precise port position 301 due to mesh snapping. The stored precise coordinates of the optical port allow the layout creation system 100 to compensate for the offset vector 325 between the precise port position 301 and the snapping port position 311 of the previously placed component.

[0056] For example, layout design tool 102 connects to design database 106 to access precise port position 301 defined by precise coordinates and capture port position 311 defined by capture coordinates. Curve layout engine 104 can return precise coordinates and capture coordinates to layout design tool 102 in response to a request for component placement, and curve layout engine 104 can store precise coordinates and capture coordinates in design database 106. For a subsequent connector request to place another component connected to a previously placed component, layout design tool 102 retrieves the precise port position 301 and capture port position 311 of the previously placed component from design database 106, calculates an offset vector 325 between precise port position 301 and capture port position 311, and sends the offset vector 325 along with the capture port position 311 in the connector request to curve layout engine 104. In one embodiment, the precise coordinates and capture coordinates of the optical port are each stored as parameter values ​​of the capture shape 310 in a port object in data storage 106. As a result, layout design tool 102 can access both the precise port position 301 and capture port position 311 of the optical port. Design database 106 may store only the precise coordinates of the optical port, or it may store the precise coordinates of other points where the component is placed. Precise coordinates can be represented in various ways in design database 106. In some embodiments, precise coordinates in design database 106 are represented by an offset vector between the precise coordinates and the capture coordinates (e.g., instead of the x, y values ​​of the precise coordinates).

[0057] refer to Figure 5 When the layout design tool 102 transmits the specified connection to the curve layout engine 104 Figure 3A When a connector request is made for the third shape 500 of the rotating shape 300 (which may be a PCell or an optical connector), the layout design tool 102 includes an offset vector 325 in addition to the parameter values ​​used to define the third shape 500. The parameter values ​​of the third shape 500 may include information 500 about previously placed components to be connected to the third shape, such as the capture port position 311 of the rotating shape 300 and the rotation angle θ of the third shape 500.

[0058] The Curve Layout Engine 104 receives a connector request from the Layout Design Tool 102, which includes a snap port position 311 and an offset vector 325. In response, the Curve Layout Engine 104 uses the offset vector 325 and the snap port position 311 to calculate the precise port position 301 of the rotated shape 300, such as by moving the snap port position 311 by an offset equal to the reciprocal of the offset vector 325 to reach the precise port position 301. Note that if shape 300 or 500 represents a PCell, any design database transformations associated with PCell(s) must be considered when determining the offset vector 325. For example, transformations can be applied after the shape has been generated, and such transformations do not change any port attributes. Therefore, a shape rotated by 30 degrees will have a port set to 30 degrees. The same object can be transformed (e.g., R90, which applies a 90-degree rotation). The port will still have a 30-degree attribute, but in global design coordinates, the effective angle will be 90 + 30 = 120 degrees.

[0059] The curve layout engine 104 uses the precise port position 301 of the rotated shape 300 as the anchor point position to calculate the precise coordinates of the third shape 500. For example... Figure 6 As shown, the curve layout engine 104 determines the precise port position 501 along the edge located at the precise edge position 502 aligned with the precise port position 301. The precise edge position 502 of the third shape 500 is placed adjacent to the precise edge position 302 of the rotated shape 300. This can be achieved by rotating the third shape 500, wherein the precise port position 501 is aligned with the precise port position 301.

[0060] like Figure 7 As shown, the curve layout engine 104 then snaps the third shape 500 to the fixed coordinate grid of the layout design tool 102 in the same manner used to generate the snap shape 310 from the rotated shape 300 (e.g., by applying the same iterative snap rounding). Snapping the third shape 500 to the fixed coordinate grid may include calculating the snap coordinates using precise coordinates. The snapped third shape 510, along with the corresponding snap port position 511 and snap edge position 512, has the same precision as the fixed coordinate grid of the layout design tool 102.

[0061] As a result, the snap edge position 512 of snap shape 510 is adjacent to the snap edge position 312 of snap shape 310, and the snap port position 511 of snap shape 510 is aligned with the snap port position 311 of snap shape 310. The components represented by snap shapes 310 and 510 are connected without gaps or overlaps. In response to the connector request, curve layout engine 104 returns the positioning of snap shape 510 to layout design tool 102, including snap coordinates for displaying snap shape 510 and precise coordinates for connecting other shapes to snap shape 510. Curve layout engine 104 stores the precise coordinates of the components in design database 106 for subsequent connector requests.

[0062] Figure 8 A flowchart depicts a process 800 for laying out a photonic integrated circuit. Process 800 is discussed as being performed by a layout creation system 100, although other types of computing systems and devices may be used. Process 800 may include more or fewer steps, and the steps may be performed in different orders.

[0063] The curve placement engine 104 receives a request 802 from the placement design tool 102 to place photonic components within the layout of the photonic integrated circuit. The photonic components can be represented by parameterized cells and their parameters. In another example, the photonic component can be an optical connector. The request can be a building block request to add a new component, change the positioning of an existing component, or a connector request to align a component with a previously placed component. Component positioning within the layout is represented in the design database 106 using a grid with fixed coordinates.

[0064] The Curve Layout Engine 104 calculates 804 precise and snap coordinates for the positioning of photonic components. Snap coordinates have the same accuracy as the fixed coordinate grid. Precise coordinates have higher accuracy than snap coordinates.

[0065] To add a new component or change the positioning of an existing component, a request can include the component's position and rotation. This position can be defined by the location of the optical port or the position of some other point on the component. The Curve Layout Engine 104 uses the component's position and rotation to calculate precise coordinates. A component can rotate within its positioning by angles that are not multiples of 90 degrees. The Curve Layout Engine uses precise coordinates to calculate snap coordinates, such as by applying iterative snap rounding.

[0066] To connect a component to a previously placed component, the request may include the precise coordinates of the optical port of the previously placed component, which will be aligned with the optical port of the component to be placed. The precise coordinates in the request may be represented by snap coordinates and the offset between the snap coordinates and the precise coordinates. The precise coordinates of the previously placed component may be stored in design database 106 and retrieved by layout design tool 102 from design database 106 to generate the connector request. In design database 106, the precise coordinates of the placed component may be represented as an offset from the snap coordinates. Curve layout engine 104 calculates the precise coordinates by aligning the optical port of the component with the precise coordinates of the optical port of the previously placed component, and rotating the component such that the edge including the optical port of the component is adjacent to the edge of the optical port of the previously placed component. The component may be rotated by an angle not a multiple of 90 degrees in its positioning. Based on the precise coordinates, the edge of the optical port of the component is adjacent to the edge of the optical port of the previously placed component without overlap or gap. Based on the precise coordinates, the edge of the optical port of the component has the same orientation (e.g., rotation angle) as the edge of the optical port of the previously placed component. The curve layout engine uses precise coordinate calculations to capture coordinates, such as by applying iterative capture rounding.

[0067] In design database 106, the positioning of the photon component is represented using both precise coordinates and snap coordinates. For example, curve layout engine 104 returns the calculated precise coordinates and snap coordinates of the component to layout design tool 102. Layout design tool 102 stores the precise coordinates and snap coordinates of the component in design database 106. In design database 106, the precise coordinates of the component can be represented as an offset from the component's snap coordinates. In some embodiments, the component is represented by an object in design database 106, and the component's precise coordinates are stored as part of the object.

[0068] The layout design tool 102 displays the 808 layout based on a fixed coordinate grid. For example, each component placed in the layout is displayed using the component's snap coordinates. In some embodiments, the layout design tool 102 is used for the physical layout of an electronic device based on a grid with fixed coordinates at a predetermined interval, and thus the points of the components snap to the grid at the snap coordinates. In some embodiments, the photonic integrated circuit includes electrical circuitry. The layout of the photonic integrated circuit includes the layout of the electrical circuitry aligned with the fixed coordinate grid. Steps 802 to 808 can be repeated to place additional components in the layout of the photonic integrated circuit.

[0069] The design database 106 is used 810 to generate photolithographic masks for fabricating photonic integrated circuits. For example, the physical layout of the photonic integrated circuits is used to generate a mask-level description for fabricating a set of photolithographic masks. The photolithographic masks can be generated using snap coordinates.

[0070] Figure 9 A set of example processes 900 for transforming and verifying design data and instructions representing a PIC during the design, verification, and fabrication of a photonic integrated circuit (PIC) is illustrated. Each of these processes can be built and enabled as multiple modules or operations. The term "EPDA" stands for "Electrophotonic Design Automation." These processes begin with the creation of a product idea 910 using information provided by a designer, which is transformed to create an artifact using a set of EPDA processes 912. When the design is complete, it is tape-out 934, which occurs when artwork (e.g., geometric patterns) for the PIC is sent to a manufacturing facility to fabricate a mask set, which is then used to manufacture the PIC. After tape-out, a die is fabricated 936 and a packaging and assembly process 938 is performed to produce a finished photonic integrated circuit 940.

[0071] The scope of specifications can range from lower-level materials and physical layout to higher-level descriptions. Higher-level descriptions can be transformed into lower-level descriptions: for example, product specifications to schematics to physical layouts and then to mask-level descriptions. Each lower level of abstraction, as a less abstract description, adds more useful details to the design description, such as more details about the described modules. These lower levels of abstraction can be computer-generated, exported from a design database, or created by another design automation process. The description at each level of abstraction is available for use by the corresponding tool at that layer. The design process can utilize... Figure 9 The sequence described herein. The described process can be implemented using EPDA products (or tools), although... Figure 9 The steps in the process focus on the photonic design steps.

[0072] During the system design phase 914, the functionality of the PIC to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be broken down into different types of modules or components.

[0073] During schematic design (918), a higher-level description can be transformed into a netlist of components. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the PIC, and the nodes of the graph structure represent how the components are interconnected.

[0074] During the layout or physical implementation 924, physical placement (e.g., the positioning of the circuit components described above) and wiring (connection of the circuit components via waveguides) occur.

[0075] During analysis 926, circuit functionality is verified at the physical layout level, allowing for refinement of the schematic and / or layout design. During physical verification 928, the physical layout design is checked to ensure manufacturing constraints are correct. During resolution enhancement 930, the geometry of the layout can be transformed to improve how the circuit design is manufactured.

[0076] During the tape-out process, data for the production of the photomask is created (after applying photolithography enhancement, where appropriate). During mask data preparation 932, the photomask used for producing the finished PIC is produced using the "tape-out" data.

[0077] Computer systems (such as) Figure 10 The storage subsystem of the computer system 1000 can be used to store some or all of the EPDA products described herein, as well as the programs and data structures used by the products for developing units for the library and for the physical and logical design of the library.

[0078] Figure 10 An example machine is shown within a computer system 1000, which can execute a set of instructions to cause the machine to perform any or more methods discussed herein. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0079] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specifies the action the machine should take. Furthermore, while a single machine is described, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any one or more methods discussed herein.

[0080] Example computer system 1000 includes processing device 1002, main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), static memory 1006 (e.g., flash memory, static random access memory (SRAM) etc.) and data storage device 1018, which communicate with each other via bus 1030.

[0081] Processing device 1002 represents one or more processors, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing combinations of instruction sets. Processing device 1002 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1002 may be configured to execute instructions 1026 to perform the operations and steps described herein.

[0082] The computer system 1000 may also include a network interface device 1008 for communication via a network 1020. The computer system 1000 may also include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generation device 1016 (e.g., a speaker), a video processing unit 1028, and an audio processing unit 1032.

[0083] Data storage device 1018 may include a machine-readable storage medium 1024 (also referred to as a non-transitory computer-readable medium) thereon storing one or more sets of instructions 1026 or software embodying any one or more of the methods or functions described herein. Instructions 1026 may also reside wholly or at least partially in main memory 1004 and / or processing device 1002 during execution by computer system 1000, which also constitute machine-readable storage media.

[0084] In some implementations, instruction 1026 includes instructions for implementing functions corresponding to this disclosure. Although machine-readable storage medium 1024 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine and processing device 1002 to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0085] Some of the parts described in detail above have been presented in terms of algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most efficient way for those skilled in the art of data processing to communicate their work to others skilled in the art. An algorithm can be a series of operations that lead to a desired result. These operations are operations that require physical manipulation of physical quantities. These quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0086] However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless explicitly stated otherwise in this disclosure, it should be understood that throughout the description, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage devices.

[0087] This disclosure also relates to an apparatus for performing the operations described herein. The apparatus may be specifically constructed for its intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, each connected to a computer system bus.

[0088] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems can be used with the program based on the teachings herein, or it can be demonstrated that constructing more specialized devices to perform the methods is convenient. Furthermore, no particular programming language is referenced in describing this disclosure. It should be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0089] This disclosure can be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0090] In the foregoing disclosure, implementations of this disclosure have been described with reference to specific examples thereof. It is obvious that various modifications may be made thereto without departing from the broader spirit and scope of this disclosure as set forth in the appended claims. Where elements are referred to in the singular tense in this disclosure, more than one element may be depicted in the drawings, and similar elements may be labeled with similar numbers. Therefore, this disclosure and the drawings should be considered illustrative rather than restrictive.

Claims

1. A method for layout of photonic integrated circuits, comprising: A request is received to place a first photonic component within a layout of a photonic integrated circuit, wherein the positioning of the component within the layout is represented in a design database using a grid with fixed coordinates; The processor calculates precise coordinates and capture coordinates for positioning the first photonic component, wherein the capture coordinates have the same accuracy as the fixed coordinate grid, and the precise coordinates have a higher accuracy than the capture coordinates. Calculating the precise coordinates includes: The layout design processing device transmits the request to the curve layout processing device for placing the first photonic component, wherein the layout design processing device displays the layout based on the fixed coordinate grid; and The layout design processing device receives the precise coordinates of the first photonic component from the curve layout processing device; In the design database, the positioning of the first photonic component is represented by both the precise coordinates and the capture coordinates; The snap coordinates from the design database are used to display the layout of the photonic integrated circuit on the layout design processing device; and During the process, the first photonic component is placed within the layout of the photonic integrated circuit using the precise coordinates from the design database to manufacture the photonic integrated circuit.

2. The method of claim 1, wherein the request to place the first photonic component comprises: A request to align the first optical port of the first photonic component with the second optical port of a previously placed second photonic component in the layout; And the precise coordinates used for positioning the first photonic component are calculated based on the precise coordinates representing the positioning of the second photonic component.

3. The method of claim 2, wherein, based on the precise coordinates, the edge of the first optical port is adjacent to the edge of the second optical port without overlap or gap.

4. The method of claim 2, wherein the second photonic component is rotated in its positioning by an angle that is not a multiple of 90 degrees.

5. The method of claim 4, wherein, based on the precise coordinates, the edge of the first optical port has the same orientation as the edge of the second optical port.

6. The method of claim 1, wherein the precise coordinates are at least 1000 times more precise than the captured coordinates.

7. The method of claim 1, wherein the precise coordinates have sufficient accuracy to reduce optical losses and design rule check (DRC) failures between the optical ports of the components.

8. The method of claim 1, wherein in the design database, the precise coordinates are represented as offsets from the capture coordinates.

9. The method of claim 1, wherein the first photonic component is represented by a parameterization unit and parameters of the parameterization unit.

10. The method of claim 1, wherein the first photonic component is an optical connector.

11. The method of claim 1, wherein the first photonic component is represented by an object in the design database, and the precise coordinates are stored as part of the object.

12. The method of claim 1, wherein the photonic integrated circuit includes electrical circuitry, and the layout of the photonic integrated circuit includes a layout of the electrical circuitry aligned with the fixed coordinate grid.

13. The method according to claim 1, further comprising: The design database is used to generate a photolithographic mask for manufacturing the photonic integrated circuit.

14. A system for laying out photonic integrated circuits, comprising: Memory, storing instructions; as well as A processor, coupled to the memory, executes the instructions, which, when executed, cause the processor to: A request is received to place a first photonic component within a layout of a photonic integrated circuit, wherein the positioning of the component within the layout is represented in a design database using a grid with fixed coordinates; Calculating precise coordinates and capture coordinates for positioning the first photonic component, wherein the capture coordinates have the same accuracy as the fixed coordinate grid, and the precise coordinates have a higher accuracy than the capture coordinates, and calculating the precise coordinates includes: The layout design processing device transmits the request to the curve layout processing device for placing the first photonic component, wherein the layout design processing device displays the layout based on the fixed coordinate grid; and The layout design processing device receives the precise coordinates of the first photonic component from the curve layout processing device; In the design database, the positioning of the first photonic component is represented by both the precise coordinates and the capture coordinates; The snap coordinates from the design database are used to display the layout of the photonic integrated circuit on the layout design processing device; and During the process, the first photonic component is placed within the layout of the photonic integrated circuit using the precise coordinates from the design database to manufacture the photonic integrated circuit.

15. The system of claim 14, wherein the request to place the first photonic component comprises: A request to align the first optical port of the first photonic component with the second optical port of a previously placed second photonic component in the layout; The instructions also cause the processor to calculate the precise coordinates for the positioning of the first photonic component, and to calculate the precise coordinates based on the precise coordinates representing the positioning of the second photonic component.

16. The system of claim 15, wherein, based on the precise coordinates, the edge of the first optical port is adjacent to the edge of the second optical port without overlap or gap.

17. A non-transitory computer-readable medium comprising stored instructions, said instructions causing the processor, when executed by a processor, to: A request is received to place a first photonic component within a layout of a photonic integrated circuit, wherein the positioning of the component within the layout is represented in a design database using a grid with fixed coordinates; Calculating precise coordinates and capture coordinates for positioning the first photonic component, wherein the capture coordinates have the same accuracy as the fixed coordinate grid, and the precise coordinates have a higher accuracy than the capture coordinates, and calculating the precise coordinates includes: The layout design processing device transmits the request to the curve layout processing device for placing the first photonic component, wherein the layout design processing device displays the layout based on the fixed coordinate grid; and The layout design processing device receives the precise coordinates of the first photonic component from the curve layout processing device; The positioning of the first photonic component is represented by both the precise coordinates and the capture coordinates; The snap coordinates from the design database are used to display the layout of the photonic integrated circuit on the layout design processing device; and During the process, the first photonic component is placed within the layout of the photonic integrated circuit using the precise coordinates from the design database to manufacture the photonic integrated circuit.

18. The computer-readable medium of claim 17, wherein the precise coordinates are represented as an offset from the capture coordinates.

19. The computer-readable medium of claim 17, wherein the photonic integrated circuit includes electrical circuitry, and the layout of the photonic integrated circuit includes a layout of the electrical circuitry aligned with the fixed coordinate grid.

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