Integrated circuit, data processing apparatus and method

Abstract

The embodiments of the present disclosure disclose integrated circuits, data processing devices and methods. The integrated circuit comprises: a processor circuit and an accelerator circuit; the processor circuit comprises a processor, a first data storage area and a first data input / output interface; the accelerator circuit comprises an accelerator and a second data input / output interface, wherein the second data input / output interface is electrically connected with the first data input / output interface, so that the accelerator circuit and the first data storage area interact information, which can reduce the congestion phenomenon on the processor bus and improve the service quality of the application.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to an integrated circuit, a data processing apparatus, and a method. Background Technology

[0002] To improve the data processing capabilities of general-purpose processors (such as CPUs), accelerators can be installed on them. Accelerators can be used for data processing, such as encoding and decoding an image, or processing data between layers of a neural network model.

[0003] An accelerator integrated into the CPU core and with an extended instruction set is called a tightly coupled accelerator. However, placing an accelerator within the CPU core increases the complexity of CPU core manufacturing and also means that the accelerator's operation is subject to CPU timing constraints. Summary of the Invention

[0004] This disclosure is provided to briefly introduce the concepts, which will be described in detail in the subsequent Detailed Description section. This disclosure is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0005] This disclosure provides an integrated circuit, a data processing apparatus, and a method.

[0006] In a first aspect, embodiments of this disclosure provide an integrated circuit, including: a processor circuit and an accelerator circuit; the processor circuit includes a processor, a first data storage area, and a first data input / output interface; the accelerator circuit includes an accelerator and a second data input / output interface, wherein the second data input / output interface is electrically connected to the first data input / output interface to enable the accelerator circuit to interact with the first data storage area.

[0007] In a second aspect, embodiments of this disclosure provide a data processing apparatus, including an integrated circuit as described in the first aspect. The integrated circuit includes a processor circuit and an accelerator circuit. The processor circuit includes a processor, a first data storage area, and a first data input / output interface. The accelerator circuit includes an accelerator and a second data input / output interface, wherein the second data input / output interface is electrically connected to the first data input / output interface to enable the accelerator circuit to interact with the first data storage area.

[0008] Thirdly, embodiments of this disclosure provide a data processing method applied to the integrated circuit described in the first aspect. The method includes: in response to receiving a data processing request, a processor circuit determines address data corresponding to the data processing request; sends the address data to an accelerator circuit; the accelerator circuit obtains data to be processed corresponding to the request from a first data storage area of ​​the processor circuit based on the address data; and the accelerator circuit sends the processing result of the data to be processed to the processor circuit through a connection between a first data input / output interface and a second data input / output interface.

[0009] The integrated circuit, data processing apparatus, and method provided in this disclosure, by incorporating a processor circuit and an accelerator circuit within the integrated circuit, wherein the processor circuit includes a processor, a first data storage area, and a first data input / output interface, and the accelerator circuit includes an accelerator and a second data input / output interface, wherein the second data input / output interface is electrically connected to the first data input / output interface, enabling the accelerator circuit to interact with the first data storage area. On the one hand, the accelerator's access to the first data storage area of ​​the processor circuit is no longer limited by the processor's internal bus; on the other hand, when the accelerator accesses the first data storage area, it does not excessively impact the processor, thereby reducing congestion on the processor bus and improving the application's Quality of Service (QoS). Attached Figure Description

[0010] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0011] Figure 1 These are schematic diagrams illustrating the structure of some embodiments of integrated circuits provided in this disclosure;

[0012] Figure 2 These are schematic diagrams of structures according to other embodiments of the integrated circuits provided in this disclosure;

[0013] Figure 3 These are schematic diagrams illustrating the structure of some embodiments of the data processing apparatus provided in this disclosure;

[0014] Figure 4 This is a flowchart illustrating the data processing method provided in this disclosure. Detailed Implementation

[0015] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0016] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0017] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0018] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0019] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0020] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0021] Please refer to Figure 1 This illustrates a schematic structural diagram of the integrated circuit provided in this disclosure. Figure 1 As shown, the integrated circuit includes:

[0022] The processor circuit 11 and the accelerator circuit 12 are included. The processor circuit 11 includes a processor 111, a first data storage area 113, and a first data input / output interface 112. The processor 111 is connected to the data storage area 113 via a first bus disposed within the processor circuit 11.

[0023] The accelerator circuit 12 includes an accelerator 121 and a second data input / output interface 122. The second data input / output interface 122 is electrically connected to the first data input / output interface 112.

[0024] To achieve the electrical connection between the second data input / output interface 122 and the first data input / output interface 112, a connecting line can be provided between the two interfaces to enable data transmission. Furthermore, a serial communication module or a parallel communication module can also be provided between the second and first data input / output interfaces.

[0025] The serial communication module here can be, for example, a Serdes lane. Through the Serdes lane, multiple low-speed parallel signals from the transmitting end (accelerator circuit or processor circuit) are converted into high-speed serial signals. These signals are then transmitted through connecting lines, and finally, at the receiving end (processor circuit or accelerator circuit), the high-speed serial signals are converted back into low-speed parallel signals. This point-to-point serial communication technology can fully utilize the channel capacity of the connecting lines, reduce the required transmission channels and the number of device pins, and increase signal transmission speed, thereby significantly reducing communication costs.

[0026] The parallel communication module described above may include a set of parallel lines. These parallel lines in the parallel communication module transmit signals received from the transmitting end to the receiving end in parallel.

[0027] The processor here can be a general-purpose processor (i.e., a central processing unit, CPU), a graphics processing unit, etc. The aforementioned general-purpose processor can access the data storage area through the first bus.

[0028] The first data storage area 113 may include a cache, dynamic random access memory (DRAM), and static random access memory (SRAM).

[0029] The first data storage area 113 can correspond to a corresponding address. The processor 111 and the accelerator 121 store data in the first data storage area 113 or read data from the first data storage area 113 according to the address.

[0030] The first data storage area 113 can store the data processing results generated by the accelerator 121 after processing the data, or cache the data to be processed.

[0031] Accelerator 121 can be used for specialized data processing, such as processing image data or processing large amounts of intermediate data. Therefore, the amount of data that the accelerator needs to compute is relatively large, and the amount of data resulting from the computation of accelerator 121 is also relatively large.

[0032] To improve the data processing capabilities of integrated circuits, a dedicated accelerator for data processing can be added within the integrated circuit housing the processor. This accelerator can share the processor's first bus. However, because the accelerator shares the first bus with the processor, it is still limited by the bus's bandwidth. Furthermore, the larger on-chip bandwidth occupied by the accelerator can easily cause data transmission congestion, leading to quality of service issues. Additionally, fabricating the accelerator within the processor circuitry increases the complexity of the processor circuitry, resulting in a lower yield rate.

[0033] In this embodiment, by placing the accelerator circuit outside the processor circuit, the accelerator circuit interacts with the processor circuit through its own second data input / output interface and the processor circuit's first data input / output interface. On one hand, the accelerator's access to the processor circuit's first data storage area is no longer restricted by the processor's internal bus. On the other hand, when the accelerator accesses the first data storage area, it does not excessively impact the processor, reducing congestion on the processor bus and improving the application's Quality of Service (QoS). Furthermore, compared to placing the accelerator inside the processor circuit, placing it outside the processor circuit simplifies the processor circuit manufacturing process and improves the yield rate during processor circuit manufacturing.

[0034] In some optional implementations of this embodiment, a second data storage area may be provided in the accelerator circuit 12. The second data storage area may, for example, include static random-access memory (SRAM). The second data storage area can store the data to be processed and intermediate processing results. Data interaction between the accelerator and the second data storage area will not affect the data channel of the processor circuit. This can further reduce congestion on the processor bus and further improve the quality of service of the application.

[0035] Please refer to Figure 2 This illustrates schematic diagrams of the structures of some other embodiments of the integrated circuits provided in this disclosure. Figure 1 The embodiments shown are the same. Figure 2The integrated circuit shown includes a processor circuit 21 and an accelerator circuit 22. The processor circuit 21 includes a processor 211 and a first data storage area 213, with the processor 211 connected to the first data storage area 213 via a first bus disposed within the processor circuit 21. The processor circuit 21 includes a first data input / output interface 212. The accelerator circuit 22 includes an accelerator 221 and a second data input / output interface 222.

[0036] and Figure 1 The difference is that the accelerator circuit in this embodiment includes multiple second data input / output interfaces.

[0037] The processor circuit 21 includes a processor 211, multiple first data input / output interfaces 212, and multiple first data storage areas 213. Each first data storage area 213 corresponds to one first data input / output interface 212. For example... Figure 2 As shown, the processor circuit 21 may include data storage areas 0, ..., data storage area X, data storage area Y, and data storage area Z.

[0038] A first data input / output interface 212 corresponds one-to-one with a second data input / output interface 222. A second data input / output interface 222 is electrically connected to its corresponding first data input / output interface 212.

[0039] Each first data storage area corresponds to a first data input / output interface 212. That is, the first data storage area can interact with the accelerator through the first data input / output interface.

[0040] The electrical connection between the aforementioned second data input / output interface 222 and its corresponding first data input / output interface 212 can be implemented in accordance with... Figure 1 The electrical connection of the second data input / output interface in the illustrated embodiment is implemented in the same way as that of the first data input / output interface.

[0041] A first data storage area can correspond to a first identifier. The first identifier may include numbers, characters, etc., represented by binary code. Optionally, the first identifier may be the number of the first data storage area represented by the aforementioned numbers or characters. The processor 211 or the accelerator 221 can access the first data storage area through the first identifier corresponding to the first data storage area.

[0042] It should be noted that the first data storage area may include data storage units such as cache, dynamic random access memory (DRAM), and static random access memory (SRAM). Each data storage unit may include multiple physical storage spaces.

[0043] The data to be processed or intermediate data typically sent to the processor 211 may include a corresponding address. The processor can determine the target first identifier based on the address of the data to be processed or intermediate data using a first preset hash function. Then, it accesses the target first data storage area 213 indicated by the target first identifier through the first bus within the processor circuit 21.

[0044] In some optional implementations of this embodiment, the processor circuit 21 may include a plurality of processors 211.

[0045] In these optional implementations, multiple processors 211 can work collaboratively within the processor circuit 21 via a first bus. Each processor 211 can access different first data storage areas based on a first identifier of the first data storage area. Each first data storage area 213 can cache the data from the processors 211. In some application scenarios, each processor 211 can access its respective first data storage area via a first network-on-chip (NoC) configured within the processor circuit.

[0046] In some optional implementations, a first data input / output interface 212 may correspond to a second identifier. The second identifier may include numbers or characters. Optionally, the second identifier of a first data input / output interface 212 may be the same as the first identifier of the first data storage area 213 corresponding to the first data input / output interface 212. A second data input / output interface 222 may correspond to a third identifier. The third identifier may include numbers or characters. The second identifier corresponding to the first data input / output interface 212 and the third identifier corresponding to the second data input / output interface 222 can be mapped to the first identifier corresponding to the first data storage area corresponding to the first data input / output interface 212 through a preset mapping relationship.

[0047] In these optional implementations, the accelerator circuit 22 further includes an address determination unit 223. The address determination unit 223 is used to determine a target first identifier corresponding to the first data storage area based on the address of the data to be processed, and to determine a target first data input / output interface 212 and a target second data input / output interface 222 based on the target first identifier. For example, it determines a target second identifier corresponding to the target first data input / output interface 212 and a target third identifier corresponding to the target second data input / output interface 222 based on the target first identifier. Further, the accelerator 221 interacts with the target first data storage area corresponding to the target first identifier based on the target first data input / output interface 212 and the target second data input / output interface 222, and the connection between them.

[0048] In some application scenarios, a second preset hash function can be set in the address determination unit 223. The address determination unit 223 can use the second preset hash function to calculate the target first identifier based on the address of the data to be processed.

[0049] In one optional implementation, the target path length for accessing the target first data storage area through the target first data input / output interface 212 and the target second data input / output interface 222 is less than the path length for accessing the target first data storage area through other first data input / output interfaces and other second data input / output interfaces.

[0050] The aforementioned path length may include the first data input / output interface 212, the second data input / output interface 222, and the data channel inside the processor circuit.

[0051] For illustrative purposes, for the target first data storage area Z, the paths to reach the target data storage area are: (1) first data input / output interface a - second data input / output interface a'; (2) first data input / output interface b - second data input / output interface b' - processor circuit internal data channel d. The path in (1) is shorter than the path in (2).

[0052] The path from the first data input / output interface a to the second data input / output interface a' (1) can be used as the target path. The first data input / output interface a is the target first data input / output interface, and the second data input / output interface a' is the target second data input / output interface.

[0053] In these application scenarios, the accelerator 221 uses the shortest path to access the target first data storage area for data access. This reduces the number of nodes used for data transmission, which on the one hand improves the speed of data interaction between the accelerator and the target first data storage area, and on the other hand avoids channel congestion caused by multiple nodes in the processor circuit when the accelerator accesses the first data storage area within the processor circuit.

[0054] In other application scenarios, the time taken for the accelerator 221 to access the target first data storage area through the target first data input / output interface and the target second data input / output interface is less than the time taken to access the target first data storage area through other first data input / output interfaces and other second data input / output interfaces.

[0055] In these application scenarios, when congestion occurs on the path between the original first data input / output interface and the second data input / output interface used for data interaction between the accelerator 221 and the target first data storage area, the address determination unit 223 can re-determine the target first data input / output interface and the target second data input / output interface, allowing the path between the target first data input / output interface and the target second data input / output interface to bypass the data transmission congestion path. This ensures smooth data interaction between the accelerator and the target first data storage area.

[0056] In some alternative implementations, the accelerator circuit 22 may include a second buffer region and multiple accelerators 221. The multiple accelerators are each connected to the second buffer region via a second bus. In this way, each accelerator can access the second buffer region via the second bus to achieve data interaction between the accelerator and the second buffer region.

[0057] Multiple accelerators 221 are connected to each of the second data input / output interfaces 222 via a second bus.

[0058] The topology of the second bus includes one of the following: ring topology, mesh topology, and star topology.

[0059] The second bus includes either a cached coherent bus or a non-cached coherent bus.

[0060] Furthermore, the accelerator circuit 22 includes multiple accelerators 221. Each of the multiple accelerators is connected to a second data input / output interface via a data channel of a second on-chip network disposed within the accelerator circuit.

[0061] The multiple accelerators 221 here can be accelerators that perform the same type of data processing or accelerators that perform different types of data processing.

[0062] and Figure 1 Compared to the illustrated embodiment, the integrated circuit provided in this embodiment has multiple first data storage areas and multiple first data input / output interfaces in the processor circuit; and multiple second data input / output interfaces in the accelerator circuit. When the accelerator accesses a first data storage area, it determines a better transmission path and uses the better data transmission path to interact with the first data storage area. This embodiment can be applied to scenarios with multiple first data storage areas and / or multiple processors. Furthermore, by connecting the accelerator circuit to the processor circuit through multiple first data input / output interfaces, it avoids channel congestion caused by connecting to the processor circuit through a single first data input / output interface, thus preventing service quality issues caused by excessive processor circuit resource consumption.

[0063] Among the optional implementations of the integrated circuits provided in this disclosure, Figure 1 The processor circuit and accelerator circuit shown in the integrated circuit, and Figure 2 The processor circuit and accelerator circuit in the integrated circuit of the illustrated embodiment can be packaged in the same package using a preset packaging method.

[0064] Please continue to refer to this. Figure 3 This illustrates a structural schematic diagram of some embodiments of a data processing apparatus according to the present disclosure. For example... Figure 3 As shown, the data processing device 30 includes an integrated circuit 31. The integrated circuit 31 includes a processor circuit and an accelerator circuit; the processor circuit includes a processor, a first data storage area, and a first data input / output interface; the accelerator circuit includes an accelerator and a second data input / output interface, wherein the second data input / output interface is electrically connected to the first data input / output interface to enable information interaction between the accelerator circuit and the first data storage area.

[0065] Please refer to Figure 4 It illustrates a flowchart of the data processing method according to this disclosure, applied to... Figure 1 The integrated circuit shown. (As shown in the image) Figure 4 As shown, the data processing method includes:

[0066] Step 401: In response to receiving a data processing request, the processor circuit determines the address data corresponding to the data processing request; and sends the address data to the accelerator circuit.

[0067] The integrated circuit includes a processor circuit and an accelerator circuit; the processor circuit includes a processor, a first data storage area, and a first data input / output interface, wherein the processor is connected to the first data storage area via a first bus disposed within the processor circuit; the accelerator circuit includes an accelerator and a second data input / output interface, wherein the accelerator is connected to the second data input / output interface via a second bus.

[0068] The first data input / output interface is electrically connected to the second data input / output interface.

[0069] When the processor circuit receives a request for data to be processed, it can send the address data to the accelerator circuit according to the connected first data input / output interface and second data input / output interface.

[0070] Step 402: The accelerator circuit obtains the data to be processed corresponding to the request to be processed from the first data storage area of ​​the processor circuit according to the address data.

[0071] Specifically, the accelerator circuit can obtain the data to be processed from the first data storage area through the first data input / output interface and the second data input / output interface.

[0072] In some application scenarios, the processor circuit mentioned above includes multiple first data storage areas and multiple first data input / output interfaces, with one first data storage area corresponding to one first data input / output interface; the accelerator circuit also includes multiple second data input / output interfaces, with one first data input / output interface corresponding to one second data input / output interface; the second data input / output interface is electrically connected to its corresponding first data input / output interface.

[0073] The first data storage area corresponds to the first identifier. The data input / output interface corresponds to the second identifier; the second data input / output interface corresponds to the third identifier.

[0074] In these application scenarios, the accelerator circuit also includes an address determination unit. The address determination unit can determine a target first identifier using a preset hash function based on the address of the received data to be processed. Then, it determines a target first data storage area based on the target first identifier. Next, it determines a target second identifier and a target third identifier corresponding to the target first data storage area. Finally, it determines a target first data input / output interface and a target second data input / output interface based on the target second identifier and the target third identifier, respectively. The accelerator interacts with the target first data storage area corresponding to the target first address through the target second data input / output interface and the target first data input / output interface.

[0075] The target path length for the accelerator to access the target first data storage area through the target second data input / output interface and the target first data input / output interface is less than the path length for accessing the target data storage area through other first data input / output interfaces and other second data input / output interfaces.

[0076] The time taken for the accelerator to access the target data storage area through the target second data input / output interface and the target first data input / output interface is less than the time taken to access the target data storage area through other first data input / output interfaces and other second data input / output interfaces.

[0077] Step 403: The accelerator circuit sends the processing result of the data to be processed to the processor circuit through the connection between the first data input / output interface and the second data input / output interface.

[0078] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0079] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0080] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. An integrated circuit, comprising: Processor circuitry and accelerator circuitry; The processor circuit includes a processor, a first data storage area, and a first data input / output interface; The accelerator circuit includes an accelerator and a second data input / output interface, wherein the second data input / output interface is electrically connected to the first data input / output interface to enable the accelerator circuit to interact with the first data storage area. The processor circuit includes multiple first data storage areas and multiple first data input / output interfaces, with one first data storage area corresponding to one first data input / output interface; the accelerator circuit also includes multiple second data input / output interfaces, with one first data input / output interface corresponding to one second data input / output interface. The second data input / output interface is electrically connected to its corresponding first data input / output interface.

2. The integrated circuit according to claim 1, characterized in that, The electrical connection path between the second data input / output interface and the first data input / output interface includes: Serial communication module; or Parallel communication module.

3. The integrated circuit according to claim 1, characterized in that, The processor circuit also includes multiple processors; The plurality of processors are connected to the plurality of first data storage areas via a first bus.

4. The integrated circuit according to claim 1, characterized in that, Each of the first data storage areas corresponds to a first identifier; the accelerator circuit also includes an address determination unit. The address determination unit is used to determine a first target identifier based on the address of the data to be processed, and to determine a first target data input / output interface and a second target data input / output interface based on the first target identifier. The accelerator interacts with the first data storage area of ​​the target corresponding to the first target identifier through the second target data input / output interface and the first target data input / output interface.

5. The integrated circuit according to claim 4, characterized in that, The target path length for the accelerator to access the target first data storage area through the target second data input / output interface and the target first data input / output interface is less than the path length for accessing the target first data storage area through other first data input / output interfaces and other second data input / output interfaces.

6. The integrated circuit according to claim 4, characterized in that, The time taken for the accelerator to access the target first data storage area through the target second data input / output interface and the target first data input / output interface is less than the time taken to access the target first data storage area through other first data input / output interfaces and other second data input / output interfaces.

7. The integrated circuit according to claim 6, characterized in that, The accelerator circuit includes a second buffer region and multiple accelerators; The plurality of accelerators are respectively connected to the second buffer area and each of the second data input / output interfaces via the second bus.

8. The integrated circuit according to claim 7, wherein the topology of the second bus includes one of the following: ring topology, mesh topology, and star topology.

9. The integrated circuit according to claim 7, characterized in that, The second bus includes either a cached coherent bus or a non-cached coherent bus.

10. The integrated circuit according to any one of claims 1-9, characterized in that, The processor circuit and the accelerator circuit are located in the same package.

11. A data processing apparatus comprising an integrated circuit as described in any one of claims 1-10, the integrated circuit comprising: Processor circuitry and accelerator circuitry; The processor circuit includes a processor, a first data storage area, and a first data input / output interface; The accelerator circuit includes an accelerator and a second data input / output interface, wherein the second data input / output interface is electrically connected to the first data input / output interface to enable the accelerator circuit to interact with the first data storage area. The processor circuit includes multiple first data storage areas and multiple first data input / output interfaces, with one first data storage area corresponding to one first data input / output interface; the accelerator circuit also includes multiple second data input / output interfaces, with one first data input / output interface corresponding to one second data input / output interface. The second data input / output interface is electrically connected to its corresponding first data input / output interface.

12. A data processing method, applied to an integrated circuit as described in any one of claims 1-10, comprising: In response to receiving a data processing request, the processor circuitry determines the address data corresponding to the data processing request; The address data is sent to the accelerator circuit. The accelerator circuit obtains the data to be processed corresponding to the request to be processed from the first data storage area of ​​the processor circuit according to the address data; The accelerator circuit sends the processing results of the data to be processed to the processor circuit through the connection between the first data input / output interface and the second data input / output interface.

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