Faulty sram screening method, device and software and hardware system

Abstract

The application provides a screening method and device for a faulty SRAM, and a software and hardware system, comprising: setting a test temperature; based on the test temperature, using a plurality of test models to test a to-be-tested SRAM according to a pre-set read-write sequence; judging whether the test flow of each test model passes; if not, ending the test flow and determining the to-be-tested SRAM as a faulty SRAM. The application tests the SRAM based on the set test temperature, uses a plurality of test models to screen the SRAM, and when the test flow of each test model does not pass, directly ends the test flow and determines the SRAM as the screened SRAM. The screening model is various and the test is fast, and the faulty SRAM can be quickly and comprehensively screened out.

Description

Technical Field

[0001] This invention relates to the field of data filtering technology, and in particular to a method, apparatus, and hardware / software system for filtering faulty SRAMs. Background Technology

[0002] Existing embedded chips typically include built-in SRAM to meet system program execution and various data caching needs, such as the controller chip in an SSD. During the entire product manufacturing and testing process, the focus is generally only on domain-specific tests. For example, for SSD platters, the focus is primarily on bad block screening of the back-end storage medium, Nand Flash. However, SRAM, as a crucial component of the entire system, often lacks or has its reliability testing adequately guaranteed. Due to its manufacturing process and electrical characteristics, SRAM may experience some bit corruption or instability. If this occurs during operation, it will be catastrophic for the entire system.

[0003] Current SSD manufacturing processes either lack or only perform simple SRAM overwrite tests, failing to detect faulty bits or only identifying severely damaged, consistently faulty bits. They also fail to promptly screen out weaker SRAM segments with a certain probability of error. Furthermore, they cannot detect faults that are relatively stable at room temperature but exhibit bit flipping at high temperatures. Therefore, current technology cannot guarantee system stability. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a method, apparatus and hardware / software system for screening faulty SRAMs, which can effectively screen out SRAMs that are at risk of failure, thereby improving the stability of the entire system.

[0005] In a first aspect, embodiments of the present invention provide a method for screening faulty SRAMs. The method includes: setting a test temperature; testing the SRAM to be tested using multiple test models according to a pre-set read / write order based on the test temperature; determining whether the test process of each test model passes; if not, ending the test process and identifying the SRAM to be tested as a faulty SRAM.

[0006] In conjunction with the first aspect, the present invention provides a first possible implementation of the first aspect, wherein the multiple test models include a first model, a second model, and a third model; wherein the first model, the second model, and the third model respectively include one of a sequential write-read verification model, a delayed read verification model, and a continuous read verification model, and the first model, the second model, and the third model are different from each other; the step of testing the SRAM under test using multiple test models according to a preset read-write order includes: first testing the SRAM under test using the first model according to the preset read-write order; when the test of the first model passes, testing the SRAM under test using the second model; when the test of the second model passes, testing the SRAM under test using the third model; the step of determining whether the test process of each test model passes includes: if the test of any one test model fails, then determining that the test process of the test model fails.

[0007] In conjunction with the first aspect, this embodiment of the invention provides a second possible implementation of the first aspect, wherein the step of testing the SRAM under test using multiple test models includes: writing test data using a predefined writing method according to a preset source data writing rule; performing a read verification operation on the SRAM under test based on the test data according to a preset verification method; determining whether the verification result of the read verification operation passes; if not, ending the read verification operation and identifying the SRAM under test in the verification method as a faulty SRAM.

[0008] In conjunction with the first aspect, this embodiment of the invention provides a third possible implementation of the first aspect, wherein the preset verification method includes a first verification method and a second verification method, wherein the first verification method and the second verification method respectively include one of CPU verification and DMACC verification, and the first verification method and the second verification method are different from each other; the step of performing a read verification operation on the SRAM to be tested based on the preset verification method and the test data includes: comparing the test data with the data of the SRAM to be tested using the first verification method to perform a read verification operation; determining whether the read verification result of the first verification method passes; if not, ending the read verification operation and identifying the SRAM to be tested in the first verification method as a faulty SRAM; if yes, comparing the test data with the data of the SRAM to be tested using the second verification method to perform a read verification operation; determining whether the read verification result of the second verification method passes; if not, ending the read verification operation and identifying the SRAM to be tested in the second verification method as a faulty SRAM; if yes, completing the read verification operation.

[0009] In conjunction with the first aspect, this invention provides a fourth possible implementation of the first aspect, wherein the source data writing rule includes a source data set and a writing order corresponding to the source data set; the source data set includes multiple test data sets, wherein the multiple test data sets are typical test data for testing SRAM faults; the writing method includes a CPU writing method and a preset module writing method; the SRAM to be tested includes a capacity size; if the test model is a sequential write-read verification model, then the sequential write-read verification model is used to test the SRAM to be tested, and the test data is written according to the preset source data writing rule and a predefined writing method; the step of performing a read verification operation on the SRAM to be tested based on the preset verification method and the test data includes: determining the first test data in the writing order corresponding to the source data set as the test data corresponding to the read verification operation. Based on the capacity of the SRAM under test, test data matching the capacity of the SRAM under test is written using CPU writing. After the test data is written, a read verification operation is performed on the test data for the SRAM under test. After the read verification operation passes, the next test data in the writing order corresponding to the source data set is determined as the test data corresponding to the read verification operation, and based on the capacity of the SRAM under test, the next test data in the source data set matching the capacity of the SRAM under test is written using CPU writing. This process continues until each test data in the writing order is determined as the test data corresponding to the read verification operation and is written using CPU writing. After the read verification operation on the SRAM under test passes, the CPU writing method is switched to the preset module writing method, and each test data corresponding to the read verification operation is rewritten.

[0010] In conjunction with the first aspect, the present invention provides a fifth possible implementation of the first aspect, wherein if the test model is a delayed read verification model, the delayed read verification model is used to test the SRAM to be tested; the step of performing a read verification operation on the SRAM to be tested based on the test data after the test data is written further includes: after the test data is written, waiting for a preset time threshold, and then performing a read verification operation on the SRAM to be tested based on the test data.

[0011] In conjunction with the first aspect, this embodiment of the invention provides a sixth possible implementation of the first aspect, wherein if the test model is a continuous read verification model, the continuous read verification model is used to test the SRAM under test; both the first verification method and the second verification method include a preset number of verification repetitions; the source data writing rule also includes a preset byte size, wherein the preset byte size is smaller than the capacity size of the SRAM under test; according to the capacity size of the SRAM under test, test data that meets the capacity size of the SRAM under test is written by CPU writing method; after the test data is written, the step of performing a read verification operation on the SRAM under test for the test data includes: writing test data of a preset byte size by CPU writing method; after the preset byte size of test data is written, using the first verification method and the second verification method to sequentially compare the preset byte size of test data with the preset byte size of data of the SRAM under test, and performing the comparison process according to the preset number of verification repetitions to perform a read verification operation on the SRAM under test.

[0012] Secondly, embodiments of the present invention also provide a faulty SRAM screening device, which is used to execute the above-described faulty SRAM screening method. The device includes: a temperature setting module for setting a test temperature; a test module for testing the SRAM to be tested using a test model according to a pre-set read / write order based on the test temperature; a judgment module for judging whether the test process of the test model is successful; and a screening module for ending the test process and identifying the SRAM to be tested as a faulty SRAM when the judgment result of the judgment module is negative.

[0013] Thirdly, embodiments of the present invention also provide a hardware and software system for screening SRAM. This hardware and software system for screening SRAM is used to execute the above-mentioned method for screening faulty SRAM. The hardware and software system for screening SRAM includes an SSD controller chip, and a CPU module and a DMACC module configured on the SSD controller chip. The CPU module and the DMACC module are connected via a bus. The bus also connects to the SRAM to be tested. The CPU module is used to perform a write operation of the CPU write mode corresponding to the test model and a read verification operation of the first verification mode corresponding to the test model on the SRAM to be tested. The DMACC module is used to perform a write operation of the preset module write mode corresponding to the test model and a read verification operation of the second verification mode corresponding to the test model on the SRAM to be tested. The hardware and software system also includes a storage module for storing firmware programs and test results. The firmware programs are used to implement the test strategy for screening SRAM.

[0014] Fourthly, embodiments of the present invention also provide a server, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the above-described method for screening faulty SRAM.

[0015] The embodiments of this invention bring the following beneficial effects: This invention provides a method, apparatus, and hardware / software system for screening faulty SRAMs, comprising: setting a test temperature; testing the SRAM to be tested using multiple test models according to a pre-set read / write order based on the test temperature; determining whether the test process of each test model passes; if not, ending the test process and identifying the SRAM to be tested as a faulty SRAM. This invention tests the SRAM based on a set test temperature, employs multiple test models to screen the SRAM, and directly ends the test process when the test process of each test model fails, identifying the SRAM as a screened SRAM. The diverse screening models enable rapid and comprehensive screening of faulty SRAMs.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating a method for screening faulty SRAMs according to an embodiment of the present invention;

[0020] Figure 2 A flowchart illustrating another method for screening faulty SRAMs provided in an embodiment of the present invention;

[0021] Figure 3 This is a flowchart illustrating the testing of the SRAM under test using a sequential write-read verification model, as provided in an embodiment of the present invention.

[0022] Figure 4A flowchart for writing test data provided in an embodiment of the present invention;

[0023] Figure 5 This is a flowchart of a data read verification operation for the SRAM under test provided in an embodiment of the present invention;

[0024] Figure 6 This is a flowchart illustrating the testing of the SRAM under test using a delayed read verification model, as provided in an embodiment of the present invention.

[0025] Figure 7 This is a flowchart illustrating the testing of the SRAM under test using a continuous read verification model, as provided in an embodiment of the present invention.

[0026] Figure 8 A schematic diagram of a faulty SRAM screening device provided in an embodiment of the present invention;

[0027] Figure 9 This is a schematic diagram of the structure of a server provided in an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Existing embedded chips typically include built-in Static Random-Access Memory (SRAM) to meet the needs of system program execution and various data caching requirements, such as the controller chip of a Solid State Disk (SSD). During the production and testing process of a product, the focus is generally only on domain-specific tests. For example, for SSD platters, the focus is mainly on bad block screening of the back-end storage medium, NAND Flash. However, SRAM, as a crucial component of the entire system, often lacks or has weakened reliability testing guarantees. Due to its manufacturing process and electrical characteristics, SRAM may experience some bit corruption or instability. If this occurs during operation, it will be catastrophic for the entire system.

[0030] Current SSD manufacturing processes do not perform SRAM screening, which makes it impossible to eliminate faulty and unstable SRAM. Alternatively, they may only perform simple SRAM overwrite tests, failing to detect corrupted data, especially the smallest data storage unit—the bits. They may only detect severely corrupted bits, while failing to promptly screen out weaker SRAM with a certain probability of error. Furthermore, current technologies cannot effectively screen out the following SRAM failure modes: 1. SRAM is relatively stable at room temperature, but has a certain probability of bit data flipping at high temperatures; 2. Some SRAM bits are unstable, and repeated read verification may result in bit data flipping; 3. Some SRAM bits have poor data retention capabilities and may flip after a period of time. Therefore, current technologies cannot screen out all faulty SRAM, thus compromising system stability.

[0031] Based on this, the present invention provides a method, apparatus and hardware / software system for screening faulty SRAMs, which can effectively screen out SRAMs that are at risk of failure, thereby improving the stability of the entire system.

[0032] To facilitate understanding of this embodiment, a method for screening faulty SRAMs disclosed in this invention will first be described in detail. Figure 1 A flowchart of a method for screening faulty SRAMs is shown, such as... Figure 1 The flowchart shown illustrates a method for screening faulty SRAMs, which includes the following steps:

[0033] Step S102: Set the test temperature.

[0034] Step S104: Based on the test temperature, and according to the pre-set read / write order, use multiple test models to test the SRAM under test.

[0035] Specifically, when screening for faulty SRAMs, SRAM faults are more easily exposed at high temperatures. Therefore, the SSD corresponding to the SRAM to be tested is placed in a high-temperature chamber and tested after power-on. Specifically, the test temperature of the high-temperature chamber can be 70 degrees Celsius.

[0036] Furthermore, in this embodiment of the invention, the above-mentioned test model includes multiple test models. Specifically, in screening faulty SRAMs, this embodiment of the invention uses multiple test models to screen and test the SRAMs to be tested. This method can effectively superimpose multiple screening methods, effectively screen out SRAMs with various fault problems, and thus ensure the stability of the entire system.

[0037] Step S106: Determine whether the test process for each test model has passed.

[0038] Step S108: If not, the test process ends and the SRAM under test is identified as a faulty SRAM.

[0039] Specifically, when the test model tests the SRAM to be tested, it will determine whether any step of the test process has passed. Only if the current step passes will the next step be tested. If the current step fails, it means that the SRAM in that step is a faulty SRAM. In this case, the faulty SRAM is directly filtered out and will not be tested in subsequent steps.

[0040] This invention provides a method for screening faulty SRAMs. The SRAMs are tested based on a set test temperature, and multiple test models are used to screen the SRAMs. In addition, if the test process of each test model fails, the test process is terminated directly, and the SRAM is identified as the screened SRAM. The diverse screening models enable the rapid and comprehensive screening of faulty SRAMs.

[0041] For ease of understanding, Figure 1 Based on this, embodiments of the present invention also provide another method for screening faulty SRAMs. This method mainly focuses on the steps described above, which involve testing the SRAM under test using multiple test models according to a pre-set read / write order based on test temperature (this step is implemented through steps S204-S208 below). Figure 2 A flowchart of another method for screening faulty SRAMs is shown, specifically, as follows: Figure 2 The flowchart shown is for another method of screening faulty SRAMs, which includes the following steps:

[0042] Step S202: Set the test temperature.

[0043] Step S204: Based on the test temperature, and according to the pre-set read / write order, first use the first model to test the SRAM to be tested.

[0044] Step S206: When the first model passes the test, the second model is used to test the SRAM to be tested.

[0045] Step S208: When the second model passes the test, the third model is used to test the SRAM to be tested.

[0046] Specifically, the aforementioned multiple test models include a first model, a second model, and a third model; wherein the first model, the second model, and the third model each include one of a sequential write-read verification model, a delayed read verification model, and a continuous read verification model, and the first model, the second model, and the third model are different from each other.

[0047] Furthermore, the first model mentioned above may include a sequential write-read verification model, the second model mentioned above may include a delayed read verification model, and the third model mentioned above may include a continuous read verification model.

[0048] Specifically, the above sequential write-read verification model is a test implemented by verifying the SRAM in sequence after the source data of the SRAM size used for verification has been written. The source data used by this model includes all typical data patterns used to test the SRAM, such as 0x0, 0xFF, 0x55AA, and 0xAA55. Therefore, this model can perform a full data coverage test on the SRAM, thereby determining whether there are data errors in the SRAM.

[0049] The aforementioned delayed read verification model is implemented by performing a read verification test after writing the source data to the SRAM, under high temperature conditions, and waiting for a certain period of time. In other words, the delayed read verification model increases the waiting time compared to the sequential write-read verification model. Specifically, in this test model, after waiting for a certain period of time under high temperature conditions, it can obtain test results regarding data instability, such as whether the SRAM data has flipped, thereby testing the data retention capability.

[0050] The aforementioned continuous read verification model performs read verification on each unit of source data after it has been written, starting from the initial data in the SRAM. Unlike the sequential write-read verification model, which performs read verification after writing the entire SRAM size of source data, this model performs read verification after each unit of data has been written, and also performs multiple read verifications on the same location. This allows for verification of SRAM stability and the filtering out SRAMs prone to bit flipping. Specifically, the aforementioned unit of source data can be a pre-defined Dword size, with SRAMs filtered at two-byte granularities.

[0051] Furthermore, to ensure the timeliness of the screening and quickly identify faulty SRAMs, a sequential write-read verification model can be used to test and directly screen out SRAMs that will fail during the full data coverage process. Then, a delayed read verification model can be used for testing, and finally, a continuous read verification model can be used for testing to screen out the remaining SRAMs that are likely to have problems.

[0052] First, the SRAM under test is tested using a sequential write-read verification model. After the sequential write-read verification model passes the test, the SRAM under test is then tested using a delayed read verification model. After the delayed read verification model passes the test, the SRAM under test is then tested using a continuous read verification model. When the continuous read verification model passes the test, it indicates that the SRAM under test is fault-free. Using this SRAM can effectively ensure the stability of the system.

[0053] Step S210: If any test model fails the test, then the test process of the test model is determined to have failed.

[0054] In step S212, if the test process fails, the test process ends and the SRAM under test is identified as a faulty SRAM.

[0055] Specifically, the present invention aims to screen out faulty SRAMs. If any of the three test models fails, it means that the SRAM in that test is a faulty SRAM. In this case, there is no need to use the next test model for testing. This screening method performs multiple screenings of the SRAM, which can fully test and screen the SRAM, thereby screening out all faulty SRAMs.

[0056] Another method for screening faulty SRAMs provided in this embodiment of the invention uses sequential write-read verification model, delayed read verification model and continuous read verification model to test SRAM respectively. It can sequentially perform full data coverage test on SRAM, test the data retention capability of SRAM, and screen SRAMs that are likely to fail. The test models are rich and comprehensive, which can screen out SRAMs with various faults, thereby ensuring the stability of the system.

[0057] Furthermore, for ease of understanding, in Figure 1 and Figure 2 Based on this, embodiments of the present invention also provide another method for screening faulty SRAMs. This method mainly describes the steps when the above test model is a sequential write-read verification model. Figure 3 A flowchart illustrating the testing of the SRAM under test using a sequential write-read verification model is shown, such as... Figure 3 As shown, the method includes:

[0058] Step S302: Write test data using a predefined writing method according to the preset source data writing rules.

[0059] Specifically, the aforementioned source data writing rules include a source data set, which includes multiple test data sets. Specifically, the multiple test data sets in the aforementioned source data set include 0x0, 0xFF, 0xAA55, 0x55AA, etc., wherein the aforementioned multiple test data sets are typical test data for testing the SRAM fault.

[0060] Furthermore, the aforementioned source data writing rules also include the writing order corresponding to the aforementioned source data set. The aforementioned writing methods can include CPU-based writing and preset module-based writing. The preset module-based writing method can perform the writing operation through a DMACC module, which is a hardware module within the SSD system capable of reading and writing SRAM. Furthermore, the SRAM also includes its capacity. In specific implementation, the step of writing test data can be performed through the following steps: Figure 4 A flowchart for writing test data is shown, such as... Figure 4 As shown, this step includes:

[0061] Step S1: Determine the first test data in the write order corresponding to the source data set as the test data corresponding to the read verification operation, and write test data that meets the capacity of the SRAM to be tested through CPU writing method according to the capacity of the SRAM to be tested.

[0062] Step S2: After the test data is written, perform a read verification operation on the SRAM to be tested based on the test data.

[0063] Specifically, if the source data set includes four types of test data such as 0x0, 0xFF, 0xAA55, and 0x55AA, where 0x0 can be the first test data, then the source data of the SRAM capacity can be written by the CPU module. For example, if the SRAM is 1M in size, then the CPU module writes 1M of 0x0 data, and then performs a read verification operation on the SRAM to be tested based on this 1M of 0x0 test data.

[0064] Step S3: After the read verification operation passes, the next test data in the write order corresponding to the source data set is determined as the test data corresponding to the read verification operation. Based on the capacity of the SRAM to be tested, the next test data in the source data set that meets the capacity of the SRAM to be tested is written by the CPU.

[0065] Specifically, among the four test data types 0x0, 0xFF, 0xAA55, and 0x55AA included in the above source data set, 0xFF can be the second test data. Therefore, after the read verification test of the 1M test data 0x0 passes, the CPU module writes 1M of 0xFF data, and then performs a read verification operation on the SRAM to be tested based on this 1M 0xFF test data.

[0066] Step S4 continues until each test data in the writing sequence is identified as the test data corresponding to the read verification operation and is written through the CPU writing method. After the read verification operation of the SRAM to be tested passes, the CPU writing method is switched to the preset module writing method, and each test data corresponding to the read verification operation is rewritten.

[0067] Specifically, after the CPU has completed writing the four test data (0x0, 0xFF, 0xAA55, and 0x55AA) included in the source data set according to the above steps, and after the read verification test is passed, the CPU module writing mode can be switched to the preset module writing mode. The preset module writes the four test data (0x0, 0xFF, 0xAA55, and 0x55AA) included in the source data set according to the above steps, and then performs the read verification process. At this time, the SRAM can be fully overwritten, thereby achieving a full data coverage test.

[0068] Step S304: Based on the preset verification method, perform a read verification operation on the SRAM to be tested according to the test data.

[0069] Specifically, the aforementioned preset verification methods include a first verification method and a second verification method, wherein the first verification method and the second verification method each include one of CPU verification and DMACC verification, and the first verification method and the second verification method are different from each other.

[0070] Furthermore, CPU verification can be used as the first verification method to perform read verification on the SRAM, that is, the CPU module accesses the SRAM to perform read verification. Then, DMACC verification can be used as the second verification method, that is, the DMACC module accesses the SRAM to perform read verification. Here, the first verification method refers to performing the read verification operation first, and the second verification method is used to perform the read verification operation after the first verification method has passed.

[0071] In practical implementation, the following steps can be used to perform data read verification operations on the SRAM under test. Specifically, Figure 5 A flowchart illustrating the data read verification operation of the SRAM under test is shown, such as... Figure 5 As shown, this step includes:

[0072] Step S10: The test data is compared with the data of the SRAM to be tested using the first verification method to perform a read verification operation.

[0073] Step S11: Determine whether the read verification result of the first verification method passes.

[0074] Step S12: If not, end the read verification operation and identify the SRAM to be tested in the first verification method as a faulty SRAM.

[0075] Specifically, the first verification method compares the previously written source data, starting from the initial data of the SRAM under test, with the data in the SRAM under test to achieve data overwriting. The read verification result corresponding to the first verification method is then determined. When the data overwriting is successful, it means that there is no data in the SRAM under test that does not match the source data, that is, all the data in the SRAM is correct. At this time, the read verification of the SRAM is considered successful. However, when the read verification detects SRAM data that does not match the written source data, it means that the SRAM data is incorrect. In this case, the SRAM is identified as an SRAM that has failed the data overwriting, that is, a faulty SRAM. At this time, the read verification operation ends, and the second verification method is no longer used for verification.

[0076] Step S13: If so, compare the test data with the data of the SRAM to be tested using the second verification method to perform a read verification operation.

[0077] Step S14: Determine whether the read verification result of the second verification method passes.

[0078] Step S15: If not, end the read verification operation and identify the SRAM to be tested in the second verification method as a faulty SRAM.

[0079] Step S16: If yes, complete the read verification operation.

[0080] Specifically, similar to the read verification operation of the first verification method, after the read verification operation of the first verification method passes, the second verification method is used to perform a second read verification on the SRAM data corresponding to the current source data, so as to filter out the faulty SRAM that cannot be filtered out by the first verification method.

[0081] Step S306: Determine whether the verification result of the read verification operation is successful.

[0082] Step S308: If not, end the read verification operation and identify the SRAM to be tested in the verification method as a faulty SRAM.

[0083] Specifically, when both the first and second verification methods pass the read verification operation, it indicates that the SRAM has passed the data coverage test. In this embodiment of the invention, when using the delayed read verification model for testing, after the SRAM undergoes full coverage of the data pattern, it can completely filter out SRAMs that are consistently faulty, such as those where a certain bit is always 0 or always 1.

[0084] Furthermore, in the above Figure 3 Based on this, the embodiments of the present invention also provide another method for screening faulty SRAMs. This method mainly describes the steps when the above test model is a delayed read verification model. Figure 6 A flowchart illustrating the testing of the SRAM under test using a delayed read verification model is shown, such as... Figure 6 As shown, the method includes:

[0085] Step S602: Write test data using a predefined writing method according to the preset source data writing rules.

[0086] Step S604: After the test data is written, wait for a preset time threshold, and then perform a read verification operation on the SRAM to be tested based on the test data.

[0087] Step S606: Determine whether the verification result of the read verification operation is successful.

[0088] Step S608: If not, end the read verification operation and identify the SRAM to be tested in the verification method as a faulty SRAM.

[0089] Specifically, when testing the SRAM under test using the delayed read verification model, the CPU module first writes the first test data in the source data set. After waiting for a preset time threshold, a read verification operation is performed using the first verification method. Once the read verification operation using the first verification method passes, a read verification operation is performed using the second verification method. This process continues until the read verification operation using the second verification method passes. Then, the CPU module writes the second data in the source data set, and after waiting for the preset time threshold, read verifications are performed sequentially in the same order. The read verification process of the delayed read verification model is consistent with that of the sequential write read verification model, and will not be elaborated further. Furthermore, after the CPU module has written each test data in the source data set, the DMACC module is switched to write each test data in the source data set using the aforementioned writing method. After each test data is written, a preset time threshold must also be waited for before a read verification operation is performed. The preset time threshold is determined based on the latency characteristics of the SRAM under test; the specific value of the time threshold is not limited here.

[0090] The embodiments of the present invention use a continuous read verification model to test the SRAM under test. After the data is retained for a specified time in a high-temperature environment, it can identify SRAMs with poor data retention capabilities.

[0091] Furthermore, in the above Figure 3 Based on this, embodiments of the present invention also provide another method for screening faulty SRAMs. This method mainly describes the steps when the above test model is a continuous read verification model. Figure 7 A flowchart illustrating the testing of the SRAM under test using a continuous read verification model is shown, such as... Figure 7 As shown, the method includes:

[0092] Step S702: The first test data in the writing order corresponding to the source data set is determined as the test data corresponding to the read verification operation, and test data of a preset byte size is written through the CPU writing method.

[0093] Specifically, in addition to the writing order of the source data sets, the above source data writing rules also include a preset byte size; specifically, the preset byte size may include the Dword size, and the SRAM is filtered according to a granularity of two bytes, wherein the preset byte size is smaller than the capacity of the SRAM to be tested.

[0094] Step S704: After the test data of the preset byte size is written, the test data of the preset byte size is compared with the data of the preset byte size of the SRAM to be tested using the first verification method and the second verification method in turn, and the comparison process is performed according to the preset number of verification repetitions to perform a read verification operation on the SRAM to be tested.

[0095] In the specific implementation, after the source data of the above-mentioned Dword size is written through the CPU module, the first verification method is used to perform the read verification operation. At this time, the first verification method is used to compare the test data of the preset byte size with the data of the corresponding preset byte size starting from the starting data of the SRAM to be tested. When the read verification operation of the first verification method passes, the second verification method is used to perform the read verification operation in the same way as the above-mentioned read verification method.

[0096] Furthermore, both the first and second verification methods mentioned above include a preset number of verification repetitions. That is, when using the first verification method to read and verify the SRAM, not only is a single comparison performed on the data of that byte size, but the current position of the SRAM is also repeatedly compared multiple times according to the preset number of verification repetitions. Specifically, the preset number of verification repetitions can be 20 times. By comparing the SRAM data at the same position multiple times, faulty SRAMs with probabilistic flipping can be effectively filtered out. Furthermore, the specific value of the preset number of verification repetitions is only to illustrate the probability of that number of repetitions and does not represent a limitation on the specific value of that number of repetitions.

[0097] Step S706: After the read verification operation passes, the next test data in the write order corresponding to the source data set is determined as the test data corresponding to the read verification operation. Based on the capacity of the SRAM to be tested, the next test data in the source data set that meets the capacity of the SRAM to be tested is written by the CPU.

[0098] Step S708: Continue until each test data in the writing sequence is determined to be the test data corresponding to the read verification operation and is written through the CPU writing method. After the read verification operation of the SRAM to be tested passes, the CPU writing method is converted to the preset module writing method, and each test data corresponding to the read verification operation is rewritten.

[0099] Step S710: Based on the preset verification method, perform a read verification operation on the SRAM to be tested according to the test data.

[0100] Specifically, after the CPU module finishes writing a preset byte size of test data for each test data, it reads and verifies it using the first verification method. After the read verification operation of the first verification method passes, it reads and verifies it using the second verification method. Then, it writes the remaining preset byte size of test data for this test data. This process continues until the CPU module finishes writing all the test data in the source data set. Then, it switches to the DMACC module to execute the writing process in this embodiment of the invention and performs the corresponding read verification operation using the same read verification method.

[0101] Step S712: Determine whether the verification result of the read verification operation is successful.

[0102] Step S714: If not, end the read verification operation and identify the SRAM to be tested in the verification method as a faulty SRAM.

[0103] Specifically, when using the continuous read verification model to test the SRAM under test, multiple tests are performed on data of byte size, and SRAM data with a probability of bit flipping is filtered out during the read verification operation. The test method of the test model in this embodiment of the invention targets small data bytes and performs multiple verifications on the same position, which can more accurately filter out faulty SRAM.

[0104] Furthermore, the embodiments of the present invention simultaneously use the above three test models, and combine them with a high-temperature chamber environment, as well as a dual read-write verification method of CPU and DMACC to screen SRAM, which can effectively screen out SRAM with multiple fault modes, thereby ensuring the stability of the system.

[0105] Furthermore, based on the above embodiments, this invention also provides a faulty SRAM screening device, which is used to perform the steps of the above-described faulty SRAM screening method. Figure 8 A schematic diagram of a faulty SRAM screening device is shown. Specifically, as... Figure 8 The diagram shows a structural schematic of a faulty SRAM screening device, which includes:

[0106] Temperature setting module 801 is used to set the test temperature;

[0107] Test module 802 is used to test the SRAM under test using a test model based on the test temperature and in a pre-set read / write order.

[0108] Module 803 is used to determine whether the test process of the test model has passed.

[0109] The filtering module 804 is used to end the test process and identify the SRAM to be tested as a faulty SRAM when the judgment result of the judgment module is negative.

[0110] Furthermore, the aforementioned test module 802 is also used to test the SRAM under test using the first model according to a pre-set read / write order; when the test of the first model passes, the test of the SRAM under test using the second model is used; when the test of the second model passes, the test of the SRAM under test using the third model is used; the aforementioned judgment module 803 is also used to determine that the test process of the test model has failed when the test of any test model fails.

[0111] Furthermore, the aforementioned test module 802 is also used to write test data according to a preset source data writing rule and a predefined writing method; perform a read verification operation on the SRAM to be tested based on the test data according to a preset verification method; determine whether the verification result of the read verification operation passes; if not, end the read verification operation and identify the SRAM to be tested in the verification method as a faulty SRAM.

[0112] Furthermore, the aforementioned test module 802 is also used to compare the test data with the data of the SRAM under test using a first verification method to perform a read verification operation; determine whether the read verification result of the first verification method passes; if not, end the read verification operation and identify the SRAM under test in the first verification method as a faulty SRAM; if yes, compare the test data with the data of the SRAM under test using a second verification method to perform a read verification operation; determine whether the read verification result of the second verification method passes; if not, end the read verification operation and identify the SRAM under test in the second verification method as a faulty SRAM; if yes, complete the read verification operation.

[0113] Furthermore, the aforementioned test module 802 is also used to determine the first test data in the write order corresponding to the source data set as the test data corresponding to the read verification operation, and write test data that meets the capacity of the SRAM under test through CPU writing mode according to the capacity of the SRAM under test; after the test data is written, a read verification operation is performed on the test data for the SRAM under test; after the read verification operation passes, the next test data in the write order corresponding to the source data set is determined as the test data corresponding to the read verification operation, and the next test data in the source data set that meets the capacity of the SRAM under test is written through CPU writing mode according to the capacity of the SRAM under test; until each test data in the write order is determined as the test data corresponding to the read verification operation and written through CPU writing mode, and after the read verification operation performed on the SRAM under test passes, the CPU writing mode is converted to the preset module writing mode, and each test data corresponding to the read verification operation is rewritten.

[0114] Furthermore, the aforementioned test module 802 is also used to perform a read verification operation on the SRAM to be tested after the test data has been written and after waiting for a preset time threshold.

[0115] Furthermore, the aforementioned test module 802 is also used to write test data of a preset byte size via CPU writing; after the preset byte size test data is written, the preset byte size test data is compared with the preset byte size data of the SRAM under test in turn using the first verification method and the second verification method, and the comparison process is executed according to the preset number of verification repetitions to perform a read verification operation on the SRAM under test.

[0116] The faulty SRAM screening device provided in this embodiment of the invention has the same technical features as the faulty SRAM screening method provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0117] Furthermore, based on the above embodiments, this invention also provides a hardware and software system for screening SRAM. This hardware and software system for screening SRAM is used to execute the above-mentioned method for screening faulty SRAM. The hardware and software system for screening SRAM includes an SSD controller chip, and a CPU module and a DMACC module configured on the SSD controller chip. The CPU module and the DMACC module are connected via a bus. The bus also connects to the SRAM to be tested. The CPU module is used to perform a write operation of the CPU write mode corresponding to the test model and a read verification operation of the first verification mode corresponding to the test model on the SRAM to be tested. The DMACC module is used to perform a write operation of the preset module write mode corresponding to the test model and a read verification operation of the second verification mode corresponding to the test model on the SRAM to be tested. The hardware and software system also includes a storage module for storing firmware programs and test results. The firmware program is used to implement the test strategy for screening SRAM.

[0118] The hardware and software system for screening SRAM provided in this embodiment of the invention has the same technical features as the method for screening faulty SRAM provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0119] This invention also provides a server, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the above-described... Figures 1 to 7 The steps of any of the methods shown. The server described above may be an SSD hard disk device, wherein the SSD hard disk device further includes an LED light, which can visually display the SRAM test results, or the SRAM test results can be viewed through a host computer tool.

[0120] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the above-described... Figures 1 to 7 The steps of any of the methods shown.

[0121] This invention also provides a schematic diagram of a server structure, as shown in the embodiment of the invention. Figure 9 The diagram shows the structure of the server, which includes a processor 91 and a memory 90. The memory 90 stores computer-executable instructions that can be executed by the processor 91. The processor 91 executes these computer-executable instructions to implement the aforementioned... Figures 1 to 7 Any of the methods shown.

[0122] exist Figure 9 In the illustrated embodiment, the server further includes a bus 92 and a communication interface 93, wherein the processor 91, the communication interface 93, and the memory 90 are connected via the bus 92.

[0123] The memory 90 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 93 (which can be wired or wireless), such as the Internet, wide area network, local area network, or metropolitan area network. The bus 92 may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. The bus 92 can be divided into an address bus, a data bus, and a control bus. For ease of representation, Figure 9 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0124] The processor 91 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 91 or by instructions in software form. The processor 91 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory. The processor 91 reads the information in the memory and, in conjunction with its hardware, completes the aforementioned task. Figures 1 to 7 Any of the methods shown.

[0125] The present invention provides a computer program product for a method, apparatus and hardware / software system for screening faulty SRAMs, including a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0126] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and apparatus described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0127] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0128] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0129] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0130] Finally, it should be noted that the above embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for screening faulty SRAMs, characterized in that, The method includes: Set the test temperature; Based on the test temperature, the SRAM under test is tested using multiple test models according to a pre-set read / write order. Determine whether the test process for each of the aforementioned test models passes; If not, the test process ends and the SRAM under test is identified as a faulty SRAM; The multiple test models include a first model, a second model, and a third model; wherein the first model, the second model, and the third model each include one of a sequential write-read verification model, a delayed read verification model, and a continuous read verification model, and the first model, the second model, and the third model are different from each other; The steps of testing the SRAM under test using multiple test models according to a pre-set read / write order include: According to the pre-set read / write order, the first model is used to test the SRAM to be tested first; When the first model passes the test, the second model is used to test the SRAM to be tested. When the second model passes the test, the third model is used to test the SRAM to be tested. The step of determining whether the test process for each of the test models passes includes: If any of the test models fails the test, then the test process of the test model is determined to have failed.

2. The method according to claim 1, characterized in that, The steps of testing the SRAM under test using multiple test models include: According to the preset source data writing rules, test data is written using a predefined writing method; Based on a preset verification method, a read verification operation is performed on the SRAM to be tested according to the test data; Determine whether the verification result of the read verification operation passes; If not, the read verification operation ends, and the SRAM to be tested in the verification method is identified as a faulty SRAM.

3. The method according to claim 2, characterized in that, The preset verification method includes a first verification method and a second verification method, wherein the first verification method and the second verification method each include one of CPU verification and DMACC verification, and the first verification method and the second verification method are different from each other. The step of performing a read verification operation on the SRAM under test based on the test data according to the preset verification method includes: The test data is compared with the data of the SRAM to be tested using the first verification method to perform the read verification operation. Determine whether the read verification result of the first verification method passes; If not, the read verification operation ends, and the SRAM to be tested in the first verification method is identified as a faulty SRAM; If so, the test data is compared with the data of the SRAM to be tested using the second verification method to perform the read verification operation; Determine whether the read verification result of the second verification method passes; If not, the read verification operation ends, and the SRAM to be tested in the second verification method is identified as a faulty SRAM; If so, complete the read verification operation.

4. The method according to claim 3, characterized in that, The source data writing rules include a source data set and a writing order corresponding to the source data set; the source data set includes multiple test data sets, wherein the multiple test data sets are typical test data for testing SRAM faults; the writing methods include CPU writing and preset module writing; the SRAM to be tested includes its capacity size; If the test model is a sequential write-read verification model, then the sequential write-read verification model is used to test the SRAM under test. The steps of writing test data according to a preset source data writing rule and using a predefined writing method, and performing a read verification operation on the SRAM under test based on the test data according to the preset verification method, include: The first test data in the write order corresponding to the source data set is determined as the test data corresponding to the read verification operation, and the test data that meets the capacity of the SRAM to be tested is written through the CPU writing method according to the capacity of the SRAM to be tested. After the test data is written, a read verification operation is performed on the SRAM to be tested based on the test data. After the read verification operation passes, the next test data in the write order corresponding to the source data set is determined as the test data corresponding to the read verification operation. Based on the capacity of the SRAM to be tested, the next test data in the source data set that meets the capacity of the SRAM to be tested is written through the CPU writing method. The process continues until each test data in the writing sequence is identified as the test data corresponding to the read verification operation and is written using the CPU writing method. After the read verification operation performed on the SRAM under test passes, the CPU writing method is switched to the preset module writing method, and each test data corresponding to the read verification operation is rewritten.

5. The method according to claim 4, characterized in that, If the test model is a delayed read verification model, then the delayed read verification model is used to test the SRAM to be tested; The step of performing a read verification operation on the SRAM under test based on the test data after the test data has been written further includes: After the test data is written, wait for a preset time threshold, and then perform a read verification operation on the SRAM to be tested based on the test data.

6. The method according to claim 4, characterized in that, If the test model is a continuous read verification model, then the continuous read verification model is used to test the SRAM to be tested; Both the first and second verification methods include a preset number of verification repetitions; the source data writing rules also include a preset byte size, wherein the preset byte size is smaller than the capacity of the SRAM to be tested; The step of writing test data that meets the capacity size of the SRAM under test using the CPU writing method according to the capacity size of the SRAM under test; and performing a read verification operation on the SRAM under test based on the test data after the test data is written, includes: Test data of a preset byte size is written using the CPU writing method; After the preset byte size of test data is written, the preset byte size of test data is compared with the preset byte size of data of the SRAM under test using the first verification method and the second verification method in sequence, and the comparison process is performed according to the preset number of verification repetitions to perform a read verification operation on the SRAM under test.

7. A device for screening faulty SRAMs, characterized in that, The faulty SRAM screening device is used to perform the faulty SRAM screening method according to any one of claims 1-6; The device includes: Temperature setting module, used to set the test temperature; The testing module is used to test the SRAM under test using a test model according to a pre-set read / write order based on the test temperature. The judgment module is used to determine whether the test process of the test model has passed; The filtering module is used to end the test process and identify the SRAM to be tested as a faulty SRAM when the judgment result of the judgment module is negative. The multiple test models include a first model, a second model, and a third model; wherein the first model, the second model, and the third model each include one of a sequential write-read verification model, a delayed read verification model, and a continuous read verification model, and the first model, the second model, and the third model are different from each other; The testing module is further configured to: test the SRAM under test using the first model according to a pre-set read / write order; when the test of the first model passes, test the SRAM under test using the second model; when the test of the second model passes, test the SRAM under test using the third model. The judgment module is further configured to: determine that the test process of the test model has failed when any one of the test models fails the test.

8. A hardware and software system for screening SRAM, characterized in that, The hardware and software system for screening SRAM is used to execute the method for screening faulty SRAM as described in any one of claims 1-6; The software and hardware system for screening SRAM includes an SSD controller chip, and a CPU module and a DMACC module configured on the SSD controller chip. The CPU module and DMACC module are connected via a bus; the SRAM to be tested is also connected to the bus. The CPU module is used to perform a write operation of the CPU write mode corresponding to the test model and a read verification operation of the first verification mode corresponding to the test model on the SRAM to be tested. The DMACC module is used to perform a write operation of the preset module write mode corresponding to the test model and a read verification operation of the second verification mode corresponding to the test model on the SRAM to be tested. The hardware and software system also includes a storage module for storing firmware programs and test results; The firmware program is used to implement a test strategy for screening SRAM.

9. A server, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method for screening faulty SRAM as described in any one of claims 1-6.

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