Thermoelectric semiconductor devices and their fabrication methods

Abstract

A thermoelectric semiconductor device includes a heat-dissipating semiconductor module and a flash memory die stack mounted on a substrate. The heat-dissipating module includes a first semiconductor die, such as a controller, and a second semiconductor die, such as a thermoelectric semiconductor die, to cool the first semiconductor die during operation. The thermoelectric semiconductor die can be mounted to the controller die at the wafer level.

Description

Background Technology

[0001] The robust growth in demand for portable consumer electronics has driven the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, are widely used to meet the ever-increasing demands for digital information storage and exchange. Their portability, versatility, and robust design, along with their high reliability and large capacity, make them ideal for a wide variety of electronic devices, including digital cameras, digital music players, video game consoles, PDAs, cellular phones, and solid-state drives.

[0002] While many different packaging configurations are known, flash memory semiconductor devices are typically assembled as system-in-package (SIP) or multi-chip module (MTF), in which multiple semiconductor memory dies are mounted together with controller dies such as ASICs and interconnected to the upper surface of a small-occupying-area substrate.

[0003] Current semiconductor packages operate using the high-speed PCIe interface standard. Current and next-generation semiconductor packages also operate at high power and high frequencies. All these factors cause semiconductor packages, and specifically controller dies, to generate significant amounts of heat. This heat can cause die failure and premature aging of the semiconductor dies. Therefore, it is necessary to reduce the operating temperature of current and future semiconductor packages. Attached Figure Description

[0004] Figure 1 This is a flowchart illustrating the process of forming a heat-dissipating semiconductor module according to an embodiment of the present invention.

[0005] Figure 2 This is a front view of a semiconductor wafer showing a first set of semiconductor dies formed in and / or on the first main surface of the wafer.

[0006] Figure 3 This is a front view of a semiconductor wafer showing a second set of semiconductor dies formed in and / or on the first main surface of the wafer.

[0007] Figure 4-8 These are edge views of thermoelectric semiconductor dies and heat dissipation semiconductor modules at various manufacturing stages according to embodiments of the present invention.

[0008] Figure 9 This is a flowchart illustrating an embodiment of the present invention for forming a thermoelectric semiconductor device using a heat dissipation semiconductor module.

[0009] Figure 10-15 This is an edge view of a thermoelectric semiconductor device including a heat dissipation semiconductor module at various manufacturing stages, according to an embodiment of the present invention.

[0010] Figure 16 This is an edge view showing a portion of a thermoelectric semiconductor device containing a heat-dissipating semiconductor module that operates according to the Seebeck effect.

[0011] Figure 17 It operates based on the Seebeck effect. Figure 16 A schematic diagram of a heat dissipation semiconductor module.

[0012] Figure 18 This is an edge view showing a portion of a thermoelectric semiconductor device containing a heat-dissipating semiconductor module that operates according to the Peltier effect.

[0013] Figure 19 It operates based on the Peltier effect. Figure 18 A schematic diagram of a heat dissipation semiconductor module. Detailed Implementation

[0014] The present invention will now be described with reference to the accompanying drawings, which, in an embodiment, relate to a thermoelectric semiconductor device including a heat-dissipating semiconductor module. In an embodiment, the thermoelectric semiconductor device includes a flash memory die stack mounted on a substrate and a heat-dissipating module. The heat-dissipating module includes a first semiconductor die, which in an embodiment may be a controller die attached to a second semiconductor die, which in an embodiment may be a thermoelectric semiconductor die for cooling the first semiconductor die. The thermoelectric semiconductor die can be mounted to the controller die at the wafer level, wherein the bottom surface of the thermoelectric semiconductor die is positioned at the interface between the dies.

[0015] The thermoelectric semiconductor die may be doped with pn regions, which generate a voltage potential across the thickness of the die under a temperature gradient between the top and bottom surfaces of the thermoelectric semiconductor die, and vice versa. Therefore, the thermoelectric semiconductor die can absorb heat from the controller die according to two different operating modes. In the first operating mode, the thermoelectric semiconductor die absorbs heat from the controller die according to the Seebeck effect. Here, the controller die heats up due to its operation, which in turn heats the bottom surface of the thermoelectric semiconductor die and generates a temperature gradient between the top and bottom surfaces of the second semiconductor die. This temperature gradient causes a voltage potential and a current flow away from the bottom surface of the thermoelectric semiconductor die, thus absorbing heat from the controller die when thermal energy is converted into electrical energy at the interface between the dies. In the second operating mode, the thermoelectric semiconductor die absorbs heat from the first semiconductor die according to the Peltier effect due to the applied voltage potential between the top and bottom surfaces of the second semiconductor die. This voltage potential and current flow create a temperature gradient in the thermoelectric semiconductor die, with the cold side located at the bottom surface of the die. This cold surface at the interface between the dies absorbs heat from the controller die.

[0016] In the embodiments described herein, the first semiconductor die is described as a controller die, such as an ASIC, for controlling communication between the thermoelectric semiconductor device and the host device. However, it should be understood that in other embodiments, the first semiconductor die to which the thermoelectric semiconductor die is attached can be a variety of different semiconductor dies.

[0017] It should be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey the invention to those skilled in the art. In fact, the invention is intended to cover alternatives, modifications, and equivalents to these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, many specific details are set forth in order to provide a thorough understanding of the invention. However, those skilled in the art will understand that the invention may be practiced without such specific details.

[0018] The terms “top” and “bottom,” “upper” and “lower”, and “vertical” and “horizontal” as used herein, and their forms, are for illustrative and explanatory purposes only and are not intended to limit the description of the technology, as the items mentioned may be interchangeable in position and orientation. Furthermore, as used herein, the terms “generally” and / or “about” mean that, for a given application, the specified dimensions or parameters may vary within acceptable manufacturing tolerances. In one embodiment, the acceptable manufacturing tolerance is ±2.5%.

[0019] For the purposes of this disclosure, the connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when the first element is referred to as a connection, attachment, or coupling to the second element, the first element and the second element can be directly connected, attached, or coupled to each other or indirectly connected, attached, or coupled to each other. When the first element is referred to as a direct connection, attachment, or coupling to the second element, there is no intermediate element between the first element and the second element (other than adhesives or metals used for connecting, attaching, or coupling the first element and the second element).

[0020] Reference Figure 1 and 9 Flowchart and Figure 2-8 The views in 10-19 illustrate embodiments of the invention. Figure 1-8 The description includes a heat-dissipating semiconductor module comprising a first semiconductor die and a second semiconductor die, and a method for manufacturing the same. Figure 9-19 Describes a thermoelectric semiconductor device including a heat dissipation semiconductor module and a method for manufacturing the same.

[0021] First refer to Figure 1 The flowchart shows that a first semiconductor wafer 100 can begin as a wafer material ingot, which can be formed in step 200. In one example, the ingot used to form the first wafer 100 can be single-crystal silicon grown according to a Czochralski (CZ) or floating zone (FZ) process. However, in another embodiment, the first wafer 100 can be formed from other materials and other processes. In step 202, the first semiconductor wafer 100 can be diced from the ingot, and on the first main surface 102 ( Figure 2 ) and the second main surface 104 opposite to surface 102 Figure 6 Both surfaces are polished to provide a smooth surface. At this point in the manufacturing process, the semiconductor wafer 100 may be approximately 760 micrometers (μm).

[0022] In step 204, the first main surface 102 may undergo various processing steps to divide the first wafer 100 into a first semiconductor die group 108. Figure 2 and 6 The first wafer 100 is formed on the first main surface 102, and an integrated circuit of the corresponding first semiconductor die 108 is formed thereon. In step 206, the second main surface of the first wafer 100 may be thinned to its final thickness in a back-side polishing process. The final thickness may be, for example, 25 μm to 50 μm, but may be greater or less than the thickness in other embodiments. In step 208, metal ball bumps 109 may be formed on the second main surface 104 of the first wafer. Figure 6 The integrated circuit can be electrically coupled to the metal bump bond 109 via a metallization layer (not shown) formed by metal interconnects and vias. The metal bump bond 109 can be formed of gold through pillar bumps, or using other metals and / or similar processes. The bump bond 109 can be formed in various patterns, the patterns being contained in a first direction ( Figure 6 The bumps extending on the left / right side of the middle are bonded to the row of 109 and / or in the second direction orthogonal to the first direction (entering the middle). Figure 6 The columns of bump bonding 109 extending on the page. The surface 102 containing the integrated circuit is also referred to herein as active surface 102, and the surface 104 is also referred to herein as non-active surface.

[0023] In one embodiment, semiconductor die 108 may be, for example, a controller die, such as an ASIC for controlling communication between a semiconductor device using die 108 and a host device. However, as mentioned, in another embodiment, die 108 may be other types of dies. In another instance, semiconductor die 108 from first wafer 100 may be an AI (artificial intelligence) semiconductor chip. Such a chip can be used to perform artificial intelligence processing on data stored in a stack of memory dies. It is also conceivable that die 108 may be a flash memory die, such as 2D NAND flash memory or 3D BiCS (bit-cost scalable), V-NAND, or other 3D flash memory. Other types of dies are possible for die 108. The number of semiconductor dies 108 shown on first wafer 100 in the figures is for illustrative purposes, and first wafer 100 may contain more semiconductor dies 108 than shown in other embodiments.

[0024] Before, after, or simultaneously with the fabrication of the first wafer 100, the second wafer 110 may be processed in steps 210-218. The second semiconductor wafer 110 may begin as a wafer material ingot, which may be formed in step 210. In one example, the ingot used to form the second wafer 110 may be single-crystal silicon grown according to a Czochralski (CZ) or floating region (FZ) process. However, in another embodiment, the second wafer 110 may be formed from other materials and other processes. In step 212, the second semiconductor wafer 110 may be diced from the ingot, and on the first main surface 112 ( Figure 2 ) and the second main surface 114 opposite to surface 112 Figure 4 Both surfaces are polished to provide a smooth surface. At this point in the manufacturing process, the semiconductor wafer 110 may be approximately 760 micrometers (μm).

[0025] In step 216, the second wafer 110 may undergo various processing steps to divide the second wafer 110 into a second semiconductor die group 118. Figure 3-6 The second semiconductor die 118 is doped with each of its adjacent pn charge carrier regions 116. The second die 118 can be doped using known doping techniques that introduce impurities into the second wafer 110 to change the adjacent region 116 to pn carriers of different charges. Region 116 can be formed as follows: Figure 3 The columns shown are as follows. Alternatively, the doping of the second wafer 110 may be limited to those regions forming the second set of semiconductor dies 118.

[0026] Figure 4This is an edge view of a single die 118 from wafer 110. The view shows a p-doped region 116a immediately adjacent to an n-doped region 116b. The view shows a die 118 doped over a portion of its thickness between a first or top main surface 112 and a second or bottom main surface 114. In another embodiment, the die 118 of the second wafer 110 may be doped over a smaller or larger thickness, encompassing the full thickness of the second wafer 110. In step 218, a copper layer 120 or other electrical and thermal conductors may be sputtered onto the top main surface 112 of the die 118 of the second wafer 110, such as... Figure 5 As shown in the image.

[0027] After forming the first set of dies 108 and the second set of dies 118 in the corresponding wafers 100 and 110, the wafers can be bonded to each other in step 220, such as... Figure 6 As shown in the diagram. Wafer 110 may, for example, be flipped and bonded to wafer 100. Wafer 100 may have copper pads (not shown) on its first main surface, and the wafers may be bonded using Cu-to-Cu bonding. Other bonding techniques are possible. Die 118 may have the same size as die 108 and be positioned within wafer 110 such that when the wafers are bonded, dies 108 and 118 are coupled together, as shown in the diagram. Figure 7 As shown in the edge view. Wafer mapping technology can be used to ensure that dies 108 and 118 are aligned with each other when wafer 110 is flipped and bonded to wafer 100. In another embodiment, it is conceivable that die 118 may be slightly larger or smaller than die 108. In step 224, the exposed surface of the second wafer 110 may be thinned to its final thickness in a back-side polishing process, as shown in 7. If not before the back-side polishing process, the full thickness of the thinned wafer 110 may be doped after the back-side polishing process. The final thickness of the second wafer may be, for example, 25 μm to 50 μm, but may be greater or less than the thickness in other embodiments. Figure 7 As shown, wafer 110 now has a top main surface 114 (which has been flipped) and a bottom main surface 112. Wafer 100 has a top main surface 102 and a bottom main surface 104.

[0028] In step 226, a copper layer 124 or other electrical and thermal conductors may be sputtered onto the top surface 114 of the bare die 118 of the wafer 110, such as... Figure 8 As shown in the figure, the copper layer 124 can be sputtered such that it has a first portion 124a over the p-doped region and a second portion 124b over the n-doped region, wherein the first portion 124a and the second portion 124b are electrically isolated from each other.

[0029] Once layer 124 is formed on top surface 114, the coupled semiconductor dies 108 and 118 can be cut apart in step 228. Several methods, including sawing, laser cutting, stealth laser cutting, waterjet cutting, and others, can be used to cut the dies 108 and 118. The cut semiconductor dies 108 and 118 (in...) Figure 8 (As shown in the figure) This document refers to the thermal semiconductor module 140, or simply HDSM 140.

[0030] The HDSM 140 can be mounted on a substrate together with one or more memory dies to form a thermoelectric semiconductor device, as will be discussed later. Figure 9 Flowcharts and Figure 10-19 As described in the view. Although Figure 10-19 Individual thermoelectric semiconductor devices 150 or a portion thereof are shown, but it should be understood that devices 150 may be batched together with multiple other thermoelectric semiconductor devices on the substrate panel to achieve economies of scale. The number of rows and columns of devices 150 on the substrate panel may vary.

[0031] The substrate panel used for manufacturing the thermoelectric semiconductor device 150 begins with multiple substrates 152 (again, Figure 10-19 (An example of such a substrate is shown). Substrate 152 can be various chip carrier media for transmitting signals between a semiconductor die on the substrate and a host device. These chip carrier media include printed circuit boards (PCBs), lead frames, or tape autobonding (TAB) carriers. In the case of a PCB, the substrate can be formed from a core sandwiched between a pair of conductive layers. The core can be formed from various dielectric materials such as polyimide laminates, epoxy resins containing FR4 and FR5, bismaleimide triazine (BT), etc. The conductive layers can be formed from copper or copper alloys, copper-plated or copper-plated alloys, Alloy 42 (42Fe / 58Ni), copper-plated steel, or other metals and materials suitable for use on a substrate panel.

[0032] In step 250, conductive patterns of vias, leads, and / or pads may be formed in and through the substrate 152. The substrate 152 may be drilled to define vias, which are then plated with and / or filled with conductive metal. Conductive patterns of traces and contact pads may then be formed on the top and / or bottom main planar surfaces of the substrate 152. Figure 10An example of a substrate 152 is shown, comprising vias 154, traces 156, and contact pads 158 formed on a first main planar surface of the substrate 152. The pattern of vias 154, traces 156, and contact pads 158 shown on the surface of the substrate 152 is shown as an example, and the substrate 152 may contain more or fewer vias, traces, and / or contact pads in other embodiments, and they may be located in different positions in other embodiments. The conductive patterns on the top and / or bottom surfaces of the substrate 152 may be formed using various known processes including, for example, various photolithography processes.

[0033] Refer again Figure 9 Next, the substrate 152 can be inspected in step 254. This step may include automated optical inspection (AOI). Once the inspection is performed, a solder mask 160 can be applied to the upper and / or lower surfaces of the substrate 152 in step 256. After the solder mask is applied, the contact pads 158 and any other areas to be soldered can be plated with Ni / Au, Alloy 42, etc., in step 258, for example, in a known electroplating or thin film deposition process.

[0034] Following inspection, in step 262, one or more passive components (not shown) may be mounted on substrate 152, including, for example, one or more capacitors, resistors, and / or inductors, but encompassing other components. In step 264, the HDSM 140 flip chip may be mounted onto the substrate, such as... Figure 11 As shown in the edge view. HDSM 140 can be physically and electrically coupled to contact pads 158 using bump bonding 109 on the bottom surface 104 of HDSM 140. In step 270, underfill epoxy 164 can be injected or flowed beneath HDSM 140, as... Figure 12 As shown, this is to seal any space between HDSM 140 and substrate 152. In another embodiment, bottom filling step 270 may be omitted.

[0035] In step 272, one or more semiconductor dies 170 may be mounted on substrate 152, such as Figure 13 As shown in the edge view. The semiconductor die 170 may be, for example, a flash memory die, such as 2D NAND flash memory or 3D BiCS (bit-cost scalable), V-NAND or other 3D flash memory, but other types of dies 170 may be used. These other types of semiconductor dies include, but are not limited to, controller dies such as ASICs, or RAM such as SDRAM, DDR SDRAM, LPDDR and GDDR.

[0036] Although Figure 13Four dies are shown, but in other embodiments, a different number of dies 170 may be present, including, for example, 1, 2, 8, 16, 32, 64, or other numbers of dies. Each die 170 may include dies along the edge of the semiconductor die (entering...). Figure 13 The page contains multiple die bonding pads 172. The dies may be stepped off such that the die bonding pads 172 of one die 170 are not covered by the next die 170 mounted thereon. In another embodiment, the dies 170 may be offset in opposite directions, or a first group of dies 170 may be offset in a first direction and a second group of dies 170 may be offset in the opposite direction.

[0037] In step 274, the HDSM 140 can be electrically interconnected to the substrate using bonding wire 176, and the semiconductor dies 170 can be electrically interconnected to each other and to the substrate 152 using bonding wire 178, as follows. Figure 14 As shown in the diagram. Bonding wires 176 and 178 can be formed using various wire bonding techniques. In one example, a wire bonding capillary (not shown) may initially form balls on pads (not shown) of copper portions 124a and 124b using thermal, ultrasonic energy, and / or pressure. The capillary may then extend wire 176 and form a wedge bond on contact pad 158 of the substrate to electrically couple the thermoelectric semiconductor die 118 of the HDSM 140 to the substrate 152. As noted above, the first semiconductor die 108 of the HDSM 140 is electrically coupled to the substrate when flip-chip bonded to the substrate via bump bonding 109. Bonding wire 178 may be formed similarly downwards and across die bonding pad 172 to electrically couple the memory dies to each other and to the substrate. Other wire bonding techniques may be used.

[0038] After the HDSM 140 and the die 170 are electrically connected to the substrate 152, in step 278 and as follows Figure 15 The semiconductor device 150 shown is encapsulated in a molding compound 180. The molding compound 180 may comprise, for example, solid epoxy resin, phenolic resin, fused silica, crystalline silica, carbon black, and / or metal hydroxide. Other molding compounds from other manufacturers are also included. The molding compound can be applied using various known processes, including compression molding, FFT (flow-free thin) molding, transfer molding, or injection molding techniques.

[0039] In the case where the thermoelectric semiconductor device 150 is used as a BGA (ball grid array) device, the solder balls 182 can be attached to the contact pads 158 on the lower surface of the substrate 152, such as Figure 15As shown in the diagram. Solder balls 182 can be used to solder the semiconductor device 150 to a host device, such as a printed circuit board (not shown). In cases where the thermoelectric semiconductor device 150 will be used as an LGA (planar grid array) device, the solder balls can be replaced with contact fingers on the lower surface of the substrate 152.

[0040] As noted above, the semiconductor device 150 may be formed on a panel of a substrate. After the semiconductor device 150 is formed and packaged, the devices 150 may be separated from each other in step 282 to form the finished semiconductor device 150 as shown in 15. The semiconductor device 150 may be separated by any of a variety of cutting methods, including sawing, waterjet cutting, laser cutting, water-guided laser cutting, dry dielectric cutting, and diamond-coated wire cutting. While straight-line cutting will define the semiconductor device 150 as generally rectangular or square, it should be understood that in other embodiments of the invention, the semiconductor device 150 may have shapes other than rectangular and square.

[0041] The present invention provides a thermoelectric semiconductor device 150 comprising heat dissipation from a semiconductor die 108 within the device, and a method for manufacturing said thermoelectric semiconductor device. Heat is dissipated from the semiconductor die 108 via a thermoelectric semiconductor die 118, which dissipates according to the Seebeck effect (hereinafter referred to as...). Figure 16 and 17 (Explanation) and / or the Peltier effect (as discussed below) Figure 18 and 19 (Explanation) Remove heat.

[0042] First refer to Figure 16 and 17 This diagram shows a portion of the HDSM 140 and substrate 152 of device 150. As noted above, the semiconductor die 108 may be, for example, a controller die, but in other instances, the semiconductor die may be other types of dies. During operation, die 108 will generate heat. As noted in the Background section, the heat generated by die 108 may damage die 108 or other dies within device 150.

[0043] The thermoelectric semiconductor die 118 is therefore configured to cool the die 108. Heat from the die 108 will heat the bottom surface 112 of the thermoelectric semiconductor die 118, thus causing heat to accumulate on the bottom surface 112 (T). H ) and top surface 114 (T C A temperature gradient is generated between them. For example, by Figure 17 As indicated by arrow 192 in the image, this temperature gradient (T) H -T CThis will cause charge migration from the hot surface to the cold surface of the bare die 118 in regions 116a and 116b according to the Seebeck effect. This charge migration will... Figure 16 Current is generated in the direction of arrow 194, passing through the bonding wire 176 and the conductor within the substrate 152.

[0044] Under the principle of energy conservation, this electrical energy is converted from thermal energy, specifically from heat from the bottom surface 112 of the die 108 and die 118. In this manner, in this embodiment, the thermoelectric die 118 absorbs heat from the die 108, thereby cooling the die 108. This method of absorbing heat from the die 108 according to the Seebeck effect, without the supply of external current to the cooling die 108, is referred to as passive heat dissipation.

[0045] Now for reference Figure 18 and 19 This illustrates a portion of the HDSM 140 and substrate 152 of device 150. This embodiment operates based on the Peltier effect and includes a current source 196 applied, for example, through contact pads 158 of substrate 152. Figure 19 This current will cause charge migration in pn regions 116a and 116b from the bottom surface 114 to the top surface 112 of the thermoelectric bare plate 118. This charge migration will create a temperature gradient between the top and bottom surfaces, as heat is transferred from the bottom surface 112 (T). C ) is carried towards the top surface 114 (T) H The cooling of the bottom surface 112 draws heat from the bare die 108, thus cooling the bare die 108. The bonding wires 176 also dissipate heat from the top surface 114 (T). H The heat is transferred to the contact pads 158 of the substrate 152, and then dissipated into the surrounding environment through the thermal traces of the substrate 152. In this embodiment, the extraction of heat from the die 108 based on the Peltier effect, where cooling of the die 108 is achieved by applying an external current, is referred to as active heat dissipation.

[0046] In summary, examples of the present invention relate to a method for forming a heat-dissipating semiconductor module, comprising the following steps: forming a first set of semiconductor dies on a first wafer by forming an integrated circuit and a metallization layer in a region defining the first set of semiconductor dies on a first main surface of the first wafer; forming a second set of semiconductor dies on a second wafer by doping a pn region at least in a region defining the second set of semiconductor dies on the second wafer and forming an electrical conductor at least in a region defining the second set of semiconductor dies on the main surface of the second wafer; attaching a first semiconductor wafer and a second semiconductor wafer together, the first set of semiconductor dies formed on the first wafer and the second set of semiconductor dies formed on the second wafer, such that the first set of semiconductor dies and the second set of semiconductor dies are aligned with each other after the first semiconductor wafer and the second semiconductor wafer are attached together, and corresponding pairs of aligned and connected first semiconductor dies and second semiconductor dies from the first set of semiconductor dies and the second set of semiconductor dies respectively form a heat-dissipating semiconductor module in a heat-dissipating semiconductor module; and dicing the heat-dissipating semiconductor module from the attached first semiconductor wafer and the second semiconductor wafer.

[0047] In another example, the present invention relates to a method for forming a heat-dissipating semiconductor module, comprising the steps of: forming a first set of semiconductor dies on a first wafer, which is performed by forming an integrated circuit and a metallization layer in a region defining the first set of semiconductor dies on a first main surface of the first wafer; forming a second set of semiconductor dies on a second wafer, the second set of semiconductor dies being thermoelectric semiconductor dies, which is formed by doping at least a pn region in a region defining the second set of semiconductor dies on the second wafer such that a temperature gradient or voltage potential between the first and second surfaces of the semiconductor dies of the second set of semiconductor dies causes charge carriers to be generated in the semiconductor dies. The process involves a migration step between the first surface and the second surface; attaching a first semiconductor wafer and a second semiconductor wafer together, forming a first set of semiconductor dies on the first wafer and a second set of semiconductor dies on the second wafer, such that the first set of semiconductor dies and the second set of semiconductor dies are aligned with each other after the first semiconductor wafer and the second semiconductor wafer are attached together, and corresponding pairs of aligned and connected first semiconductor dies and second semiconductor dies from the first set of semiconductor dies and the second set of semiconductor dies each form a heat dissipation semiconductor module in a heat dissipation semiconductor module; and cutting the heat dissipation semiconductor module from the attached first semiconductor wafer and the second semiconductor wafer.

[0048] In another example, the present invention relates to a method of forming a thermoelectric semiconductor device, comprising the steps of: attaching a heat dissipation semiconductor module to a substrate, the heat dissipation semiconductor module being formed by attaching a first wafer including a controller die to a second wafer including a thermoelectric semiconductor die and dicing the first and second wafers such that the controller die attached to the thermoelectric semiconductor die forms a plurality of heat dissipation semiconductor modules including the heat dissipation semiconductor module; attaching one or more flash memory dies to the substrate; electrically coupling the heat dissipation semiconductor module to the substrate; and electrically coupling one or more flash memory dies to the substrate.

[0049] For purposes of illustration and description, the foregoing specific embodiments of the invention have been presented. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and with various modifications suitable for the particular intended use. It is intended that the scope of the invention be defined by the appended claims.

Claims

1. A method for forming a heat-dissipating semiconductor module, comprising the following steps: Forming a first set of semiconductor dies on a first wafer is performed by forming an integrated circuit and a metallization layer in a first main surface of the first wafer in a region defining the first set of semiconductor dies. A second set of semiconductor dies is formed on a second wafer. The second set of semiconductor dies is a thermoelectric semiconductor die, which is achieved by doping at least a pn region in a region of the second wafer defining the second set of semiconductor dies, such that a temperature gradient or voltage potential between the first and second surfaces of the semiconductor dies causes charge carriers to migrate between the first and second surfaces of the semiconductor dies. Specifically, a first electrically conductive portion and a second electrically conductive portion, electrically isolated from each other, are formed on the second surface of the semiconductor dies by sputtering. The first electrically conductive portion is located above the p-doped region, and the second electrically conductive portion is located above the n-doped region. The first set of semiconductor dies and the second set of semiconductor dies on the first wafer and the second wafer are formed such that, after bonding the first semiconductor wafer and the second semiconductor wafer, the first set of semiconductor dies and the second set of semiconductor dies are aligned to form the heat dissipation semiconductor module; and The second group of semiconductor dies is a thermoelectric semiconductor die used to cool the first group of semiconductor dies.

2. The method of claim 1, wherein the step of forming the first set of semiconductor dies and the second set of semiconductor dies further comprises the step of forming semiconductor dies from the first set to have the same size as semiconductor dies from the second set.

3. The method of claim 1, wherein the step of forming the first set of semiconductor dies includes the step of forming the first set of semiconductor dies into controller dies.

4. The method of claim 1, wherein the step of forming the second set of semiconductor dies includes, after connecting the heat dissipation semiconductor module to the circuit and heating the first semiconductor die, configuring the second semiconductor die to have a voltage potential between the first surface and the second surface of the semiconductor die.

5. The method of claim 1, wherein the step of forming the second set of semiconductor dies includes, after connecting the heat dissipation semiconductor module to the circuit and allowing current to flow through the circuit, configuring the second set of semiconductor dies to have a temperature gradient between the first surface and the second surface of the semiconductor dies.

6. A method for forming a thermoelectric semiconductor device, comprising the following steps: A first wafer is received comprising a first set of semiconductor dies, the first semiconductor dies including an integrated circuit having a metallization layer in a first main surface of the first wafer in a region defining the first set of semiconductor dies; A second wafer is received comprising a second set of semiconductor dies, the second semiconductor die including a thermoelectric semiconductor die formed by doping at least a pn region in a region defining the second semiconductor die of the second wafer such that a temperature gradient or voltage potential between a first surface and a second surface of the second semiconductor die causes charge carriers to migrate between the first surface and the second surface of the second semiconductor die, wherein a first electrically conductive portion and a second electrically conductive portion electrically isolated from each other are formed on the second surface of the second semiconductor die by sputtering, the first electrically conductive portion being located above the p-doped region and the second electrically conductive portion being located above the n-doped region; and A first semiconductor wafer and a second semiconductor wafer are joined together, and the first semiconductor die and the second semiconductor die on the first wafer and the second wafer are aligned to form a heat-dissipating semiconductor module; and The second semiconductor die is a thermoelectric semiconductor die used to cool the first semiconductor die.

7. The method of claim 6, further comprising the step of cutting the heat dissipation semiconductor module.

8. The method of claim 7, further comprising the step of forming a first electrical conductor on a first main surface of the second wafer at least in the region defining the second set of semiconductor dies.

9. The method of claim 8, further comprising the step of forming a second conductive layer on a second main surface opposite to the first main surface on the second semiconductor wafer.

10. The method of claim 9, wherein the step of forming the second conductive layer on the second main surface of the second semiconductor wafer occurs after the step of dicing the heat dissipation semiconductor module from the attached first semiconductor wafer and the second semiconductor wafer.

11. The method of claim 6, further comprising the step of back-side grinding a second main surface of the first semiconductor wafer opposite to the first main surface of the first semiconductor wafer, and then attaching the first semiconductor wafer and the second semiconductor wafer.

12. The method of claim 11, further comprising, after the step of back-side grinding of the second main surface of the first semiconductor die, forming bump bonding on the second main surface of the first semiconductor die.

13. The method for forming a thermoelectric semiconductor device according to claim 6, further comprising the following steps: Attach the heat dissipation semiconductor module to the substrate; The first semiconductor die of the heat dissipation semiconductor module is electrically coupled to the substrate; as well as The second semiconductor die of the heat dissipation semiconductor module is electrically coupled to the substrate.

14. The method of claim 13, wherein the step of electrically coupling the first semiconductor die to the substrate includes the step of flip-chip bonding the first semiconductor die to a first set of contact pads on the substrate.

15. The method of claim 14, wherein the step of electrically coupling the second semiconductor die to the substrate includes the step of bonding the second semiconductor die wires to a second set of contact pads on the substrate.

16. The method of claim 13, further comprising the step of attaching and electrically coupling one or more flash memory dies to the substrate.

17. The method of claim 16, wherein the one or more flash memory dies are stacked on top of each other, and the stack is positioned adjacent to the heat dissipation semiconductor module.

18. A method for forming a thermoelectric semiconductor device, comprising the following steps: A heat dissipation semiconductor module is attached to a substrate. The heat dissipation semiconductor module is formed by attaching a first wafer including a controller die to a second wafer including a thermoelectric semiconductor die and dicing the first and second wafer assemblies such that the controller die attached to the thermoelectric semiconductor die forms a plurality of heat dissipation semiconductor modules containing the heat dissipation semiconductor module. The thermoelectric semiconductor die is doped with pn regions such that a temperature gradient or voltage potential between the first and second surfaces of the thermoelectric semiconductor die causes cooling of the controller die. The second surface of the thermoelectric semiconductor die has a first electrically conductive portion and a second electrically conductive portion electrically isolated from each other, the first electrically conductive portion being located above the p-doped region and the second electrically conductive portion being located above the n-doped region. One or more flash memory dies are attached to the substrate adjacent to the heat dissipation semiconductor module; Electrically coupling the heat dissipation semiconductor module to the substrate; and The one or more flash memory dies are electrically coupled to the substrate, wherein the substrate facilitates electrical communication between the controller die and the one or more flash memory dies; and The thermoelectric semiconductor die is used to cool the controller die.

19. The method of claim 18, wherein the step of electrically coupling the heat dissipation semiconductor module to the substrate includes the step of electrically coupling bump bonding on the surface of the controller die to contact pads on the substrate.

20. The method of claim 19, wherein the contact pads comprise a first set of contact pads, and the step of electrically coupling the heat dissipation semiconductor module to the substrate further comprises the step of electrically coupling the surface of the thermoelectric semiconductor die to a second set of contact pads on the substrate.

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