Semiconductor structure and its preparation method

Abstract

This invention relates to a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a through-silicon via (TSV) within the substrate, wherein the depth of the TSV is less than the thickness of the substrate; forming an inner liner layer on the sidewalls and bottom of the TSV, and forming a conductive layer within the TSV; wherein the inner liner layer includes a polishing stop layer. In the above method for fabricating the semiconductor structure, the addition of a polishing stop layer during the fabrication of the inner liner layer allows for precise control of the polishing progress during subsequent polishing processes, enabling timely adjustment of the polishing speed and preventing over-polishing that could damage the conductive layer within the TSV.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices and their manufacturing, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] With the development of semiconductor technology, the feature size of integrated circuits is constantly shrinking, and the interconnect density of devices is constantly increasing. Traditional two-dimensional packaging can no longer meet the needs of the industry. Therefore, vertical interconnect stacked packaging based on through silicon via (TSV) technology, with its key technological advantages of short-distance interconnection and high-density integration, has gradually led the trend of packaging technology development.

[0003] In existing through-silicon via (TSV) technology, when grinding after filling the TSV with metal material, it is difficult to effectively control the grinding rate and thickness, which can easily lead to over-grinding. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the over-polishing problem that occurs in through-silicon via (TSV) technology.

[0005] A method for fabricating a semiconductor structure includes: providing a substrate; forming a through-silicon via (TSV) within the substrate, wherein the depth of the TSV is less than the thickness of the substrate; forming an inner liner layer on the sidewalls and bottom of the TSV, and forming a conductive layer within the TSV; the inner liner layer includes a polishing stop layer.

[0006] In the above-mentioned semiconductor structure fabrication method, a grinding stop layer is added during the fabrication of the inner liner. This allows for the determination of the grinding progress and timely adjustment of the grinding speed during subsequent grinding processes, preventing over-grinding that could damage the conductive layer in the through-silicon via.

[0007] In one embodiment, an inner liner layer is formed on the sidewalls and bottom of the through-silicon via (TSV), and a conductive layer is formed within the TSV, comprising: forming a first polishing stop layer on the upper surface of the substrate and on the sidewalls and bottom of the TSV; forming a first filling dielectric layer on the surface of the first polishing stop layer; forming a second polishing stop layer on the surface of the first filling dielectric layer; forming a second filling dielectric layer on the surface of the second polishing stop layer; forming a conductive layer on the surface of the second filling dielectric layer, the conductive layer covering the upper surface of the second filling dielectric layer and filling the TSV; and removing the conductive layer, the second filling dielectric layer, the second polishing stop layer, and the first filling dielectric layer located on the substrate.

[0008] In one embodiment, both the first filling dielectric layer and the second filling dielectric layer include a silicon oxide layer, and both the first polishing stop layer and the second polishing stop layer include a silicon nitride layer or a silicon carbonitride layer.

[0009] In one embodiment, the substrate includes an array region and a peripheral region surrounding the array region, with through-silicon vias located in the peripheral region; the substrate includes a substrate and a first dielectric layer on the upper surface of the substrate, with a plurality of device cells arranged in an array within the first dielectric layer of the array region; after removing the conductive layer and the second filling dielectric layer on the substrate, and before removing the second polishing stop layer on the substrate, the method further includes: forming interconnect vias that expose the device cells; forming interconnect material layers within the interconnect vias and on the upper surface of the second polishing stop layer; removing the interconnect material layer on the upper surface of the second polishing stop layer; simultaneously removing the second polishing stop layer and the first filling dielectric layer on the substrate, removing the interconnect material layer on the first polishing stop layer, leaving the interconnect material layer within the interconnect vias as an interconnect structure, with the upper surface of the interconnect structure flush with the upper surface of the first polishing stop layer.

[0010] In one embodiment, after forming the interconnect structure, the method further includes: forming a second dielectric layer on the upper surface of the first grinding stop layer, the upper surface of the interconnect structure, the upper surface of the inner liner layer and the upper surface of the conductive layer; forming a trench in the second dielectric layer, the trench exposing the interconnect structure and the conductive layer; and forming a metal layer in the trench.

[0011] In one embodiment, after forming the conductive layer within the through-silicon via, the method further includes: thinning the substrate on the back side until the bottom of the conductive layer is exposed.

[0012] In one embodiment, a back-side thinning process is used to thin the substrate using a polishing process. The back-side thinning of the substrate includes: thinning the substrate at a first polishing rate until a polishing stop layer is exposed; and continuing to thin the substrate at a second polishing rate until the bottom of the conductive layer is exposed; wherein the second polishing rate is less than the first polishing rate.

[0013] In one embodiment, the first dielectric layer includes a silicon nitride layer or a silicon oxide layer, the second dielectric layer includes a silicon oxide layer, and the interconnect structure includes at least one of a tungsten layer, an aluminum layer, a copper layer, and a titanium nitride layer.

[0014] In one embodiment, the device unit includes a memory unit.

[0015] In one embodiment, the width of the interconnect via is smaller than the width of the through silicon via.

[0016] A semiconductor structure includes: a substrate; a through-silicon via (TSV) located within the substrate, the depth of the TSV being less than the thickness of the substrate; an inner liner layer located at least on the sidewalls and bottom of the TSV, the inner liner layer including a polishing stop layer; and a conductive layer located within the TSV and filling the TSV.

[0017] In one embodiment, the inner liner includes a first polishing stop layer, a first filling dielectric layer, a second polishing stop layer, and a second filling dielectric layer stacked sequentially from the substrate to the conductive layer.

[0018] In one embodiment, both the first filling dielectric layer and the second filling dielectric layer include a silicon oxide layer, and both the first polishing stop layer and the second polishing stop layer include a silicon nitride layer or a silicon carbonitride layer.

[0019] In one embodiment, the substrate includes an array region and a peripheral region surrounding the array region, with through-silicon vias located in the peripheral region; the substrate includes a substrate and a first dielectric layer on the upper surface of the substrate, with a plurality of device cells arranged in an array within the first dielectric layer of the array region; a first polishing stop layer extends to the upper surface of the first dielectric layer; the semiconductor structure further includes: an interconnect structure, the bottom of which is in contact with the device cells, and the upper surface of which is flush with the upper surface of the first polishing stop layer; a second dielectric layer located on the upper surface of the first polishing stop layer, the upper surface of the inner liner layer, and the upper surface of the conductive layer; and a metal layer located within the second dielectric layer and in contact with the device cells and the conductive layer.

[0020] In one embodiment, the first dielectric layer includes a silicon nitride layer or a silicon oxide layer, the second dielectric layer includes a silicon oxide layer, the interconnect structure includes at least one of a tungsten layer, an aluminum layer, a copper layer, and a titanium nitride layer, and the device unit includes a memory unit.

[0021] In the aforementioned semiconductor structure, a grinding stop layer is formed in the inner liner of the through-silicon via (TSV). During the process of drilling the TSV on the back side of the substrate, the grinding stop layer can be used to determine the grinding progress, adjust the grinding speed in time, and avoid over-grinding that could damage the conductive layer in the TSV. Attached Figure Description

[0022] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application.

[0023] Figure 2 This is a schematic diagram of the cross-sectional structure of a substrate according to one embodiment of this application.

[0024] Figure 3 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a through-silicon via in one embodiment of this application.

[0025] Figure 4 This is a schematic cross-sectional view of the semiconductor structure obtained after forming the inner liner layer in one embodiment of this application.

[0026] Figure 5 This is a schematic cross-sectional view of a semiconductor structure obtained after forming a conductive layer on the upper surface of the second filling dielectric layer and inside the silicon via in one embodiment of this application.

[0027] Figure 6 This is a schematic cross-sectional view of a semiconductor structure obtained after forming a conductive layer in a through-silicon via in one embodiment of this application.

[0028] Figure 7 This is a schematic cross-sectional view of the semiconductor structure obtained after forming interconnect vias in one embodiment of this application.

[0029] Figure 8 This is a schematic cross-sectional view of the semiconductor structure obtained after forming an interconnect material layer in one embodiment of this application.

[0030] Figure 9 This is a schematic cross-sectional view of the semiconductor structure obtained after forming the interconnect structure in one embodiment of this application.

[0031] Figure 10 This is a schematic cross-sectional view of the semiconductor structure obtained after forming the second dielectric layer in one embodiment of this application.

[0032] Figure 11 This is a schematic cross-sectional view of a semiconductor structure obtained after forming a trench in the second dielectric layer in one embodiment of this application.

[0033] Figure 12 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a metal layer in one embodiment of this application.

[0034] Figure 13 This is a schematic cross-sectional view of a semiconductor structure obtained by back-side thinning of a substrate in one embodiment of this application.

[0035] Explanation of reference numerals in the attached figures: 11, substrate; 111, first dielectric layer; 112, substrate; 12, device unit; 13, through-silicon via; 141, first polishing stop layer; 142, first filling dielectric layer; 143, second polishing stop layer; 144, second filling dielectric layer; 15, conductive layer; 16, interconnect via; 17, interconnect material layer; 18, interconnect structure; 19, second dielectric layer; 20, trench; 21, metal layer. Detailed Implementation

[0036] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0038] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it may be directly on the other film layer or there may be intermediate film layers. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate layers. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0039] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0040] In existing through-silicon via (TSV) technologies, when grinding after filling the TSV with metal material, it is difficult to effectively control the grinding rate and thickness, easily leading to over-grinding. To address these issues, one embodiment of this application provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, it includes:

[0041] S10: Provides substrate 11.

[0042] As an example, such as Figure 2 As shown, the substrate 11 may include a substrate 112 and a first dielectric layer 111 on the upper surface of the substrate 112. A plurality of device cells 12 arranged in an array are further formed within the first dielectric layer 111. The device cells 12 may be memory cells, and the first dielectric layer 111 may be a silicon nitride layer or a silicon oxide layer. Optionally, the upper surface of the first dielectric layer 111 may be planarized, for example, by chemical mechanical polishing.

[0043] S20: A through-silicon via 13 is formed in the substrate 11, wherein the depth of the through-silicon via 13 is less than the thickness of the substrate 11.

[0044] Specifically, the substrate 11 includes an array region and a peripheral region surrounding the array region. In this embodiment, the through-silicon via (TSV) 13 is formed in the peripheral region. As an example, the TSV 13 can be formed in the peripheral region of the substrate 11 using photolithography. Figure 3As shown, the through-silicon via 13 penetrates the first dielectric layer 111 and extends partially into the substrate 112.

[0045] S30: An inner liner layer is formed on the sidewall and bottom of the through-silicon via 13, and a conductive layer 15 is formed inside the through-silicon via 13; the inner liner layer includes a grinding stop layer.

[0046] Specifically, the inner liner layer comprises a filling medium layer and a grinding stop layer stacked sequentially. For example... Figures 4 to 5 As shown, the steps for forming the inner liner layer and the conductive layer 15 are as follows:

[0047] S31: A first grinding stop layer 141 is formed on the upper surface of the substrate 11 and the sidewalls and bottom of the through silicon via 13.

[0048] S32: A first filling medium layer 142 is formed on the surface of the first grinding stop layer 141.

[0049] S33: A second grinding stop layer 143 is formed on the surface of the first filling medium layer 142.

[0050] S34: A second filling medium layer 144 is formed on the surface of the second grinding stop layer 143.

[0051] S35: A conductive layer 15 is formed on the surface of the second filling dielectric layer 144, the conductive layer 15 covering the upper surface of the second filling dielectric layer 144 and filling the through silicon via 13.

[0052] S36: Remove the conductive layer 15, the second filling dielectric layer 144, the second polishing stop layer 143, and the first filling dielectric layer 142 located on the substrate 11.

[0053] The first filling dielectric layer 142 and the second filling dielectric layer 144 can be silicon oxide layers, the first polishing stop layer 141 and the second polishing stop layer 143 can be silicon nitride layers or silicon carbonitride layers, and the conductive layer 15 can be copper.

[0054] As an example, a schematic diagram of the cross-sectional structure of the semiconductor structure obtained after forming an inner liner layer on the sidewall and bottom of the through-silicon via 13 is shown below. Figure 4 As shown. Figure 5This is a schematic cross-sectional view of the semiconductor structure formed after the conductive layer 15 covers the upper surface of the second filling dielectric layer 144 and fills the through-silicon via 13. The conductive layer 15 can be formed on the surface of the second filling dielectric layer 144 using an electroplating process. Optionally, after forming the first polishing stop layer 141, the first filling dielectric layer 142, the second polishing stop layer 143, the second filling dielectric layer 144, and the conductive layer 15, a planarization process, such as chemical mechanical polishing, can be performed on the surfaces of each material layer.

[0055] The above-described semiconductor structure fabrication method incorporates a grinding stop layer during the fabrication of the inner liner. This allows for precise control of the grinding progress during subsequent grinding processes, enabling timely adjustments to the grinding speed and preventing over-grinding that could damage the conductive layer 15 within the through-silicon via 13.

[0056] In one embodiment, after removing the conductive layer 15 and the second filling dielectric layer 144 located on the substrate 11, and before removing the second polishing stop layer 143 located on the substrate 11, the following steps are included:

[0057] S361: Form an interconnect via 16, which exposes the device unit 12.

[0058] Figure 6 This is a schematic cross-sectional view of the semiconductor structure formed after removing the conductive layer 15 and the second filling dielectric layer 144 located on the substrate 11. To form the interconnect via 16, it is possible to... Figure 6 A photoresist layer with a photolithographic pattern is formed on the structure shown, and the position of the photolithographic pattern corresponds to the device unit 12 in the first dielectric layer 111. Then, based on the photolithographic pattern, the second polishing stop layer 143, the first filling dielectric layer 142, the first polishing stop layer 141, and the first dielectric layer 111 are etched to form interconnect vias 16, such as... Figure 7 As shown.

[0059] S362: An interconnect material layer 17 is formed in the interconnect via 16 and on the upper surface of the second grinding stop layer 143.

[0060] As an example, the interconnect material layer 17 can be at least one of a tungsten layer, an aluminum layer, a copper layer, and a titanium nitride layer. A schematic cross-sectional view of the semiconductor structure obtained after forming the interconnect material layer 17 is shown below. Figure 8 As shown.

[0061] S363: Remove the interconnect material layer 17 located on the upper surface of the second grinding stop layer 143.

[0062] S364: While removing the second polishing stop layer 143 and the first filling medium layer 142 located on the substrate 11, remove the interconnect material layer 17 located on the first polishing stop layer 141, and retain the interconnect material layer 17 in the interconnect via 16 as an interconnect structure 18, the upper surface of the interconnect structure 18 being flush with the upper surface of the first polishing stop layer 141.

[0063] To form the interconnect structure 18, excess interconnect material layer 17 needs to be removed. Specifically, firstly, the polishing equipment is controlled to polish the interconnect material layer 17 on the upper surface of the second polishing stop layer 143 to remove it. When polishing reaches the second polishing stop layer 143, the polishing resistance changes; for example, the polishing resistance increases significantly. At this point, the polishing speed of the polishing equipment is reduced, and polishing continues to remove the second polishing stop layer 143 and the first filling dielectric layer 142. Finally, when polishing reaches the first polishing stop layer 141, the polishing resistance changes again. At this point, the polishing equipment is stopped, resulting in the interconnect structure 18. A schematic cross-sectional view of the semiconductor structure obtained after forming the interconnect structure 18 is shown below. Figure 9 As shown, the upper surface of the interconnect structure 18 is flush with the upper surface of the first polishing stop layer 141. The interconnect structure 18 may be at least one of a tungsten layer, an aluminum layer, a copper layer, and a titanium nitride layer.

[0064] In one embodiment, after forming the interconnect structure 18, the following is also included:

[0065] S365: A second dielectric layer 19 is formed on the upper surface of the first polishing stop layer 141, the upper surface of the interconnect structure 18, the upper surface of the inner liner layer, and the upper surface of the conductive layer 15.

[0066] As an example, a schematic diagram of the cross-sectional structure of the semiconductor structure obtained after forming the second dielectric layer 19 is shown below. Figure 10 As shown. The material of the second dielectric layer 19 can be the same as that of the first filling dielectric layer 142 or the second filling dielectric layer 144, that is, the second dielectric layer 19 can be a silicon oxide layer.

[0067] S366: A trench 20 is formed in the second dielectric layer 19, the trench 20 exposing the interconnect structure 18 and the conductive layer 15.

[0068] As an example, a schematic diagram of the cross-sectional structure of the semiconductor structure obtained after forming trench 20 is shown in Figure 11. The trench 20 can be formed using photolithography.

[0069] S367: A metal layer 21 is formed within the trench 20.

[0070] Optionally, the metal layer 21 can be copper. First, an electroplating process is used to form the metal layer 21 in the trench 20 and on the upper surface of the second dielectric layer 19. Then, a chemical mechanical polishing process is used to remove the metal layer 21 on the upper surface of the second dielectric layer 19, leaving the metal layer 21 in the trench 20 and performing a planarization treatment on its surface, so that the metal layer 21 in the trench 20 is flush with the upper surface of the second dielectric layer 19.

[0071] In one embodiment, after forming the conductive layer 15 within the through-silicon via 13, the method further includes:

[0072] S40: Thin the back side of the substrate 112 until the bottom of the conductive layer 15 is exposed.

[0073] Exposing the bottom of the conductive layer 15 allows different wafers to be connected through the conductive layer 15 in the through-silicon via 13, achieving vertical interconnect stacked packaging. Specifically, the back-side thinning step of the substrate 112 includes:

[0074] S41: Thin the back side of the substrate 112 at a first polishing rate until the polishing stop layer is exposed;

[0075] S42: Continue back-side thinning of the substrate 112 at a second grinding rate until the bottom of the conductive layer 15 is exposed;

[0076] S43: The second grinding rate is less than the first grinding rate.

[0077] For example, the back side of substrate 112 can be thinned at a first grinding rate. When the grinding equipment reaches the first grinding stop layer 141, a signal indicating increased grinding resistance can be detected, thus identifying the first grinding stop layer 141. The grinding rate is then reduced to a second grinding rate, and grinding continues. When the grinding equipment reaches the second grinding stop layer 143, a signal indicating increased grinding resistance can be detected again, thus identifying the second grinding stop layer 143. Optionally, the grinding equipment can continue grinding at the second grinding rate until the bottom of the conductive layer 15 is exposed. Optionally, the grinding equipment can also reduce the grinding rate again to a third grinding rate and continue grinding at the third grinding rate until the bottom of the conductive layer 15 is exposed. The third grinding rate is less than the second grinding rate, and the second grinding rate is less than the first grinding rate. After thinning the back side of substrate 112 until the bottom of the conductive layer 15 is exposed, the cross-sectional structure of the resulting semiconductor structure is shown in the figure. Figure 13 As shown.

[0078] The above-mentioned semiconductor structure fabrication method, by setting a grinding stop layer in the inner liner layer of the through silicon via 13, can determine the grinding progress by detecting whether grinding has reached the grinding stop layer when thinning the back side of the substrate 112, and adjust the grinding rate in time to prevent over-grinding and avoid damage to the conductive layer 15, thereby affecting the electrical performance of the conductive layer 15.

[0079] In one embodiment, the width of the interconnect via 16 is smaller than the width of the through-silicon via 13. The interconnect via 16 is located in the array region, and its size generally matches the size of the device cell 12. As the feature size of the device cell 12 continuously shrinks, the size of the interconnect via 16 also shrinks accordingly. The through-silicon via 13, located on the periphery of the array region, is not directly related to the size of the device cell 12. Appropriately increasing the width of the through-silicon via 13, making it wider than the interconnect via 16, can reduce the resistance of the conductive layer 15 within the through-silicon via 13.

[0080] Another embodiment of this application also discloses a semiconductor structure, such as Figure 12 As shown, it includes: a substrate 11; a through-silicon via 13 located within the substrate 11, the depth of the through-silicon via 13 being less than the thickness of the substrate 11; an inner liner layer located at least on the sidewalls and bottom of the through-silicon via 13, the inner liner layer including a polishing stop layer; and a conductive layer 15 located within the through-silicon via 13 and filling the through-silicon via 13.

[0081] Specifically, such as Figure 12 As shown, the substrate 11 may include a substrate 112 and a first dielectric layer 111 on the upper surface of the substrate 112. A plurality of device cells 12 arranged in an array are formed within the first dielectric layer 111. The device cells 12 may be memory cells or front-channel isolation structures. The first dielectric layer 111 may be a silicon nitride layer or a silicon oxide layer. Through-silicon vias 13 penetrate the first dielectric layer 111 and partially extend into the substrate 112.

[0082] As an example, such as Figure 12As shown, a portion of the inner liner layer is located on the sidewall and bottom of the through-silicon via 13, and another portion is located on the upper surface of the first dielectric layer 111. The inner liner layer includes a grinding stop layer. The function of the grinding stop layer is to allow for timely adjustment of the grinding speed based on the position of the grinding stop layer when grinding the back side of the substrate 11 (i.e., the side near the bottom of the through-silicon via 13), preventing over-grinding and improving both grinding efficiency and precision. For example, before reaching the grinding stop layer, grinding can be performed at a faster speed without worrying about over-grinding damaging the conductive layer 15. When grinding reaches the grinding stop layer, the grinding equipment receives a signal indicating a change in grinding resistance, allowing the user to know the current grinding progress, i.e., that it is approaching the bottom of the conductive layer 15, and to appropriately reduce the grinding speed for more precise grinding.

[0083] In one embodiment, the inner liner includes a first polishing stop layer 141, a first filling dielectric layer 142, a second polishing stop layer 143, and a second filling dielectric layer 144, which are stacked sequentially from the substrate 11 to the conductive layer 15.

[0084] Please continue to refer to this. Figure 12 The inner liner layer has two grinding stop layers. The grinding equipment can use the first grinding stop layer 141 and the second grinding stop layer 143 to more precisely adjust the grinding speed, further improving grinding efficiency and accuracy. For example, the back side of the substrate 112 can be thinned at a first grinding rate. When the grinding equipment reaches the first grinding stop layer 141, it can detect a signal indicating increased grinding resistance, thus identifying the first grinding stop layer 141 and reducing the grinding rate to a second grinding rate to continue grinding. When the grinding equipment reaches the second grinding stop layer 143, it can again detect a signal indicating increased grinding resistance, thus identifying the second grinding stop layer 143. Optionally, the grinding equipment can continue grinding at the second grinding rate until the bottom of the conductive layer 15 is exposed. Optionally, the grinding equipment can also reduce the grinding rate again to a third grinding rate and continue grinding at the third grinding rate until the bottom of the conductive layer 15 is exposed. The third grinding rate is lower than the second grinding rate, and the second grinding rate is lower than the first grinding rate. The semiconductor structure in this embodiment has multiple grinding stop layers. Users can confidently grind at a relatively fast speed before reaching the next grinding stop layer without worrying about over-grinding. Only after reaching the grinding stop layer can the grinding speed be adjusted for more careful and precise grinding, thus improving grinding efficiency while ensuring grinding accuracy.

[0085] In one embodiment, the first filling dielectric layer 142 and the second filling dielectric layer 144 both include a silicon oxide layer, and the first polishing stop layer 141 and the second polishing stop layer 143 both include a silicon nitride layer or a silicon carbonitride layer.

[0086] As an example, this embodiment uses silicon nitride (Si3N4) as the grinding stop layer. Silicon nitride is a structural ceramic material with high hardness and wear resistance, making it very suitable as a mask stop layer. When the grinding equipment grinds to the silicon nitride layer, the grinding equipment can clearly detect the increase in grinding resistance, thereby reminding the user to reduce the grinding speed and prevent over-grinding.

[0087] In one embodiment, the substrate 11 includes an array region and a peripheral region surrounding the array region, and the through-silicon via 13 is located in the peripheral region. Figure 12 As shown, the substrate 11 includes a substrate 112 and a first dielectric layer 111 located on the upper surface of the substrate 112. A plurality of device units 12 arranged in an array are formed in the first dielectric layer 111 of the array region. The first polishing stop layer 141 extends to the upper surface of the first dielectric layer 111. The semiconductor structure further includes: an interconnect structure 18, the bottom of which is in contact with the device unit 12, and the upper surface of which is flush with the upper surface of the first polishing stop layer 141; a second dielectric layer 19 located on the upper surface of the first polishing stop layer 141, the upper surface of the inner liner layer, and the upper surface of the conductive layer 15; and a metal layer 21 located within the second dielectric layer 19 and in contact with the device unit 12 and the conductive layer 15.

[0088] Specifically, such as Figure 12 As shown, the metal layer 21 includes several metal structures, which respectively contact the interconnect structure 18 and the conductive layer 15. The metal layer 21 includes a copper metal structure. The interconnect structure 18 includes at least one layer selected from tungsten, aluminum, copper, and titanium nitride. The device unit 12 includes a memory unit. The first dielectric layer 111 includes a silicon nitride layer or a silicon oxide layer, and the second dielectric layer 19 includes a silicon oxide layer.

[0089] One embodiment of this application also discloses a semiconductor structure, such as Figure 13 As shown, it includes: a substrate 11; a through-silicon via 13 located within the substrate 11, the depth of the through-silicon via 13 being equal to the thickness of the substrate 11; an inner liner layer located at least on the sidewall of the through-silicon via 13, the inner liner layer including a polishing stop layer; and a conductive layer 15 located within the through-silicon via 13 and filling the through-silicon via 13.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an array region and a peripheral region located around the array region, the substrate including a substrate and a first dielectric layer located on the upper surface of the substrate, wherein a plurality of device units arranged in an array are formed in the first dielectric layer of the array region; A through-silicon via is formed in the peripheral region within the substrate, wherein the depth of the through-silicon via is less than the thickness of the substrate; An inner liner layer is formed on the sidewalls and bottom of the through-silicon via, and a conductive layer is formed inside the through-silicon via; The inner liner includes a first polishing stop layer, a first filling medium layer, a second polishing stop layer and a second filling medium layer stacked sequentially from the substrate to the conductive layer, wherein the first polishing stop layer extends to the upper surface of the first medium layer; Interconnect vias are formed, which expose the device cells; An interconnect material layer is formed within the interconnect via and on the upper surface of the second grinding stop layer; Remove the interconnect material layer located on the upper surface of the second grinding stop layer; While removing the second polishing stop layer and the first filling medium layer on the substrate, the interconnect material layer on the first polishing stop layer is also removed. The interconnect material layer remaining in the interconnect via is the interconnect structure, and the upper surface of the interconnect structure is flush with the upper surface of the first polishing stop layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The method of forming an inner liner layer on the sidewalls and bottom of the through-silicon via (TSV) and forming a conductive layer within the TSV includes: A first polishing stop layer is formed on the upper surface of the substrate and the sidewalls and bottom of the through-silicon via; A first filling medium layer is formed on the surface of the first grinding stop layer; A second grinding stop layer is formed on the surface of the first filling medium layer; A second filling medium layer is formed on the surface of the second grinding stop layer; A conductive layer is formed on the surface of the second filling dielectric layer, the conductive layer covering the upper surface of the second filling dielectric layer and filling the through silicon via; Remove the conductive layer, the second filling dielectric layer, the second polishing stop layer, and the first filling dielectric layer located on the substrate.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Both the first filling dielectric layer and the second filling dielectric layer include a silicon oxide layer, and both the first polishing stop layer and the second polishing stop layer include a silicon nitride layer or a silicon carbonitride layer.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that, After forming the interconnect structure, it also includes: A second dielectric layer is formed on the upper surface of the first polishing stop layer, the upper surface of the interconnect structure, the upper surface of the inner liner layer, and the upper surface of the conductive layer; A trench is formed within the second dielectric layer, the trench exposing the interconnect structure and the conductive layer; A metal layer is formed within the trench.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming the conductive layer within the through-silicon via, the method further includes: The substrate is thinned on the back side until the bottom of the conductive layer is exposed.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The substrate is thinned on the back side using a grinding process, wherein the back side thinning of the substrate includes: The substrate is thinned on the back side at a first polishing rate until the second polishing stop layer is exposed; The substrate is further thinned on the back side at a second polishing rate until the bottom of the conductive layer is exposed; the second polishing rate is less than the first polishing rate.

7. The method for preparing a semiconductor structure according to claim 4, characterized in that, The first dielectric layer includes a silicon nitride layer or a silicon oxide layer, the second dielectric layer includes a silicon oxide layer, and the interconnect structure includes at least one of a tungsten layer, an aluminum layer, a copper layer, and a titanium nitride layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The device unit includes a memory unit.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The width of the interconnect via is smaller than the width of the through silicon via.

10. A semiconductor structure, characterized in that, include: The substrate includes an array region and a peripheral region surrounding the array region. The substrate includes a substrate and a first dielectric layer on the upper surface of the substrate. A plurality of device units arranged in an array are formed in the first dielectric layer of the array region. A through-silicon via (TSV) is located in the peripheral region within the substrate, and the depth of the TSV is less than the thickness of the substrate. The inner liner is located at least on the sidewall and bottom of the through silicon via, and the inner liner includes a first polishing stop layer, a first filling dielectric layer, a second polishing stop layer and a second filling dielectric layer stacked sequentially from the substrate; A conductive layer is located within the through-silicon via and fills the through-silicon via; An interconnect structure, wherein the bottom of the interconnect structure is in contact with the device unit, and the upper surface of the interconnect structure is flush with the upper surface of the first polishing stop layer; The second dielectric layer is located on the upper surface of the first grinding stop layer, the upper surface of the inner liner layer, and the upper surface of the conductive layer. A metal layer is located within the second dielectric layer and is in contact with the device unit and the conductive layer.

11. The semiconductor structure according to claim 10, characterized in that, Both the first filling dielectric layer and the second filling dielectric layer include a silicon oxide layer, and both the first polishing stop layer and the second polishing stop layer include a silicon nitride layer or a silicon carbonitride layer.

12. The semiconductor structure according to claim 10, characterized in that, The first dielectric layer includes a silicon nitride layer or a silicon oxide layer, the second dielectric layer includes a silicon oxide layer, the interconnect structure includes at least one of a tungsten layer, an aluminum layer, a copper layer, and a titanium nitride layer; the device unit includes a memory unit.

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