A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The embodiment of the present disclosure provides a preparation method of a semiconductor structure and the semiconductor structure, wherein the method comprises the following steps: providing a substrate, wherein a support structure is formed on the substrate; forming a plurality of capacitor holes in the support structure; forming a lower electrode in the capacitor hole, wherein the lower electrode covers the sidewall and the bottom of the capacitor hole; forming a first dielectric layer, wherein the first dielectric layer covers the surface of the lower electrode; forming a first upper electrode, wherein the first upper electrode covers the surface of the first dielectric layer; removing part of the support structure between the capacitor holes to form a containing cavity, wherein the containing cavity at least exposes part of the lower electrode, and the remaining support structure is located on part of the sidewall of the lower electrode; forming a second dielectric layer, wherein the second dielectric layer covers the sidewall and the bottom of the containing cavity; and forming a second upper electrode, wherein the second upper electrode covers the upper surface of the second dielectric layer and the first upper electrode.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] With the development and advancement of technology, the size of semiconductor devices is becoming smaller and smaller, and semiconductor devices are constantly developing towards miniaturization and high integration. Dynamic random access memory (DRAM), as a semiconductor device that allows for high-speed and random writing and reading of data, is widely used in data storage devices or apparatuses.

[0003] DRAM structures typically use capacitors to store information. Although the manufacturing process is relatively mature, there are still many problems with capacitor structures in actual operation that need to be improved. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure, including:

[0005] A substrate is provided on which a support structure is formed;

[0006] Multiple capacitor holes are formed within the support structure;

[0007] A lower electrode is formed within the capacitor hole, and the lower electrode covers the sidewall and bottom of the capacitor hole;

[0008] A first dielectric layer is formed, which covers the surface of the lower electrode;

[0009] A first upper electrode is formed, which covers the surface of the first dielectric layer;

[0010] The portion of the support structure located between the capacitor holes is removed to form a receiving cavity, which at least exposes a portion of the lower electrode, while the remaining support structure is located on a portion of the sidewall of the lower electrode;

[0011] A second dielectric layer is formed, which covers the sidewalls and bottom of the receiving cavity;

[0012] A second upper electrode is formed, which covers the upper surface of the second dielectric layer and the first upper electrode.

[0013] In some embodiments, the first dielectric layer and the second dielectric layer are made of different materials and / or have different sizes.

[0014] In some embodiments, the dielectric constant of the material of the first dielectric layer is less than or equal to 3.9, and the dielectric constant of the second dielectric layer is greater than 3.9.

[0015] In some embodiments, in a direction parallel to the substrate, the width of the second dielectric layer is greater than or equal to the width of the first dielectric layer, and / or,

[0016] In a direction perpendicular to the substrate, the height of the second dielectric layer is greater than or equal to the height of the first dielectric layer.

[0017] In some embodiments, the opening size of the capacitor hole is less than or equal to 25 nm in a direction parallel to the substrate.

[0018] In some embodiments, a lower electrode is formed within the capacitor hole, including:

[0019] Deposited electrode material, the electrode material covering the sidewalls and bottom of the capacitor hole, and covering the upper surface of the support structure;

[0020] An etching process is performed to remove the electrode material located on the upper surface of the support structure, while the electrode material remaining on the sidewalls and bottom of the capacitor hole forms the lower electrode.

[0021] In some embodiments, a portion of the support structure located between the capacitor holes is removed to form a receiving cavity, including:

[0022] A mask layer is formed on the first upper electrode, the mask layer including an etching window, the orthographic projection of the etching window on the substrate overlapping the orthographic projection of a portion of the support structure on the substrate;

[0023] The first upper electrode, the first dielectric layer, and the support structure exposed by the etching window are etched to form the receiving cavity, which at least exposes a portion of the lower electrode, and the unetched support structure covers a portion of the sidewall of the lower electrode.

[0024] In some embodiments, forming a second dielectric layer includes:

[0025] A deposition medium material is used to cover the sidewalls and bottom of the receiving cavity and the upper surface of the first upper electrode;

[0026] An etching process is performed to remove the portion of the dielectric material covering the upper surface of the first upper electrode, and the remaining dielectric material layer constitutes the second dielectric layer.

[0027] This disclosure also provides a semiconductor structure, including:

[0028] A substrate and a support structure located on the substrate, wherein the support structure has a plurality of capacitor holes;

[0029] The lower electrodes are discretely disposed within a plurality of said capacitor holes, and the support structure is located on a portion of the sidewall of the lower electrodes;

[0030] A first dielectric layer covers the surface of the lower electrode;

[0031] A first upper electrode, the first upper electrode covering the first dielectric layer;

[0032] A second dielectric layer, the second dielectric layer at least covering a portion of the sidewall of the lower electrode;

[0033] The second upper electrode covers the upper surface of the second dielectric layer and the first upper electrode.

[0034] In some embodiments, the first dielectric layer and the second dielectric layer are made of different materials and / or have different dimensions.

[0035] In some embodiments, the dielectric constant of the first dielectric layer is less than or equal to 3.9, and the dielectric constant of the second dielectric layer is greater than 3.9.

[0036] In some embodiments, in a direction parallel to the substrate, the width of the second dielectric layer is greater than or equal to the width of the first dielectric layer, and / or,

[0037] In a direction perpendicular to the substrate, the height of the second dielectric layer is greater than or equal to the height of the first dielectric layer.

[0038] In some embodiments, the opening size of the capacitor hole is less than or equal to 25 nm in a direction parallel to the substrate.

[0039] In some embodiments, the first dielectric layer covers the side surface, bottom surface, and top surface of the lower electrode, and also covers the upper surface of the support structure.

[0040] In some embodiments, the semiconductor structure further includes a node contact plug located between the lower electrode and the substrate.

[0041] The semiconductor structure fabrication method and semiconductor structure provided in this disclosure include: providing a substrate on which a support structure is formed; forming a plurality of capacitor holes within the support structure; forming a lower electrode within the capacitor holes, the lower electrode covering the sidewalls and bottom of the capacitor holes; forming a first dielectric layer covering the surface of the lower electrode; forming a first upper electrode covering the surface of the first dielectric layer; removing a portion of the support structure located between the capacitor holes to form a receiving cavity, the receiving cavity at least exposing a portion of the lower electrode, the remaining support structure located on a portion of the sidewalls of the lower electrode; forming a second dielectric layer covering the sidewalls and bottom of the receiving cavity; and forming a second upper electrode covering the upper surfaces of the second dielectric layer and the first upper electrode. Thus, not only is a sub-capacitor structure for storing charge formed within the space defined by the capacitor hole, but another sub-capacitor structure for storing charge is also formed within the space formed after removing part of the support structure. The two sub-capacitors are independent of each other, yet cooperate to form the capacitor structure, improving the space utilization of the capacitor structure and significantly increasing the surface area of ​​the capacitor structure, thereby increasing the charge storage capacity of the capacitor structure, i.e., increasing the capacitance of the capacitor structure. In addition, in the embodiments of this disclosure, the first dielectric layer and the second dielectric layer located inside and outside the lower electrode are formed in two steps respectively. The materials and dimensions of both can be adjusted according to the actual situation, effectively avoiding the constraints of spatial size changes on the final semiconductor structure, i.e., the capacitor structure. Even under extreme size conditions, the semiconductor structure can achieve a high capacitance while obtaining a high integration density.

[0042] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0045] Figures 2 to 13 A process flow diagram of the method for fabricating a semiconductor structure provided in this disclosure embodiment;

[0046] Figure 14The semiconductor structure provided in the embodiments of this disclosure is along Figure 13 A top view of the cross section along the A1-A2 direction. Detailed Implementation

[0047] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0048] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0049] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0050] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0051] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0053] In practical manufacturing processes, to improve integration density, the size of capacitor vias is typically reduced, resulting in a significant decrease in via diameter. When the dielectric layers formed inside and outside the via are of the same material and thickness, there is insufficient space inside the via to accommodate the dielectric layer and top electrode. To address this, operators fill the space defined by the via with electrode material, then expose the outer walls of the electrode material through etching. The dielectric layer and electrode material are then sequentially formed on these sidewalls to create the capacitor structure. While this method adapts to the trend of shrinking vias, it sacrifices the capacitor structure that should have been formed inside the via, leading to a decrease in capacitance.

[0054] Therefore, how to obtain a semiconductor structure with a large capacitance while reducing the size of the capacitor aperture has become a difficult problem.

[0055] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0056] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the method includes the following steps:

[0057] Step S101: Provide a substrate on which a support structure is formed;

[0058] Step S102: Form multiple capacitor holes within the support structure;

[0059] Step S103: Form a lower electrode inside the capacitor hole, the lower electrode covering the sidewall and bottom of the capacitor hole;

[0060] Step S104: Form a first dielectric layer, the first dielectric layer covering the surface of the lower electrode;

[0061] Step S105: Form a first upper electrode, the first upper electrode covering the surface of the first dielectric layer;

[0062] Step S106: Remove part of the support structure located between the capacitor holes to form a receiving cavity, the receiving cavity exposing at least part of the lower electrode, and the remaining support structure is located on part of the sidewall of the lower electrode;

[0063] Step S107: Form a second dielectric layer, which covers the sidewalls and bottom of the receiving cavity;

[0064] Step S108: Form a second upper electrode, which covers the upper surface of the second dielectric layer and the first upper electrode.

[0065] In this embodiment, not only is a sub-capacitor for storing charge formed within the space defined by the capacitor hole, but another sub-capacitor for storing charge is also formed within the space formed after removing part of the support structure. These two sub-capacitors are independent yet cooperate to form the capacitor structure, improving the space utilization of the capacitor structure and significantly increasing its surface area, thereby increasing the capacitor structure's charge storage capacity, i.e., increasing its capacitance. Furthermore, in this embodiment, the first and second dielectric layers located inside and outside the lower electrode are formed in two separate steps. The materials and dimensions of both layers can be adjusted according to actual conditions, effectively avoiding the constraints of spatial dimension changes on the final semiconductor structure, i.e., the capacitor structure. Even under extreme size conditions, the semiconductor structure can achieve high capacitance while maintaining high integration density.

[0066] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0067] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figures 2 to 13A process flow diagram of the method for fabricating a semiconductor structure provided in this disclosure embodiment; Figure 14 The semiconductor structure provided in the embodiments of this disclosure is along Figure 13 A top view of the cross section along the A1-A2 direction.

[0068] The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0069] First, execute step S101, as follows: Figure 2 As shown, a substrate 10 is provided, on which a support structure 11 is formed.

[0070] Here, the substrate material can be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, but is not limited to these. The substrate can also be a silicon substrate on an insulator surface or a germanium substrate on an insulator surface. In some embodiments, the substrate can be a silicon substrate.

[0071] In the actual process, before forming the support structure 11 on the substrate 10, the method further includes:

[0072] An insulating layer 12 is formed on the substrate;

[0073] The insulating layer 12 is etched to form a plurality of discrete openings (not shown in the figure) in the insulating layer 12;

[0074] Multiple discrete node contact plugs 14 are formed in the opening (not shown in the figure).

[0075] Optionally, the material used to form the node contact plug may be one or a combination of polycrystalline silicon, metal silicides, conductive metals, and conductive metal nitrides. Specifically, metal silicides may include, but are not limited to, cobalt silicide (CoSix); conductive metals may include, but are not limited to, tungsten (W); and conductive metal nitrides may include, but are not limited to, titanium nitride (TiN).

[0076] Continue to refer to Figure 2 In some embodiments, after forming the node contact plug 14, forming the support junction 11 includes:

[0077] Substrate 10 is provided;

[0078] A sacrificial layer 15 is formed on the substrate 10, and the sacrificial layer 15 covers the surface of the insulating layer 12 and the node contact plug 14.

[0079] A first support layer 111 is formed on the sacrificial layer 15, and the first support layer 111 covers the surface of the sacrificial layer;

[0080] A sacrificial layer 15 is formed on the first support layer 111, and the sacrificial layer 15 covers the surface of the first support layer 111.

[0081] A second support layer 112 is formed on the sacrificial layer 15, and the second support layer 112 covers the surface of the sacrificial layer 15;

[0082] The first support layer 111 and the second support layer 112 constitute the support structure 11.

[0083] In actual processes, the materials forming the sacrificial layer may include, but are not limited to, SiO2 treated with organic solutions (PGS, BPSG, TEOS or HDP); the materials forming the first support layer and the second support layer may include, but are not limited to, Si3N4 or SiCN.

[0084] Next, proceed to step S102, as follows: Figure 3 As shown, multiple capacitor holes H1 are formed within the support structure 11.

[0085] Here, the capacitor hole H1 exposes the node contact plug 14. When other conductive structures, such as the lower electrode, are subsequently formed in the capacitor hole H1, the node contact plug 14 can be used to electrically connect the conductive structures in the capacitor hole with other structures, such as transistor structures.

[0086] In some specific embodiments, the opening size of the capacitor hole H1 in the direction parallel to the substrate can be less than or equal to 25nm, such as 20nm or 15nm, thereby adapting to the requirements of the process size of memory devices, such as DRAM devices, which are gradually approaching the limit, and improving the device integration.

[0087] In actual processes, etching processes can be used to form capacitor holes, specifically, at least one or a combination of dry etching or wet etching processes.

[0088] Next, proceed to step S103, as follows: Figure 5 As shown, a lower electrode is formed inside the capacitor hole, and the lower electrode covers the sidewall and bottom of the capacitor hole.

[0089] In some specific embodiments, such as Figure 4 and Figure 5 As shown, a lower electrode 13 is formed within the capacitor hole H1, comprising:

[0090] Electrode material 13a is deposited, which covers the sidewalls and bottom of capacitor hole H1 and the upper surface of support structure 11.

[0091] An etching process is performed to remove the electrode material 13a located on the upper surface of the support structure 11, while the electrode material 13a remaining on the sidewall and bottom of the capacitor hole H1 forms the lower electrode 13.

[0092] In some embodiments, the material of the lower electrode may include one or more conductive materials, such as doped semiconductors, conductive metal nitrides, metals, metal silicides, conductive oxides, or combinations thereof, for example, one or a combination of polycrystalline silicon, titanium nitride, tantalum nitride, tungsten, etc.

[0093] Here, the material of the lower electrode can include, but is not limited to, titanium nitride.

[0094] Next, proceed to step S104, as follows: Figure 6 As shown, a first dielectric layer L1 is formed, which covers the surface of the lower electrode 13.

[0095] Continue to refer to Figure 6 As can be seen, the first dielectric layer L1 covers the side surface, bottom surface and top surface of the lower electrode 13, and also covers the upper surface of the support structure between adjacent capacitor holes H1.

[0096] Here, the material of the first dielectric layer includes a low dielectric constant material, such as at least one or a combination of silicon carbide, silicon carbonitride (SiCN), silicon carbon oxychloride (SiCO), silicon oxide, etc.

[0097] Then, proceed to step S105, as follows: Figure 7 As shown, a first upper electrode 161 is formed, which covers the surface of the first dielectric layer L1.

[0098] Optionally, the material of the first upper electrode can be the same as or different from that of the lower electrode; no specific restrictions are imposed here.

[0099] Next, proceed to step S106, as follows: Figure 10 As shown, a portion of the support structure 11 located between capacitor holes H1 is removed to form a receiving cavity H2, which exposes at least a portion of the lower electrode 13. The remaining support structure 11 is located on a portion of the sidewall of the lower electrode 13.

[0100] In this embodiment of the present disclosure, the size of the cavity H2 can be greater than or equal to the size of the capacitor hole H1 under the manufacturing process, for example, it can be 30nm, 50nm, etc.

[0101] In some specific embodiments, it is worth noting that while continuously reducing the size of the capacitor aperture H1 to accommodate the gradual approaching limit of semiconductor memory device process dimensions, the size of the receiving cavity H2 can still be guaranteed to remain unaffected. In this embodiment, a complete capacitor is first formed within the capacitor aperture H1, and then the receiving cavity H2 is formed. Another capacitor is then formed using a separate process. This allows for the applicability of the sizes of the capacitor aperture H1 and the receiving cavity H2, and the control and adjustment of the performance (e.g., capacitance value, electrical performance) of the two capacitors. For example, different dielectric layer materials and different dielectric layer sizes can be selected to achieve a balance between capacitance and electrical performance in the final capacitor structure.

[0102] In some embodiments, such as Figures 8 to 10 As shown, the portion of the support structure 11 located between the capacitor holes H1 is removed to form a receiving cavity H2, including:

[0103] A mask layer M is formed on the first upper electrode 161. The mask layer M includes an etching window H3. The orthographic projection of the etching window H3 on the substrate 10 overlaps with the orthographic projection of a portion of the support structure 11 on the substrate 10.

[0104] The first upper electrode 161, the first dielectric layer L1, and the support structure 11 exposed by the etching window H3 are etched to form a receiving cavity H2, which exposes at least a portion of the lower electrode 13. The unetched support structure 11 covers a portion of the sidewall of the lower electrode 13.

[0105] Here, after etching part of the support structure, part of the outer wall of the lower electrode is exposed, and the remaining support structure is also located on the outer wall of the lower electrode.

[0106] In actual processes, such as Figure 9 and Figure 10 As shown, after etching the first upper electrode 161, the first dielectric layer L1, and the support structure 11 exposed by the etching window H3, the initial receiving cavity H2' can be obtained; then, the receiving cavity H2 can be obtained by removing the sacrificial layer 15 located around the initial receiving cavity H2'.

[0107] In actual processes, etching processes can be used to form the cavity, specifically, at least one or a combination of dry etching or wet etching processes.

[0108] Next, continue with step S107, as follows: Figure 12 As shown, a second dielectric layer L2 is formed, which covers the sidewalls and bottom of the receiving cavity H2.

[0109] In some embodiments, such as Figure 11 and Figure 12 As shown, a second dielectric layer L2 is formed, comprising:

[0110] Deposited dielectric material L2a covers the sidewalls and bottom of the receiving cavity H2 and the upper surface of the first upper electrode 161;

[0111] An etching process is performed to remove the portion of dielectric material L2a covering the upper surface of the first upper electrode 161, and the remaining dielectric material L2a constitutes the second dielectric layer L2.

[0112] In some embodiments, in a direction perpendicular to the substrate, the height of the second dielectric layer is greater than or equal to the height of the first dielectric layer; for example, the upper surface of the second dielectric layer L2 is higher than the upper surface of the first dielectric layer L1.

[0113] Understandably, unlike conventional processes where the first and second dielectric layers are an integral structure formed in the same process step, when the first and second dielectric layers are formed in different process steps, it is easy for the first and second dielectric layers to be not tightly bonded at the joint position during actual operation, resulting in a short circuit caused by direct electrical connection between the lower electrode and the subsequently formed upper electrode.

[0114] Therefore, in this embodiment of the present disclosure, after forming the second dielectric layer covering the sidewalls and bottom of the receiving cavity and the upper surface of the first upper electrode, the second dielectric layer with a higher height than the first dielectric layer is obtained by removing only the second dielectric layer located on the upper surface of the first upper electrode without continuing to etch the second dielectric layer located near the top surface of the receiving cavity. This etching method can maintain the original and good bonding state of the first dielectric layer and the second dielectric layer. Compared with the method of continuing to etch the second dielectric layer to make the first dielectric layer and the second dielectric layer have the same height, this embodiment of the present disclosure has the advantages of reducing etching time, simplifying the process, and preventing semiconductor structure failure.

[0115] Here, the second dielectric layer comprises a high dielectric constant material. Specifically, the material of the second dielectric layer may include, but is not limited to, at least one or a combination of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), hafnium silicon nitride oxide (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and / or praseodymium oxide (Pr2O3).

[0116] Understandably, since the first dielectric layer L1 and the second dielectric layer L2 are formed in two different process steps, the materials and sizes of the first dielectric layer L1 and the second dielectric layer L2 may be different depending on the specific circumstances in actual operation.

[0117] For example, in some specific embodiments, as the process dimensions approach their limits, the capacitor aperture H1 often has a smaller size than the receiving cavity H2. The dielectric constant of the first dielectric layer is, for example, less than or equal to 3.9, and silicon dioxide can be used, while the dielectric constant of the second dielectric layer is greater than 3.9, and hafnium oxide can be used, for example. It is understandable that because size reduction easily leads to a significant reduction in the size of the capacitor aperture, forming a high dielectric constant material inside it can easily cause an increase in leakage current, affecting the performance of the semiconductor structure. Therefore, it is preferable to use a low dielectric constant material for the first dielectric layer to ensure electrical performance. In this case, since the second dielectric layer is located within the space formed after the support structure is etched, it is formed in a space with a larger surface area compared to the first dielectric layer. When a high dielectric constant material is used for the second dielectric layer, leakage current is less likely to occur. Therefore, a high dielectric constant material can be used for the second dielectric layer to improve capacitance.

[0118] In some embodiments, the width of the second dielectric layer is greater than or equal to the width of the first dielectric layer in a direction parallel to the substrate.

[0119] Thus, by setting the first dielectric layer and the second dielectric layer to have different widths, such as the width of the first dielectric layer being smaller than the width of the second dielectric layer, the requirement to obtain a structure for storing charge in both spaces can be met in the case of miniaturization or extreme size, thereby improving the capacitance of the final semiconductor structure.

[0120] However, this is not the only possibility. It is understood that in some other embodiments, the width of the first dielectric layer may be equal to or greater than the width of the second dielectric layer, and the specific width may be flexibly adjusted according to the actual situation.

[0121] Finally, proceed with step S108, as follows: Figure 13 and Figure 14 As shown, a second upper electrode 162 is formed, which covers the upper surface of the second dielectric layer L2 and the first upper electrode 161.

[0122] Here, the second upper electrode 162 and the first upper electrode 161 together constitute the upper electrode 16. The materials of the second upper electrode 162 and the first upper electrode 161 can be the same or different. In some specific embodiments, the materials of the second upper electrode 162 and the first upper electrode 161 include, but are not limited to, titanium nitride.

[0123] Thus, structures for storing charge are formed both within the space defined by the capacitor hole and within the space formed after etching the support structure.

[0124] Here, the lower electrode 13, the first dielectric layer L1, and the first upper electrode 161 form a sub-capacitor, and the lower electrode 13, the second dielectric layer L2, and the second upper electrode 162 form another sub-capacitor. The two sub-capacitors share the lower electrode and together form the capacitor structure C.

[0125] In summary, it can be seen that in the embodiments of this disclosure, since the first dielectric layer and the second dielectric layer are formed in two different steps, the size and material of the first dielectric layer located within the space defined by the capacitor hole can be flexibly selected and adjusted according to the actual situation, thereby ultimately forming a structure for storing charge within the space defined by the capacitor hole. The material and thickness of the second dielectric layer located in the space formed after removing part of the support structure are not limited by the size of the capacitor hole and the size of the space, and can be formed normally and even adjusted according to the actual situation. Compared with conventional technology, the embodiments of this disclosure can significantly improve the flexibility of the semiconductor structure formation process and effectively improve the capacitance of the semiconductor structure even under extreme size limitations.

[0126] This disclosure also provides a semiconductor structure, such as... Figure 13 and Figure 14 As shown, it includes:

[0127] Substrate 10 and support structure 11 located on substrate 10, wherein the support structure has a plurality of capacitor holes H1;

[0128] The lower electrode 13 is discretely disposed within a plurality of said capacitor holes H1, and the support structure 11 is located on a portion of the sidewall of the lower electrode 13.

[0129] A first dielectric layer L1 covers the surface of the lower electrode 13;

[0130] First upper electrode 161, the first upper electrode 161 covers the first dielectric layer L1;

[0131] The second dielectric layer L2 covers at least a portion of the sidewall of the lower electrode 13;

[0132] The second upper electrode 162 covers the upper surface of the second dielectric layer L2 and the first upper electrode 161.

[0133] In some specific embodiments, the opening size of the capacitor hole H1 in the direction parallel to the substrate can be less than or equal to 25nm, such as 20nm or 15nm, thereby adapting to the requirements of the process size of memory devices, such as DRAM devices, which are gradually approaching the limit, and improving the device integration.

[0134] Here, the lower electrode 13, the first dielectric layer L1, and the first upper electrode 161 form a sub-capacitor, and the lower electrode 13, the second dielectric layer L2, and the second upper electrode 162 form another sub-capacitor. The two sub-capacitors share the lower electrode and together form the capacitor structure C.

[0135] In other words, the embodiments of this disclosure provide capacitor structures both within the space defined by the capacitor hole and within the space formed after etching the support structure, which can effectively improve the capacitance of the semiconductor structure.

[0136] In actual processes, the substrate material can be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, but is not limited to these. The substrate can also be a silicon substrate on an insulator surface or a germanium substrate on an insulator surface. In some embodiments, the substrate can be a silicon substrate.

[0137] Optionally, the material of the lower electrode 13 may include one or more conductive materials, such as doped semiconductors, conductive metal nitrides, metals, metal silicides, conductive oxides, or combinations thereof, for example, one or a combination of polycrystalline silicon, titanium nitride, tantalum nitride, tungsten, etc. In some specific embodiments, the material of the lower electrode 13 includes, but is not limited to, titanium nitride.

[0138] It is understood that the materials of the second upper electrode 162 and the first upper electrode 161 can be the same or different. In some specific embodiments, the materials of the second upper electrode 162 and the first upper electrode 161 include, but are not limited to, titanium nitride.

[0139] Continue to refer to Figure 13 As can be seen, the first dielectric layer L1 covers the side surface, bottom surface and top surface of the lower electrode 13, and covers the upper surface of the support structure 11.

[0140] In some embodiments, in a direction perpendicular to the substrate, the height of the second dielectric layer is greater than or equal to the height of the first dielectric layer, for example, the upper surface of the second dielectric layer L2 is higher than the upper surface of the first dielectric layer L1.

[0141] Understandably, unlike conventional structures where the first and second dielectric layers are integral and formed in the same step, in this embodiment, the two dielectric layers are two independently configured parts. One part is the first dielectric layer located on the side surface, bottom surface, and top surface of the lower electrode, and the other part is the second dielectric layer located on the outer wall of the lower electrode. The two have a joint at the side wall of the first dielectric layer located on the upper surface of the lower electrode. When the second dielectric layer has a higher height than the first dielectric layer, it is easier for them to form a good and tight joint, which can effectively prevent short circuits caused by direct electrical connection between the lower and upper electrodes due to insufficient joint between the first and second dielectric layers.

[0142] In addition, in actual processes, by setting the upper surface of the second dielectric layer to be higher than the upper surface of the first dielectric layer, the etching time when forming the second dielectric layer can be effectively reduced and the process can be simplified.

[0143] Since the first dielectric layer L1 and the second dielectric layer L2 are independent of each other in the embodiments of this disclosure, it is understood that in some embodiments, the first dielectric layer L1 and the second dielectric layer L2 are made of different materials and / or have different dimensions.

[0144] In actual manufacturing processes, the dielectric constant of the first dielectric layer L1 is less than or equal to 3.9, and the dielectric constant of the second dielectric layer is greater than 3.9.

[0145] Optionally, in some embodiments, the material of the first dielectric layer includes, but is not limited to, at least one or a combination of silicon carbide, silicon carbonitride (SiCN), silicon carbon oxyoxide (SiCO), silicon oxide, etc.; the material of the second dielectric layer may include, but is not limited to, at least one or a combination of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), hafnium silicon nitride (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and / or praseodymium oxide (Pr2O3), etc.

[0146] Here, it's understandable that due to the miniaturization of dimensions, the size of the capacitor aperture is significantly reduced. If the first dielectric layer inside is made of a high-dielectric-constant material, it can easily lead to an increase in leakage current, affecting the performance of the semiconductor structure. Therefore, it's best to use a low-dielectric-constant material for the first dielectric layer. Since the second dielectric layer is located within the space formed after the support structure is etched, it has a larger surface area than the first dielectric layer. When a high-dielectric-constant material is used for the second dielectric layer, leakage current is less likely to occur. Therefore, a high-dielectric-constant material can be used for the second dielectric layer to increase its capacitance.

[0147] Optionally, in some embodiments, the width of the second dielectric layer is greater than or equal to the width of the first dielectric layer in a direction parallel to the substrate.

[0148] Thus, by setting the first dielectric layer and the second dielectric layer to have different widths, for example, the width of the first dielectric layer L1 is smaller than the width of the second dielectric layer L2, the requirement of obtaining a capacitor structure in both spaces can be met in the case of miniaturization or extreme size, so as to improve the capacitance of the final semiconductor structure.

[0149] However, this is not the only possibility. It is understood that in some other embodiments, the width of the first dielectric layer may be equal to or greater than the width of the second dielectric layer, and the specific width may be flexibly adjusted according to the actual situation.

[0150] Continue to refer to Figure 13 As can be seen, in some embodiments, the semiconductor structure also includes a node contact plug 14, which is located between the lower electrode 13 and the substrate 10.

[0151] In addition, in this embodiment of the present disclosure, an insulating layer 12 is provided between adjacent contact plugs 14, and the insulating layer 12 serves to isolate the adjacent contact plugs 14.

[0152] Optionally, the material used to form the node contact plug may be one or a combination of polycrystalline silicon, metal silicides, conductive metals, and conductive metal nitrides. Specifically, metal silicides may include, but are not limited to, cobalt silicide (CoSix); conductive metals may include, but are not limited to, tungsten (W); and conductive metal nitrides may include, but are not limited to, titanium nitride (TiN).

[0153] In summary, in the embodiments of this disclosure, since the first dielectric layer and the second dielectric layer are formed in two different steps, the size and material of the first dielectric layer located within the space defined by the capacitor hole can be flexibly selected and adjusted according to actual conditions. This allows for the formation of a charge storage structure within the space defined by the capacitor hole. Furthermore, the material and thickness of the second dielectric layer located in the space formed after removing part of the support structure are not limited by the size of the capacitor hole or the space itself, and can be formed normally and even adjusted according to actual conditions. Compared with conventional techniques, the embodiments of this disclosure significantly improve the flexibility of the semiconductor structure formation process and effectively increase the capacitance of the semiconductor structure even at extreme size limits.

[0154] It should be noted that the semiconductor device fabrication method provided in this disclosure can be applied to DRAM structures or other semiconductor devices, and is not limited thereto. The embodiments of the semiconductor device fabrication method provided in this disclosure and the embodiments of the semiconductor devices belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0155] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which a support structure is formed; Multiple capacitor holes are formed within the support structure, and the opening size of the capacitor holes is less than or equal to 25 nm in the direction parallel to the substrate. A lower electrode is formed within the capacitor hole, and the lower electrode covers the sidewall and bottom of the capacitor hole; A first dielectric layer is formed, which covers the surface of the lower electrode, and the dielectric constant of the material of the first dielectric layer is less than or equal to 3.

9. A first upper electrode is formed, which covers the surface of the first dielectric layer; The portion of the support structure located between the capacitor holes is removed to form a receiving cavity, which at least exposes a portion of the lower electrode, while the remaining support structure is located on a portion of the sidewall of the lower electrode; A second dielectric layer is formed, which covers the sidewalls and bottom of the receiving cavity, and the dielectric constant of the second dielectric layer is greater than 3.9; A second upper electrode is formed, which covers the upper surface of the second dielectric layer and the first upper electrode.

2. The method according to claim 1, characterized in that, The first dielectric layer and the second dielectric layer are made of different materials and / or have different dimensions.

3. The method according to claim 1 or 2, characterized in that, In a direction parallel to the substrate, the width of the second dielectric layer is greater than or equal to the width of the first dielectric layer, and / or In a direction perpendicular to the substrate, the height of the second dielectric layer is greater than or equal to the height of the first dielectric layer.

4. The method according to claim 1, characterized in that, A lower electrode is formed within the capacitor hole, comprising: Deposited electrode material, the electrode material covering the sidewalls and bottom of the capacitor hole, and covering the upper surface of the support structure; An etching process is performed to remove the electrode material located on the upper surface of the support structure, while the electrode material remaining on the sidewalls and bottom of the capacitor hole forms the lower electrode.

5. The method according to claim 4, characterized in that, Removing a portion of the support structure located between the capacitor holes to form a receiving cavity, comprising: A mask layer is formed on the first upper electrode, the mask layer including an etching window, the orthographic projection of the etching window on the substrate overlapping the orthographic projection of a portion of the support structure on the substrate; The first upper electrode, the first dielectric layer, and the support structure exposed by the etching window are etched to form the receiving cavity, which at least exposes a portion of the lower electrode, and the unetched support structure covers a portion of the sidewall of the lower electrode.

6. The method according to claim 5, characterized in that, Forming a second dielectric layer includes: A deposition medium material is used to cover the sidewalls and bottom of the receiving cavity and the upper surface of the first upper electrode; An etching process is performed to remove the portion of the dielectric material covering the upper surface of the first upper electrode, and the remaining dielectric material constitutes the second dielectric layer.

7. A semiconductor structure, characterized in that, include: A substrate and a support structure located on the substrate, wherein the support structure has a plurality of capacitor holes, and the opening size of the capacitor holes is less than or equal to 25 nm in a direction parallel to the substrate; The lower electrodes are discretely disposed within a plurality of said capacitor holes, and the support structure is located on a portion of the sidewall of the lower electrodes; A first dielectric layer covers the surface of the lower electrode, and the dielectric constant of the first dielectric layer is less than or equal to 3.

9. A first upper electrode, the first upper electrode covering the first dielectric layer; A second dielectric layer, which at least covers a portion of the sidewall of the lower electrode, has a dielectric constant greater than 3.

9. The second upper electrode covers the upper surface of the second dielectric layer and the first upper electrode.

8. The structure according to claim 7, characterized in that, The first dielectric layer and the second dielectric layer are made of different materials and / or have different dimensions.

9. The structure according to claim 7 or 8, characterized in that, In a direction parallel to the substrate, the width of the second dielectric layer is greater than or equal to the width of the first dielectric layer, and / or In a direction perpendicular to the substrate, the height of the second dielectric layer is greater than or equal to the height of the first dielectric layer.

10. The structure according to claim 7, characterized in that, The first dielectric layer covers the side surface, bottom surface and top surface of the lower electrode, and also covers the upper surface of the support structure.

11. The structure according to claim 10, characterized in that, The semiconductor structure also includes a node contact plug located between the lower electrode and the substrate.

Images