Electronic circuit comprising an RF switch with reduced parasitic capacitance

Abstract

Embodiments of the present disclosure relate to electronic circuits comprising RF switches with reduced parasitic capacitance. The present disclosure relates to an electronic circuit comprising a semiconductor substrate, a radio frequency switch corresponding to a MOS transistor, the MOS transistor comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, a conductive pillar topped by a metal track, at least two connection elements, each connection element connecting one of the doped semiconductor regions, and each connection element being formed by the conductive pillar and the conductive track of each metallization level. The electronic circuit further comprises a trench between two connection elements, the trench passing completely through the stack of insulating layers of one metallization level, and further partially through the stack of insulating layers of the metallization level closest to the substrate, and a heat spreading device for heat spreading of the trench.

Description

Technical Field

[0001] This disclosure relates generally to electronic circuits, and more specifically to electronic circuits including RF switches. Background Technology

[0002] A radio frequency (RF) switch is a device that transmits high-frequency signals through a transmission path. RF switches can be made of metal-oxide-semiconductor field-effect transistors, hereinafter referred to as MOS transistors.

[0003] Electronic circuitry, including RF switches, is used as an example in front-end devices that integrate all the circuitry between at least one hybrid stage of the power amplifier for the antenna and receiver and / or transmitter. These electronic circuits are used in a wide variety of radio frequency products and applications. Examples include wireless systems and FM radio systems.

[0004] Ideally, both the parasitic capacitance and on-resistance of the RF switch should be as low as possible. Summary of the Invention

[0005] One embodiment overcomes all or part of the disadvantages of known electronic circuits, including RF switches.

[0006] One embodiment provides an electronic circuit including a semiconductor substrate, a radio frequency switch corresponding to a MOS transistor, the MOS transistor including a doped semiconductor region in the substrate, at least two metallization levels covering the substrate, each metallization level including a stack of insulating layers, a conductive post with a metal track on top, at least two connection elements each connecting to one of the doped semiconductor regions, each connection element being formed by the conductive post and conductive track of each metallization level, the electronic circuit further including a trench between the two connection elements and a heat dissipation device adapted to dissipate heat outside the trench, the trench completely passing through the stack of insulating layers of one metallization level and further partially passing through the stack of insulating layers of the metallization level closest to the substrate.

[0007] According to one embodiment, the heat dissipation device is also a moisture protection device, suitable for preventing moisture from reaching the insulation layer exposed in the trench.

[0008] According to one embodiment, the trench has a height greater than or equal to 1 μm (micrometer). According to one embodiment, the trench has a height greater than 1 μm.

[0009] According to one embodiment, the trench has an average width greater than or equal to 100 nm (nanometers). According to another embodiment, the trench has an average width greater than 100 nm.

[0010] According to one embodiment, the heat dissipation device includes a coating covering the sides of the trench.

[0011] According to one embodiment, the coating is moisture-proof.

[0012] According to one embodiment, the thickness of the coating varies between 10 nm and 500 nm.

[0013] According to one embodiment, the coating is made of one or more materials with good thermal conductivity.

[0014] According to one embodiment, the coating is made of aluminum nitride, molybdenum disulfide, graphene, and / or silicon with ceramic particles.

[0015] According to one embodiment, the trench is at least partially filled with air, gas, a mixture of gases, or a partial vacuum.

[0016] According to one embodiment, the heat dissipation device includes a plug that at least partially fills the trench.

[0017] According to one embodiment, the plug is moisture-proof.

[0018] According to one embodiment, the heat dissipation device includes a cap on top of a closed trench.

[0019] According to one embodiment, the cover is moisture-proof.

[0020] One embodiment provides a system that includes an antenna and electronic circuitry, as previously defined, the electronic circuitry being linked to the antenna.

[0021] One embodiment provides a method of manufacturing an electronic circuit including a semiconductor substrate, a radio frequency switch corresponding to a MOS transistor, the MOS transistor including a doped semiconductor region in the substrate, at least two metallization levels covering the substrate, each metallization level including a stack of insulating layers, a conductive pillar with a metal track on top, at least two connection elements each connecting to one of the doped semiconductor regions, each connection element being formed by the conductive pillar and conductive track of each metallization level, the manufacturing method further including forming a trench between the two connection elements, the trench completely penetrating the stack of insulating layers of one metallization level and further partially penetrating the stack of insulating layers of the metallization level closest to the substrate, and forming a heat dissipation device suitable for dissipating heat outside the trench. Attached Figure Description

[0022] The above-described features, advantages, and others will be described in detail by way of example rather than limitation, with reference to the accompanying drawings, wherein:

[0023] Figure 1 The diagram illustrates the parasitic capacitance of an electronic circuit that includes a radio frequency (RF) switch.

[0024] Figure 2A cross-section of an embodiment of an electronic circuit, including an RF switch, is shown in part and schematically.

[0025] Figure 3 A cross-section of another embodiment of an electronic circuit, including an RF switch, is shown in part and schematically.

[0026] Figure 4 A cross-section of another embodiment of an electronic circuit, including an RF switch, is shown in part and schematically.

[0027] Figure 5 A cross-section of another embodiment of an electronic circuit, including an RF switch, is shown in part and schematically.

[0028] Figure 6 It is a block diagram of electronic components;

[0029] Figure 7 A cross-section of the electronic circuit used to perform the first simulation is shown;

[0030] Figure 8 It is relative to Figure 7 The image shows a reduced grayscale image of the parasitic capacitance CBEOL of the trench height and width of the electronic circuit shown, which has uncoated trenches.

[0031] Figure 9 It is relative to Figure 7 The image shows a reduced grayscale image of the parasitic capacitance CBEOL of the trench height and width of the electronic circuit shown, which has trenches with a coating.

[0032] Figure 10 A cross-section of the electronic circuit used to perform the second simulation is shown;

[0033] Figure 11 yes Figure 10 The grayscale image shows the temperature in an electronic circuit without grooves.

[0034] Figure 12 yes Figure 10 The grayscale image shows the temperature in an electronic circuit with uncoated trenches; and

[0035] Figure 13 yes Figure 10 The image shows a temperature grayscale image of an electronic circuit with coated trenches. Detailed Implementation

[0036] Similar features are indicated by similar reference numerals in the figures. In particular, common structural and / or functional features in various embodiments may have the same reference numerals, and the same structures, dimensions, and material properties may be deployed.

[0037] For clarity, only the steps and elements useful for understanding the embodiments described herein are described in detail. In particular, electronic devices that implement electronic circuits with RF switches are not described in detail, and the described embodiments are compatible with common applications.

[0038] Unless otherwise stated, when referring to two elements connected together, it means a direct connection without any intermediate elements other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled through one or more other elements.

[0039] In the following description, when referring to qualifiers of relative position, such as terms “on,” “under,” “above,” “below,” “lower,” “upper,” etc., they should be taken into account unless otherwise specified regarding the orientation of the accompanying drawings or the electronic circuitry in its normal use position.

[0040] Unless otherwise stated, the expressions “about,” “probably,” “substantially,” and “approximately” indicate within 10%, preferably within 5%. Furthermore, unless otherwise stated, the terms “insulating” and “conductive” are considered herein to mean “electrically insulating” and “conductive,” respectively.

[0041] In the following description, when the membrane or layer has a permeability of less than 10 to water at 40°C. -1 A membrane or layer is considered moisture-proof at a rate of g / (m²*day). Moisture permeability can be measured using the High Accelerated Stress Test (HAST), which follows the standard operating procedure JEDEC pretreatment procedure JESD 22A113.

[0042] In the following description, a material is referred to as a good thermal conductor or a good heat conductor when its thermal conductivity is greater than or equal to 140 W / (mK).

[0043] Figure 1 The illustration shows some parasitic capacitances that need to be considered in the concept of an electronic circuit, which includes an RF switch made of a MOS transistor. Figure 1 The right side shows a cross-section of electronic circuit 10, and the left side shows a detailed view of electronic circuit 10.

[0044] The electronic circuit 10 includes a semiconductor substrate 12, an insulating layer 14 sandwiched between the substrate 12 and a semiconductor substrate 16 corresponding to the semiconductor layer, an RF switch corresponding to the MOS transistor 20, and a connection element 22. As a variant, the semiconductor substrate 12, the insulating layer 14, and the semiconductor layer 16 may be replaced by a single semiconductor substrate.

[0045] Transistor 20 includes drain and source semiconductor regions 24 and 26 formed in and on semiconductor layer 16, a gate insulator 28 on face 30 of semiconductor layer 16, and a conductive gate 32 covering the gate insulator 28. The conductive gate 32 may have a multilayer structure, for example, including a stack of two layers 32-1 and 32-2. Connecting elements 22 include connecting element 34 connected to drain region 24 and connecting element 36 connected to source region 26. Connecting elements 34 and 36 extend through a stack of insulating layers 38 covering face 30.

[0046] Some parasitic capacitances to consider are:

[0047] The capacitance Cm between connecting elements 34 and 36;

[0048] The capacitance Cgm between the upper part of connecting elements 34 and 36 and gate 32;

[0049] The capacitance Cgc between the lower part of connecting elements 34 and 36 and gate 32;

[0050] Through insulating layer 14, there is a capacitance Cboxl between drain region 24 and source region 26;

[0051] The capacitance Cboxv between drain region 24 and substrate 15, and between source region 26 and substrate 12;

[0052] The capacitance Cfe between the drain region 24 and the gate 32, and between the source region 26 and the gate 32, is achieved through the insulating spacer.

[0053] The capacitance Cfi between the drain region 24 and the gate 32, and between the source region 26 and the gate 32, is achieved through the semiconductor layer 16 and the gate insulator 28.

[0054] Through semiconductor layer 16, the capacitance Ci between drain region 24 and source region 26; and

[0055] The capacitance Cov of the gate insulator 28 is between the drain region 24 and the gate 32, and between the source region 26 and the gate 32.

[0056] It should be noted that capacitances Cov, Cfi, and Ci depend on the voltage applied to the drain region 24, source region 26, and / or gate 32. The capacitance symbol Cm is typically used for connection elements 34 and 36 of the first metallization level. For connection elements 34 and 36 made of portions of several metallization levels, the symbol CBEOL can be used for all parasitic capacitances between the different portions of connection elements 34 and 36. Therefore, capacitance CBEOL includes capacitance Cm.

[0057] Typically, to compare the performance of different RF switches, two coefficients, Ron and Coff, are used. The coefficient Coff is a capacitance, defined by the following relationship:

[0058] Coff=(Cgd+Ci+Cboxv) / 2+Cm+Cboxl

[0059] as well as:

[0060] Cgd = Cov + Cfi + Cfe + Cgc + Cgm

[0061] The coefficient Ron corresponds to the resistivity of the channel of transistor 20 when it is turned on. In particular, it is generally desirable that the product of the coefficients Ron and Coff be as low as possible.

[0062] Figure 2 A cross-section of an embodiment of electronic circuit 40 is shown in part and schematically.

[0063] The electronic circuit 40 includes a semiconductor substrate 42, an insulating layer 44 sandwiched between the semiconductor substrate 42 and a semiconductor substrate 46, and a semiconductor substrate 46 corresponding to the semiconductor layer having an upper surface 48. An insulating block 49 may be disposed in the semiconductor layer 46 to laterally isolate portions of the semiconductor layer 46.

[0064] Electronic circuit 40 includes an RF switch corresponding to MOS transistor 50, in Figure 2 The example shows three transistors 50.

[0065] Each transistor 50 includes drain and source semiconductor regions 52, 54 corresponding to doped regions formed in the semiconductor layer 46, a gate insulator 58 on surface 48, and a conductive gate 60 covering the gate insulator 58. For example, semiconductor regions 52, 54 can be a first doped region 52 and a second doped region 54. One of the first doped region and the second doped region 52, 54 is a gate region, and the other is a drain region. The transistors are connected via conductive tracks of successive metallization levels. The electronic circuit 40 includes a stack of at least two metallization levels, preferably at least three metallization levels. For example, in Figure 2The diagram illustrates three metallization levels M1, M2, and M3. The first metallization level M1 is closest to semiconductor layer 46, relative to the second and third metallization levels M2 and M3. Metallization levels M1, M2, and M3 have similar structures. Therefore, the elements present in each metallization level M1, M2, and M3 in the following text will be specified according to the reference of the metallization level M1, M2, or M3 to which that element belongs, which includes the suffixes _1, _2, and _3.

[0066] For each metallization level M1, M2, and M3, the electronic circuit 40 includes:

[0067] A stack of two insulating layers 60_1, 60_2, 60_3, or a stack of more than two insulating layers 60_1, 60_2, 60_3. The stack of insulating layers 60_1, 60_2, 60_3 can be made of the same material or different materials.

[0068] Conductive tracks 62_1, 62_2, and 62_3 are located in the uppermost insulating layers 60_1, 60_2, and 60_3 of the metallization layers M1, M2, and M3; and

[0069] Junction elements 64_1, 64_2, 64_3, corresponding to, for example, conductive pillars, connect the corresponding conductive tracks 62_1, 62_2, 62_3 of the corresponding metallization levels M1, M2, M3 to the corresponding conductive track of an adjacent metallization level among the corresponding metallization levels M1, M2, M3, or connect them to the gate 60, drain region 52, or source region 54 of a transistor in transistor 50.

[0070] For each transistor 50, the electronic circuit 40 includes a connecting element 66 that contacts the drain region 52 and a connecting element 68 that contacts the source region 54. The connecting elements 66 and 68 are made of conductive tracks 62_1, 62_2, 62_3 and junction elements in three metallization levels M1, M2, and M3, which are electrically connected together.

[0071] For example, semiconductor layer 46 is a silicon layer. The thickness of semiconductor layer 46 can vary between 10 nm and 200 nm. The thickness of insulating layer 44 can vary between 15 nm and 400 nm. The gate 60 of transistor 50 can be made of polysilicon or metal. The thickness of gate 60 can vary between 30 nm and 200 nm.

[0072] The total thickness of the first metallization layer M1 can vary between 100 nm and 600 nm. The total thickness of the second metallization layer M2 can vary between 100 nm and 1 μm. The total thickness of the third metallization layer M3 can vary between 100 nm and 5 μm. Insulating layers 44, 60_1, 60_2, and 60_3 can be made of silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), or any silicon oxide etch stop layer. The thickness of the first conductive rail 62_1 can vary between 100 nm and 1 μm. The thickness of the first junction element 64_1 can vary between 100 nm and 1 μm. The thickness of the second conductive rail 62_2 can vary between 100 nm and 1 μm. The thickness of the second junction element 64_2 can vary between 100 nm and 1 μm. The thickness of the third conductive rail 62_3 can vary between 100 nm and 5 μm. The thickness of the third conductive junction element 64_3 can vary between 100 nm and 2 μm. The conductive tracks 62_1, 62_2, 62_3 and the junction elements 64_1, 64_2, 64_3 can be made of metal or metal alloys, such as aluminum (Al), copper (Cu), tungsten (W), AlCu alloys, or Cu alloys. The conductive tracks 62_1, 62_2, 62_3 and the junction elements 64_1, 64_2, 64_3 can be made of different materials. For example, conductive track 62_1 can be made of Cu, while conductive tracks 62_2 and 62_3 can be made of Al.

[0073] Electronic circuit 40 includes trenches, Figure 2 A trench 70, as shown, extends into all the insulating layers 60_1, 60_2, and 60_3 of the metallization layers M1 and M2. The trench 70 terminates in insulating layer 60_1 such that one end of the trench 70 lies within insulating layer 60_1. The trench 70 includes sidewalls 72 and a bottom wall 74. The height H of the trench 70 varies between 1 μm and 10 μm. The average width W of the trench 70, i.e., the distance between two opposing sidewalls 72, varies between 100 nm and 3 μm. The sidewalls 72 of the trench 70 may be substantially parallel or may be inclined relative to each other. For example, in some embodiments, the width of the trench 70 is greater at the top than at the bottom, causing the trench 70 to be tapered due to the inclined sidewalls.

[0074] The trench 70 is filled with one or more materials and / or air, such that the region corresponding to the volume inside the trench 70 has an average relative permittivity lower than that of the materials constituting the insulating layers 60_1, 60_2, 60_3. According to one embodiment, the region corresponding to the volume inside the trench 70 is electrically insulating.

[0075] For each trench 70, the electronic circuit 40 includes a heat dissipation device or structure 80 that allows heat dissipation, and the heat dissipation device or structure 80 preferably also allows moisture protection to prevent moisture from reaching the insulating layers 60_1, 60_2, 60_3 exposed in the trench 70. In other words, there can be a one-to-one relationship between the trench 70 and the heat dissipation device 80. In this embodiment, the heat dissipation device 80 includes a heat dissipation coating 82, which may also be moisture-proof, covering and contacting the sidewalls 72 and bottom wall 74 of the trench 70. The remainder of the trench 70 may be filled with air, gas, or fluid. The coating 82 may have a single-layer or multi-layer structure. The thickness of the coating 82 varies between 10 nm and 500 nm. The coating 82 is made of a material with good thermal conductivity, thus improving heat dissipation. Coating 82 may comprise a layer made of aluminum nitride (AlN), molybdenum disulfide (MoS2), graphene, and / or silicon having ceramic particles (e.g., AlN particles). Coating 82 may have a multilayer structure, such as comprising an AlN layer or equivalent layer and a silicon nitride (SiN) layer.

[0076] Electronic circuitry 40 may include a trench 70 for each MOS transistor 50, the trench 70 being interposed between connection elements 66 and 68 associated with that transistor 50. Electronic circuitry 40 may include trench 70, the trench 70 being interposed between connection elements 66 and 68 associated with different transistors 50.

[0077] The trench 70 can be fabricated using etching processes such as deep reactive ion etching (DRIE), focused ion beam (FIB), or laser-assisted etching. The coating 82 can be fabricated using conformal deposition processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or plasma-enhanced atomic layer deposition (PEALD).

[0078] Figure 3 A cross-section of another embodiment of the electronic circuit 90 is shown partially and schematically. The electronic circuit 90 includes, in addition to the heat dissipation device 80 corresponding to the plug 92 filling the trench 70, a... Figure 2 All components of the electronic circuit 40 shown. The plug 92 also provides moisture protection. The plug 92 preferably completely fills the trench 70 from bottom to top. As a variation, the plug 92 may not completely fill the trench 70, but rather allow the bottom of the trench 70 to be filled with air, gas, a gas mixture, fluid, or a partial vacuum. For example, the plug 92 may cover the upper end of the gap at the bottom of the trench, such that the lower end of the plug rises to the bottom wall 74 of the insulating layer 60_1 (see...). Figure 3Above. The bottom wall 74 can be referred to as the surface. The plug 92 can be made of a polymer, such as polyimide (PI) or polybenzoxazole (PBO), possibly with particles of a good thermally conductive material. The plug 92 is preferably made of a good thermally conductive material. The plug 92 can be made of AlN, for example, by spin coating.

[0079] Figure 4 A cross-section of another embodiment of electronic circuit 100 is shown partially and schematically. Electronic circuit 100 includes all the components of electronic circuit 40 except for heat sink 80 and plug 104. Heat sink 80 includes a coating 102 that covers and contacts the sidewalls 72 and bottom wall 74 of trench 70. Plug 104 completely fills the remainder of trench 70 up to the top of trench. Coating 102 may have a single-layer or multi-layer structure. Coating 102 may be moisture-proof while plug 104 may not be moisture-proof. As a variation, coating 102 may not be moisture-proof while plug 104 may be moisture-proof. As a variation, coating 102 may be moisture-proof while plug 104 may be moisture-proof. As a variation, plug 92 may not completely fill trench 70, and the portion of the bottom of trench 70 between plug 104 and coating 102 may be filled with air, gas, a gas mixture, or a partial vacuum. In other words, there may be a gap between plug 104 and coating 102 at the bottom of plug 104. In this case, coating 102 is preferably moisture-proof. The thickness of coating 102 varies between 10 nm and 500 nm. Coating 102 may comprise a layer made of AlN, MoS2, graphene, and / or silicon with ceramic particles (e.g., AlN particles). Coating 102 may have a multilayer structure, for example, comprising an AlN layer or equivalent layer and a silicon nitride (SiN) layer. Plug 104 may be made of a polymer, such as polyimide or PBO. Both coating 102 and plug 104 are preferably made of materials with good thermal conductivity.

[0080] Figure 5 A cross-section of another embodiment of electronic circuit 110 is shown partially and schematically. Electronic circuit 110 includes all the elements of electronic circuit 40 except for heat sink 80 and cover 114. Heat sink 80 includes a coating 112 that covers and contacts the sidewalls 72 and bottom layer 74 of trench 70. Cover 114 closes, covers, or seals the top of trench 70. A gap 116 in trench 70 between coating 112 and cover 114 may contain air, gas, a gas mixture, or a partial vacuum. As a variation, the gap 116 in trench 70 between coating 112 and cover 114 may be wholly or partially formed by elements previously described herein. Figure 3 and Figure 4The discussion covers the replacement fillers for plugs 92 and 104, which are the same or similar. Coating 112 may be moisture-proof while cap 114 may not be. Alternatively, coating 112 may not be moisture-proof while cap 114 may be. Alternatively, coating 112 may be moisture-proof while cap 114 may be. The thickness of coating 112 varies between 10 nm and 500 nm. Coating 112 may comprise a layer made of AlN, MoS2, graphene, and / or silicon with ceramic particles (e.g., AlN particles). Coating 112 may have a multilayer structure, such as comprising an AlN layer or equivalent layer and a silicon nitride (SiN) layer. Cap 114 may be made of a polymer, such as polyimide or PBO. The thickness of cap 114 varies between 200 nm and 3 μm. Coating 112 is preferably made of a material with good thermal conductivity.

[0081] Figure 6 This is a block diagram of electronic device 120, which includes an antenna 122, a front-end module 124, a transceiver 126, and a microprocessor 128. The microprocessor 128 exchanges signals with the transceiver 126. The transceiver 126 exchanges signals with the front-end module 124. The front-end module 124 controls the antenna 122 for transmitting or receiving radio frequency signals received by the antenna 122. Previously disclosed embodiments of electronic circuits 40, 90, 100, and 110 can be implemented to manufacture the front-end module 124.

[0082] Perform a first simulation and a second simulation. When the previously disclosed trench is provided between the connecting elements, the first simulation aims to demonstrate the reduction in the parasitic capacitance CBEOL of the transistor and the resulting reduction in the coefficient Coff.

[0083] Figure 7 A cross-section of an electronic circuit 130 used to perform the first simulation is shown. The electronic circuit 130 includes a semiconductor substrate 132 covered by an insulating layer 134. Two connection elements 136 and 138 extend through the insulating layer 134. For the first simulation, each connection element 136 and 138 is made of components of a first metallization level, namely, a conductive track of the first metallization level and a junction element between the conductive track and the substrate 132. The two connection elements 136 and 138 are separated by a distance tB between 100 nm and 1 μm. A trench 140 exists within the insulating layer 134. The trench 140 has a height hA and a width tA. The sidewalls of the trench 140 are covered by an AlN layer 142. The thickness of layer 142 is equal to 50 nm. The remainder of the trench 140 is filled with air. The trench 140 is equidistant from each connection element 136 and 138 by a distance x. The height hT is the distance between the bottom of the trench 140 and the upper surface of the insulating layer 134. The parasitic capacitance CBEOL was determined by simulating the region 144 between the two connecting components 136 and 138, including the trench 140 and the height hT.

[0084] Figure 8 When coating 142 is absent, relative to Figure 7 The image shows a grayscale graph of the reduction R (in percentage) of the parasitic capacitance CBEOL of the trench 140 with height hA and width tA in the electronic circuit 130. It appears that when the volume of the trench 140 is greater than 60% of the volume of the region 144, the reduction in capacitance CBEOL is greater than 45%. Considering that the parasitic capacitance CBEOL essentially corresponds to 45% of the parasitic capacitance Coff, this results in a reduction of the coefficient Coff greater than 20%. Since the coefficient Ron is unaffected by the presence of the trench 140, the product Ron*Coff is reduced.

[0085] Figure 9 When coating 142 is present, relative to Figure 7 The image shows a grayscale graph of the reduction R (in percentage) of the parasitic capacitance CBEOL of the trench 140 with height hA and width tA in the electronic circuit 130. It appears that when the volume of the trench 140 is greater than 50% of the volume of the region 144, the capacitance CBEOL decreases by more than 40%. Considering that the parasitic capacitance CBEOL essentially corresponds to 45% of the parasitic capacitance Coff, this results in a decrease in the coefficient Coff greater than 18%. Since the coefficient Ron is unaffected by the presence of the trench 140, the product Ron*Coff decreases.

[0086] What appears advantageous is that the trench has the highest potential height for reducing the parasitic capacitance CBEOL. (This is based on previous information regarding...) Figure 2 , 3 In the embodiments disclosed in 4 and 5, trench 70 extends through all metallization layers (e.g., M2, M3) of the electronic circuit except for the first metallization layer (e.g., M1), and trench 70 extends through a portion of the first metallization layer (e.g., M1), i.e., into the insulating layer 60_1, such that trench 70 has the highest possible height. Therefore, utilizing the previous information... Figure 2 , 3 The reduction of parasitic capacitance CBEOL in the embodiments disclosed in 4 and 5 is greater than the reduction of parasitic capacitance CBEOL. The reduction of parasitic capacitance CBEOL can be achieved by using air-filled trenches that extend only into the first metallization layer or the first and second metallization layers and are covered by the insulating layer in the metallization layer.

[0087] In addition, previously regarding Figure 2 , 3 The manufacturing process of the trench 70 in the embodiments disclosed in 4 and 5 includes an etching step performed after the fabrication of all metallization layers. Therefore, it merely adds an extra step to the existing manufacturing method without changing the steps of the existing manufacturing method. Furthermore, Figure 2 , 3The manufacturing methods of the electronic circuits shown in 4 and 5 are simpler than those of electronic circuits in which the air-filled trenches extend only in the first metallization level or the first and second metallization levels. This is because in the latter case, the insulating layer of one of the metallization levels is deposited on the trench, so it is necessary to adjust these steps to ensure that the deposits do not fill the trench and do not affect the performance of the electronic circuit.

[0088] The second simulation aims to demonstrate that the implementation of the trench as previously disclosed can improve the dissipation of heat generated by electronic components such as MOS transistors.

[0089] Figure 10 A cross-section of an electronic circuit 150 used to perform a second simulation is shown. The electronic circuit 150 includes a Si substrate 152 covered by an insulating layer 154 made of SiO2. Two connecting elements 156 and 158 extend through the insulating layer 154. For the second simulation, each connecting element 156 and 158 can be considered as a Cu pillar 160 and 162, with Cu orbitals 164 and 166 on top, and the metal pillars 160 and 162 are parallel. The distance D1 between the two connecting elements 156 and 158 is equal to 360 nm. The doped Si layer 168 on the substrate of the connecting pillars 160 and 162 can simulate a MOS transistor. A trench 170 is present in the insulating layer 154 and is filled with air. For the second simulation, the trench 170 has a height of 3 μm and a width of 300 nm. The trench 170 is equidistant from each connecting element 156 and 158. An AlN layer 172 covers the walls of the trench 170. The thickness of layer 172 is 50 nm. For example... Figure 10 As shown, in some embodiments, the insulating layer 173 may be present between the respective sidewalls of the tracks 164, 166 and the AlN layer 172.

[0090] Figure 11 , 12 Figures 1 and 13 are grayscale images of temperature T in electronic circuits 150 with different configurations. Figure 11 , 12 In Figure 13, the dark shading at the bottom corresponds to the lowest temperature, and the dark shading adjacent to the doped Si region 168 corresponds to the highest temperature. Pillars 160 and 162 and orbitals 164 and 166 are not shown in... Figure 11 , 12 As shown in 13.

[0091] Figure 11 This is a grayscale image of the temperature of electronic circuit 150 when trench 170 is not present. The vacuum between pillars 160 and 162 and between tracks 164 and 166 is filled by SiO2 layer 154.

[0092] Figure 12This is a grayscale image of the temperature of electronic circuit 150 when trench 170 is filled with air but without AlN layer 172. Trench 170 filled with air is not conducive to heat dissipation.

[0093] Figure 13 The grayscale value of the temperature of the electronic circuit 150 when both the trench 170 and the AlN layer 172 are present. Figure 5 Compared to the configuration without trenches (170), AlN layer 172 increases heat dissipation.

[0094] The electronic circuit (40; 90; 100; 110; 124) can be summarized as including a semiconductor substrate (46), a radio frequency switch corresponding to a MOS transistor (50), the radio frequency switch including doped semiconductor regions (52, 54) in the substrate, at least two metallization levels (M1, M2, M3) covering the substrate, each metallization level including a stack of insulating layers (60_1, 60_2, 60_3), and conductive pillars (64_1, 64_2) with metal tracks (62_1, 62_2, 62_3) on top. 4_2, 64_3), at least two connecting elements (66, 68), each connecting element connecting to one of the doped semiconductor regions, and each connecting element consisting of a conductive pillar and a conductive track of each metallization level, the electronic circuit further including a trench (70) between the two connecting elements and a heat dissipation device (80) suitable for dissipating heat out of the trench, the trench completely passing through the stack of insulating layers of a metallization level and further partially passing through the stack of insulating layers of the metallization level closest to the substrate.

[0095] The heat dissipation device (80) can also be a moisture protection device, suitable for preventing moisture from reaching the insulation layer exposed in the trench (70).

[0096] The trench (70) can have a height (H) greater than 1 μm.

[0097] The trench (70) can have an average width (W) greater than 100 nm.

[0098] The heat dissipation device (80) may include a coating (82) covering the side (72) of the trench (70).

[0099] The coating (82) can be moisture-proof.

[0100] The thickness of the coating (82) can be between 10 nm and 500 nm.

[0101] The coating (82) can be made of one or more good thermally conductive materials.

[0102] The coating (82) can be made of aluminum nitride (AlN), molybdenum disulfide (MoS2), graphene and / or silicon with ceramic particles.

[0103] The trench (70) can be at least partially filled with air, gas, gas mixture or partial vacuum.

[0104] The heat dissipation device (80) may include a plug (92) that at least partially fills the groove (70).

[0105] The plug (92) can be used for moisture protection.

[0106] The heat dissipation device (80) may include a cover (114) on top of the closed trench (70).

[0107] The cover (114) can be moisture-proof.

[0108] The system (120) can be summarized as including an antenna (122) and electronic circuitry (124) linked to the antenna.

[0109] The manufacturing method of the electronic circuit (40; 90; 100; 110; 124) can be summarized as including a semiconductor substrate (46), a radio frequency switch corresponding to a MOS transistor (50), the radio frequency switch including doped semiconductor regions (52, 54) in the substrate, at least two metallization layers (M1, M2, M3) covering the substrate, each metallization layer including a stack of insulating layers (60_1, 60_2, 60_3), and conductive pillars (64_1, 62_2, 62_3) on top of metal tracks (62_1, 62_2, 62_3). 64_2, 64_3), at least two connecting elements (66, 68), each connecting element connecting to one of the doped semiconductor regions, and each connecting element being formed by conductive pillars and conductive tracks of each metallization level, the method comprising forming a trench (70) between the two connecting elements, the trench (70) completely penetrating the stack of insulating layers of one metallization level and further partially penetrating the stack of insulating layers of the metallization level closest to the substrate, and forming a heat dissipation device (80) suitable for dissipating heat out of the trench.

[0110] The various embodiments described above can be combined to provide further embodiments. If it is necessary to utilize concepts from various patents, applications, and publications to provide even more advanced embodiments, aspects of the embodiments can be modified.

[0111] These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents enjoyed by such claims. Therefore, the claims are not limited to this disclosure.

Claims

1. An electronic device, the electronic device comprising: Semiconductor substrate; The MOS transistor on the semiconductor substrate; A radio frequency switch corresponding to the MOS transistor, the radio frequency switch comprising: The doped semiconductor region in the semiconductor substrate; The semiconductor substrate has at least two metallization levels, each metallization level comprising: A stack of insulating layers, the stack of insulating layers including an upper insulating layer having an upper surface facing away from the semiconductor substrate; Stacked conductive pillars extending through the insulating layer; Metal tracks within the stack of insulating layers and coupled to the conductive pillars; and At least two connecting elements, each connecting element connecting to one of the doped semiconductor regions, each connecting element including one of the conductive pillars and one of the metal orbitals of the at least two metallization levels; The trench between the two connecting elements, the trench overlapping with a first MOS transistor in the MOS transistor on the semiconductor substrate, the trench being defined by corresponding sidewalls of the stack of insulating layers and by corresponding end surfaces of corresponding insulating layers in the stack of insulating layers; and The heat dissipation structure within the trench overlaps with the first MOS transistor in the MOS transistor, and the heat dissipation structure is configured to dissipate heat outside the trench. The heat dissipation structure includes: A heat-dissipating coating extending along the respective end surface, the respective sidewall, and the upper surface of the upper insulating layer; and A plug is located in the trench and on the heat dissipation coating, and the plug and the heat dissipation coating completely fill the trench.

2. The electronic device according to claim 1, wherein: The heat dissipation structure is moisture-proof and configured to prevent moisture from reaching the insulation layer through the grooves.

3. The electronic device according to claim 1, wherein the trench has a height greater than or equal to 1µm.

4. The electronic device according to claim 1, wherein the trench has an average width greater than or equal to 100 nm.

5. The electronic device according to claim 1, wherein the heat dissipation structure completely overlaps with the first MOS transistor.

6. The electronic device according to claim 1, wherein the heat dissipation structure is moisture-proof.

7. The electronic device according to claim 1, wherein the thickness of the heat dissipation structure is from 10 nm to 500 nm.

8. The electronic device of claim 1, wherein the coating is made of at least one of the following: aluminum nitride, molybdenum disulfide, graphene, and silicon having ceramic particles.

9. The electronic device according to claim 1, wherein the plug is moisture-proof.

10. The electronic device according to claim 1, further comprising a cover covering the heat dissipation structure.

11. The electronic device of claim 10, wherein the cover is moisture-proof.

12. A method for manufacturing an electronic device, comprising: Multiple transistors are formed on the surface of a semiconductor substrate and on the insulating material of the semiconductor substrate; A plurality of stacked insulating layers are formed on the surface of the semiconductor substrate, and the transistor is covered by the plurality of insulating layers, wherein the upper insulating layer of the stacked plurality of insulating layers includes an upper surface facing away from the semiconductor substrate; A first connecting element is formed, the first connecting element extending into the insulating layer and into a first doped region in the semiconductor substrate; A second connecting element is formed, the second connecting element extending into the insulating layer and into a second doped region in the semiconductor substrate; A trench is formed between the first connecting element and the second connecting element, the trench extending into the plurality of insulating layers and overlapping with a corresponding transistor of the plurality of transistors, wherein the trench is defined by a corresponding sidewall of the plurality of insulating layers and by a corresponding end surface of a corresponding insulating layer of the plurality of insulating layers; as well as A heat dissipation structure is formed on the sidewall of the insulating layer and within the trench, wherein the heat dissipation structure includes: A heat-dissipating coating that extends along the respective end surface, the respective sidewall, and the upper surface of the upper insulating layer; and A plug is located in the trench and on the heat dissipation coating, and the plug and the heat dissipation coating completely fill the trench.

13. An electronic device, comprising: Substrate; The first doped region and the second doped region in the substrate; Multiple transistors; A plurality of insulating layers are stacked on the substrate and on the plurality of transistors, wherein the upper insulating layer of the stacked plurality of insulating layers includes an upper surface facing away from the substrate; A first connecting element extends into the plurality of insulating layers to the first doped region and is coupled to the first doped region; A second connecting element extends into the plurality of insulating layers to the second doped region and is coupled to the second doped region; A trench between the first connecting element and the second connecting element, the trench extending into the plurality of insulating layers, defined by respective sidewalls of the plurality of insulating layers, and overlapping with a first transistor of the plurality of transistors, the trench including end surfaces spaced apart from the first transistor of the plurality of transistors, and the trench including openings exposed from the plurality of insulating layers; The heat dissipation structure in the trench overlaps and aligns with corresponding transistors among the plurality of transistors, and the heat dissipation structure further includes: A heat-dissipating coating that extends along the respective end surfaces, the respective sidewalls of the plurality of insulating layers, and the upper surface of the upper insulating layer; A plug is located in the gap defined by the heat dissipation coating in the trench, and the plug and the heat dissipation coating completely fill the trench; The cover extends across the opening of the groove and is located on a corresponding portion of the heat-dissipating coating on the upper surface of the upper insulating layer.

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