Resistive memory test structure, method of operation and method of fabrication

Abstract

A resistive random access memory (RRAM) test structure, an operating method for the RRAM test structure, and a preparation method. The RRAM test structure includes a substrate, a RRAM, a current-limiting resistor, and at least one test pad disposed on the substrate. The RRAM includes a first electrode, a RRAM layer, and a second electrode sequentially provided on a surface of the substrate in a direction away from the substrate. The current-limiting resistor extends in a strip shape on the surface of the substrate. The first electrode is integrally formed in the same layer as the current-limiting resistor and is electrically connected to the at least one test pad via the current-limiting resistor. The RRAM test structure has a simple manufacturing process and can greatly reduce the test cost in the research of different RRAM material systems.

Description

Technical Field

[0001] The embodiments of this disclosure relate to a resistive random access memory (RRAM) test structure, an operation method for the RRAM test structure, and a preparation method. Background Technology

[0002] With the development of semiconductor technology, resistive random access memory (RRAM) has become a research hotspot for next-generation memory, possessing strong application potential and considered the most commercially valuable memory. For example, in the operation of RRAM, the initial state of the RRAM is first activated by a forming operation to form a conductive filament of oxygen vacancies. The forming process is equivalent to a soft breakdown of the RRAM's dielectric layer. Without additional current-limiting devices, the current overshoot generated by the large forming voltage at the instant the RRAM is formed into a low-resistivity state can cause hard breakdown of the RRAM's dielectric layer, preventing further set and reset operations. Typically, the transition of the RRAM from a high-resistivity state to a low-resistivity state is called a set, and the transition from a low-resistivity state to a high-resistivity state is called a reset. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a resistive switching memory test structure, including: a substrate and a resistive switching memory, a current limiting resistor and at least one test pad disposed on the substrate. The resistive switching memory includes a first electrode, a resistive switching memory layer and a second electrode sequentially provided on the surface of the substrate in a direction away from the substrate. The current limiting resistor extends in a strip shape on the surface of the substrate. The first electrode and the current limiting resistor are integrally formed in the same layer and are electrically connected to at least one test pad via the current limiting resistor.

[0004] For example, in a resistive switching memory test structure provided in one embodiment of this disclosure, the current-limiting resistor includes at least a portion extending in a spiral and / or a portion extending in a serpentine shape.

[0005] For example, in a resistive switching memory test structure provided in one embodiment of this disclosure, the thickness of the current-limiting resistor is less than the thickness of the first electrode in a direction perpendicular to the surface of the substrate.

[0006] For example, in a resistive switching memory test structure provided in one embodiment of this disclosure, the current-limiting resistor has a resistance value in the range of 1kΩ to 200KΩ for the portion from at least one test pad to the resistive switching memory.

[0007] For example, in a resistive switching memory test structure provided in one embodiment of this disclosure, at least one test pad is a plurality of test pads, the plurality of test pads are electrically connected to a current-limiting resistor respectively, and the path extending along the strip of the current-limiting resistor is at a different distance from the resistive switching memory.

[0008] For example, in a resistive switching memory test structure provided in one embodiment of this disclosure, at least one test pad is located on the same layer as the second electrode and is electrically connected to a current-limiting resistor through a via.

[0009] At least one embodiment of this disclosure also provides an operation method for a resistive switching memory test structure provided in at least one embodiment of this disclosure, comprising: applying a first voltage to a second electrode, and applying a second voltage to the first electrode through a current-limiting resistor in at least one test pad to activate the resistive switching memory.

[0010] For example, one embodiment of the present disclosure provides an operation method that further includes: obtaining a range of current-limiting resistor values ​​to select one of at least one test pad before activating the resistive switching memory.

[0011] For example, an embodiment of the present disclosure provides an operating method that further includes: after activating the resistive random access memory (RRAM), during the setting or resetting operation of the RRAM, bypassing the current-limiting resistor to apply an operating voltage to the first and second electrodes of the RRAM.

[0012] At least one embodiment of this disclosure also provides a method for fabricating a resistive switching memory test structure provided in at least one embodiment of this disclosure, comprising: forming a thin film stack comprising a first electrode thin film, a resistive switching memory thin film, and a second electrode thin film sequentially on a substrate; and patterning the thin film stack using a photolithography method to form the first electrode, the resistive switching memory layer, the second electrode, and a current-limiting resistor.

[0013] For example, one embodiment of the present disclosure provides a preparation method that further includes: patterning a thin film stack using a photolithography method to form at least one test pad, wherein the at least one test pad is located on the same layer as the second electrode and is electrically connected to a current-limiting resistor through a via.

[0014] For example, in a fabrication method provided in one embodiment of this disclosure, a photolithography method is used to pattern a thin film stack to form a first electrode, a resistive switching memory layer, a second electrode, and a current-limiting resistor. This includes: forming a first etching mask pattern over the second electrode thin film using a first photoresist layer; performing a first etching operation on the thin film stack using the first etching mask pattern until the first electrode thin film is exposed; forming a second etching mask pattern on the thin film stack using a second photoresist layer; and performing a second etching operation on the exposed first electrode thin film using the second etching mask pattern to obtain the first electrode and the current-limiting resistor.

[0015] For example, in a fabrication method provided in one embodiment of this disclosure, a first etching operation is performed on the thin film stack using a first etching mask pattern until the first electrode film is exposed, including: controlling the etching rate to control the thickness of the exposed first electrode film within a predetermined range, detecting the remaining thickness of the first electrode film, and setting parameters for a second etching operation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0017] Figure 1 A schematic diagram of a 1T1R structure consisting of a resistive random access memory and a transistor connected in series is shown.

[0018] Figure 2 A schematic diagram of machine current limiting is shown;

[0019] Figure 3 A schematic diagram illustrating a resistive switching memory test structure provided in at least one embodiment of the present disclosure is shown;

[0020] Figure 4 A schematic cross-sectional view of a resistive switching memory test structure provided in at least one embodiment of the present disclosure is shown;

[0021] Figure 5 A schematic flowchart illustrating an operation method for a resistive random access memory test structure provided in at least one embodiment of the present disclosure is shown.

[0022] Figure 6A A schematic flowchart illustrating a method for fabricating a resistive switching memory test structure according to at least one embodiment of the present disclosure is shown.

[0023] Figure 6B A schematic flowchart of step S602 provided in at least one embodiment of this disclosure is shown;

[0024] Figure 7 A process flow diagram is shown illustrating a method for fabricating a resistive switching memory test structure according to at least one embodiment of the present disclosure;

[0025] Figure 8 A schematic diagram of an IV scan using a resistive random access memory with machine current limiting is shown.

[0026] Figure 9A schematic diagram of an IV scan of a resistive random access memory test structure provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0028] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0029] Forming a resistive random access memory (RRAM) means using a higher voltage to softly break down the RRAM in its initial, high-resistivity state, thereby activating its operability.

[0030] In the operation of resistive random access memory (RRAM), there are generally two current limiting methods. One is transistor current limiting, which involves connecting the RRAM in series with a transistor to limit the current of the RRAM. The structure of the RRAM and transistor in series is called a 1T1R structure. Figure 1 As shown in the diagram, by controlling the gate voltage Vwl of the transistor, the current flowing through the resistive random access memory (RRAM) in the instantaneous series path after successful forming is limited, thus achieving current limiting. The transistor-based current limiting method is widely used in array-level RRAM circuits, where the transistor is fabricated in the front-end process, and the RRAM fabrication is completed in the back-end process.

[0031] Another method of rate limiting is machine rate limiting, which uses the rate limiting function built into the test equipment. Figure 2 A schematic diagram of machine current limiting is shown, for example, the test equipment is a Keysight B1500A (one of the most commonly used semiconductor device parameter analyzers), in... Figure 2 The test equipment includes a Source Measure Unit (SMU), a Waveform Generator / Fast Measure Unit (WGFMU), and a Roadsite Unit (RSU). The SMU generates signal excitation and acquires measurement response signals. The WGFMU is a test module capable of generating arbitrary voltage waveforms and extremely fast current and voltage measurements. The RSU is used to select between SMU and WGFMU branches. The current-limiting function of this test equipment comes from the limiting function of the SMU, such as current limiting. In voltage source mode, a current limit value is set; when the loop current reaches the limit value, the system switches from voltage source control to current source control.

[0032] However, both of the above-mentioned rate limiting methods have their own drawbacks.

[0033] (1) Disadvantages of using machine current limiting: In DC scanning tests, machine current limiting cannot play a current limiting role at the moment when the resistive switching memory becomes a low-resistance state because the response speed of the SMU is limited by parasitic capacitance.

[0034] like Figure 2 As shown, the stray capacitance and parasitic capacitance C between the center conductor and the outer shielding layer are typically 10. 2 The current is on the order of pF. Assuming the forming voltage is 3V and the low resistance of the RRAM is 1KΩ, the instantaneous current flowing through the RRAM at the forming point is 3mA. The discharge time constant of the capacitor at node Vs is 100ns (=100pF×1KΩ), meaning that the current flowing through the RRAM will only reach the set SMU current limit value after at least 100ns. Therefore, the method of limiting current by machine is not ideal.

[0035] In pulse testing, the resistive switching memory is more likely to be damaged to failure because the WGFMU pulse module with infinite current function is used.

[0036] (2) Disadvantages of using transistor current limiting: Current limiting of transistors greatly increases the complexity of the process. Ordinary laboratories generally do not have the conditions for on-chip transistor fabrication. Usually, transistor fabrication is completed by a foundry and then the resistive random access memory (RRAM) is fabricated in the laboratory. However, choosing a foundry will greatly increase testing costs and significantly increase time costs, which is not conducive to flexible exploration of the material system and subsequent processes of RRAM.

[0037] Alternatively, an external transistor / resistor can be used for current limiting. However, similar to machine current limiting, since the external transistor and the resistive switching memory need to be connected via probes, the parasitic capacitance of the probes cannot be avoided, which can cause current limiting failure.

[0038] At least one embodiment of this disclosure provides a resistive switching memory test structure, including: a substrate and a resistive switching memory, a current limiting resistor and at least one test pad disposed on the substrate. The resistive switching memory includes a first electrode, a resistive switching memory layer and a second electrode sequentially provided on the surface of the substrate in a direction away from the substrate. The current limiting resistor extends in a strip shape on the surface of the substrate. The first electrode and the current limiting resistor are integrally formed in the same layer and are electrically connected to at least one test pad via the current limiting resistor.

[0039] The current-limiting resistor in the resistive random access memory (RRAM) test structure provided in the above embodiments of this disclosure can be equivalent to the series resistance of the RRAM. This RRAM test structure can solve the problem that the RRAM will break down directly after forming and cannot be reset under the condition of lack of transistors. It can also solve the problem that the current limiting response speed of the machine is slow due to parasitic capacitance and stray capacitance, which leads to the RRAM being broken down and unable to be reset. Moreover, the manufacturing process of this RRAM is simple, and it can greatly reduce the testing cost when used in the study of different RRAM material systems.

[0040] At least one embodiment of this disclosure also provides an operation method and a preparation method for the above-described resistive switching memory test structure.

[0041] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.

[0042] Figure 3 A schematic diagram of a resistive switching memory test structure provided in at least one embodiment of the present disclosure is shown.

[0043] like Figure 3 As shown, the resistive switching memory test structure includes a substrate 101 and one or more resistive switching memories 102 disposed on the substrate 101, a current-limiting resistor 103, and at least one test pad 104. The current-limiting resistor 103 extends in a strip shape on the surface of the substrate 101, and the resistive switching memory 102 is electrically connected to at least one test pad 104 via the current-limiting resistor 103.

[0044] For example, in some embodiments of this disclosure, the current-limiting resistor can be equivalent to the series resistance of the resistive random access memory (RRAM), thus enabling stable testing of the electrical characteristics of small-sized, easily failing RRAMs without the need for transistors.

[0045] For example, in Figure 3In this embodiment, the current-limiting resistor 103 may include at least a spiral-extending portion and / or a serpentine-extending portion, thereby allowing the current-limiting resistor 103 to extend a greater distance per unit area. When the current-limiting resistor extends in a spiral and / or serpentine manner, the resistance value of the current-limiting resistor to be formed can be flexibly selected, making the resistive switching memory test structure provided by this disclosure embodiment highly flexible.

[0046] For example, in Figure 3 In this embodiment, there are multiple resistive switching memory (RSM) pads 102 arranged along the wires used to form the current-limiting resistor, for example, at equal intervals. A single test pad 104 is formed at the end of the wires used to form the current-limiting resistor. However, in other embodiments, multiple (two or more) test pads 104 may be formed, each individually electrically connected to the current-limiting resistor 103, and at different distances from the RSM 102 along the strip-shaped extension path of the current-limiting resistor 103. Thus, during testing, for the same RSM, one of the multiple test pads can be selected for testing according to the required current-limiting resistor value; the farther the test pad is from the RSM 102, the larger the obtained current-limiting resistor value.

[0047] Figure 4 A schematic cross-sectional view of a resistive switching memory test structure provided in at least one embodiment of the present disclosure is shown.

[0048] like Figure 4 As shown, a resistive switching memory is disposed on a substrate 201. The resistive switching memory includes a first electrode 202, a resistive switching storage layer 203, and a second electrode 204 sequentially provided on the surface of the substrate 201 in a direction away from the substrate 201. The first electrode 202 is integrally formed in the same layer with a current-limiting resistor 205 and is electrically connected to at least one test pad (not shown) via the current-limiting resistor 205.

[0049] For example, in some embodiments of this disclosure, the resistive switching memory layer 203 may further include a stacked resistive switching layer 206 and a resistive switching functional layer 207. The resistive switching layer 206 is a layer that enables the resistive switching memory to undergo resistance switching, and the resistive switching functional layer 207 plays a role in optimizing the resistive switching memory and making the resistive switching memory more stable.

[0050] For example, in some embodiments of this disclosure, the thickness of the current-limiting resistor 205 is less than the thickness of the first electrode 202 in a direction perpendicular to the surface of the substrate 201.

[0051] For example, in some embodiments of this disclosure, the test pad ( Figure 4 The electrode (not shown) is located on the same layer as the second electrode 204 and is electrically connected to the current-limiting resistor 205 through a via (not shown).

[0052] For example, in some embodiments of this disclosure, the current-limiting resistor from the test pad to the resistive switching memory has a resistance value in the range of 1kΩ to 200KΩ, which is a thin-film resistor.

[0053] Figure 5 A schematic flowchart illustrating an operation method for a resistive random access memory test structure provided in at least one embodiment of the present disclosure is shown.

[0054] like Figure 5 As shown, the operation method includes steps S501 to S503.

[0055] Step S501: Obtain the resistance range of the current-limiting resistor to select one of at least one test pad.

[0056] For example, different test pads can be selected to obtain different current-limiting resistor values. By pre-calculating the resistance range that may assist in current limiting during activation, the area of ​​the test layout can be effectively saved.

[0057] Step S502: Apply a first voltage to the second electrode and apply a second voltage to the first electrode through a current-limiting resistor in at least one test pad to activate the resistive switching memory.

[0058] For example, when the first and second voltages applied to the first and second electrodes constitute a positive voltage, oxygen atoms in the resistive switching memory layer move towards the second electrode. For example, when the positive voltage applied to the resistive switching memory reaches a certain condition (application of activation voltage), oxygen atoms can leave the crystal lattice, generating sufficient oxygen vacancies.

[0059] Step S503: During the set or reset operation of the resistive random access memory, the operating voltage is applied to the first and second electrodes of the resistive random access memory, bypassing the current limiting resistor.

[0060] For example, during the activation operation of a resistive random access memory (RRAM), it is necessary to prevent soft breakdown, so a current-limiting resistor is used for current limiting. During the set or reset operation of the RRAM, current limiting is not required, so the operating voltage is applied to the first and second electrodes of the RRAM bypasses the current-limiting resistor.

[0061] Figure 6A A schematic flowchart illustrating a method for fabricating a resistive switching memory test structure provided in at least one embodiment of this disclosure is shown.

[0062] like Figure 6A As shown, the preparation method includes steps S601 to S602.

[0063] Step S601: Form a thin film stack comprising a first electrode thin film, a resistive switching memory thin film, and a second electrode thin film sequentially on the substrate.

[0064] For example, the substrate can be a substrate material with high thin-film resistance, such as a SiO2 substrate or a Si substrate.

[0065] For example, the second electrode film can be made of materials such as TiN, W, or TaN.

[0066] For example, resistive switching memory films can include resistive switching functional films and resistive switching films. Resistive switching functional films can use materials such as TaOx, Ta, and AlOx to improve the performance of resistive switching memory, while resistive switching films can use materials such as HfOx, WOx, and TaOx to realize the resistive switching function.

[0067] For example, the first electrode thin film can be made of materials such as TiN, W, or TaN.

[0068] Step S602: Pattern the thin film stack using photolithography to form the first electrode, the resistive switching memory layer, the second electrode, and the current-limiting resistor.

[0069] For example, a cross-sectional view of the overall structure of the first electrode, resistive switching memory layer, second electrode, and current-limiting resistor formed in step S602 can be referenced. Figure 4 On the surface of the substrate, in the direction away from the substrate, there are sequentially arranged a first electrode, a resistive switching storage layer, and a second electrode. The first electrode and the current-limiting resistor are integrally formed in the same layer.

[0070] For example, the preparation method provided in the embodiments of this disclosure may further include: patterning the thin film stack using a photolithography method to form at least one test pad, wherein the at least one test pad is located on the same layer as the second electrode and is electrically connected to a current-limiting resistor through a via.

[0071] Figure 6B A schematic flowchart of step S602 provided in at least one embodiment of the present disclosure is shown.

[0072] like Figure 6B As shown, step S602 includes the following steps S611 to S604.

[0073] Step S611: Form a first etching mask pattern on the second electrode film using a first photoresist layer.

[0074] For example, a first photoresist layer is covered over the second electrode film, and a photolithography operation is performed on the first photoresist layer to form a first etch mask pattern.

[0075] Step S612: Using the first etching mask pattern, perform a first etching operation on the thin film stack until the first electrode thin film is exposed.

[0076] Step S613: Form a second etching mask pattern on the thin film stack using a second photoresist layer.

[0077] For example, a second photoresist layer is deposited on a thin film stack, and a photolithography operation is performed on the second photoresist layer to form a second etch mask pattern.

[0078] Step S614: Using the second etching mask pattern, perform a second etching operation on the exposed first electrode film to obtain the first electrode and the current-limiting resistor.

[0079] For example, in some embodiments of this disclosure, step S612 may include: controlling the etching rate to control the thickness of the exposed first electrode film within a predetermined range, detecting the remaining thickness of the first electrode film, and setting parameters for the second etching operation.

[0080] For example, the remaining thickness of the first electrode film can be detected by a four-probe sheet resistance tester, thereby making the thickness of the subsequently formed current-limiting resistor in the direction perpendicular to the substrate surface less than the thickness of the first electrode.

[0081] The current-limiting resistor is obtained by etching the first electrode thin film. Since the first electrode is generally made of a metal or metallic material thin film with good conductivity, it is necessary to calculate the resistance value and perform layout design to fabricate a sufficiently long metal line to obtain a sufficiently large current-limiting resistor. According to the resistance formula:

[0082] R = ρL / (Wd)

[0083] Where ρ is the resistivity of the first electrode material, L is the line length, and W and d are the line width and the thickness of the first electrode film, respectively (in...). Figure 4 (As indicated by the Chinese symbol). Different current-limiting resistors can be obtained by controlling the thickness of the first electrode film and the length of the lines. Setting a large resistance range makes it easier to find a suitable resistance value for the current-limiting resistor during the activation operation.

[0084] The preparation method provided in at least one embodiment of this disclosure has simple process steps, and the current-limiting resistor can be easily prepared together with the resistive switching memory, which greatly simplifies the complexity and reliability of resistive switching memory testing. Compared with the preparation process of the 1T1R structure, the complexity and difficulty are greatly simplified, and the testing cost can be greatly reduced when used for the study of different resistive switching memory material systems.

[0085] Figure 7 A process flow diagram is shown for a method of fabricating a resistive switching memory test structure provided in at least one embodiment of the present disclosure.

[0086] like Figure 7As shown, firstly, a thin film stack consisting of a first electrode film, a resistive switching memory film, and a second electrode film is formed on the substrate using a coating device to obtain an initial sample. A cross-sectional schematic diagram of the initial sample is shown below. Figure 7 As shown in (a) in the figure.

[0087] Then, photoresist is coated over the second electrode film and photolithography is performed on the photoresist, such as... Figure 7 As shown in (b) of the diagram.

[0088] Next, a hard metal layer (e.g., a metal material with good hardness and low resistivity such as platinum or lead) is vapor-deposited or sputtered onto the sample, including the photoresist pattern obtained after photolithography. The thickness of this hard metal layer is less than the thickness of the photoresist pattern, thus separating the hard metal layer on the photoresist pattern from the rest of the hard metal layers. For example, the hard metal is used for pin testing and defining device dimensions. A schematic cross-sectional view obtained after this step is shown below. Figure 7 As shown in (c) in the figure.

[0089] Then, the photoresist and the hard metal on the photoresist are peeled off to form a first etching mask pattern formed by the remaining hard metal layer, the cross-sectional view of which is shown below. Figure 7 As shown in (d) in the figure.

[0090] Then, the thin film stack is etched using the first etching mask pattern until the first electrode thin film is exposed, as shown in the cross-section. Figure 7 As shown in (e). For example, dry etching can be used; for example, the thickness of the exposed first electrode film can be controlled within a predetermined range by controlling the etching rate, for example, by using a four-probe sheet resistance meter to detect the remaining thickness of the first electrode film and setting the parameters of the second etching operation.

[0091] Then, photoresist is formed again on the thin film stack of the sample, and photolithography is performed to obtain a second etching mask pattern formed by the photoresist itself, such as... Figure 7 As shown in (f) in the figure.

[0092] Then, using the second etching mask pattern, the exposed first electrode film is etched to obtain the current-limiting resistor, the cross-sectional view of which is shown below. Figure 7 As shown in (g) in the diagram; the second etching mask pattern protects the portion of the first electrode film used to form the current-limiting resistor. Similarly, for example, a four-probe sheet resistance meter can be used to check if the etching is clean, ensuring as little as possible that no first electrode film residue remains, preventing the current-limiting resistor from being short-circuited. Finally, a resist removal operation is performed to complete the fabrication, as shown in the diagram. Figure 7 As shown in (h).

[0093] It should be noted that when the etching mask pattern is directly formed using a photoresist layer, the step of forming the hard metal layer can be omitted. The etching operation can be performed on the thin film stack after obtaining the first etching mask pattern in the first photolithography operation; the embodiments disclosed herein do not limit this.

[0094] Figure 8 A schematic diagram of a conventional IV scan using a resistive random access memory with machine current limiting is shown.

[0095] like Figure 8 As shown, for a resistive random access memory (RRAM) with no current limit and relying on machine current limiting, the machine current limit value is displayed as 200μA in the IV curve. After activating the RRAM, it is impossible to perform reset or set operations, and the RRAM is directly damaged.

[0096] Figure 9 A schematic diagram of an IV scan of a resistive random access memory test structure provided in at least one embodiment of the present disclosure is shown.

[0097] like Figure 9 As shown, for the resistive random access memory (RRAM) test structure provided in at least one embodiment of this disclosure, the RRAM test structure, in addition to the RRAM, also has a current-limiting resistor. During the set and reset operations after successful activation of the RRAM, the current-limiting resistor can be bypassed to apply the corresponding operating voltage to the first and second electrodes of the RRAM. Figure 9 The results show that the resistive random access memory has a stable and good resistive window.

[0098] The following points need to be explained:

[0099] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0100] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0101] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A resistive switching memory (RSM) test structure, comprising a substrate and an RSM, a current-limiting resistor, and at least one test pad disposed on the substrate. in, The resistive switching memory includes a first electrode, a resistive switching memory layer, and a second electrode sequentially provided on the surface of the substrate in a direction away from the substrate. The current-limiting resistor extends in a strip shape on the surface of the substrate. The first electrode is integrally formed in the same layer as the current-limiting resistor, and is electrically connected to the at least one test pad via the current-limiting resistor; The first electrode and the current-limiting resistor are formed by performing a second etching operation on the exposed first electrode film using a second etching mask pattern, and the current-limiting resistor includes at least a spiral-extended portion and / or a serpentine-extended portion.

2. The resistive switching memory test structure according to claim 1, wherein, In a direction perpendicular to the surface of the substrate, the thickness of the current-limiting resistor is less than the thickness of the first electrode.

3. The resistive switching memory test structure according to claim 2, wherein, The current-limiting resistor is a thin-film resistor with a resistance value in the range of 1kΩ to 200KΩ from the at least one test pad to the resistive switching memory.

4. The resistive switching memory test structure according to claim 3, wherein, The at least one test pad is a plurality of test pads, which are electrically connected to the current-limiting resistor respectively, and have different distances from the resistive switching memory along the strip-shaped extension path of the current-limiting resistor.

5. The resistive switching memory test structure according to claim 4, wherein, The at least one test pad is located on the same layer as the second electrode and is electrically connected to the current-limiting resistor through a via.

6. A method of operating the resistive switching memory test structure according to any one of claims 1-5, comprising: A first voltage is applied to the second electrode, and a second voltage is applied to the first electrode through the current-limiting resistor in one of the at least one test pads to activate the resistive switching memory.

7. The operating method according to claim 6 further includes: Before activating the resistive switching memory, the resistance range of the current-limiting resistor is obtained to select one of the at least one test pad.

8. The operating method according to claim 6 further includes: After activating the resistive random access memory (RRAM), during the setting or resetting operation of the RRAM, the operating voltage is applied to the first and second electrodes of the RRAM, bypassing the current-limiting resistor.

9. A method for fabricating a resistive switching memory test structure according to any one of claims 1-5, comprising: A thin film stack comprising a first electrode thin film, a resistive switching memory thin film, and a second electrode thin film is formed on the substrate in sequence; The thin film stack is patterned using photolithography to form the first electrode, the resistive switching memory layer, the second electrode, and the current-limiting resistor.

10. The preparation method according to claim 9, further comprising: The thin film stack is patterned using photolithography to form the at least one test pad, wherein the at least one test pad is located on the same layer as the second electrode and is electrically connected to the current-limiting resistor through a via.

11. The preparation method according to claim 9, wherein, Patterning the thin film stack using the photolithography method to form the first electrode, the resistive switching memory layer, and the second electrode, as well as forming the current-limiting resistor, includes: A first etching mask pattern is formed on top of the second electrode film using a first photoresist layer; Using the first etching mask pattern, the thin film stack is etched until the first electrode thin film is exposed. The second etching mask pattern is formed on the thin film stack using a second photoresist layer; Using the second etching mask pattern, the exposed first electrode film is subjected to the second etching operation to obtain the first electrode and the current-limiting resistor.

12. The preparation method according to claim 11, wherein, Using the first etching mask pattern, a first etching operation is performed on the thin film stack until the first electrode thin film is exposed, including: The thickness of the exposed first electrode film is controlled within a predetermined range by controlling the etching rate. The remaining thickness of the first electrode film is detected and the parameters for the second etching operation are set.

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