Transient Voltage Suppression Device

Abstract

The present invention discloses a transient voltage suppression device, which includes at least one P-type lightly doped structure and at least one electrostatic discharge structure. The electrostatic discharge structure includes an N-type lightly doped well region, an N-type well region, a first P-type heavily doped region and a first N-type heavily doped region. The N-type lightly doped well region is located in the P-type lightly doped structure, the N-type well region is located in the N-type lightly doped well region, and the doping concentration of the N-type lightly doped well region is less than the doping concentration of the N-type well region. The first P-type heavily doped region is located in the N-type well region, and the first N-type heavily doped region is located in the P-type lightly doped structure.

Description

Technical Field

[0001] The present invention relates to a suppression device, and in particular to a transient voltage suppression device. Background Art

[0002] Electrostatic discharge (ESD) damage has become a major reliability issue for CMOS integrated circuit products using nanometer-scale CMOS processes. Electrostatic discharge protection devices are generally designed to release electrostatic discharge energy, thereby preventing integrated circuit chips from being damaged by ESD.

[0003] The working principle of the electrostatic discharge protection device is as follows Figure 1 As shown. Figure 1 In the embodiment, the ESD protection device 1 is connected in parallel with the protection circuit 2 on the integrated circuit chip. When an ESD event occurs, the ESD protection device 1 will be triggered immediately. In this way, the ESD protection device 1 can provide an extremely low resistance path to release the instantaneous ESD current, so that the energy of the instantaneous ESD current can be released by the ESD protection device 1. Figure 2 This is a cross-sectional view of the structure of a silicon-controlled rectifier in the prior art. Figure 2 The silicon controlled rectifier 3 includes a P-type substrate 30, an N-type well region 31, an N-type heavily doped region 32, a P-type heavily doped region 33, an N-type heavily doped region 34, a P-type heavily doped region 35, a first pin 36 and a second pin 37. The N-type well region 31 is located in the P-type substrate 30, the N-type heavily doped region 32 and the P-type heavily doped region 33 are located in the N-type well region 31, and the N-type heavily doped region 34 and the P-type heavily doped region 35 are located in the P-type substrate 30. The N-type heavily doped region 32 and the P-type heavily doped region 33 are coupled to the first pin 36, and the N-type heavily doped region 34 and the P-type heavily doped region 35 are coupled to the second pin 37. When a positive electrostatic discharge voltage is applied to the first pin 36 and the second pin 37 is grounded, the electrostatic discharge current flows from the first pin 36 to the second pin 37 via the P-type heavily doped region 33, the N-type well region 31, the P-type substrate 30 and the N-type heavily doped region 34. In order to increase the holding voltage of the silicon-controlled rectifier 3, the doping concentration of the N-type well region 31 needs to be increased. However, the high doping concentration of the N-type well region 31 will increase the junction capacitance between the N-type well region 31 and the P-type substrate 30. In addition, the electrostatic discharge current flows along the surface of the P-type substrate 30 to reduce the electrostatic discharge tolerance of the silicon-controlled rectifier 3.

[0004] Therefore, the present invention aims at the above-mentioned problems and proposes a transient voltage suppression device to solve the problems in the prior art. Summary of the invention

[0005] An object of the present invention is to provide a transient voltage suppression device which increases the holding voltage and has a low capacitance.

[0006] In one embodiment of the present invention, a transient voltage suppression device is provided, which includes at least one P-type lightly doped structure and at least one electrostatic discharge structure. The electrostatic discharge structure is arranged in the P-type lightly doped structure. The electrostatic discharge structure includes an N-type lightly doped well region, an N-type well region, a first P-type heavily doped region and a first N-type heavily doped region. The N-type lightly doped well region is arranged in the P-type lightly doped structure, and the N-type well region is arranged in the N-type lightly doped well region, wherein the doping concentration of the N-type lightly doped well region is less than the doping concentration of the N-type well region. The first P-type heavily doped region is arranged in the N-type well region, and the first N-type heavily doped region is arranged in the P-type lightly doped structure.

[0007] In an embodiment of the present invention, the first P-type heavily doped region and the N-type lightly doped well region are coupled to a first pin, and the first N-type heavily doped region and the P-type lightly doped structure are coupled to a second pin.

[0008] In one embodiment of the present invention, the electrostatic discharge structure further includes a second N-type heavily doped region and a second P-type heavily doped region. The second N-type heavily doped region is disposed in the N-type lightly doped well region, wherein the first P-type heavily doped region is located between the second N-type heavily doped region and the first N-type heavily doped region, and the N-type lightly doped well region is coupled to the first pin via the second N-type heavily doped region. The second P-type heavily doped region is disposed in the P-type lightly doped structure, wherein the P-type lightly doped structure is coupled to the second pin via the second P-type heavily doped region.

[0009] In one embodiment of the present invention, the electrostatic discharge structure further includes a third N-type heavily doped region, which is disposed in the N-type lightly doped well region and located between the first P-type heavily doped region and the first N-type heavily doped region, wherein the third N-type heavily doped region is electrically floating.

[0010] In one embodiment of the present invention, the electrostatic discharge structure also includes a P-type well region, which is arranged in the P-type lightly doped structure, wherein the doping concentration of the P-type well region is greater than the doping concentration of the P-type lightly doped structure, the first N-type heavily doped region and the second P-type heavily doped region are arranged in the P-type well region, and the P-type lightly doped structure is coupled to the second pin with the P-type well region via the second P-type heavily doped region.

[0011] In one embodiment of the present invention, the second N-type heavily doped region surrounds the N-type well region and the first P-type heavily doped region.

[0012] In one embodiment of the present invention, at least one electrostatic discharge structure also includes two electrostatic discharge structures, the first N-type heavily doped regions of all the electrostatic discharge structures are coupled to each other through a conductive line, the first P-type heavily doped region of one of all the electrostatic discharge structures is coupled to the N-type lightly doped well region by a first pin, and the first P-type heavily doped region of another of all the electrostatic discharge structures is coupled to the N-type lightly doped well region by a second pin.

[0013] In one embodiment of the present invention, at least one electrostatic discharge structure also includes two electrostatic discharge structures, at least one P-type lightly doped structure includes two P-type lightly doped structures, the first N-type heavily doped region of all electrostatic discharge structures and all P-type lightly doped structures are coupled to each other through a conductive line, the first P-type heavily doped region of one of all electrostatic discharge structures is coupled to the N-type lightly doped well region with a first pin, and the first P-type heavily doped region of another of all electrostatic discharge structures is coupled to the N-type lightly doped well region with a second pin.

[0014] In one embodiment of the present invention, the P-type lightly doped structure is a P-type lightly doped substrate.

[0015] In one embodiment of the present invention, the P-type lightly doped structure is a P-type lightly doped epitaxial layer, and the P-type lightly doped epitaxial layer is disposed on an N-type lightly doped substrate.

[0016] Based on the above, the transient voltage suppression device forms an N-type well region between the N-type lightly doped well region and the first P-type heavily doped region, thereby increasing the holding voltage and having a low capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of an electrostatic discharge protection device connected to a circuit to be protected on an integrated circuit chip in the prior art.

[0018] Figure 2 The figure is a structural cross-sectional view of a silicon-controlled rectifier in the prior art.

[0019] Figure 3 It is a structural cross-sectional view of the first embodiment of the transient voltage suppression device of the present invention.

[0020] Figure 4 It is a structural cross-sectional view of a second embodiment of the transient voltage suppression device of the present invention.

[0021] Figure 5 It is a structural cross-sectional view of a third embodiment of the transient voltage suppression device of the present invention.

[0022] Figure 6 Graphs showing current and voltage of transient voltage suppression devices according to the first, second and third embodiments of the present invention.

[0023] Figure 7 It is a structural cross-sectional view of a fourth embodiment of the transient voltage suppression device of the present invention.

[0024] Figure 8 It is a structural cross-sectional view of a fifth embodiment of the transient voltage suppression device of the present invention.

[0025] Fig. 9 It is a structural cross-sectional view of a sixth embodiment of the transient voltage suppression device of the present invention.

[0026] Fig.10 FIG. 4 is a structural cross-sectional view of a seventh embodiment of a transient voltage suppression device according to the present invention.

[0027] Explanation of the accompanying drawings: 3-silicon controlled rectifier; 30-P-type substrate; 31-N-type well region; 32-N-type heavily doped region; 33-P-type heavily doped region; 34-N-type heavily doped region; 35-P-type heavily doped region; 36-first pin; 37-second pin; 4-transient voltage suppression device; 40-P-type lightly doped structure; 41-N-type lightly doped well region; 42-N-type well region; 43-first P-type heavily doped region; 44-first N-type heavily doped region; 45-first pin; 46-second pin; 47-second N-type heavily doped region; 48-second P-type heavily doped region; 49-third N-type heavily doped region; 50-P-type well region; S-electrostatic discharge structure; Vop-operating voltage; W-conductive wire. DETAILED DESCRIPTION

[0028] The embodiments of the present invention will be further explained below with the help of the relevant drawings. As much as possible, the same reference numerals represent the same or similar components in the drawings and the specification. In the drawings, the shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that the components not specifically shown in the drawings or described in the specification are in the form known to those skilled in the art. Those skilled in the art may make various changes and modifications based on the contents of the present invention.

[0029] Unless otherwise specified, some conditional sentences or words, such as "can", "could", "might", or "may", are generally intended to express that the embodiment of the case has, but can also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may not be required.

[0030] The description of "one embodiment" or "an embodiment" in the following text refers to a specific element, structure or feature associated with at least one embodiment. Therefore, multiple descriptions of "one embodiment" or "an embodiment" appearing in multiple places in the following text do not refer to the same embodiment. Furthermore, specific components, structures and features in one or more embodiments may be combined in an appropriate manner.

[0031] Certain words are used in the specification and claims to refer to specific components. However, those with ordinary knowledge in the technical field should understand that the same component may be referred to by different nouns. The specification and claims do not use differences in names as a way to distinguish components, but use differences in the functions of the components as a basis for distinction. The "including" mentioned in the specification and claims is an open-ended term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or indirectly electrically or signal connected to the second element through other elements or connection means.

[0032] The present invention is particularly described by the following examples, which are only used for illustration, because for those skilled in the art, various changes and modifications can be made without departing from the spirit and scope of the present disclosure, so the protection scope of the present invention should be determined by the claims. Throughout the specification and claims, unless the content clearly specifies, the meaning of "one" and "the" includes this type of description including "one or at least one" described elements or components. In addition, as used in the present invention, unless it is obvious from the specific context that the plurality is excluded, the singular article also includes the description of plural elements or components. Moreover, when applied in this description and all claims, unless the content clearly specifies, the meaning of "in which" may include "in which" and "on it". The terms used in the specification and claims, unless otherwise specified, generally have the ordinary meaning of each term used in this field, in the content of this invention and in the special content. Certain terms used to describe the present invention will be discussed below or elsewhere in this specification to provide practitioners with additional guidance in describing the present invention. The use of examples anywhere throughout the specification, including examples of any term discussed herein, is for illustrative purposes only and certainly does not limit the scope and meaning of the present invention or any exemplified term. Likewise, the present invention is not limited to the various embodiments set forth in this specification.

[0033] In the following description, a transient voltage suppression device is provided, which forms an N-type well region between an N-type lightly doped well region and a first P-type heavily doped region, thereby increasing a holding voltage and having a low capacitance.

[0034] Figure 3 FIG. 1 is a cross-sectional view of the structure of the first embodiment of the transient voltage suppression device of the present invention. Figure 3, the first embodiment of the transient voltage suppression device 4 is introduced below. The transient voltage suppression device 4 includes at least one P-type lightly doped structure 40 and at least one electrostatic discharge structure S. For convenience and clarity, the first embodiment takes a P-type lightly doped structure 40 and an electrostatic discharge structure S as an example. The electrostatic discharge structure S is arranged in the P-type lightly doped structure 40. The electrostatic discharge structure S includes an N-type lightly doped well region 41, an N-type well region 42, a first P-type heavily doped region 43, a first N-type heavily doped region 44, a first pin 45 and a second pin 46. In the first embodiment, the P-type lightly doped structure 40 takes a P-type lightly doped substrate as an example. The N-type lightly doped well region 41 is arranged in the P-type lightly doped structure 40, and the N-type well region 42 is arranged in the N-type lightly doped well region 41. The doping concentration of the N-type lightly doped well region 41 is less than the doping concentration of the N-type well region 42. The first P-type heavily doped region 43 is disposed in the N-type well region 42, and the first N-type heavily doped region 44 is disposed in the P-type lightly doped structure 40. The first P-type heavily doped region 43 and the N-type lightly doped well region 41 can be coupled to the first pin 45. The first N-type heavily doped region 44 and the P-type lightly doped structure 40 can be coupled to the second pin 46.

[0035] In some embodiments, the electrostatic discharge structure S may further include a second N-type heavily doped region 47 and a second P-type heavily doped region 48. The doping concentration of the second N-type heavily doped region 47 is higher than the doping concentration of the N-type well region 42. The second N-type heavily doped region 47 is disposed in the N-type lightly doped well region 41, and the first P-type heavily doped region 43 is located between the second N-type heavily doped region 47 and the first N-type heavily doped region 44. The N-type lightly doped well region 41 is coupled to the first pin 45 through the second N-type heavily doped region 47, and the second P-type heavily doped region 48 is disposed in the P-type lightly doped structure 40. The P-type lightly doped structure 40 is coupled to the second pin 46 through the second P-type heavily doped region 48.

[0036] When a positive electrostatic discharge voltage is applied to the first pin 45 and the second pin 46 is grounded, the electrostatic discharge current flows from the first pin 45 to the second pin 46 through the first P-type heavily doped region 43, the N-type well region 42, the N-type lightly doped well region 41, the P-type lightly doped structure 40 and the first N-type heavily doped region 44. In this example, the transient voltage suppression device 4 can be used as a silicon-controlled rectifier. In order to have low capacitance, the transient voltage suppression device 4 needs to have a low junction capacitance between the N-type lightly doped well region 41 and the P-type lightly doped structure 40. The first P-type heavily doped region 43, the N-type well region 42, the N-type lightly doped well region 41 and the P-type lightly doped structure 40 form a PNP bipolar junction transistor. Because of the presence of the N-type well region 42, by increasing or changing the doping concentration of the N-type well region 42, the current gain of the PNP bipolar junction transistor will be reduced to increase the holding voltage of the transient voltage suppression device 4. And because the junction between the N-type lightly doped well region 41 and the P-type lightly doped structure 40 is not changed, the characteristic of low junction capacitance can still be maintained. When a positive electrostatic discharge voltage is applied to the second pin 46 and the first pin 45 is grounded, the electrostatic discharge current flows from the second pin 46 through the second P-type heavily doped region 48, the P-type lightly doped structure 40, the N-type lightly doped well region 41 and the second N-type heavily doped region 47. In this example, the transient voltage suppression device 4 can be used as a diode.

[0037] Figure 4 2 is a cross-sectional view of the structure of the second embodiment of the transient voltage suppression device of the present invention. Figure 4 , the second embodiment of the transient voltage suppression device 4 is introduced below. Compared with the first embodiment, the electrostatic discharge structure S of the second embodiment further includes a third N-type heavily doped region 49, which is disposed in the N-type lightly doped well region 41 and located between the first P-type heavily doped region 43 and the first N-type heavily doped region 44, wherein the third N-type heavily doped region 49 is electrically floating, and the remaining features have been disclosed in the first embodiment and will not be repeated here.

[0038] In some embodiments, the first P-type heavily doped region 43, the N-type well region 42, the third N-type heavily doped region 49, the N-type lightly doped well region 41 and the P-type lightly doped structure 40 form a horizontal PNP bipolar junction transistor. Since the third N-type heavily doped region 49 is electrically floating and has a higher doping concentration than the N-type lightly doped well region 41, the current gain of the horizontal PNP bipolar junction transistor is smaller than the current gain of the vertical PNP bipolar junction transistor formed by the first P-type heavily doped region 43, the N-type well region 42, the N-type lightly doped well region 41 and the P-type lightly doped structure 40. Therefore, when a positive electrostatic discharge voltage is applied to the first pin 45 and the second pin 46 is grounded, the holding voltage of the second embodiment is higher than the holding voltage of the first embodiment. Because the current gain of the horizontal PNP BJT is suppressed, when a positive ESD voltage is applied to the first pin 45 and the second pin 46 is grounded, most of the ESD current will pass through the deeper vertical PNP BJT to enhance the ESD tolerance of the TVS device 4.

[0039] When a positive electrostatic discharge voltage is applied to the second pin 46 and the first pin 45 is grounded, the electrostatic discharge current flows from the second pin 46 to the first pin 45 through the second P-type heavily doped region 48, the P-type lightly doped structure 40, the N-type lightly doped well region 41, the third N-type heavily doped region 49, the N-type well region 42 and the second N-type heavily doped region 47. The first path through the second P-type heavily doped region 48, the P-type lightly doped structure 40, the N-type lightly doped well region 41 and the second N-type heavily doped region 47 is away from the surface of the P-type lightly doped structure 40. The second path through the second P-type heavily doped region 48, the P-type lightly doped structure 40, the N-type lightly doped well region 41, the third N-type heavily doped region 49, the N-type well region 42 and the second N-type heavily doped region 47 is close to the surface of the P-type lightly doped structure 40. Therefore, the second path is shorter than the first path, and the on-resistance of the second path is smaller than the on-resistance of the first path, so that the on-resistance of the overall diode on the electrostatic discharge path can be reduced.

[0040] Figure 5 FIG. 1 is a cross-sectional view of the structure of the third embodiment of the transient voltage suppression device of the present invention. Figure 5 The third embodiment of the transient voltage suppression device 4 is introduced below. Compared with the first embodiment, the second N-type heavily doped region 47 of the third embodiment surrounds the N-type well region 42 and the first P-type heavily doped region 43, and the remaining features have been disclosed in the first embodiment and will not be repeated here.

[0041] In the third embodiment, the first P-type heavily doped region 43, the N-type well region 42, the second N-type heavily doped region 47, the N-type lightly doped well region 41 and the P-type lightly doped structure 40 form a horizontal PNP bipolar junction transistor. Since the second N-type heavily doped region 47 is forward biased, when a positive electrostatic discharge voltage is applied to the first pin 45 and the second pin 46 is grounded, the current gain of the horizontal PNP bipolar junction transistor will be smaller than the current gain of the vertical PNP bipolar junction transistor. Therefore, when a positive electrostatic discharge voltage is applied to the first pin 45 and the second pin 46 is grounded, the holding voltage of the third embodiment will be greater than the holding voltage of the second embodiment. Because the current gain of the horizontal PNP bipolar junction transistor is suppressed, when a positive electrostatic discharge voltage is applied to the first pin 45 and the second pin 46 is grounded, most of the electrostatic discharge current will pass through the deeper vertical PNP bipolar junction transistor to enhance the electrostatic discharge tolerance of the transient voltage suppression device 4.

[0042] When a positive electrostatic discharge voltage is applied to the second pin 46 and the first pin 45 is grounded, the electrostatic discharge current flows from the second pin 46 to the first pin 45 through the second P-type heavily doped region 48, the P-type lightly doped structure 40, the N-type lightly doped well region 41, the second N-type heavily doped region 47, the N-type well region 42 and the second N-type heavily doped region 47. The first path through the second P-type heavily doped region 48, the P-type lightly doped structure 40, the N-type lightly doped well region 41 and the second N-type heavily doped region 47 is away from the surface of the P-type lightly doped structure 40. The second path through the second P-type heavily doped region 48, the P-type lightly doped structure 40, the N-type lightly doped well region 41, the second N-type heavily doped region 47, the N-type well region 42 and the second N-type heavily doped region 47 is close to the surface of the P-type lightly doped structure 40. Therefore, the second path is shorter than the first path, and the on-resistance of the second path is smaller than the on-resistance of the first path, so that the on-resistance of the overall diode on the electrostatic discharge path can be reduced.

[0043] Figure 6 The current and voltage curves of the transient voltage suppression device of the first, second and third embodiments of the present invention are shown in FIG. Figure 6 , which is a current and voltage curve diagram of the silicon-controlled rectifier of the prior art, the first, second and third embodiments. Figure 6 As shown, the holding voltage of the silicon-controlled rectifier of the prior art is lower than the operating voltage Vop of the circuit to be protected. On the contrary, the holding voltages of the silicon-controlled rectifiers of the first, second and third embodiments are higher than the operating voltage Vop of the circuit to be protected. In addition, the holding voltage of the silicon-controlled rectifier of the third embodiment is higher than the holding voltage of the silicon-controlled rectifier of the second embodiment. The holding voltage of the silicon-controlled rectifier of the second embodiment is higher than the holding voltage of the silicon-controlled rectifier of the first embodiment.

[0044] Figure 7FIG. 4 is a cross-sectional view of the structure of the fourth embodiment of the transient voltage suppression device of the present invention. Figure 7 , the fourth embodiment of the transient voltage suppression device 4 is introduced below. Compared with the second embodiment, the electrostatic discharge structure S of the fourth embodiment further includes a P-type well region 50, which is disposed in the P-type lightly doped structure 40. The doping concentration of the P-type well region 50 is greater than the doping concentration of the P-type lightly doped structure 40, and the first N-type heavily doped region 44 and the second P-type heavily doped region 48 are disposed in the P-type well region 50. The P-type lightly doped structure 40 is coupled to the second pin 46 with the P-type well region 50 through the second P-type heavily doped region 48, and the remaining features have been disclosed in the second embodiment and will not be repeated here.

[0045] In the fourth embodiment, the N-type well region 42, the third N-type heavily doped region 49, the N-type lightly doped well region 41, the P-type lightly doped structure 40, the P-type well region 50 and the first N-type heavily doped region 44 form a horizontal NPN bipolar junction transistor. Since the doping concentration of the P-type well region 50 is higher than the doping concentration of the P-type lightly doped structure 40, the current gain of the horizontal NPN bipolar junction transistor is suppressed. Therefore, when a positive electrostatic discharge voltage is applied to the first pin 45 and the second pin 46 is grounded, the holding voltage of the fourth embodiment is higher than the holding voltage of the second embodiment. Because the current gain of the horizontal NPN bipolar junction transistor is suppressed, when a positive electrostatic discharge voltage is applied to the first pin 45 and the second pin 46 is grounded, most of the electrostatic discharge current will pass through the deeper vertical PNP bipolar junction transistor to enhance the electrostatic discharge tolerance of the transient voltage suppression device 4.

[0046] When a positive electrostatic discharge voltage is applied to the second pin 46 and the first pin 45 is grounded, the electrostatic discharge current flows from the second pin 46 to the first pin 45 through the second P-type heavily doped region 48, the P-type well region 50, the P-type lightly doped structure 40, the N-type lightly doped well region 41, the third N-type heavily doped region 49, the N-type well region 42 and the second N-type heavily doped region 47.

[0047] The P-type well region 50 may also be used for Figure 3 , Figure 4 and Figure 5 When the P-type well region 50 is applied to Figure 3 , Figure 4 and Figure 5 When the structure is configured as shown in FIG. 1 , the P-type well region 50 is disposed in the P-type lightly doped structure 40 . In addition, the doping concentration of the P-type well region 50 is higher than the doping concentration of the P-type lightly doped structure 40 . The first N-type heavily doped region 44 and the second P-type heavily doped region 48 are disposed in the P-type well region 50 .

[0048] In order to form a bidirectional transient voltage suppression device with a high holding voltage, the fifth embodiment and the sixth embodiment of the present invention are described below.

[0049] Figure 8 FIG. 5 is a cross-sectional view of the structure of the fifth embodiment of the transient voltage suppression device of the present invention. Figure 8 The difference between the fifth embodiment and the first embodiment is that the fifth embodiment forms two electrostatic discharge structures S. In addition, the first N-type heavily doped region 44 and the second P-type heavily doped region 48 of the electrostatic discharge structure S are coupled to each other through a conductive line W. The first P-type heavily doped region 43, the N-type lightly doped well region 41 and the second N-type heavily doped region 47 of one of the electrostatic discharge structures S are coupled to the first pin 45, and the first P-type heavily doped region 43, the N-type lightly doped well region 41 and the second N-type heavily doped region 47 of one of the electrostatic discharge structures S are coupled to the second pin 46.

[0050] When a positive electrostatic discharge voltage is applied to the first pin 45 and the second pin 46 is grounded, the electrostatic discharge current flows from the first pin 45 to the second pin 46 through the first P-type heavily doped region 43, the N-type well region 42, the N-type lightly doped well region 41, the P-type lightly doped structure 40, the first N-type heavily doped region 44, the conductive line W, the second P-type heavily doped region 48, the P-type lightly doped structure 40, the N-type lightly doped well region 41, the N-type well region 42, and the second N-type heavily doped region 47. When a positive electrostatic discharge voltage is applied to the second pin 46 and the first pin 45 is grounded, the electrostatic discharge current flows from the second pin 46 to the second pin 46 through the first P-type heavily doped region 43, the N-type well region 42, the N-type lightly doped well region 41, the P-type lightly doped structure 40, the first N-type heavily doped region 44, the conductive line W, the second P-type heavily doped region 48, the P-type lightly doped structure 40, the N-type lightly doped well region 41, the N-type well region 42, and the second N-type heavily doped region 47.

[0051] Fig. 9 FIG. 6 is a cross-sectional view of the structure of the sixth embodiment of the transient voltage suppression device of the present invention. Fig. 9 The difference between the sixth embodiment and the first embodiment is that the sixth embodiment forms two electrostatic discharge structures S and two P-type lightly doped structures 40. In addition, the first N-type heavily doped region 44 of the electrostatic discharge structure S is coupled to the second P-type heavily doped region 48 and the P-type lightly doped structure 40 through a conductive line W. The first P-type heavily doped region 43, the N-type lightly doped well region 41 and the second N-type heavily doped region 47 of one of the electrostatic discharge structures S are coupled to the first pin 45, and the first P-type heavily doped region 43, the N-type lightly doped well region 41 and the second N-type heavily doped region 47 of one of the electrostatic discharge structures S are coupled to the second pin 46.

[0052] When a positive electrostatic discharge voltage is applied to the first pin 45 and the second pin 46 is grounded, the electrostatic discharge current flows from the first pin 45 to the second pin 46 through the first P-type heavily doped region 43, the N-type well region 42, the N-type lightly doped well region 41, the P-type lightly doped structure 40, the first N-type heavily doped region 44, the conductive line W, the second P-type heavily doped region 48, the P-type lightly doped structure 40, the N-type lightly doped well region 41, the N-type well region 42, and the second N-type heavily doped region 47. When a positive electrostatic discharge voltage is applied to the second pin 46 and the first pin 45 is grounded, the electrostatic discharge current flows from the second pin 46 to the second pin 46 through the first P-type heavily doped region 43, the N-type well region 42, the N-type lightly doped well region 41, the P-type lightly doped structure 40, the first N-type heavily doped region 44, the conductive line W, the second P-type heavily doped region 48, the P-type lightly doped structure 40, the N-type lightly doped well region 41, the N-type well region 42, and the second N-type heavily doped region 47.

[0053] Fig.10 FIG. 1 is a cross-sectional view of the structure of the seventh embodiment of the transient voltage suppression device of the present invention. Fig.10 , the seventh embodiment is introduced below. The seventh embodiment differs from the first embodiment in the P-type lightly doped structure 40. In the seventh embodiment, the P-type lightly doped structure 40 is a P-type lightly doped epitaxial layer, and the P-type lightly doped epitaxial layer is disposed on an N-type lightly doped substrate 51. The remaining features have been disclosed in the first embodiment and will not be repeated here.

[0054] Figure 7 The P-type well region 50 in the Figure 8 , Fig. 9 and Fig.10 When the P-type well region 50 is applied to Figure 8 , Fig. 9 and Fig.10 When the structure is constructed on the P-type well region 50, the P-type well region 50 is disposed in each P-type lightly doped structure 40. In addition, the doping concentration of the P-type well region 50 is higher than the doping concentration of the P-type lightly doped structure 40, and the first N-type heavily doped region 44 and the second P-type heavily doped region 48 are disposed in the P-type well region 50.

[0055] According to the above embodiment, the transient voltage suppression device forms an N-type well region between the N-type lightly doped well region and the first P-type heavily doped region, thereby increasing the holding voltage and having a low capacitance.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of implementation of the present invention. Therefore, all equivalent changes and modifications made according to the shape, structure, characteristics and spirit described in the claims of this invention should be included in the protection scope of the present invention.

Claims

1. A transient voltage suppression device, characterized in that: include: at least one P-type lightly doped structure; as well as At least one electrostatic discharge structure is provided in the at least one P-type lightly doped structure, wherein the at least one electrostatic discharge structure comprises: An N-type lightly doped well region, disposed in the at least one P-type lightly doped structure; An N-type well region, disposed in the N-type lightly doped well region, wherein the doping concentration of the N-type lightly doped well region is less than the doping concentration of the N-type well region; a first P-type heavily doped region, disposed in the N-type well region; and A first N-type heavily doped region is disposed in the at least one P-type lightly doped structure.

2. The transient voltage suppression device according to claim 1, characterized in that: The first P-type heavily doped region and the N-type lightly doped well region are coupled to a first pin, and the first N-type heavily doped region and the at least one P-type lightly doped structure are coupled to a second pin.

3. The transient voltage suppression device according to claim 2, characterized in that: The at least one electrostatic discharge structure further comprises: a second N-type heavily doped region, disposed in the N-type lightly doped well region, wherein the first P-type heavily doped region is located between the second N-type heavily doped region and the first N-type heavily doped region, and the N-type lightly doped well region is coupled to the first pin via the second N-type heavily doped region; and A second P-type heavily doped region is disposed in the at least one P-type lightly doped structure, wherein the at least one P-type lightly doped structure is coupled to the second pin through the second P-type heavily doped region.

4. The transient voltage suppression device according to claim 3, characterized in that: The at least one electrostatic discharge structure further includes a third N-type heavily doped region, which is disposed in the N-type lightly doped well region and located between the first P-type heavily doped region and the first N-type heavily doped region, wherein the third N-type heavily doped region is electrically floating.

5. The transient voltage suppression device according to claim 4, characterized in that: The at least one electrostatic discharge structure also includes a P-type well region, which is arranged in the at least one P-type lightly doped structure, wherein the doping concentration of the P-type well region is greater than the doping concentration of the at least one P-type lightly doped structure, the first N-type heavily doped region and the second P-type heavily doped region are arranged in the P-type well region, and the at least one P-type lightly doped structure is coupled to the second pin with the P-type well region via the second P-type heavily doped region.

6. The transient voltage suppression device according to claim 3, characterized in that: The second N-type heavily doped region surrounds the N-type well region and the first P-type heavily doped region.

7. The transient voltage suppression device according to claim 1, characterized in that: The at least one electrostatic discharge structure also includes two electrostatic discharge structures, the first N-type heavily doped regions of the two electrostatic discharge structures are coupled to each other through a conductive line, the first P-type heavily doped region of one of the two electrostatic discharge structures is coupled to the N-type lightly doped well region by a first pin, and the first P-type heavily doped region of the other of the two electrostatic discharge structures is coupled to the N-type lightly doped well region by a second pin.

8. The transient voltage suppression device according to claim 1, characterized in that: The at least one electrostatic discharge structure also includes two electrostatic discharge structures, and the at least one P-type lightly doped structure includes two P-type lightly doped structures. The first N-type heavily doped regions of the two electrostatic discharge structures and the two P-type lightly doped structures are coupled to each other through a conductive line, and the first P-type heavily doped region of one of the two electrostatic discharge structures is coupled to the N-type lightly doped well region by a first pin, and the first P-type heavily doped region of the other of the two electrostatic discharge structures is coupled to the N-type lightly doped well region by a second pin.

9. The transient voltage suppression device according to claim 1, characterized in that: The at least one P-type lightly doped structure is a P-type lightly doped substrate.

10. The transient voltage suppression device according to claim 1, characterized in that: The at least one P-type lightly doped structure is a P-type lightly doped epitaxial layer, and the P-type lightly doped epitaxial layer is disposed on an N-type lightly doped substrate.

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