Integrated assembly and method of forming an integrated assembly

Abstract

This application relates to integrated assemblies and methods of forming integrated assemblies. Some embodiments include an integrated assembly having first and second source / drain regions laterally offset from one another. A metal silicide is adjacent to lateral surfaces of the source / drain regions. A metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source / drain regions via the metal silicide and the metal. A capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes and into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

Description

Technical Field

[0001] Integrated assemblies (e.g., integrated memory). Methods for forming integrated assemblies. Background Technology

[0002] The integrated assembly may include memory. An example memory configuration 1200 is shown in Figure 1. A transistor (access device) 1206 includes horizontally extending segments of semiconductor material 1204, wherein these segments include source / drain regions 1238 and 1240 and a channel region 1242. A capacitor 1208 is coupled to the transistor 1206 via conductive interconnects 1244. In some applications, the conductive interconnects may be considered as part of the capacitor and, for example, as part of the storage node of these capacitors.

[0003] Memory cell 1210 includes transistor 1206 and capacitor 1208. The memory cells are arranged within a memory configuration (memory array) 1200, wherein this array has rows 1224 extending along the illustrated z-axis and columns 1246 extending along the illustrated x-axis. Digital lines 1212 extend along column 1246 and are coupled to the source / drain regions 1238 of transistor 1206. Word lines 1214 extend along row 1224 of the memory array and are adjacent to the channel region 1242 of transistor 1206. In the illustrated embodiment, each word line includes two segments located on opposite sides of the channel region 1242. In other embodiments, word lines may include other suitable configurations and may, for example, include a single component only on one side of the channel region, or may include a full-around-gate configuration, etc.

[0004] Word line 1214 is typically spaced from channel region 1242 by a gate dielectric material (e.g., silicon dioxide), but this gate dielectric material is not shown in FIG1 for the sake of simplification.

[0005] The body region (channel region) 1242 of transistor 1206 is coupled to a conductive plate 1248. This plate can be used to allow excess carriers (e.g., holes) to drain from the body region 1242 during some operating modes of memory cell 1210.

[0006] Figure 2 shows a cross-sectional side view of the assembly 1200 of Figure 1 along the y-axis, and illustrates some of the structures described above with reference to Figure 1. Transistor 1206 is shown extending horizontally along the y-axis. Word line 1214 is shown extending vertically along the z-axis, and digital line 1212 is shown extending horizontally into and out of the page relative to the cross-sectional view of Figure 2. Conductive plate 1248 (Figure 1) is not shown in Figure 2 for simplicity.

[0007] The capacitors 1208 of the laterally adjacent memory cells 1210 are shown as sharing the plate electrode 1250 in the memory configuration 1200 of FIG2.

[0008] Substrate 1216 supports components of memory configuration 1200. This substrate may include semiconductor materials; and may include, for example, monocrystalline silicon, substantially composed of monocrystalline silicon, or composed of monocrystalline silicon. Substrate 1216 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction including semiconducting materials, comprising (but not limited to) bulk semiconducting materials, such as a semiconducting wafer (alone or in a combination of other materials), and a layer of semiconducting materials (alone or in a combination of other materials). The term "substrate" refers to any support structure comprising (but not limited to) the semiconductor substrate described above. In some applications, substrate 1216 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. These materials may comprise one or more of, for example, refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0009] Figure 3 illustrates another example of a memory configuration 1300. A transistor (access device) 1306 includes horizontally extending segments of semiconductor material 1304, wherein these segments include source / drain regions 1338 and 1340, and a channel region 1342. A capacitor 1308 is coupled to the transistor 1306 via a conductive interconnect 1344. In some applications, the conductive interconnect may be considered as part of the capacitor, and may be considered, for example, as part of a storage node of such capacitors.

[0010] Memory cell 1310 includes transistor 1306 and capacitor 1308. The memory cell is arranged within a memory configuration (memory array) 1300. Digital line 1312 extends along a column of the memory array and is coupled to the source / drain region 1338 of transistor 1306. The digital line extends vertically along the z-axis.

[0011] Word line 1314 extends along the rows of the memory array and is adjacent to the channel region 1342 of transistor 1306. Word line 1314 is spaced apart from channel region 1342 by gate dielectric material 1305.

[0012] The body region (channel region) 1342 of transistor 1306 is coupled to a conductive plate 1348. This plate can be used to allow excess carriers (e.g., holes) to drain from the body region 1342 during some operating modes of memory cell 1310.

[0013] Figure 4 shows a cross-sectional side view of assembly 1300 of Figure 3 along the x-axis, and illustrates some of the structures described above with reference to Figure 3. Transistor 1306 is shown extending horizontally along the x-axis. Digital line 1312 is shown extending vertically along the z-axis, and word line 1314 is shown extending horizontally into and out of the page relative to the cross-sectional view of Figure 4.

[0014] The capacitors 1308 of the horizontally adjacent memory cells 1310 are shown as sharing a plate electrode 1350.

[0015] The components shown in memory configuration 1300 are supported by substrate 1316. This substrate may be a semiconductor substrate.

[0016] The memory illustrated in Figure 1-4 utilizes laterally extended capacitors coupled to the source / drain regions of the access device. Achieving high-conductivity coupling between the laterally extended capacitors and the source / drain regions of the access device can be challenging. Therefore, a novel architecture with good electrical coupling between the source / drain regions and the laterally extended capacitors is needed, along with methods for forming this new architecture. Summary of the Invention

[0017] Describing an integrated assembly. The integrated assembly may include: a first source / drain region, and a second source / drain laterally offset relative to the first source / drain region, wherein the first and second source / drain regions comprise conductive doped silicon; a metal silicide material adjacent to the lateral surfaces of the first and second source / drain regions; a metal-containing region adjacent to the metal silicide material, wherein one of the metal-containing regions is a first metal-containing region and associated with the first source / drain region, and the other of the metal-containing regions is a second metal-containing region and associated with the second source / drain region; a laterally extending container-shaped first capacitor electrode coupled to the first metal-containing region, wherein the container shape of the first capacitor electrode opens along a first lateral direction; and a laterally extending container-shaped second capacitor electrode coupled to... The second metal-containing region is coupled, wherein the container shape of the second capacitor electrode opens along a second lateral direction opposite to the first lateral direction; a capacitor dielectric material is used to line the inner surfaces of the container-shaped first and second capacitor electrodes; and a shared capacitor electrode extends vertically between the first and second capacitor electrodes and extends into the lined first and second capacitor electrodes; the shared capacitor electrode, the capacitor dielectric material, and the first capacitor electrode are incorporated together into a first laterally extending capacitor; and the shared capacitor electrode, the capacitor dielectric material, and the second capacitor electrode are incorporated together into a second laterally extending capacitor, wherein the second laterally extending capacitor is laterally offset relative to the first laterally extending capacitor.

[0018] An integrated assembly is described. The integrated assembly may include: pillars of stacked shared capacitor electrode material extending vertically through alternating first and second levels. The first level is a capacitor-containing level comprising paired, laterally extending capacitors, each pair of said paired capacitors comprising a first capacitor and a second capacitor, wherein the second capacitor is substantially a mirror image of the first capacitor in a plane extending vertically through the center of the pillar of the shared electrode material. The capacitor includes a container-shaped electrode coupled to a source / drain region associated with an access device. The coupling to the source / drain regions occurs through conductive bridges comprising metal-containing regions and metal silicide-containing regions. The metal-containing regions directly abut the container-shaped electrode, and the metal silicide-containing regions directly abut the source / drain regions. The second level is an insulating level comprising one or more insulating materials.

[0019] A method is described. The method of forming an integrated assembly may include: forming an alternating stack of first and second levels; the first level comprising a semiconductor material and the second level comprising an insulating material; forming an opening extending through the stack; recessing the semiconductor material of the first level to form a laterally extending cavity near the opening; the remaining region of the semiconductor material defining a lateral perimeter of the cavity away from the opening; doping the semiconductor material along the lateral perimeter of the cavity; combining a metal along the lateral perimeter of the cavity with an exposed portion of the semiconductor material to form a first metal-containing composition along the lateral perimeter; forming a second metal-containing composition along the first metal-containing composition; the first and second metal-containing compositions together forming a conductive bridge; lining the cavity with a first capacitor electrode material; a region of the first capacitor electrode material directly abutting the conductive bridge; forming a capacitor dielectric material within the lined cavity to narrow the cavity; and forming a second capacitor electrode material within the narrowed cavity to fill the cavity; pillars of the second capacitor electrode material formed within the opening and engaging with the second capacitor electrode material within the cavity. Attached Figure Description

[0020] Figure 1 is a schematic three-dimensional view of the area of ​​a prior art integrated assembly.

[0021] Figure 2 is a schematic cross-sectional side view of a region of a prior art assembly similar to that in Figure 1.

[0022] Figure 3 is a schematic three-dimensional view of the area of ​​the prior art integrated assembly.

[0023] Figure 4 is a schematic cross-sectional side view of a region of a prior art assembly similar to that in Figure 3.

[0024] Figure 5-15It is a schematic cross-sectional side view of the instance area of ​​the instance integrated assembly at the instance process stage of the instance method. Detailed Implementation

[0025] Some embodiments include a metal / metal silicide conductive bridge providing a laterally extended capacitor between the capacitor electrodes and the source / drain regions of an access device (e.g., an access transistor) to achieve a highly conductive connection between the source / drain regions and the capacitor electrodes. A memory cell may include an access device and a capacitor. The memory cell may be, for example, a dynamic random access memory (DRAM) cell and may be utilized in a highly integrated memory array. Reference Figure 5-15 Describe an example implementation.

[0026] See Figure 5 The integrated assembly 10 includes a substrate 12 and a material 14 above the substrate. The substrate 12 may include a semiconductor material and may include, for example, monocrystalline silicon, be substantially composed of monocrystalline silicon, or be composed of monocrystalline silicon. The substrate 12 may be referred to as a semiconductor substrate.

[0027] Material 14 may be an insulating etch-stopping material and may include any suitable composition. In some embodiments, material 14 may include a metal oxide. In some embodiments, material 14 may include ZrO. x Basically composed of ZrO x Composed of, or made of ZrO x Composition, where x is a number. In some embodiments, ZrO x It can be called zirconium oxide.

[0028] Stack 16 is formed over material 14. Stack 16 includes alternating first and second levels 18 and 20. First level 18 includes semiconductor material 22, and second level 20 includes insulating material. In the illustrated embodiment, at least some of the insulating material within the second level 20 includes a first composition 24 and a second composition 26. Level 20 may include one or both of compositions 24 and 26. In some embodiments, composition 24 may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide. In some embodiments, composition 26 may include silicon nitride, be substantially composed of silicon nitride, or be composed of silicon nitride. In some embodiments, level 20 may include one or more insulating compositions as a complement or alternative to one or both of the indicated compositions 24 and 26.

[0029] Semiconductor material 22 may include any suitable composition; and in some embodiments may include one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., substantially composed of them, or composed of them; wherein the term III / V semiconductor material refers to semiconductor materials comprising elements selected from Groups III and V of the periodic table (where Groups III and V are old-fashioned nomenclature and are now referred to as Groups 13 and 15). In some embodiments, semiconductor material 22 may include silicon, substantially composed of silicon, or composed of silicon.

[0030] Semiconductor material 22 may correspond to a channel material similar to materials 1242 and 1342 described above with reference to Figures 1-4. In these embodiments, Figure 5 The configuration can correspond to a process stage for manufacturing a memory similar to any of the memories described above with reference to Figures 1-4. Accordingly, vertically extending digital lines or vertically extending word lines can be... Figure 5 The area near the assembly 10 shown.

[0031] Finally, laterally extending capacitors are formed along layer 18, and these capacitors may be similar to capacitors 1208 and 1308 in Figures 1-4. Accordingly, the capacitors may be incorporated into the memory cells of the three-dimensional memory array. Although Figure 5 The embodiments shown depict a stack 16 comprising two of the layers 18, but it should be understood that in some embodiments, the stack 16 may comprise a large number of vertically stacked layers 18; and may include, for example, eight of the vertically stacked layers 18, 16 of the vertically stacked layers 18, 32 of the vertically stacked layers 18, 64 of the vertically stacked layers 18, 128 of the vertically stacked layers 18, 256 of the vertically stacked layers 18, 512 of the vertically stacked layers 18, and so on.

[0032] Insulating material 24 is shown as the uppermost material of assembly 10. It should be understood that other materials (e.g., photolithographically patterned photoresist, hard masking material, anti-reflective material, etc.) may be disposed above stack 16 during the patterning of the openings (described below). These other materials are not illustrated for the sake of simplicity.

[0033] See Figure 6 The opening 28 is formed to extend through the stack 16. In the illustrated embodiment, the opening stops the upper surface of the etch-stop material 14. In other embodiments, the opening may penetrate into the etch-stop material 14.

[0034] The opening 28 shown can be a longitudinally extending groove (wherein this groove is relative to...) Figure 6The cross-sectional view extends into and out of the page, and the trenches may represent a large number of substantially the same trenches formed through the stack 16 during the patterning of the three-dimensional memory (e.g., a memory similar to any of the memories described above with reference to Figures 1-4).

[0035] Opening 28 has sidewalls 29 extending along materials 22, 24 and 26 of layers 18 and 20.

[0036] See Figure 7 Semiconductor material (channel material) 22 is recessed from the sidewall 29 of the opening 28 to form a cavity 30 extending laterally outward from the opening. In some embodiments, the laterally extending cavity 30 may be considered to be adjacent to the opening 28.

[0037] Cavity 30 can be formed using any suitable process. In some embodiments, material 22 may include silicon, and the cavity may be formed using an etchant comprising tetramethylammonium hydroxide (TMAH).

[0038] During the formation of cavity 30, only some semiconductor material 22 is removed from layer 18. The remaining area of ​​semiconductor material 22 defines the lateral perimeter 32 of the cavity, wherein these lateral perimeters are located away from opening 28.

[0039] See Figure 8 Dopant flows into opening 28 and along cavity 30 to dope the region of semiconductor material 22, thereby forming source / drain regions 34 along the transverse perimeter 32. The dopant within source / drain regions 34 is illustrated using a dotted diagram to aid the reader's observation of the source / drain regions. Source / drain regions 34 may be similar to regions 1240 and 1340 described above with reference to Figures 1-4.

[0040] The dopant may include any suitable composition. In some embodiments, the dopant may include one or both of phosphorus and arsenic, the semiconductor material 22 may include silicon, and the source / drain region 34 may correspond to an n-type doped region.

[0041] See Figure 9 The metal and the exposed portion of the semiconductor material 22 within the cavity 30 are combined to form a first metal-containing composition 36 adjacent to the source / drain region 34, and then a second metal-containing composition 38 adjacent to the first metal-containing composition 36 is formed. In some embodiments, the first metal-containing composition 36 can be considered as being along the transverse perimeter 32 of the semiconductor material 22 in the cavity 30. Figure 8 It is formed at the marked location.

[0042] The first metal-containing composition 36 may include a combination of a metal and a semiconductor material 22. For example, in some embodiments, the semiconductor material 22 may include silicon, and the first metal-containing composition 36 may include a metal silicide (e.g., titanium silicide, tungsten silicide, etc.), consisting essentially of a metal silicide, or consisting of a metal silicide. In some embodiments, the first metal-containing composition may be considered to include one or both of WSi and TiSi, consisting essentially of one or both of WSi and TiSi, or consisting of one or both of WSi and TiSi, wherein the chemical formula indicates the major component rather than a specific stoichiometry.

[0043] The second metal-containing composition 38 may include the same metal as the first metal-containing composition 36. In some embodiments, the second metal-containing composition 38 may include one or both of tungsten and titanium, and is substantially composed of one or both of tungsten and titanium.

[0044] Metallic compositions 36 and 38 can be formed by allowing a metal-containing precursor (e.g., a metal halide) to flow into the opening 28 and along the cavity 30.

[0045] The first and second metal-containing components 36 and 38 can be considered as forming a conductive bridge 40.

[0046] See Figure 10 A first capacitor electrode material 42 is formed across the assembly 10. The first capacitor electrode material is lined with an opening 28 and a cavity 30. Region 44 of the first capacitor electrode material 42 is adjacent to the metallic material 38 of the conductive bridge 40.

[0047] The first capacitor electrode material 42 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the first capacitor electrode material 42 may include a metal nitride (e.g., titanium nitride), be substantially composed of metal nitrides, or be composed of metal nitrides.

[0048] See Figure 11 Sacrificial material 46 is formed within opening 28 and cavity 30. Sacrificial material 46 may include any suitable composition, and in some embodiments may include silicon (e.g., one or both of polycrystalline and amorphous silicon), substantially composed of silicon, or composed of silicon.

[0049] See Figure 12The opening 28 is reconstructed using one or more suitable etching processes. Etching removes excess material 42 along the sidewalls 29 of the opening 28. Sacrificial material 46 acts as a protective material for the protective material 42 within the cavity 30.

[0050] See Figure 13 Material 46 was removed from cavity 30. Figure 12 ).

[0051] See Figure 14 A capacitor dielectric material 48 is formed within the opening 28 and the cavity 30. The capacitor dielectric material can be considered as narrowing the cavity. Subsequently, a second capacitor electrode material 50 is formed within the opening 28 and the narrowed cavity 30. The second capacitor electrode material 50 fills the narrowed cavity.

[0052] In some embodiments, the second capacitor electrode material 50 within the opening 28 may be configured to extend vertically through the pillar 52 of the stack 16, and this pillar may be configured to engage with the region 54 of the second capacitor electrode material 50 extending laterally within the cavity 30.

[0053] The capacitor dielectric material 48 may include any suitable composition. In some embodiments, the capacitor dielectric material 48 may include silicon dioxide, and is substantially composed of silicon dioxide, or is composed of silicon dioxide. In some embodiments, the capacitor dielectric material 48 may include one or more high-k compositions (e.g., alumina, zirconium oxide, hafnium oxide, etc.), and is substantially composed of one or more high-k compositions, or is composed of one or more high-k compositions; wherein the term high-k means a dielectric constant greater than that of silicon dioxide (i.e., greater than about 3.9).

[0054] The second electrode material 50 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the second electrode material 50 may include one or more metals, be substantially composed of one or more metals, or be composed of one or more metals. For example, the second electrode material 50 may include tungsten, be substantially composed of tungsten, or be composed of tungsten.

[0055] See Figure 15 Excess material 48 and 50 is removed from the upper surface of the stack 16 using a planarization process, thereby forming a planarized upper surface 55 extending across the upper surface of the stack 16. The planarization process may include, for example, chemical mechanical polishing (CMP).

[0056] Figure 15The configuration includes capacitors 60 along layer 18. Each of the capacitors includes an electrode material 42 configured as a container-shaped first electrode 62, a region of capacitor dielectric material 48, and a region of capacitor electrode material 50. In some embodiments, the capacitor electrode material 50 may be considered to be configured as a shared capacitor electrode, wherein the shared capacitor electrode is shared among laterally adjacent capacitors within layer 18. For example, one of the layers 18 in Figure 15 The layer is marked 18a, and includes a pair of laterally adjacent capacitors marked 60a and 60b. Capacitors 60a and 60b each include capacitor electrodes marked 62a and 62b, respectively. Capacitor electrodes 62a and 62b may be referred to as the first and second capacitor electrodes, respectively. The first and second capacitor electrodes 62a and 62b are laterally extending container-shaped electrodes. The container-shaped first electrode 62a opens along a first lateral direction A1, and the container-shaped second electrode 62b opens along a second lateral direction A2 opposite to the first lateral direction A1.

[0057] The capacitor dielectric material 48 lines the inner surfaces of the container-shaped first and second capacitor electrodes 62a and 62b. A shared capacitor electrode material 50 extends vertically between the first and second capacitor electrodes 62a and 62b, and a region 54 of the shared capacitor electrode extends into the openings of the container-shaped first and second capacitor electrodes 62a and 62b. The shared capacitor electrode material 50 is spaced apart from the capacitor electrodes 62a and 62b by the capacitor dielectric material 48.

[0058] In the illustrated embodiment, the first and second capacitors 60a and 60b are laterally offset from each other, and are substantially mirror images of each other along a plane 68 extending vertically through the center of a pillar 52 of the shared electrode material 50. The term “substantially mirror image” means a mirror image within reasonable manufacturing and measurement tolerances.

[0059] The source / drain regions 34 along layer 18a are labeled 34a and 34b. Regions 34a and 34b may be referred to as the first and second source / drain regions, respectively. These first and second source / drain regions are laterally offset from each other.

[0060] The conductive bridges 40 within layer 18a are labeled 40a and 40b, respectively. Conductive bridge 40a electrically couples the electrode 62a of the first capacitor 60a to the first source / drain region 34a, and conductive bridge 40b electrically couples the electrode 62b of the second capacitor 60b to the second source / drain region 34b.

[0061] In some embodiments, Figure 15The capacitor 60 may be incorporated into a three-dimensional memory array of the type described above with reference to Figures 1-4. The capacitor 60 may be located within a memory cell of the memory array and may be similar to capacitors 1208 and 1308 of Figures 1-4. In some embodiments, the capacitor 60 may be located within a memory array comprising vertically extending digital lines similar to digital lines 1312 described with reference to Figures 3 and 4, and in some embodiments, the capacitor 60 may be located within a memory array comprising vertically extending word lines similar to word lines 1214 described with reference to Figures 1 and 2.

[0062] In some embodiments, the capacitors 60 shown along each of the layers 18 may be referred to as paired capacitors, wherein they share a common plate electrode (i.e., a plate electrode comprising electrode material 50). The capacitors 60a and 60b along layer 18a may be considered to correspond to a set of paired capacitors, and similarly, the paired capacitors 60 along the other layers 18 may be considered to be other sets of paired capacitors.

[0063] In some embodiments, paired capacitors 60a and 60b can be considered together as a capacitor assembly along layer 18a. This capacitor assembly is one of many substantially identical capacitor assemblies along the first layer 18. In some embodiments, the first layer 18 may be referred to as a capacitor assembly layer (or a capacitor-containing layer). Any suitable number of these capacitor assembly layers may be present within a three-dimensional memory device (e.g., a device similar to any of the prior art devices of Figures 1-4). In some embodiments, at least eight, at least 16, at least 32, at least 64, at least 128, at least 256, at least 512, and so on, of capacitor assembly layers 18 may be present.

[0064] One advantage of the embodiments described herein is that the conductive bridge 40 provides a highly conductive connection between the source / drain region 34 and the electrode 62 of the capacitor 60, which can improve the performance (e.g., access speed) of the memory device formed according to the embodiments described herein compared to conventional memory devices.

[0065] The assemblies and structures discussed above can be utilized within integrated circuits (the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate); and can be incorporated into electronic systems. These electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and so on.

[0066] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0067] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The use of the term “dielectric” in some instances and the term “insulating” (or “electrically insulating”) in others is used to provide linguistic variation within this disclosure to simplify the premises of the appended claims, rather than to indicate any significant chemical or electrical differences.

[0068] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some cases and another in others may be to provide linguistic variation within this disclosure to simplify the premises of the appended claims.

[0069] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The description provided herein and the appended claims relate to any structure having the described relationships between various features, regardless of whether the structure is in or rotated relative to the specific orientation of the drawings.

[0070] Unless otherwise specified, the cross-sectional views accompanying the drawings show only the features within the plane of the cross-section and not the material behind the plane of the cross-section, in order to simplify the drawings.

[0071] When a structure is referred to above as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure, or there may be intervening structures. In contrast, when a structure is referred to as "directly on another structure," "immediately adjacent to another structure," or "directly against another structure," there are no intervening structures. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless explicitly stated otherwise), but rather indicate upright alignment.

[0072] A structure (e.g., a layer, material, etc.) may be described as “vertically extending” to indicate that the structure extends generally upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend generally orthogonally relative to the upper surface of the substrate.

[0073] Some embodiments include an integrated assembly having a first source / drain region and a second source / drain laterally offset relative to the first source / drain region. The first and second source / drain regions comprise conductive doped silicon. A metal silicide material is adjacent to the lateral surfaces of the first and second source / drain regions. A metal-containing region is adjacent to the metal silicide material. One of the metal-containing regions is a first metal-containing region and associated with the first source / drain region, and the other of the metal-containing regions is a second metal-containing region and associated with the second source / drain region. A laterally extending, container-shaped first capacitor electrode is coupled to the first metal-containing region, wherein the container shape of the first capacitor electrode opens along a first lateral direction. A laterally extending, container-shaped second capacitor electrode is coupled to the second metal-containing region, wherein the container shape of the second capacitor electrode opens along a second lateral direction opposite to the first lateral direction. A capacitor dielectric material lines the inner surfaces of the first and second capacitor electrodes. A shared capacitor electrode extends vertically between the first and second capacitor electrodes and extends into the lined first and second capacitor electrodes. A shared capacitor electrode, capacitor dielectric material, and a first capacitor electrode are incorporated together into a first laterally extending capacitor. A shared capacitor electrode, capacitor dielectric material, and a second capacitor electrode are incorporated together into a second laterally extending capacitor, wherein the second laterally extending capacitor is laterally offset relative to the first laterally extending capacitor.

[0074] Some embodiments include an integrated assembly comprising pillars of shared capacitor electrode material extending vertically through alternating first and second levels. The first level is a capacitor-containing level comprising paired, laterally extending capacitors. Each pair of paired capacitors comprises a first capacitor and a second capacitor, wherein the second capacitor is substantially a mirror image of the first capacitor in a plane extending vertically through the center of the pillar of shared electrode material. The capacitors include container-shaped electrodes coupled to source / drain regions associated with the access device. Coupling to the source / drain regions occurs through conductive bridges comprising metal-containing regions and metal silicide-containing regions. The metal-containing regions directly abut the container-shaped electrodes, and the metal silicide-containing regions directly abut the source / drain regions. The second level is an insulating level comprising one or more insulating materials.

[0075] Some embodiments include a method of forming an integrated assembly. Alternating stacks of first and second levels are formed. The first level comprises a semiconductor material, and the second level comprises an insulating material. An opening is formed to extend through the stack. The semiconductor material of the first level is recessed to form a laterally extending cavity near the opening. The remaining region of the semiconductor material defines a lateral perimeter of the cavity away from the opening. The semiconductor material along the lateral perimeter of the cavity is doped. A metal is combined with an exposed portion of the semiconductor material along the lateral perimeter of the cavity to form a first metal-containing composition along the lateral perimeter. A second metal-containing composition is formed along the first metal-containing composition. The first and second metal-containing compositions together form a conductive bridge. The cavity is lined with a first capacitor electrode material. A region of the first capacitor electrode material directly abuts the conductive bridge. A capacitor dielectric material is formed within the lined cavity to narrow the cavity. A second capacitor electrode material is formed within the narrowed cavity to fill the cavity. Posts of the second capacitor electrode material are formed within the opening and bonded to the second capacitor electrode material within the cavity.

[0076] As per the provisions, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims have the full scope as stated in the writing and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising: A first source / drain region, and a second source / drain region that is laterally offset relative to the first source / drain region; The first and second source / drain regions comprise conductive doped silicon. A metal silicide material, with its lateral surface adjacent to the first and second source / drain regions; A metal-containing region adjacent to the metal silicide material; one of the metal-containing regions is a first metal-containing region and associated with the first source / drain region, and the other of the metal-containing regions is a second metal-containing region and associated with the second source / drain region; A laterally extending container-shaped first capacitor electrode coupled to the first metal-containing region, wherein the container shape of the first capacitor electrode opens along a first lateral direction; A laterally extending container-shaped second capacitor electrode coupled to the second metal-containing region, wherein the container shape of the second capacitor electrode opens along a second lateral direction opposite to the first lateral direction; A capacitor dielectric material, which lines the inner surfaces of the container-shaped first and second capacitor electrodes; as well as A shared capacitor electrode extends vertically between the first and second capacitor electrodes and extends into the lined first and second capacitor electrodes; The shared capacitor electrode, the capacitor dielectric material, and the first capacitor electrode are incorporated together into the first laterally extending capacitor; Furthermore, the shared capacitor electrode, the capacitor dielectric material, and the second capacitor electrode are incorporated together into the second laterally extending capacitor, wherein the second laterally extending capacitor is laterally offset relative to the first laterally extending capacitor.

2. The integrated assembly of claim 1, wherein the first and second capacitor electrodes comprise metal nitrides.

3. The integrated assembly of claim 1, wherein the first and second capacitor electrodes comprise titanium nitride.

4. The integrated assembly of claim 1, wherein the metal-containing region comprises tungsten.

5. The integrated assembly of claim 1, wherein the metal silicide comprises tungsten silicide.

6. The integrated assembly of claim 1, wherein the metal-containing region comprises titanium.

7. The integrated assembly of claim 1, wherein the metal silicide comprises titanium silicide.

8. The integrated assembly of claim 1, comprising a memory array, wherein the first and second capacitors are located within the first and second memory cells of the memory array.

9. The integrated assembly of claim 8, wherein the memory array includes vertically extending word lines.

10. The integrated assembly of claim 8, wherein the memory array includes vertically extending digital lines.

11. The integrated assembly of claim 1, wherein the first and second capacitors together constitute a capacitor assembly, wherein the capacitor assembly is one of a plurality of substantially identical capacitor assemblies; wherein the capacitor assembly is along a capacitor assembly hierarchy; wherein the capacitor assembly hierarchy alternates vertically with an insulating hierarchy; and wherein at least eight of the capacitor assembly hierarchies are present.

12. An integrated assembly comprising: Vertically extending pillars through alternating stacks of shared capacitor electrode material in the first and second layers; The first level is a capacitor level comprising paired, laterally extending capacitors; each pair of said paired, laterally extending capacitors includes a first capacitor and a second capacitor, wherein the second capacitor extends along a plane that is substantially a mirror image of the first capacitor, passing through the center of the pillar of the shared capacitor electrode material; the capacitor includes a container-shaped electrode coupled to a source / drain region associated with the same access device; the coupling to the source / drain region occurs through a conductive bridge comprising a metal-containing region and a metal silicide-containing region; the metal-containing region directly abuts the container-shaped electrode, and the metal silicide-containing region directly abuts the source / drain region; and The second level is an insulation level that includes one or more insulating materials.

13. The integrated assembly of claim 12, wherein the metal silicide region comprises tungsten silicide and / or titanium silicide.

14. The integrated assembly of claim 13, wherein the metal-containing region comprises tungsten and / or titanium.

15. The integrated assembly of claim 12, wherein the insulating layer comprises silicon dioxide and silicon nitride.

16. The integrated assembly of claim 12, wherein the source / drain regions comprise n-type doped silicon.

17. The integrated assembly of claim 12, wherein the stack comprises at least eight of the first layer containing capacitors.

18. The integrated assembly of claim 12, wherein the stack comprises at least 16 of the first layer containing capacitors.

19. The integrated assembly of claim 12, wherein the stack comprises at least 32 of the first layer containing capacitors.

20. The integrated assembly of claim 12, wherein the stack comprises at least 64 of the first layer containing capacitors.

21. A method of forming an integrated assembly, comprising: This forms an alternating stack of first and second levels; The first layer includes a semiconductor material, and the second layer includes an insulating material; Forming an opening that extends through the stack; The semiconductor material of the first layer is recessed to form a laterally extending cavity near the opening; The remaining region of the semiconductor material defines the lateral perimeter of the cavity away from the opening; The semiconductor material is doped along the transverse perimeter of the cavity; The metal is combined with the exposed portion of the semiconductor material along the transverse perimeter of the cavity to form a first metal-containing composition along the transverse perimeter, wherein the first metal-containing composition comprises a metal silicide; A second metal-containing composition is formed along the first metal-containing composition, wherein the second metal-containing composition comprises a metal; the first and second metal-containing compositions together form a conductive bridge. The cavity is lined with the first capacitor electrode material; The region of the first capacitor electrode material directly abuts the conductive bridge; A capacitor dielectric material is formed inside the lined cavity to narrow the cavity; as well as A second capacitor electrode material is formed within the narrowed cavity to fill the cavity; A post of the second capacitor electrode material is formed within the opening and engages with the second capacitor electrode material within the cavity.

22. The method of claim 21, wherein the second layer comprises silicon dioxide.

23. The method of claim 21, wherein the second layer comprises silicon nitride.

24. The method of claim 21, wherein the second layer comprises both silicon nitride and silicon dioxide.

25. The method of claim 21, wherein the capacitor dielectric material comprises silicon dioxide.

26. The method of claim 21, wherein the capacitor dielectric material comprises a high-k composition.

27. The method of claim 21, wherein the semiconductor material comprises silicon.

28. The method of claim 27, wherein the first metal-containing component comprises tungsten silicide.

29. The method of claim 28, wherein the second metal-containing component comprises tungsten.

30. The method of claim 29, wherein the first capacitor electrode material comprises titanium nitride.

31. The method of claim 30, wherein the second capacitor electrode material comprises tungsten.

32. The method of claim 21, wherein the stack comprises at least eight of the first layers.

33. The method of claim 21, wherein the stack comprises at least 64 of the first level.

34. The method of claim 21, wherein the stack comprises at least 512 of the first level.

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