Memory device and method of forming the same

Abstract

A memory device and method of forming the same. In one embodiment, a memory device includes a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming the same. Background Technology

[0002] Semiconductor memory is used in integrated circuits for electronic applications, including radios, televisions, mobile phones, and personal computing devices. Semiconductor memory falls into two main categories: volatile memory and non-volatile memory. Volatile memory includes Random Access Memory (RAM), which can be further divided into two subcategories: Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). Both SRAM and DRAM are volatile because they lose stored data when power is turned off.

[0003] On the other hand, non-volatile memory can retain the data stored on it. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM). The advantages of ferroelectric random access memory include its fast write / read speed and small size. Summary of the Invention

[0004] A memory device includes: a first word line above a substrate, the first word line including a first conductive material; a second memory film intersecting the first word line; a first memory film between the first memory film and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.

[0005] A memory device includes: a memory cell above a substrate, the memory cell including a thin-film transistor, the thin-film transistor further including: a gate including a first wire and a portion of a work function tuning layer, the work function tuning layer being disposed on a sidewall of the first wire, the first wire extending along a first direction; a gate dielectric including a portion of a memory thin film, the memory thin film being disposed on a sidewall of the work function tuning layer; a channel region including a portion of a semiconductor thin film, the semiconductor thin film being disposed on a sidewall of the memory thin film; and a source / drain electrode including a portion of a second wire, the second wire being disposed on a sidewall of the semiconductor thin film, the second wire extending along a second direction perpendicular to the first direction.

[0006] A method for forming a memory device includes: forming word lines between a pair of dielectric layers, the word lines being formed of a first conductive material; recessing first sidewalls of the word lines from the first sidewalls of the dielectric layers to form first sidewall grooves between the dielectric layers; forming conductive spacers in the first sidewall grooves and on the first sidewalls of the word lines, the first conductive spacers being formed of a second conductive material, the second conductive material being different from the first conductive material; forming a memory thin film on the sidewalls of the first conductive spacers and on the first sidewalls of the dielectric layers; forming a semiconductor thin film on the sidewalls of the memory thin film; and forming bit lines on the sidewalls of the semiconductor thin film. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading them in conjunction with the accompanying drawings, and in the following detailed description. It is worth noting that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figures 1A to 1C An example of a memory array according to some embodiments is illustrated;

[0009] Figures 2 to 22C This is a view of an intermediate stage in the fabrication of a memory array according to some embodiments;

[0010] Figures 23 to 24 This is a view of an intermediate stage in the fabrication of a memory array according to some other embodiments.

[0011] [Symbol Explanation]

[0012] 50: Memory Array

[0013] 52: Memory Unit

[0014] 54: Transistor

[0015] 56: Arrow

[0016] 102: Substrate

[0017] 104: Multi-layer stacking

[0018] 104A: Area

[0019] 104B: Area

[0020] 104C: Region

[0021] 106: Dielectric layer

[0022] 106A: Dielectric layer

[0023] 106B: Dielectric layer

[0024] 106C: Dielectric layer

[0025] 106D: Dielectric layer

[0026] 108: Sacrificial Layer

[0027] 108A: Sacrificial Layer

[0028] 108B: Sacrificial Layer

[0029] 108C: Sacrificial Layer

[0030] 110: Mask

[0031] 112: Opening

[0032] 114: Stepped structure

[0033] 116: Intermetallic dielectric

[0034] 122: Trench

[0035] 122A: Trench

[0036] 122B: Trench

[0037] 124: Opening

[0038] 126: Character Line

[0039] 126A: Character Line

[0040] 126B: Character Line

[0041] 126C: Character Line

[0042] 128: Padding layer

[0043] 130: Main layer

[0044] 132: Sidewall groove

[0045] 134: Conductive layer

[0046] 136: Conductive spacer

[0047] 136A: Conductive spacer

[0048] 136B: Conductive spacer

[0049] 142: Memory film

[0050] 144: Semiconductor thin films

[0051] 146: Quarantine Zone

[0052] 148: Opening

[0053] 152: Wire

[0054] 152B: Bitline

[0055] 152S: Source line

[0056] 154: Opening

[0057] 156: Quarantine Zone

[0058] 160: Interconnection Layer

[0059] 160A: First interconnect layer

[0060] 160B: Second Interconnect Layer

[0061] 162: Interconnector

[0062] 162B: Bit Line Interconnect

[0063] 162L: Wire

[0064] 162L1: First-stage conductor

[0065] 162S: Interconnection

[0066] 162V: Conductive via

[0067] 162V1: First-level conductive via

[0068] 164: Dielectric layer

[0069] 166: Conductive contact Detailed Implementation

[0070] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. As used herein, forming a first feature on a second feature means that the first feature is formed in direct contact with the second feature. Additionally, numbers and / or words may be repeatedly referenced in various examples in this disclosure. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0071] Furthermore, spatially relative terms (e.g., "below," "below," "under," "above," "above," etc.) are used here to simply describe the relationship between an element or feature as shown in the figure and another element or feature. In addition to the orientation illustrated in the figure, these spatially relative terms cover different orientations of the device during use or operation. These devices can be rotated in other ways (90 degrees or other angles), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0072] Various embodiments provide a three-dimensional memory array having multiple vertically stacked memory cells. Each memory cell includes a transistor. Each transistor includes an insulating memory film that provides the gate dielectric for the transistor and can be polarized to store digital values. Each transistor also includes a word line and a work function material, which together provide the gate for the transistor. The work function material is located between the word line and the insulating memory film of the corresponding transistor. The work function of the transistor can be tuned by selecting the work function material. Furthermore, the work function material serves as an adhesion layer to improve the adhesion between the word line and the insulating memory film. This reduces the number of interface traps between the gate dielectric and the gate of the transistor. Reducing the number of interface traps allows the insulating memory film to maintain more read / write cycles, thereby increasing the lifetime of the memory array.

[0073] Figures 1A to 1C An example of a memory array 50 according to some embodiments is illustrated. Figure 1A An example of a portion of the memory array 50 is shown in a 3D view; Figure 1B Draw the circuit diagram of memory array 50; Figure 1C Another example of a portion of a memory array 50 is illustrated in a three-dimensional view. The memory array 50 includes a plurality of memory cells 52 arranged in a grid of columns and rows. The memory cells 52 are further vertically stacked to provide a three-dimensional memory array, thereby increasing device density. The memory array 50 can be disposed within an interconnect structure of a semiconductor wafer, which can be formed in a back-to-line (BEOL) process. For example, the memory array 50 can be disposed within an interconnect layer of a semiconductor wafer, such as being formed on one or more active elements (e.g., transistors) on a semiconductor substrate.

[0074] In some embodiments, the memory array 50 is a NOR memory array or the like. Each memory cell 52 includes a transistor 54 having an insulating memory film 142 as a gate dielectric. In some embodiments, the transistor 54 is a thin-film transistor (TFT). In some embodiments, the gate (partially) of each transistor 54 is provided by a portion of a corresponding word line 126, the first source / drain of each transistor 54 is provided by a portion of a corresponding bit line 152B, and the second source / drain electrode of each transistor 54 is provided by a portion of a corresponding source line 152S. Memory cells 52 in the same horizontal column of the memory array 50 may share a common word line 126, while memory cells 52 in the same vertical row of the memory array 50 may share a common source line 152S and a common bit line 152B.

[0075] The memory array 50 includes multiple vertically stacked word lines 126, which are disposed between pairs of adjacent dielectric layers 106. The word lines 126 extend in a direction parallel to the main surface of the underlying substrate (e.g., the Y direction). Figures 1A to 1C (Not shown separately). Character lines 126 can have a stepped configuration, such that the lower character line 126 is longer than the endpoint of the upper character line 126 and extends laterally beyond the endpoint of the upper character line 126. For example, in... Figure 1A In the diagram, the stacked layers of character lines 126 are illustrated with the topmost character line 126 being the shortest and the bottommost character line 126 being the longest. The individual lengths of the character lines 126 can increase in the direction toward the substrate below. In this way, a portion of each character line 126 is accessible from above the memory array 50, and conductive contacts 166 (see [reference]) are also present. Figure 1C The exposed portion of each word line 126 can be formed. In embodiments where the memory array 50 is disposed in the interconnect layer of a semiconductor wafer, the conductive contact 166 can be, for example, an interconnect 162 connecting the exposed portion of the word line 126 to an upper interconnect layer (see...). Figure 1C ) through holes.

[0076] The memory array 50 also includes a plurality of bit lines 152B and a plurality of source lines 152S. The bit lines 152B and source lines 152S may each extend in a direction perpendicular to the word line 126 along its length (e.g., the Z direction). An isolation region 146 is disposed between the bit lines 152B and the source lines 152S and isolates adjacent bit lines 152B from the source lines 152S.

[0077] Pairs of bit lines 152B and source lines 152S, along with intersecting word lines 126, define the boundary of each memory cell 52, and isolation regions 156 are disposed between adjacent pairs of bit lines 152B and source lines 152S and isolate them. In some embodiments, the source lines 152S are electrically coupled to ground. Although Figure 1A The illustration shows a specific placement of bit line 152B relative to source line 152S, but it should be understood that the placement of bit line 152B and source line 152S may be reversed in other embodiments.

[0078] The memory array 50 also includes a semiconductor thin film 144. The semiconductor thin film 144 can provide channel regions for the transistors 54 of the memory cells 52. For example, when an appropriate voltage (e.g., higher than the corresponding threshold voltage (Vth) of the corresponding transistor 54) is applied through the corresponding word line 126, the region of the semiconductor thin film 144 intersecting the word line 126 can allow current to flow from the bit line 152B to the source line 152S (e.g., in the direction shown by arrow 56).

[0079] A memory thin film 142 is disposed between word line 126 and semiconductor thin film 144, and the memory thin film 142 can provide a gate dielectric for transistor 54. In some embodiments, the memory thin film 142 is formed of a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. Therefore, the memory array 50 can also be referred to as a ferroelectric random access memory (FeRAM) array. Alternatively, the memory thin film 142 can be a multilayer structure, including a silicon nitride layer between two layers of silicon oxide (e.g., an oxide-nitride-oxide structure), different ferroelectric materials, different types of memory layers (e.g., capable of storing bits), or the like.

[0080] In embodiments where the memory film 142 is formed of a ferroelectric material, the memory film 142 can be polarized along two different directions, and the polarization direction can be changed by applying an appropriate voltage difference across the memory film 142 and generating an appropriate electric field. The polarization can be relatively localized (e.g., typically contained within each boundary of the memory cell 52), and a continuous region of the memory film 142 can extend across multiple memory cells 52. Depending on the polarization direction of a specific region of the memory film 142, the threshold voltage of the corresponding transistor 54 varies, and a value (e.g., 0 or 1) can be stored. For example, when a region of the memory film 142 has a first polarization direction, the corresponding transistor 54 can have a relatively low threshold voltage, while when a region of the memory film 142 has a second polarization direction, the corresponding transistor 54 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage offset. A larger threshold voltage offset makes reading the digital value stored in the corresponding memory cell 52 easier (e.g., less prone to error).

[0081] To perform a write operation on memory cell 52 in this embodiment, a write voltage is applied to a portion of the memory film 142 corresponding to memory cell 52. The write voltage can be applied, for example, by applying an appropriate voltage to the corresponding word line 126, the corresponding bit line 152B, and the corresponding source line 152S. By applying the write voltage to a portion of the memory film 142, the polarization direction of that region of the memory film 142 can be changed. In this way, the corresponding threshold voltage of the corresponding transistor 54 can be switched from a low threshold voltage to a high threshold voltage, and vice versa, and a digital value can be stored in memory cell 52. Because word line 126 intersects with bit line 152B and source line 152S, a single memory cell 52 can be selected for the write operation.

[0082] To perform a read operation on memory cell 52 in this embodiment, a read voltage (a voltage between a low threshold voltage and a high threshold voltage) is applied to the corresponding word line 126. Depending on the polarization direction of the corresponding region of memory film 142, the transistor 54 of memory cell 52 may or may not be turned on. In this way, bit line 152B may or may not discharge through source line 152S (e.g., ground), and the digital value stored in memory cell 52 can be determined. Because word line 126 intersects with bit line 152B and source line 152S, a single memory cell 52 can be selected for the read operation.

[0083] Figure 1AFurther reference cross-sections of the memory array 50 used in subsequent figures are shown. Cross-section A-A' is in the X direction and extends through bit line 152B / source line 152S and isolation region 146. Cross-section C-C' is in the Y direction and extends along the vertical axis of word line 126. For clarity, subsequent figures refer to these reference cross-sections.

[0084] Figures 2 to 22C This is a view of an intermediate stage in the manufacturing of a memory array 50 according to some embodiments. For memory cell 52 (see...) Figures 1A to 1B Transistor 54 (see) Figures 1A to 1B The manufacturing process is illustrated. Figure 2 , 3 4, 5, 6, 7, 8, 9, 10 and Figure 11 It is a 3D view. Figure 12 , 13 14, 15, 16, 17, 18A, 19A, 20A, 21A and Figure 22A Is along with Figure 1A as well as Figure 21B The cross-sectional view shown is similar to the reference section A-A' in Figures 18B, 19B, 20B, and 21B. Figure 22B It is a top view. Figure 22C Is along with Figure 1A A cross-sectional view similar to the reference section C-C' is shown. A portion of the memory array 50 is depicted.

[0085] exist Figure 2 The image shows a substrate 102. The substrate 102 can be a semiconductor substrate, such as a host semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 102 can be a wafer, such as a silicon wafer. Typically, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 102 can include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0086] Although not shown in Figure 2, circuitry and / or interconnects may be formed over substrate 102. The circuitry includes active elements (e.g., transistors) on the top surface of substrate 102. The transistor may include a channel region, a gate structure on the channel region, and source / drain regions adjacent to the channel region. In some embodiments, the transistor may be a planar field-effect transistor (FET), a fin field-effect transistor (finFET), a nanofield-effect transistor (nanoFET), or the like. An interlayer dielectric surrounds and isolates the source / drain regions and the gate structure. An interconnect structure, including one or more stacked dielectric layers and interconnects formed in one or more dielectric layers, is situated above the interlayer dielectric. The interconnect structure may include any number of dielectric layers with interconnects disposed therein. The interconnect structure may be electrically connected to the gate structure and the source / drain regions to form functional circuitry. In some embodiments, the functional circuitry formed by the interconnect structure may include logic circuitry, memory circuitry, a sense amplifier, a controller, input / output circuitry, image sensor circuitry, or the like or combinations thereof. In addition, other active components (such as diodes or the like) and / or passive components (such as capacitors, resistors or the like) may also be incorporated into the functional circuit.

[0087] A multilayer stack 104 is formed over a substrate 102 (including circuitry and / or interconnects that may be formed over the substrate 102). The multilayer stack 104 is then patterned to form a stepped structure for the memory array 50. Although the multilayer stack 104 is depicted as contacting the substrate 102, any number of intermediate layers may be disposed between substrates 102. For example, one or more interconnect layers including interconnects in a dielectric layer (e.g., a low-dielectric layer) may be disposed between the substrate 102 and the multilayer stack 104. In some embodiments, the interconnects may be patterned to provide power, ground, and / or signal lines to active elements on the substrate 102 and / or the memory array 50 (see [link to documentation]). Figures 1A to 1C ).

[0088] The multilayer stack 104 includes alternating dielectric layers 106 (including dielectric layers 106A, 106B, 106C, and 106D) and sacrificial layers 108 (including sacrificial layers 108A, 108B, and 108C). The dielectric layers 106 are formed of a first dielectric material, while the sacrificial layers 108 are formed of a second dielectric material. Acceptable dielectric materials include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; the like; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. Each layer of the multilayer stack 104 can be formed by any acceptable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes. The dielectric layers 106 will be used to isolate subsequently formed transistors. The sacrificial layers 108, also referred to as dummy layers, will be selectively replaced with word lines of transistors in subsequent processes. Therefore, the second dielectric material of the sacrificial layer 108 exhibits high etch selectivity relative to the first dielectric material of the dielectric layer 106. In some embodiments, the dielectric layer 106 is formed of silicon oxide, while the sacrificial layer 108 is formed of silicon nitride. Other combinations of dielectric materials having acceptable etch selectivity to each other may also be used. In the illustrated embodiment, the multilayer stack 104 includes four dielectric layers 106 and three sacrificial layers 108. It should be understood that the multilayer stack 104 may include other numbers of dielectric layers 106 and sacrificial layers 108.

[0089] exist Figure 3 In this process, a mask 110 is formed over the multilayer stack 104. The mask 110 can be formed of photoresist, such as a single-layer photoresist, a three-layer photoresist, or the like. The photoresist can be formed using spin coating or similar techniques. The mask 110 is then patterned to expose the multilayer stack 104 in region 104A while masking the remainder of the multilayer stack 104. For example, the topmost layer of the multilayer stack 104 (e.g., dielectric layer 106D) can be exposed in region 104A. In embodiments where the mask 110 is a photoresist, it can be patterned using acceptable photolithography techniques.

[0090] exist Figure 4In this process, a mask 110 is used as an etching mask to etch exposed portions of the multilayer stack 104 in region 104A. Etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral particle beam etching (NBE), or combinations thereof. Etching can be anisotropic. Etching can remove portions of the dielectric layer 106D and sacrificial layer 108C in region 104A and define opening 112. Because the dielectric layer 106D and sacrificial layer 108C have different material compositions, the etchants used to remove the exposed portions of these layers can be different. In some embodiments, the sacrificial layer 108C acts as an etch stop layer when etching the dielectric layer 106D, and the dielectric layer 106C acts as an etch stop layer when etching the sacrificial layer 108C. In this way, portions of the dielectric layer 106D and sacrificial layer 108C can be selectively removed without removing the remaining layers of the multilayer stack 104, and opening 112 can extend to the desired depth. Alternatively, a timed etching process can be used to stop etching the opening 112 after it reaches the desired depth. In the resulting structure, the dielectric layer 106C is exposed in region 104A.

[0091] exist Figure 5 In this embodiment, mask 110 is trimmed to expose additional portions of the multilayer stack 104. In embodiments where mask 110 is a photoresist, it can be trimmed using acceptable photolithography techniques. As a result of this trimming, the width of mask 110 is reduced, and portions of the multilayer stack 104 in regions 104A and 104B can be exposed. For example, the top surface of dielectric layer 106C can be exposed in region 104A, and the top surface of dielectric layer 106D can be exposed in region 104B.

[0092] exist Figure 6In this process, mask 110 is used as an etching mask to remove portions of dielectric layer 106D, sacrificial layer 108C, dielectric layer 106C, and sacrificial layer 108B in regions 104A and 104B using an acceptable etching process. The etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral particle beam etching (NBE), similar processes, or combinations thereof. The etching can be anisotropic. The etching extends opening 112 further into the multilayer stack 104. Because dielectric layers 106D and 106C, and sacrificial layers 108C and 108B have different material compositions, the etchants used to remove the exposed portions of these layers can be different. In some embodiments, sacrificial layer 108C serves as an etch stop layer when etching dielectric layer 106D; dielectric layer 106C serves as an etch stop layer when etching sacrificial layer 108C; sacrificial layer 108B serves as an etch stop layer when etching dielectric layer 106C; and dielectric layer 106B serves as an etch stop layer when etching sacrificial layer 108B. In this way, portions of dielectric layers 106D, 106C, and sacrificial layers 108C, 108B can be selectively removed without removing the remaining layers of the multilayer stack 104, and the opening 112 can be extended to the desired depth. Furthermore, during the etching process, the unetched portions of dielectric layer 106 and sacrificial layer 108 serve as a mask for the underlying layers, thus allowing dielectric layer 106D and sacrificial layer 108C (see...) to be etched. Figure 5 The previous pattern of the dielectric layer 106C and the sacrificial layer 108B are transferred to the lower dielectric layer 106C and the sacrificial layer 108B. In the resulting structure, the dielectric layer 106B is exposed in region 104A and the dielectric layer 106C is exposed in region 104B.

[0093] exist Figure 7 In this embodiment, mask 110 is trimmed to expose additional portions of the multilayer stack 104. In embodiments where mask 110 is a photoresist, it can be trimmed using acceptable photolithography techniques. As a result of the trimming, the width of mask 110 is reduced, and portions of the multilayer stack 104 in regions 104A, 104B, and 104C can be exposed. For example, the top surface of dielectric layer 106B can be exposed in region 104A; the top surface of dielectric layer 106C can be exposed in region 104B; and the top surface of dielectric layer 106D can be exposed in region 104C.

[0094] exist Figure 8In this process, portions of dielectric layers 106D, 106C, and 106B in regions 104A, 104B, and 104C are removed using a mask 110 as an etching mask through an acceptable etching process. The etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral particle beam etching (NBE), or similar processes or combinations thereof. The etching can be anisotropic. The etching extends the opening 112 further into the multilayer stack 104. In some embodiments, sacrificial layer 108C acts as an etch stop layer when etching dielectric layer 106D; sacrificial layer 108B acts as an etch stop layer when etching dielectric layer 106C; and sacrificial layer 108A acts as an etch stop layer when etching dielectric layer 106B. In this way, portions of dielectric layers 106D, 106C, and 106B can be selectively removed without removing the remaining layers of the multilayer stack 104, and the opening 112 can extend to a desired depth. Furthermore, during the etching process, each sacrificial layer 108 acts as a mask for the underlying layers; therefore, sacrificial layers 108C and 108B (see...) Figure 7 The previous pattern of the ) is transferred to the lower dielectric layers 106C and 106B. In the resulting structure, the sacrificial layer 108A is exposed in region 104A; the sacrificial layer 108B is exposed in region 104B; and the sacrificial layer 108C is exposed in region 104C.

[0095] In Figure 9, mask 110 can be removed. In embodiments where mask 110 is a photoresist, it can be removed by any acceptable ashing or wet stripping process. Therefore, the stepped structure 114 is formed from the remainder of the multilayer stack 104. The stepped structure includes a stack of alternating layers in dielectric layer 106 and sacrificial layer 108. As described above, sacrificial layer 108 will be used in subsequent processes with transistor 54 (see...). Figures 1A to 1B The character lines are selectively replaced. The lower sacrificial layer 108 is wider and extends laterally beyond the upper sacrificial layer 108, and the width of each sacrificial layer 108 increases in the direction toward the substrate 102. For example, sacrificial layer 108A may be longer than sacrificial layer 108B, and sacrificial layer 108B may be longer than sacrificial layer 108C. In this way, conductive contacts can be formed from above the stepped structure 114 with the wires formed in subsequent processing steps.

[0096] In Figure 10, an intermetallic dielectric (IMD) 116 is deposited over the stepped structure 114. The IMD 116 can be formed of a dielectric material and can be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or flow-through chemical vapor deposition. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. The IMD 116 extends along the sidewalls of the dielectric layer 106 and the sidewalls of the sacrificial layer 108. Furthermore, the IMD 116 may contact the top surface of each sacrificial layer 108. After the IMD 116 is formed, a removal process is applied to the IMD 116 to remove excess dielectric material over the stepped structure 114. In some embodiments, processes such as chemical mechanical polishing (CMP), etching back, combinations thereof, or similar processes may be used. The planarization process exposes the stepped structure 114 such that the stepped structure 114 and the top surface of the intermetallic dielectric 116 are horizontal after the planarization process is completed.

[0097] exist Figure 11 In this process, trenches 122 are patterned within stepped structures 114 and intermetallic dielectric 116. The trenches 122 can be patterned using acceptable photolithography and etching techniques, such as selective etching of stepped structures 114 (e.g., selectively removing the dielectric material of dielectric layer 106 and sacrificial layer 108 at a rate faster than removing other materials). Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral particle beam etching (NBE), similar processes, or combinations thereof. Etching can be anisotropic. After patterning, portions of stepped structures 114 are disposed between the respective trenches 122. As described above, sacrificial layer 108 will be incorporated into transistor 54 (see [link to process description]) in subsequent processes. Figures 1A to 1B Selective replacement of character lines. The subsequently formed wires can be separated from each other by etching trenches 122 through sacrificial layer 108.

[0098] In Figure 12, the sacrificial layer 108 is removed to form sidewall openings 124. Sidewall openings 124 extend between adjacent trenches 122. Sidewall openings 124 can be formed by any acceptable etching process, such as a process selectively removing the material of the sacrificial layer 108 (e.g., selectively removing the material of the sacrificial layer 108 at a faster rate than removing the material of the dielectric layer 106). The etching can be isotropic. In an embodiment where the dielectric layer 106 is formed of silicon oxide and the sacrificial layer 108 is formed of silicon nitride, the sacrificial layer 108 can be removed by wet etching using phosphoric acid (H3PO4). In another embodiment, dry etching selectively removing the material of the sacrificial layer 108 can be used.

[0099] exist Figure 13 In this process, word lines 126 (including word lines 126A, 126B, and 126C) for the memory array 50 are formed in sidewall openings 124, thereby completing the process of replacing the sacrificial layer 108 with wires. Each word line 126 may include one or more layers, such as a seed layer, adhesive layer, barrier layer, diffusion layer, filler layer, or the like. In some embodiments, each word line 126 includes a pair of pad layers 128, such as a diffusion barrier layer, adhesive layer, or the like, and a main layer 130 sandwiched between the pad layers 128. Each pad layer 128 extends along the top surface of the bottom surface of the corresponding main layer 130 located within the corresponding sidewall opening 124. The pad layers 128 are formed of a first conductive material that can be used to aid in the growth or adhesion of subsequently deposited materials, such as metal nitrides, such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like. The main layer 130 may be formed of a second conductive material, such as a metal, such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, their alloys, or similar. The material of the pad layer 128 is a material that has good adhesion to the material of the dielectric layer 106, while the material of the main layer 130 is a material that has good adhesion to the material of the pad layer 128 and has low resistivity. In some embodiments, the pad layer 128 is formed of titanium nitride and the main layer 130 is formed of tungsten. The materials of the pad layer 128 and the main layer 130 may be formed by acceptable deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes. For example, the pad layer 128 may be deposited in the trench 122 and around the dielectric layer 106 using a conformal deposition process such as atomic layer deposition, and the main layer 130 may subsequently be deposited on the pad layer 128 using a conformal deposition process such as atomic layer deposition. Any acceptable etching process can be performed, such as dry etching (e.g., reactive ion etching (RIE), neutral particle beam etching (NBE), or similar), wet etching, or similar processes or combinations thereof, to remove excess material from the sidewalls of dielectric layer 106 in trench 122. The etching can be anisotropic. The thickness of pad layer 128 can be less than the thickness of main layer 130.

[0100] Although not shown separately Figure 13 In this context, it should be understood that character lines 126 are conductors extending in the Y direction. Character lines 126 have a length similar to the sacrificial layer 108 they replace. This is due to the stepped shape of the stepped structure 114 (see, for example...). Figure 11 The character line 126 may have a varying length that increases in the direction toward the substrate 102. For example, character line 126A may be longer than character line 126B, and character line 126B may be longer than character line 126C.

[0101] As will be discussed later in Figures 14 to 15 Figure 16 The described conductive spacer 136 (see Figure 16 The conductive spacer 136 will be formed on the sidewall of character line 126. The conductive spacer 136 is formed of a work function material, which can be selected to adjust the work function of transistor 54 to a desired amount (see [link to documentation]). Figures 1A to 1B The threshold voltage of transistor 54 can therefore be tuned more accurately. In this embodiment, the conductive spacer 136 is formed by a single patterning process. The single patterning process includes recessing the character line 126 to form sidewall recesses 132 (see...). Figure 14 The sidewall recess 132 is filled with conductive layer 134 (see...). Figure 15 ), and remove excess material from the conductive layer 134 in the trench 122 to form conductive spacers 136 (see Figure 16 The conductive spacer 136 can be formed by other acceptable processes. In another embodiment (subsequently discussed) Figures 23 to 24 (As described), the conductive spacer 136 is formed through a multi-patterning process.

[0102] exist Figure 14In this process, trench 122 is extended to form sidewall recesses 132 for conductive spacers between dielectric layers 106. Specifically, the portion of the sidewall of the word line 126 exposed by trench 122 is recessed from the portion of the sidewall of the dielectric layer 106 exposed by trench 122 to form sidewall recesses 132. Sidewall recesses 132 may expose both the top and bottom surfaces of dielectric layer 106. Although the sidewalls of word line 126 are depicted as recessed, the sidewalls may be straight or convex. Sidewall recesses 132 may be formed by any acceptable etching process, such as a selective etching process for the material of word line 126 (e.g., selectively removing material from word line 126 at a rate faster than removing material from dielectric layer 106). The etching may be isotropic. In embodiments where the character line 126 includes a pad layer 128 formed of titanium nitride and a main layer 130 formed of tungsten, and the dielectric layer 106 is formed of silicon oxide, the trench 122 can be extended without plasma by dry etching using fluorine-based etchants (e.g., CF4, SF6, etc.) and / or chlorine-based etchants (e.g., Cl2). In another embodiment, selective wet etching of the material of the character line 126 can be used. In this embodiment, each sidewall groove 132 is formed by the same patterning process.

[0103] After the sidewall recess 132 is formed, the sidewall recess 132 has a depth D1 in the X direction, extending beyond the sidewall of the dielectric layer 106. A timing etch process can be used to stop etching the sidewall recess 132 after it reaches the desired depth D1. In some embodiments, the sidewall recess 132 has a depth D1 in the range of 1 nm to 5 nm. As will be described in more detail later, a work function material is formed in the sidewall recess 132. In some embodiments where the character line 126 includes a pad layer 128 formed of titanium nitride and a main layer 130 formed of tungsten, the sidewall recess 132 may be D-shaped. The sidewall recess 132 may be D-shaped because the pad layer 128 is recessed by a smaller distance than the main layer 130. For example, the etch process for patterning the sidewall recess 132 can remove material from the main layer 130 at a faster rate than the material removed from the pad layer 128. In other embodiments, the sidewall recess 132 may have other shapes.

[0104] exist Figure 15In this structure, a conductive layer 134 for conductive spacers is formed in sidewall recesses 132 and trenches 122. The conductive layer 134 can contact the top and bottom surfaces of the dielectric layer 106 and the sidewalls of the word lines 126. The conductive layer 134 can be formed in the sidewall recesses 132 by depositing the conductive layer 134 in the trenches 122 and sidewall recesses 132 until the sidewall recesses 132 are filled (or overfilled). The conductive layer 134 can be formed of any acceptable work function material to adjust the work function of the transistor to the amount required according to the application of the transistor to be formed, and it can be deposited by any acceptable deposition process. The material of the conductive layer 134 has a different work function than the material of the word lines 126. In some embodiments, the conductive layer 134 is formed of a metal or metal nitride, such as cobalt (Co), ruthenium (Ru), tungsten (W), tungsten nitride (WN0.8), tungsten carbonitride (WCN), molybdenum (Mo), molybdenum nitride (MoN), titanium nitride (TiN), combinations thereof, or the like, which may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like. In some embodiments, the conductive layer 134 is formed of a metal having a work function in the range of 4.5 eV to 5 eV, for example, at least 4.7 eV. Although the conductive layer 134 is drawn as a single layer, the conductive layer 134 may be multilayered.

[0105] The material of the conductive layer 134 is one that can be deposited at low temperatures. In some embodiments, the material of the conductive layer 134 can be deposited at a temperature of up to (e.g., less than or equal to) 500°C to meet the thermal budget of the back-end process and reduce defects that may result in additional features due to high-temperature deposition. For example: cobalt can be deposited at temperatures below 200°C by plasma-enhanced chemical vapor deposition; ruthenium can be deposited at temperatures below about 200°C by chemical vapor deposition; tungsten can be deposited at about 350°C by atomic layer deposition; tungsten nitride can be deposited at about 400°C by atomic layer deposition; tungsten carbonitride can be deposited at about 400°C by atomic layer deposition; molybdenum can be deposited at about 430°C to about 500°C by atomic layer deposition; molybdenum nitride can be deposited at about 400°C to about 500°C by atomic layer deposition; and titanium nitride can be deposited at about 430°C by atomic layer deposition.

[0106] In Figure 16, excess material of the conductive layer 134 in trench 122 is removed to form conductive spacers 136. Specifically, portions of the conductive layer 134 in trench 122, such as those on the sidewalls of dielectric layer 106, are removed. Any acceptable etching process can be performed, such as dry etching (e.g., reactive ion etching (RIE), neutral particle beam etching (NBE), or similar), wet etching, similar processes, or combinations thereof, to remove excess material of the conductive layer 134. The etching can be anisotropic. After etching, the conductive layer 134 has portions retained in the sidewall recesses 132 (thus forming conductive spacers 136). In some embodiments, the thickness of the conductive spacers 136 in the X direction is in the range of 1 nm to 5 nm. The conductive spacers 136 are disposed on the sidewalls of word lines 126 and separate word lines 126 from the subsequently formed memory film. Transistor 54 (see...) Figures 1A to 1B The gate of the memory cell is provided by a combination of word line 126 and conductive spacer 136, wherein conductive spacer 136 provides a work function tuning layer for the gate. As will be described in more detail later, conductive spacer 136 allows word line 126 to be electrically connected to a portion of the memory film while preventing word line 126 from physically contacting a portion of the memory film. Although the outer sidewall of conductive spacer 136 is drawn flush with the sidewall of dielectric layer 106, the outer sidewall of conductive spacer 136 may extend beyond or from the sidewall recess of dielectric layer 106. In other words, conductive spacer 136 may partially fill, fully fill, or overfill sidewall recess 132. Furthermore, although the sidewall of conductive spacer 136 is drawn recessed, the sidewall of conductive spacer 136 may be straight or convex.

[0107] exist Figure 17 In this structure, a memory thin film 142, a semiconductor thin film 144, and an isolation region 146 are formed in a trench 122. The memory thin film 142 is formed above the substrate 102, on the sidewalls of the dielectric layer 106, and on the sidewalls of the conductive spacer 136. The semiconductor thin film 144 is formed on the sidewalls of the memory thin film 142. A portion of the memory thin film 142 provides a gate dielectric for the transistor 54 (see...). Figures 1A to 1B A portion of the semiconductor thin film 144 provides a channel region for the transistor 54. An isolation region 146 extends through the semiconductor thin film 144, thereby separating the semiconductor thin films 144 of horizontally adjacent transistors 54 along the X direction. In the illustrated embodiment, the isolation region 146 extends through the memory thin film 142, thus also separating the memory thin film 142 of horizontally adjacent transistors 54 along the X direction. In another embodiment, the isolation region 146 is formed on the memory thin film 142 and does not extend through the memory thin film 142.

[0108] The memory film 142 is formed of any acceptable material for storing digital values, such as a material capable of switching between two different polarization directions by applying an appropriate voltage difference across the material. For example, the polarization of the material may be altered by an electric field generated by applying a voltage difference. In some embodiments, the memory film 142 is formed of a high-dielectric ferroelectric material, such as a hafnium (Hf)-based dielectric material, such as hafnium zirconium oxide (HfZrO); zirconium oxide (ZrO); hafnium oxide (HfO) or similar doped with lanthanum (La), silicon (Si), aluminum (Al), etc.; undoped hafnium oxide (HfO); or similar. In some embodiments, the memory film 142 is a multilayer structure including a silicon nitride layer (e.g., an oxide-nitride-oxide structure) between two silicon oxide layers. Other acceptable memory materials may be used. The material of the memory film 142 may be formed by any acceptable deposition process such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or similar methods. In some embodiments, the memory film 142 is formed with a thickness in the range of 3 nm to 20 nm. The memory film 142 can be formed to a greater thickness than the conductive spacer 136.

[0109] The semiconductor thin film 144 is formed of any acceptable material and is used to provide a channel region for a transistor. The semiconductor thin film 144 may be formed of a thin-film semiconductor material suitable for providing a channel region for a thin-film transistor (TFT). In some embodiments, the semiconductor thin film 144 is formed of an oxide semiconductor, such as an indium-based semiconductor material, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), or the like. In some embodiments, the semiconductor thin film 144 is formed of a silicon-based semiconductor material, such as polycrystalline silicon, amorphous silicon, or the like. Other acceptable semiconductor materials may be used. The material of the semiconductor thin film 144 may be formed by any acceptable deposition process, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or similar processes. In some embodiments, the semiconductor thin film 144 is formed with a thickness in the range of 3 nm to 20 nm. The semiconductor thin film 144 may be formed with a thickness greater than that of the conductive spacer 136.

[0110] The isolation region 146 is formed of any acceptable material used for protecting and electrically isolating the memory film 142. Acceptable dielectric materials for the isolation region 146 include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; the like; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. Other acceptable dielectric materials may be used. The material of the isolation region 146 may be formed by any acceptable deposition process, such as atomic layer deposition, chemical vapor deposition, flow chemical vapor deposition (FCVD), or similar processes.

[0111] The memory film 142, semiconductor film 144, and isolation region 146 can be formed by a combination of deposition, etching, and planarization. For example, the memory layer can be conformally deposited in the trench 122 (e.g., on the sidewalls of the conductive spacer 136 and the dielectric layer 106). The semiconductor layer can then be conformally deposited on the memory layer. The semiconductor layer can then be patterned using a suitable etching process, such as anisotropic etching using the memory layer as an etch stop layer. The memory layer can then be patterned using a suitable etching process, such as anisotropic etching using the patterned semiconductor layer as an etch mask. An isolation material can then be conformally deposited in the remaining portion of the trench 122 (e.g., on the patterned semiconductor layer and the exposed portion of the memory layer). A removal process is then applied to each layer to remove excess material above the upper dielectric layer 106 / word line 126. The portions of the memory layer, semiconductor layer, and isolation material remaining in the trench 122 after the removal process form the memory film 142, semiconductor film 144, and isolation region 146, respectively. The removal process can be a planarization process, such as a chemical mechanical polishing (CMP) process, an etch-back process, a combination thereof, or a similar process. After the planarization process, the top surfaces of the memory thin film 142, the semiconductor thin film 144, the isolation region 146, and the upper dielectric layer 106 / word line 126 are coplanar (within process variations), making them flush with each other.

[0112] As previously described, the conductive spacer 136 is formed of a work function material. The work function material of the conductive spacer 136 is selected based on the desired work function of the transistor 54 (see [link to documentation]). Figures 1A to 1B The threshold voltage of transistor 54 can therefore be tuned more accurately. Specifically, the threshold voltage of transistor 54 can be tuned to a threshold voltage that allows for easier change of the polarization direction of memory film 142. In some embodiments, the work function material of conductive spacer 136 has a work function in the range of 4.5 eV to 5 eV, for example, at least 4.7 eV. Some materials with the desired work function have high resistivity. For example, titanium nitride has a work function of about 4.6 eV, but a resistivity of about 300 µΩ·cm. The conductive spacer 136, which is formed of a work function material (instead of word line 126), allows transistor 54 to include a material with the desired work function while reducing the amount of high-resistivity material used. Word line 126 can therefore be formed of a material with low resistivity, such as tungsten. Thus, the material of word line 126 advantageously has a lower resistivity than the material of conductive spacer 136. Reducing the resistance of word line 126 helps to improve the performance of memory array 50.

[0113] Furthermore, the material of the conductive spacer 136 has good adhesion to both the word line 126 and the memory film 142. The adhesion between the memory film 142 and the conductive spacer 136 is better than its adhesion to the word line 126. Transistor 54 (see...) Figures 1A to 1B The number of interface traps between the gate dielectric and the gate can thus be reduced. Reducing the number of interface traps can increase the durability of the memory film 142, allowing it to maintain longer read / write cycles and increasing the lifetime of the memory array 50.

[0114] exist Figures 18A to 18B In this process, an opening 148 for a conductor is formed through an isolation region 146. The opening 148 can be formed by selectively removing material from the isolation region 146 (e.g., selectively removing material from the isolation region 146 at a faster rate than removing material from the memory film 142 and the semiconductor film 144). The etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral particle beam etching (NBE), similar processes, or combinations thereof. The etching can be anisotropic. For example, the opening 148 can be formed by dry etching through the isolation region 146 using ammonia (NH3) and hydrogen fluoride (HF) gases, which can be performed using an etch mask with a pattern subsequently formed for the conductor.

[0115] In Figure 19A to Figure 19B In the semiconductor thin film 144, a wire 152 is formed in an opening 148 on the sidewall. Therefore, the wire 152 extends through the isolation region 146. As discussed in more detail below, the wire 152 is a cylinder extending in the Z direction, which will be divided into bit lines and source lines of the transistor 54 (see...). Figures 1A to 1B Therefore, the wire 152 partially contacts the semiconductor thin film 144, such that the bit line and source line will be adjacent to the channel region of the transistor 54. In embodiments where the isolation region 146 extends through the memory thin film 142, the wire 152 partially contacts the memory thin film 142.

[0116] As an example of forming the conductor 152, a pad, such as a diffusion barrier layer, an adhesive layer, or the like, and a main layer are formed in the opening 148. The pad may be formed of a conductive material, such as a metal or metal nitride, such as titanium, titanium nitride, tantalum, tantalum nitride, or the like, which can be deposited by conformal deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or similar processes. In some embodiments, the pad may include an adhesive layer, and at least a portion of the adhesive layer may be processed to form a diffusion barrier layer. The main layer may be formed of a conductive material, such as a metal, such as tungsten, cobalt, ruthenium, aluminum, nickel, copper, copper alloys, silver, gold, or the like, which can be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, or similar processes. In some embodiments, the conductor 152 and the character line 126 comprise the same conductive material (e.g., tungsten). In some embodiments, the conductor 152 comprises a pad formed of titanium nitride and a main layer formed of tungsten. Subsequently, a removal process is applied to each layer to remove the upper dielectric layer 106 / word line 126, memory film 142, semiconductor film 144, and isolation region 146. The material remaining in the opening 148 after the removal process forms the conductive line 152. The removal process can be a planarization process, such as chemical mechanical polishing (CMP), etch-back, or a combination thereof. After the planarization process, the top surfaces of the upper dielectric layer 106 / word line 126, memory film 142, semiconductor film 144, isolation region 146, and conductive line 152 are coplanar (within the range of process variations), placing them at the same level.

[0117] exist Figure 20A In section 20B, an opening 154 in the isolation region is formed by a wire 152. The opening 154 separates the semiconductor thin film 144 from the wire 152 to form the transistor 54 (see section 20B). Figures 1A to 1B Specifically, each wire 152 is separated to form a bit line 152B and a source line 152S. An opening 154 can divide the wire 152 into bit lines 152B and source lines 152S of equal or unequal width. As described above, the bit lines 152B and source lines 152S serve as the source / drain electrodes of the transistor 54. In the illustrated embodiment, the opening 154 does not extend through the memory film 142. In another embodiment, the opening 154 extends through the memory film 142 such that it separates the memory film 142. After forming the opening 154, each transistor 54 includes a portion of the memory film 142, a portion of the semiconductor film 144, a portion of the bit line 152B, and a portion of the source line 152S.

[0118] In this embodiment, bit lines 152B and source lines 152S are formed in an alternating arrangement. Specifically, bit lines 152B and source lines 152S are arranged in an alternating pattern, and adjacent bit lines 152B / source lines 152S along the X direction are laterally offset from each other along the Y direction. As will be described in more detail laterally, this lateral offset of bit lines 152B and source lines 152S eliminates the need for lateral interconnects when subsequently interconnecting transistors to form functional memory. In another embodiment, bit lines 152B and source lines 152S are not formed in an alternating arrangement, such that adjacent bit lines 152B / source lines 152S along the X direction are laterally aligned along the Y direction.

[0119] Opening 154 can be formed by a selective etching process of semiconductor thin film 144 and / or wire 152 (e.g., selectively removing material from semiconductor thin film 144 and / or wire 152 at a faster rate than removing material from memory thin film 142). Etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral particle beam etching (NBE), similar processes, or combinations thereof. Etching can be anisotropic. For example, opening 154 can be formed by dry etching using, for example, C4F6 mixed with hydrogen (H2) or oxygen (O2), which can be performed using an etch mask with a subsequently formed isolation region pattern.

[0120] exist Figures 21A to 21B In this configuration, isolation region 156 is formed in opening 154. Isolation region 156 thus extends through conductor 152 and semiconductor thin film 144. As an example of forming isolation region 156, isolation material is formed in opening 154. Isolation material can be an oxide such as silicon oxide or aluminum oxide. Nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof, such as silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, silicon oxycarbonitride, or the like, can be deposited by chemical vapor deposition, atomic layer deposition, etc. In some embodiments, isolation region 156 is formed of silicon oxide. Subsequently, a removal process is applied to each layer to remove the upper dielectric layer 106 / word line 126, memory thin film 142, semiconductor thin film 144, isolation region 146, source line 152S, and bit line 152B. The isolation material remaining in opening 154 after the removal process forms isolation region 156. The removal process can be a planarization process, such as a chemical mechanical polishing (CMP) process, an etch-back process, a combination thereof, or a similar process. After the planarization process, the upper dielectric layer 106 / word line 126, memory film 142, semiconductor film 144, isolation region 146, source line 152S, bit line 152B, and the top surface of the isolation region 156 are coplanar (within the process variation range) so that they are at the same level as each other.

[0121] exist Figures 22A to 22C In this structure, one or more interconnect layers 160 for interconnection are formed above an intermediate structure. Each interconnect layer 160 includes an interconnect 162 in a dielectric layer 164. The dielectric layer 164 may include one or more layers of dielectric material, such as one or more layers of low-dielectric (LK) or ultra-low-dielectric (ELK) dielectric material. The interconnect 162 may be a metal interconnect (including wires 162L and conductive vias 162V) formed in the dielectric layer 164. The interconnect 162 is connected to bit lines 152B and source lines 152S and interconnect transistors 54 to form a functional memory. The interconnect layers 160 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or a similar process.

[0122] As described above, the dielectric layer 106 and the word line 126 can be formed in a stepped configuration. In such an embodiment, conductive contacts 166 connecting to the exposed portions of the word line 126 can be formed in the intermetallic dielectric 116. For example, prior to forming the overlay interconnect layer 160, material of the intermetallic dielectric 116 can be redeposited to fill any remaining portions of the trench 122 (see [link to documentation]). Figure 11 The conductive contact 166 can then be formed by the intermetallic dielectric 116. The conductive contact 166 can be formed by a damascene process, such as a single damascene process, a double damascene process, or a similar damascene process.

[0123] The first-stage conductive via 162V1 is located above and connected to source line 152S and bit line 152B (see [reference]). Figures 22A to 22B The first-level conductive via 162V1 refers to the conductive vias 162V formed in the first interconnect layer 160A on the bit line 152B, the source line 152S, and the intermetallic dielectric 116. Furthermore, the first-level conductive via 162V1 connects to the word line 126 and passes through the conductive contact 166 (see...). Figure 22C The first-stage conductor 162L1 is above and connected to the first-stage conductive via 162V1 (see...). Figure 22BThe first-level conductors 162L1 refer to the conductors 162L in the first interconnect layer 160A. The first-level conductors 162L1 include bit line interconnects 162B (connected to bit line 152B), source line interconnects 162S (connected to source line 152S), and word line interconnects (not shown separately) (connected to word line 126). In embodiments where bit lines 152B and source lines 152S are formed in an alternating pattern, the bit line interconnects 162B and source line interconnects 162S can be formed as straight conductors. Therefore, lateral interconnects can be omitted from the interconnect layer 160, allowing the bit line interconnects 162B and source line interconnects 162S to be formed in the first interconnect layer 160A formed on the bit lines 152B and source lines 152S. In another embodiment where bit lines 152B and source lines 152S are not arranged in an interleaved manner, bit line interconnects 162B and source line interconnects 162S may be formed in a second interconnect layer 160B, which is formed on bit lines 152B, source lines 152S, and intermetallic dielectric 116. Lateral interconnects may be formed in a first interconnect layer 160A to connect bit line interconnects 162B and source line interconnects 162S to bit lines 152B and source lines 152S, respectively.

[0124] Figures 23 to 24 This is a view of an intermediate stage of the manufacturing process of memory array 50 according to some other embodiments. Figures 23 to 24 It is along Figure 1A as well as Figure 21B The cross-sectional view shown in reference section A-A' is illustrated. A portion of the memory array 50 is depicted. This embodiment is similar to... Figures 2 to 22C The embodiment differs in that the conductive spacers 136 are formed through a multiple patterning process. The multiple patterning process can be a dual patterning process, a quadruple patterning process, or a similar process. Forming the memory array 50 using a multiple patterning process allows each patterning process to be performed at a low pattern density, which helps reduce defects in the memory array 50.

[0125] Figure 23 In the context of Figure 16A cross-sectional view of the memory array 50 at a similar manufacturing stage (e.g., after the formation of conductive spacers 136). In this embodiment, the conductive spacers 136 are formed via a dual patterning process. The dual patterning process includes forming a first subset of conductive spacers 136A and a second subset of conductive spacers 136B, respectively. In some embodiments, conductive spacers 136A are formed of a different work function material than conductive spacers 136B, such that the material of conductive spacers 136A has a different resistivity and / or a different work function than the material of conductive spacers 136B. In this way, memory cells with transistors having different threshold voltages can be formed in the same memory array 50. Forming memory cells with transistors having different threshold voltages allows for easier differentiation of memory cells when accessing memory cells sharing a common bit line 152B or a common source line 152S. In another embodiment, conductive spacers 136A and 136B are formed of the same work function material.

[0126] As an example of forming conductive spacers 136A, 136B, a first subset of trenches 122A can be patterned in the stepped structure 114 (see [link]). Figure 11 Trench 122A can be referenced. Figure 11 The description is patterned. The portion of sacrificial layer 108 exposed by trench 122A can subsequently be replaced with character lines 126. Sacrificial layer 108 can be referenced. Figures 12 to 13 The description is replaced by character line 126. A sidewall groove 132 can then be formed in the groove 122A. The sidewall groove 132 can be referenced... Figure 14 The method described is used to form the structure. A conductive spacer 136A can then be formed in the sidewall groove 132 of the trench 122A. The conductive spacer 136A can be referenced... Figures 14 to 16 The manner described is as follows. A second subset of the trenches 122B can be patterned in the stepped structure 114, either after or before the formation of the conductive spacers 136A (see [link to documentation]). Figure 11 (It can be done according to the relevant information.) Figure 11 The trench 122B is patterned in a manner described. The portion of the sacrificial layer 108 exposed by the trench 122B can then be replaced with character lines 126. The sacrificial layer 108 can be referenced... Figures 12 to 13 The description is replaced by character line 126. A sidewall groove 132 can then be formed in the groove 122B. The sidewall groove 132 can be referenced... Figure 14 The method described is used to form the structure. A conductive spacer 136B can then be formed in the sidewall groove 132 of the trench 122B. The conductive spacer 136B can be referenced... Figures 14 to 16The patterning is formed in the manner described. In this embodiment, trench 122A and the sidewall groove 132 in trench 122A are formed in a first patterning process, and trench 122B and the sidewall groove 132 in trench 122B are formed in a second patterning process, which is different from the first patterning process. For example, the second patterning process can be performed after the first patterning process.

[0127] Figure 24 In the context of Figure 22A A cross-sectional view of the memory array at a similar manufacturing stage (e.g., after the formation of interconnect layer 160). This can be seen in... Figure 23 The structure performs appropriate process steps, such as for Figures 16 to 22C Those described to obtain Figure 24 The structure is as follows. In an embodiment where the conductive spacer 136A is formed of a different work function material than the conductive spacer 136B, each bit line 152B and source line 152S contacts the conductive spacers 136A and 136B formed of the same work function material. Therefore, each transistor selected by the bit line 152B and source line 152S has the same work function. Conversely, each word line 126 contacts the conductive spacers 136A and 136B formed of different work function materials. For example, the conductive spacer 136A may contact a first sidewall of the word line 126, and the conductive spacer 136B may contact a second sidewall opposite to the word line 126. Therefore, the word line 126 can be used to select a transistor with a desired work function by changing the voltage applied through the word line 126.

[0128] The embodiment offers several advantages. The inclusion of conductive spacer 136 allows the work function of the transistor to be tuned by selecting the work function material of conductive spacer 136 rather than by selecting the material of word line 126. Word line 126 can therefore be formed of a material with low resistivity (e.g., tungsten) while still allowing tuning of the transistor's work function. Reducing the resistance of word line 126 helps improve the performance of memory array 50. Furthermore, conductive spacer 136 serves as an adhesion layer to improve adhesion between word line 126 and memory film 142. This can thus reduce the number of interface traps between the gate dielectric and the gate of transistor 54 (see [link]). Figures 1A to 1B Reducing the number of interface traps can increase the durability of the memory film 142, allowing it to maintain more read / write cycles and increasing the lifespan of the memory array 50.

[0129] In one embodiment, an apparatus includes: a first word line above a substrate, the first word line comprising a first conductive material; a second first word line intersecting the first word line; a first memory film located between the first first word line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer comprising a second conductive material having a different work function than the first conductive material, and the first conductive material having a lower resistivity than the second conductive material. In some embodiments, the apparatus further includes: a second bit line intersecting the first word line; a second memory film between the second bit line and the first word line; and a second conductive spacer located between the second memory film and the first word line, the second conductive spacer comprising a second conductive material. In some embodiments, the device further includes: a second bit line intersecting the first word line; a second memory film between the second bit line and the first word line; and a second conductive spacer between the second memory film and the first word line, the second conductive spacer comprising a third conductive material having a work function different from that of the second conductive material and the first conductive material, the first conductive material having a lower resistivity than the third conductive material. In some embodiments, the device further includes: a second word line above the first word line, intersecting the second word line; a second memory film located between the first word line and the second word line; and a second conductive spacer located between the second memory film and the second word line, the second conductive spacer comprising a second conductive material. In some embodiments of the device, the first conductive spacer is disposed on the sidewall of the first word line, and the device further includes: a dielectric layer located above a substrate, the first word line and the first conductive spacer being disposed between a pair of dielectric layers. The sidewall of the first word line is recessed from the sidewall of the dielectric layer, and the outer sidewall of the first conductive spacer is flush with the sidewall of the dielectric layer. In some embodiments of the device, the first character line includes a main layer located between pad layers, and a first conductive spacer is disposed on the sidewalls of the main layer and the sidewalls of the pad layers. The device further includes a dielectric layer above a substrate, the first character line, and the first conductive spacer disposed between a pair of dielectric layers. The sidewalls of the main layer are recessed from the sidewalls of the dielectric layers by a first distance, and the sidewalls of the pad layers are recessed from the sidewalls of the dielectric layers by a second distance, the second distance being smaller than the first distance. In some embodiments of the device, the first conductive material is tungsten, and the second conductive material is cobalt, ruthenium, tungsten, tungsten nitride, tungsten carbonitride, molybdenum, molybdenum nitride, or titanium nitride. In some embodiments of the device, the first memory film has a thickness greater than that of the first conductive spacer.

[0130] In one embodiment, a device includes: a memory cell above a substrate, the memory cell including a thin-film transistor (TFT), the TFT including: a gate including a first wire and a portion of a work function tuning layer disposed on a sidewall of the first wire, the first wire extending along a first direction; a gate dielectric including a portion of a memory film disposed on a sidewall of the work function tuning layer; a channel region including a portion of a semiconductor film disposed on a sidewall of the memory film; and a source / drain electrode including a portion of a second wire disposed on a sidewall of the semiconductor film, the second wire extending along a second direction perpendicular to the first direction. In some embodiments of the device, the first and second wires include a first conductive material, the work function tuning layer includes a second conductive material, and the first conductive material has a resistivity lower than that of the second conductive material. In some embodiments of the device, the first and second wires include a first conductive material, the work function tuning layer includes a second conductive material, and the first conductive material has a work function different from that of the second conductive material. In some embodiments, the device further includes: an interconnect above the memory cell, the interconnect connecting to the first and second wires.

[0131] In one embodiment, a method includes: forming a word line between a pair of dielectric layers, the word line being formed of a first conductive material; recessing a first sidewall of the word line from the first sidewall of the dielectric layers to form a first sidewall groove between the dielectric layers; forming a conductive spacer in the first sidewall groove and on the first sidewall of the word line, the first conductive spacer being formed of a second conductive material different from the first conductive material; forming a memory film on the sidewall of the first conductive spacer and on the first sidewall of the dielectric layers; forming a semiconductor film on the sidewall of the memory film; and forming a bit line on the sidewall of the semiconductor film. In some embodiments, the method further includes: recessing a second sidewall of the word line from a plurality of second sidewalls of the dielectric layers to form a second sidewall groove between the dielectric layers, the second sidewall of the word line opposite to the first sidewall of the word line; and forming a second conductive spacer in the second sidewall groove and on the second sidewall of the word line, the second conductive spacer being formed of a third conductive material different from the second conductive material and the first conductive material. In some embodiments of this method, the first sidewall of the character line is recessed in a first patterning process, the second sidewall of the character line is recessed in a second patterning process, and the second patterning process is performed after the first patterning process. In some embodiments, the method further includes: recessing the second sidewall of the character line from a plurality of second sidewalls of a dielectric layer to form a second sidewall groove between the dielectric layers, the second sidewall of the character line being opposite to the first sidewall of the character line; and forming a second conductive spacer in the second sidewall groove and on the second sidewall of the character line, the second conductive spacer being formed of a second conductive material. In some embodiments of the method, the first sidewall and the second sidewall of the character line are recessed in the same patterning process. In some embodiments of the method, forming the character line includes: etching a trench in a stepped structure, the stepped structure including a dielectric layer and a sacrificial layer between the dielectric layers; removing a portion of the sacrificial layer to form a sidewall opening between the dielectric layers; depositing a first conductive material in the sidewall opening and the trench; removing a portion of the first conductive material in the trench, a portion of the first conductive material remaining in the sidewall opening forming the character line. In some embodiments of the method, forming the first conductive spacer includes: depositing a second conductive material in a first sidewall groove and a trench; removing a portion of the second conductive material from the trench, leaving a portion of the second conductive material in the first sidewall groove forming the first conductive spacer. In some embodiments of the method, the second conductive material is deposited at a temperature less than or equal to 500°C.

[0132] The foregoing disclosure outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, characterized in that, include: A first character line is located above a substrate, the first character line comprising a first conductive material; The first character line intersects with the first character line; A first memory film, between the first bit line and the first word line; and A first conductive spacer is provided between the first memory film and the first character line. The first conductive spacer is in solid contact with one sidewall of the first character line. The first conductive spacer includes a second conductive material having a work function different from that of the first conductive material. The first conductive material has a resistivity lower than that of the second conductive material.

2. The apparatus as claimed in claim 1, characterized in that, Also includes: A second bit line intersects with the first bit line; A second memory film is located between the second bit line and the first word line; as well as A second conductive spacer is provided between the second memory film and the first character line, and the second conductive spacer includes the second conductive material.

3. The apparatus as described in claim 2, characterized in that, Also includes: A second character line intersects with the first character line; A second memory film, between the second bit line and the first word line; and A second conductive spacer is provided between the second memory film and the first word line. The second conductive spacer includes a third conductive material having a work function different from that of the second conductive material and the first conductive material. The first conductive material has a resistivity lower than that of the third conductive material.

4. The apparatus as claimed in claim 1, characterized in that, Also includes: A second character line is located above the first character line, where the first character line intersects with the second character line; A second memory film, between the first word line and the second word line; and A second conductive spacer is provided between the second memory film and the second character line, the second conductive spacer comprising the second conductive material.

5. The apparatus as claimed in claim 1, characterized in that, Also includes: Multiple dielectric layers are disposed above the substrate, with the first character line and the first conductive spacer disposed between a pair of the multiple dielectric layers, the sidewall of the first character line being recessed from the sidewall of the multiple dielectric layers, and an outer sidewall of the first conductive spacer being flush with the sidewall of the multiple dielectric layers.

6. The apparatus as claimed in claim 1, characterized in that, The first character line includes a main layer located between multiple pad layers, the first conductive spacer being disposed on one side wall of the main layer and multiple side walls of the multiple pad layers, and the device further includes: A plurality of dielectric layers are disposed above the substrate, wherein the first character line and the first conductive spacer are disposed between a pair of the plurality of dielectric layers, the sidewall of the main layer is recessed from the plurality of sidewalls of the plurality of dielectric layers by a first distance, and the plurality of sidewalls of the plurality of pad layers are recessed from the plurality of sidewalls of the plurality of dielectric layers by a second distance, the second distance being smaller than the first distance.

7. The apparatus as claimed in claim 1, characterized in that, The first conductive material is tungsten, and the second conductive material is cobalt, ruthenium, tungsten, tungsten nitride, tungsten carbonitride, molybdenum, molybdenum nitride, or titanium nitride.

8. The apparatus as claimed in claim 1, characterized in that, The first memory film has a thickness greater than that of the first conductive spacer.

9. A memory device, characterized in that, include: A memory cell is located above a substrate, the memory cell including a thin-film transistor, the thin-film transistor further including: A gate includes a first word line and a portion of a conductive spacer, the conductive spacer being disposed on a sidewall of the first word line and substantially contacting the sidewall of the first word line, the first word line extending along a first direction. A gate dielectric, including a portion of a memory film disposed on one sidewall of the conductive spacer. A channel region includes a portion of a semiconductor thin film disposed on one sidewall of the memory thin film; as well as A source / drain electrode includes a portion of a wire disposed on a sidewall of the semiconductor thin film, the wire extending along a second direction perpendicular to the first direction.

10. The apparatus as claimed in claim 9, characterized in that, The first character line and the conductor include a first conductive material, the conductive spacer includes a second conductive material, and the first conductive material has a resistivity lower than that of the second conductive material.

11. The apparatus as claimed in claim 9, characterized in that, The first character line and the conductor include a first conductive material, the conductive spacer includes a second conductive material, and the first conductive material has a work function different from that of the second conductive material.

12. The apparatus as claimed in claim 9, characterized in that, The device also includes: Multiple interconnects are located above the memory cell and connected to the first character line and the wire.

13. A method for forming a memory device, characterized in that, include: A word line is formed between a pair of dielectric layers, and the word line is formed of a first conductive material; A first sidewall recessing the character line forms a first sidewall groove between the dielectric layers by extending from the first sidewall of the dielectric layer. A first conductive spacer is formed in the first sidewall groove and on the first sidewall of the character line. The first conductive spacer is formed of a second conductive material, which is different from the first conductive material. A memory film is formed on one sidewall of the first conductive spacer and on the first sidewall of the dielectric layer; A semiconductor thin film is formed on one sidewall of the memory thin film; as well as A bit line is formed on one sidewall of the semiconductor thin film.

14. The method as described in claim 13, characterized in that, Also includes: A second sidewall recessed in the character line is formed from a plurality of second sidewalls of the dielectric layers to form a second sidewall groove between the dielectric layers, the second sidewall of the character line being opposite to the first sidewall of the character line; as well as A second conductive spacer is formed in the groove of the second sidewall and on the second sidewall of the character line. The second conductive spacer is formed of a third conductive material, which is different from the second conductive material and the first conductive material.

15. The method as described in claim 14, characterized in that, The first sidewall of the character line is recessed in a first patterning process, the second sidewall of the character line is recessed in a second patterning process, and the second patterning process is performed after the first patterning process.

16. The method as described in claim 13, characterized in that, Also includes: A second sidewall recessing the character line is formed from the plurality of second sidewalls of the plurality of dielectric layers to create a second sidewall groove between the plurality of dielectric layers, the second sidewall of the character line being opposite to the first sidewall of the character line; and A second conductive spacer is formed in the groove of the second sidewall and on the second sidewall of the character line, the second conductive spacer being formed of the second conductive material.

17. The method as described in claim 16, characterized in that, Also includes: The first sidewall and the second sidewall of the character line are recessed in the same patterning process.

18. The method as described in claim 13, characterized in that, The character line consists of: A trench is etched in a stepped structure, the stepped structure including the plurality of dielectric layers and a sacrificial layer between the plurality of dielectric layers; A portion of the sacrificial layer is removed to form a sidewall opening between the plurality of dielectric layers; A first conductive material is deposited in the sidewall opening and the trench; and Remove a portion of the first conductive material from the trench, leaving a portion of the first conductive material in the sidewall opening that forms the character line.

19. The method as described in claim 18, characterized in that, The first conductive spacer comprises: The second conductive material is deposited in the first sidewall groove and the trench; Remove a portion of the second conductive material from the trench, leaving a portion of the second conductive material in the first sidewall groove that forms the first conductive spacer.

20. The method as described in claim 19, characterized in that, The second conductive material is deposited at a temperature of less than or equal to 500°C.

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