Light emitting display device

Abstract

A light emitting display apparatus is provided, including a pixel circuit unit, a data distribution unit, a plurality of signal generation units, a unit light emitting diode, and a dummy opening. The pixel circuit unit is configured to generate an output current. The data distribution unit is configured to apply a data voltage to the pixel circuit unit through a data line. The plurality of signal generation units are respectively configured to apply a scan signal and a light emission control signal to the pixel circuit unit through a plurality of signal lines. The unit light emitting diode is configured to receive the output current of the pixel circuit unit and attached to the pixel circuit unit. The dummy opening is formed in an area where the pixel circuit unit, the data distribution unit, and the plurality of signal generation units are not positioned.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2021-0058692, filed on May 6, 2021, with the Korean Intellectual Property Office, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0002] One or more embodiments generally relate to a light-emitting display device, and more specifically, to a light-emitting display device using light-emitting diodes (LEDs). Background Technology

[0003] Display devices are devices used to display images; liquid crystal displays (LCDs) and light-emitting displays are examples of display devices. However, various display devices have been developed, and display devices including those using inorganic light-emitting diodes (LEDs) are also under development. The advantage of display devices using inorganic LEDs is that they do not have the disadvantage of light-emitting displays, which suffer from a drastic reduction in lifespan when exposed to moisture or air. Thus, no encapsulation layer is required, allowing inorganic LEDs to be used in outdoor environments where temperatures may be high or low, or where precipitation (e.g., rain, snow, etc.) may occur. Furthermore, large-screen display devices are being developed and can be used for outdoor advertising or performance halls, enabling images to be recognized from a distance.

[0004] The information disclosed in this section is only for understanding the background of the inventive concept and may therefore contain information that does not form prior art. Summary of the Invention

[0005] One or more embodiments can provide a light-emitting display device in which the thin-film transistor does not have different characteristics depending on its location.

[0006] One or more embodiments are capable of providing a light-emitting display device that can be used without problems typically associated with outdoor environments.

[0007] Other aspects will be set forth in the detailed description below, and will be partly apparent from disclosure or may be learned through practice of the inventive concept.

[0008] According to an embodiment, a light-emitting display device includes a pixel circuit unit, a data distribution unit, a plurality of signal generation units, a unit light-emitting diode, and a dummy opening. The pixel circuit unit is configured to generate an output current. The data distribution unit is configured to apply a data voltage to the pixel circuit unit via data lines. The plurality of signal generation units are respectively configured to apply a scan signal and a light emission control signal to the pixel circuit unit via multiple signal lines. The unit light-emitting diode is configured to receive the output current of the pixel circuit unit and is attached to the pixel circuit unit. The dummy opening is formed in an area where the pixel circuit unit, data distribution unit, and plurality of signal generation units are not positioned.

[0009] According to an embodiment, a light-emitting display device includes a plurality of light-emitting display devices attached to each other. At least one of the plurality of light-emitting display devices includes a pixel circuit unit, a data distribution unit, a plurality of signal generation units, a unit light-emitting diode, and a dummy opening. The pixel circuit unit is configured to generate an output current. The data distribution unit is configured to apply a data voltage to the pixel circuit unit via a data line. The plurality of signal generation units are respectively configured to apply a scan signal and a light emission control signal to the pixel circuit unit via a plurality of signal lines. The unit light-emitting diode is configured to receive the output current of the pixel circuit unit and is attached to the pixel circuit unit. The dummy opening is formed in a region where the pixel circuit unit, the data distribution unit, and the plurality of signal generation units are not positioned.

[0010] According to various embodiments, when forming a semiconductor layer included in a thin-film transistor, by forming dummy openings in regions of the light-emitting display device where pixel circuit units for driving light-emitting diodes (LEDs) or driver units for driving pixel circuit units are not positioned, the problem of hydrogen not being removed (or expelled) depending on the location of the thin-film transistor is eliminated (or at least mitigated), so that the characteristics of the thin-film transistor do not vary depending on its location, and can be uniform (or relatively uniform) throughout the light-emitting display device. Furthermore, in the light-emitting display device, even at locations with different component integration densities, the characteristics of the thin-film transistor can be uniform (or relatively uniform).

[0011] According to various embodiments, even if a light-emitting display device with thin-film transistors having uniform characteristics depending on the location of the thin-film transistors is installed in an outdoor environment where the temperature may be high or low, or where it may rain or snow, the degradation of display quality due to the deterioration of the characteristics of the thin-film transistors will not occur or will at least be mitigated.

[0012] The preceding general description and the following detailed description are illustrative and explanatory, and are intended to provide further explanation of the claimed subject matter. Attached Figure Description

[0013] The accompanying drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. The drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification.

[0014] Figure 1 This is a diagram showing the division of regions of a light-emitting display device according to an embodiment.

[0015] Figure 2 This is a layout diagram of the central region of a light-emitting display device according to an embodiment.

[0016] Figure 3 This is an upper layout view of the driving area of ​​a light-emitting display device according to an embodiment.

[0017] Figure 4 This is a lower layout view of the driving area of ​​a light-emitting display device according to an embodiment.

[0018] Figure 5 This is a layout diagram of the pixel circuit unit and its surroundings of a light-emitting display device according to an embodiment.

[0019] Figure 6 According to the embodiments Figure 5 The cross-sectional view of the section line VI-VI'-VI” and the surrounding pixel circuit unit.

[0020] Figure 7 This is a layout diagram of the pixel circuit unit of a light-emitting display device according to an embodiment.

[0021] Figure 8 This is a circuit diagram of the pixels of a light-emitting display device according to an embodiment.

[0022] Figure 9 It is applied according to the embodiment to Figure 8 The waveform of the signal of the pixel.

[0023] Figure 10A and Figure 10B This is an upper layout diagram of the driving area of ​​a light-emitting display device according to various embodiments.

[0024] Figure 11 This is a view showing the area where the opening according to an embodiment may be located in the light-emitting display device.

[0025] Figure 12 This is a view illustrating a light-emitting display device including a dummy driver according to an embodiment.

[0026] Figure 13 This is a circuit diagram of a stage configured to output an optical emission signal according to an embodiment.

[0027] Figure 14This is a layout diagram of a stage configured to output an optical emission signal according to an embodiment.

[0028] Figure 15 This is a cross-sectional view of a stage configured to output an optical emission signal according to an embodiment.

[0029] Figure 16 This is a circuit diagram of a stage configured to output a scan signal according to an embodiment.

[0030] Figure 17 This is a layout diagram of a stage configured to output a scan signal according to an embodiment.

[0031] Figure 18 This is a cross-sectional view of a stage configured to output a scan signal according to an embodiment.

[0032] Figure 19 This is a circuit diagram of the data allocation unit according to an embodiment.

[0033] Figure 20 This is a layout diagram of the data allocation unit according to an embodiment.

[0034] Figure 21 This is a cross-sectional view of the data allocation unit according to an embodiment.

[0035] Figure 22 It is a waveform diagram of the signals applied to the stage configured to output an optical emission signal, the stage configured to output a scan signal, and the data distribution unit, and their output signals, according to the embodiment.

[0036] Figure 23 This is a view showing the difference in display brightness of the light-emitting display devices according to a comparative example.

[0037] Figure 24 This is a view showing that the display brightness of the light-emitting display device according to an embodiment is uniform.

[0038] Figure 25 This is a schematic diagram of a large-size display device according to an embodiment.

[0039] Figure 26 , Figure 27 and Figure 28 This is a view showing various arrangements of dummy openings according to various embodiments. Detailed Implementation

[0040] In the following description, numerous specific details are set forth for purposes of explanation to provide a thorough understanding of the various embodiments. As used herein, the terms "embodiment" and "implementation" are used interchangeably and are non-limiting examples employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and arrangements are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different, but are not necessarily exclusive. For example, a particular shape, construction, and characteristic of an embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0041] Unless otherwise stated, the illustrated embodiments are to be understood as example features providing different details of some embodiments. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions, aspects, etc. (hereinafter, individually or collectively referred to as “elements”) of various examples may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0042] Crosshairs and / or shading are typically used in accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, proportion, commonality between illustrated elements, or any other characteristics, properties, etc. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of individual elements are not necessarily limited to those shown in the accompanying drawings. When embodiments can be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of the described sequence. Furthermore, the same reference numerals denote the same elements.

[0043] When an element, such as a layer, is referred to as being "on" another element, "connected to," or "bonded to" another element, it can be directly on, directly connected to, or directly bonded to the other element, or there may be intermediate elements. However, when an element is referred to as being "directly on" another element, "directly connected to," or "directly bonded to" another element, there are no intermediate elements. Other terms and / or phrases used to describe relationships between elements should be interpreted in a similar manner, such as "between" vs. "directly between," "adjacent" vs. "directly adjacent," "on" vs. "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, and / or a fluid connection. Additionally, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “selection of at least one from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0044] Although the terms “first,” “second,” etc., may be used here to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0045] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” “above,” “above,” “higher,” and “side” (e.g., as in a “sidewall”) may be used herein to describe the relationship of one element to another as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would subsequently be positioned “above” said other elements or features. Thus, the term “below” can include both above and below orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0046] The terminology used herein is for the purpose of describing some embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measured, calculated, and / or provided values ​​that would be recognized by one of ordinary skill in the art. Furthermore, throughout the disclosure, the phrase “in a plan view” indicates a view of the target portion from top, and the phrase “in a sectional view” indicates a view of a section formed by vertically cutting the target portion from the side.

[0047] Various embodiments are described herein with reference to sectional views, isometric views, perspective views, plan views, and / or exploded views as schematic diagrams of idealized embodiments and / or intermediate structures. Thus, variations in the shapes illustrated will be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, but will include deviations in shape due to, for example, manufacturing processes. In this way, the areas shown in the drawings can be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, thus not intended to be limiting.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0049] In accordance with the conventions of the art, some embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of implementing blocks, units, and / or modules by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) that performs the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the inventive concept, each block, unit, and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the inventive concept, blocks, units, and / or modules of some embodiments can be physically combined into more complex blocks, units, and / or modules.

[0050] In the following text, various embodiments will be explained in detail with reference to the accompanying drawings.

[0051] First, refer to Figure 1 To describe the divided areas of the light-emitting display device, and refer to Figures 2 to 6 Describe the structure of each region in more detail.

[0052] Figure 1 This is a diagram showing the division of regions of a light-emitting display device according to an embodiment.

[0053] A light-emitting display device (hereinafter, it may also be simply referred to as the display device) 10 can be divided into five regions, namely, a central region 10-1, a left region 10-2, a right region 10-3, an upper region 10-4, and a lower region 10-5. Additionally, it includes corner regions where the various regions meet each other, including the upper left region 10-24 where the left region 10-2 and the upper region 10-4 meet, the upper right region 10-34 where the right region 10-3 and the upper region 10-4 meet, the lower left region 10-25 where the left region 10-2 and the lower region 10-5 meet, and the lower right region 10-35 where the right region 10-3 and the lower region 10-5 meet. Each corner region possesses all the characteristics of two regions by having each characteristic of the overlapping regions among the left region 10-2, the right region 10-3, the upper region 10-4, and the lower region 10-5.

[0054] exist Figure 1 In the diagram, although the left region 10-2, right region 10-3, upper region 10-4, lower region 10-5, and each corner region 10-24, 10-25, 10-34, and 10-35 are shown as relatively large, their size can be determined in any suitable manner, such as very narrow regions. For example, the upper region 10-4 and lower region 10-5 can be very narrow and may consist of only one or two pixel rows. The left region 10-2 and right region 10-3 may include more than two pixel columns and only about five pixel columns. Here, the pixel used as the standard for pixel columns and pixel rows (see [reference]). Figure 2 The PX in the PX can be based on a unit light-emitting diode (LED) that includes three primary colors of light-emitting diodes (LEDs) (see reference). Figure 2 LDU in the middle) or multiple pixel circuit units used to drive the light-emitting diode (LED) (see reference) Figure 2 The PXC in the image can be either a single-unit light-emitting diode (LED) LDU or a combination of multiple pixel circuit units (PXC).

[0055] Left region 10-2 and right region 10-3 are also referred to as driving regions, and upper region 10-4 is also referred to as data distribution region. Here, center region 10-1 is the region in which only pixels PX are positioned such that unit light-emitting diodes (LEDs) LDUs and multiple pixel circuit units PXCs are arranged. In upper region 10-4, data distribution units are formed together with pixels PX. Data distribution units may include distributing and applying the data voltage Dm applied to the pixel circuit unit PXC to multiple data lines 171 (see example). Figure 5 The demultiplexer Demux is described. In the left region 10-2 and right region 10-3, multiple signal generation units for generating signals other than the data voltage Dm applied to the pixel circuit unit PXC are formed together with the pixel PX. The multiple signal generation units may include various signal generation units for each in various embodiments, and the following embodiments include a light emission signal generation unit and a scan signal generation unit. Furthermore, the following embodiments focus on embodiments including three scan signal generation units.

[0056] Because the corner region comprises two regions, the upper left region 10-24 where the upper region 10-4 and the left region 10-2 meet includes a data distribution unit, a signal generation unit, and a pixel PX.

[0057] Furthermore, in the following embodiments, dummy openings (see reference) are provided in areas where multiple unit light-emitting diodes (LEDs) LDUs are not attached (or otherwise formed) and positioned. Figure 5 and Figure 6The dummy opening 60 is formed separately together with the pixel circuit unit PXC and the signal generation unit. In the following text, the area where the dummy opening 60 can be located is referred to as the opening forming region 60A. According to an embodiment, the dummy opening 60 can even be located in a portion other than the opening forming region 60A. The portion where the dummy opening 60 is located can be a region where the pixel circuit unit PXC, the data distribution unit, and multiple signal generation units are located.

[0058] In the following text, refer to Figures 2 to 4 Describe the structure of each region, and first refer to Figure 2 Describe the arrangement structure of pixels PX in the central region 10-1.

[0059] Figure 2 This is a layout diagram of the central region of a light-emitting display device according to an embodiment.

[0060] In the central region 10-1 of the light-emitting display device 10, only the unit light-emitting diode (LED) LDU constituting the pixel PX and the pixel circuit unit PXC are formed, and the data distribution unit and / or signal generation unit are not included.

[0061] A pixel PX includes one unit light-emitting diode (LED) LDU and three pixel circuit units PXC. The unit LED LDU includes red, green, and blue light-emitting diodes (LEDs) LDr, LDg, and LDb. According to embodiments, the unit LED LDU may include LEDs of various color combinations. Each color LED included in the unit LED LDU receives current from a pixel circuit unit PXC and displays illuminance based on the current magnitude. As a result, there is a one-to-one correspondence between pixel circuit units PXC and LEDs, and the unit LED LDU has three LEDs, thus including three pixel circuit units PXC (PXCr, PXCg, and PXCb). However, for each embodiment, the number of LEDs and pixel circuit units PXC included in a pixel PX may be different. Furthermore, each LED LDr, LDg, and LDb included in the unit LED LDU may be an LED including an inorganic emitting layer. Compared to embodiments using organic emitting layers, inorganic light-emitting diodes (LEDs) have the advantage of maintaining their characteristics even when exposed to moisture or air, thus possessing characteristics suitable for light-emitting display devices used outdoors.

[0062] In the light-emitting display device 10, multiple unit light-emitting diodes (LEDs) LDUs can be arranged along rows and columns at predetermined intervals. A unit light-emitting diode (LED) LDU can have a square shape and can be arranged in a 2×2 matrix. In some embodiments, the LEDs are not arranged in the first row and first column; red LEDs (LEDs) LDr are located in the first row and second column, green LEDs (LEDs) LDg are located in the second row and first column, and blue LEDs (LEDs) LDb are located in the second row and second column. A unit light-emitting diode (LED) LDU can be integrally formed by aggregating red, green, and blue LEDs (LEDs) LDr, LDg, and LDb, and an anode pad (or "soldering pad") and a cathode pad connected to each unit light-emitting diode (LED) LDr, LDg, and LDb can be located on the lower surface. An anode pad can be formed for each LED (LED) LDr, LDg, and LDb, and a cathode pad can be formed such that a cathode pad is associated with each LED (LED) LDr, LDg, and LDb. The anode pad of the unit light-emitting diode (LED) LDU is formed on the panel and is electrically connected one-to-one to the diode connection portions LDEr, LDEg, and LDEb extending from each pixel circuit unit PXCr, PXCg, and PXCb, thereby receiving the output current of each pixel circuit unit PXCr, PXCg, and PXCb.

[0063] The pixel circuit unit PXC includes a red pixel circuit unit PXCr, a green pixel circuit unit PXCg, and a blue pixel circuit unit PXCb, and is electrically connected to a red light-emitting diode (LED) LDr, a green light-emitting diode (LED) LDg, and a blue light-emitting diode (LED) LDb respectively via diode connection portions LDEr, LDEg, and LDEb. For example, referring to red as an example, the output current generated from the red pixel circuit unit PXCr is transmitted through the red diode connection portion LDEr to the red anode pad located on the back of the LED unit LDU, resulting in the output current being transmitted to the red LED (LED) LDr. For other colors, the current is transmitted in the same manner. Here, the red diode connection portion LDEr, the green diode connection portion LDEg, and the blue diode connection portion LDEb each include a red anode corresponding pad, a green anode corresponding pad, and a blue anode corresponding pad, respectively, thereby being electrically connected to the red anode pad, green anode pad, and blue anode pad located on the back of the LED unit LDU. For reference, each red anode corresponding pad, green anode corresponding pad, and blue anode corresponding pad in the red diode connection portion LDEr, green diode connection portion LDEg, and blue diode connection portion LDEb can have a structure exposed to the top layer, similar to... Figure 6 The anodes correspond to pads LDA1 and LDA2.

[0064] The pixel circuit unit (PXC) must receive signals from an external source to generate output current, and in some embodiments, the PXC is connected to data lines DLr, DLg, and DLb, as well as signal lines GIL, GWL, EML, and GBL. According to embodiments, the number and type of signal lines can be varied, and voltages such as the drive voltage ELVDD can also be transmitted to the PXC.

[0065] like Figure 2As shown, data lines DLr, DLg, and DLb extend along a first direction (x-axis direction) and are connected one-to-one to each pixel circuit unit PXCr, PXCg, and PXCb. For example, the red data line DLr is electrically connected only to the red pixel circuit unit PXCr, the green data line DLg is electrically connected only to the green pixel circuit unit PXCg, and the blue data line DLb is electrically connected only to the blue pixel circuit unit PXCb. As a result, each pixel circuit unit PXCr, PXCg, and PXCb can receive different data voltages. On the other hand, signal lines GIL, GWL, EML, and GBL extend along a second direction (y-axis direction) and are commonly connected to all pixel circuit units PXCr, PXCg, and PXCb arranged in a row. As a result, all pixel circuit units PXCr, PXCg, and PXCb arranged in a row can receive signals (or substantially at the same timing).

[0066] Data lines DLr, DLg, and DLb not only pass through the areas where pixel circuit units (PXCs) and unit light-emitting diodes (LEDs) LDUs are formed, but also through areas where pixel circuit units (PXCs) and unit light-emitting diodes (LEDs) LDUs are not formed, and this area is referred to below as the data line extension area (DLA). In the data line extension area (DLA), no pixel circuit units (PXCs) and unit light-emitting diodes (LEDs) LDUs are located, and only data lines DLr, DLg, and DLb may be located.

[0067] Furthermore, signal lines GIL, GWL, EML, and GBL pass through areas where pixel circuit units (PXCs) are formed, but also through areas where PXCs are not located, and this area is referred to below as the signal line extension area (SLA). In the signal line extension area (SLA), PXCs are not located, and only signal lines GIL, GWL, EML, and GBL may be located.

[0068] Based on this basic structure, we will now describe in more detail. Figure 2 The arrangement of the central region 10-1 of the light-emitting display device 10 shown.

[0069] according to Figure 2Along the first direction (x-axis direction) extending from the data lines DLr, DLg, and DLb, unit light-emitting diodes (LEDs) LDUs, pixel circuit units (PXCs), the next row of pixel circuit units (PXCs), the next row of unit light-emitting diodes (LEDs) LDUs, and data line extension regions (DLAs) are sequentially positioned. This forms an equivalent repeating structure based on the unit light-emitting diodes (LEDs) LDUs. For example, one row of unit light-emitting diodes (LEDs) LDUs is formed based on a unit pixel arrangement structure with two rows of pixel circuit units (PXCs) located on both sides. The unit pixel arrangement structure is repeated in the first direction (x-axis direction), and the data line extension regions (DLAs) are located between the unit pixel arrangement structures. The unit pixel arrangement structure has a structure in which the pixel circuit units (PXCs) are arranged in two rows, and unit light-emitting diodes (LEDs) LDUs electrically connected to the pixel circuit units (PXCs) of one row are positioned row by row on both sides of the pixel circuit units (PXCs) of the two rows. As a result, the data line extension regions (DLAs) are located outside the unit light-emitting diodes (LEDs) LDUs of one row on both sides of the pixel circuit units (PXCs) of the two rows.

[0070] Furthermore, in the central region 10-1 of the light-emitting display device 10, pixel circuit units PXC and signal line extension regions SLA are repeatedly formed along a second direction (y-axis direction) along which signal lines GIL, GWL, EML, and GBL extend. For example, signals applied to each signal line GIL, GWL, EML, and GBL can be generated from the left region 10-2 and / or the right region 10-3 of the light-emitting display device 10.

[0071] Reference Figure 2 In the central region 10-1, a virtual opening can be formed (see reference). Figure 5 / Figure 6 The opening forming region 60A of 60) can be located in the region of the unpositioned unit light-emitting diode (LED) LDU, pixel circuit unit PXC, data line extension region DLA and signal line extension region SLA.

[0072] The dummy opening 60 is formed to prevent the characteristics of the semiconductor layer of the thin-film transistor included in the pixel circuit cell (PXC) from varying depending on location. For example, by forming the dummy opening 60 around the pixel circuit cell (PXC), the dummy opening 60 is formed during the formation of the semiconductor layer included in the thin-film transistor to eliminate position-dependent characteristic variations that occur when hydrogen or the like is not released. As a result, hydrogen is properly eliminated during the semiconductor layer manufacturing process, making the characteristics of the thin-film transistor uniform and not varying depending on location.

[0073] When reference Figure 3 and Figure 4 Instead of referencing Figure 2As shown in the diagram, the central region 10-1, the left region 10-2, upper region 10-4, lower region 10-5, and right region 10-3 have relatively high device integration. If such differences in integration exist, the differences in hydrogen accumulation in the semiconductor will be more apparent. However, in various embodiments, the dummy opening 60 is formed such that hydrogen does not accumulate in the semiconductor, so even with differences in integration, the transistor characteristics will not differ.

[0074] According to the embodiments, in addition to Figure 2 In addition to the opening forming area 60A, the dummy opening 60 can also be formed in the data line extension area DLA or the signal line extension area SLA (see reference). Figure 5 In addition, according to an embodiment, the dummy opening 60 may also be located at the lower part of the portion to which the unit light-emitting diode (LED) LDU is attached.

[0075] also, Figure 2 The size and spacing of each section shown can be varied depending on the embodiment. For example, Figure 2 The size and spacing of each part shown differ from the actual parts, allowing the actual structure to have a size and spacing that can be compared with... Figure 2 The sizes and spacing are different.

[0076] According to an embodiment, the LED LDUs are positioned at constant intervals in a first direction (x-axis direction) and a second direction (y-axis direction), such that four adjacent LED LDUs can be arranged in a square. Based on the width of the LED LDUs in the first direction (x-axis direction) or the second direction (y-axis direction), the spacing between adjacent LED LDUs in the first direction (x-axis direction) and / or the second direction (y-axis direction) can be one or more to less than 2.5 times. In this case, the LED LDUs can have a length / width of several μm to tens of μm.

[0077] The width of the pixel circuit unit (PXC) and the data line extension area (DLA) in the second direction (y-axis direction) can be the same as the width of the unit light-emitting diode (LED) LDU in the second direction (y-axis direction). The width of the pixel circuit unit (PXC) in the first direction (x-axis direction) can be more than 0.5 times and less than 1.25 times the width of the unit light-emitting diode (LED) LDU in the first direction (x-axis direction), such that if the widths of the pixel circuit units (PXC) in the first direction (x-axis direction) of two rows are added together, it can be 1 to 2.5 times or less the width of the unit light-emitting diode (LED) LDU in the first direction (x-axis direction). The width of the data line extension area (DLA) in the first direction (x-axis direction) can be greater than or equal to 1 times and less than or equal to 2.5 times the width of the unit light-emitting diode (LED) LDU in the first direction (x-axis direction).

[0078] Based on the width of the LED LDU in the first direction (x-axis direction) and the second direction (y-axis direction), the width of the signal line extension region SLA in the first direction (x-axis direction) and the second direction (y-axis direction) can be greater than or equal to 1 and less than or equal to 2.5 times.

[0079] However, according to embodiments, a single-unit light-emitting diode (LED) LDU can have nanometer (nm) units, i.e., a length / width of a few nm or larger up to several hundred nm, and the dimensional relationship and spacing of the single-unit light-emitting diode (LED) LDU with other parts can be varied.

[0080] In the above text, using Figure 2 The structure of the central region 10-1 was studied.

[0081] In the following text, refer to Figure 3 The structure of the upper left region 10-24 (i.e., the upper region of the left region 10-2) is described in more detail.

[0082] Figure 3 This is an upper layout view of the driving area of ​​a light-emitting display device according to an embodiment.

[0083] In addition to the structure of the central region 10-1, the upper left region 10-24 of the display device 10 also includes each of the characteristics of the left region 10-2 and the upper region 10-4 of the central region 10-1. For example, in addition to those formed in Figure 2In addition to the LED light-emitting diode (LDU), pixel circuit unit (PXC), data line extension area (DLA), and signal line extension area (SLA) in the central region 10-1 shown, the upper left region 10-24 also includes multiple signal generation units formed in the left region 10-2 and a data distribution unit including a demultiplexer (Demux) and an electrostatic discharge (ESD) prevention unit formed in the upper region 10-4. Here, multiple signal generation units are components for generating signals applied to each signal line GIL, GWL, EML, and GBL, and include stages GWS1, GWS2, and GWS3 for generating signals applied to the first scan line GWL, stages GIS1, GIS2, and GIS3 for generating signals applied to the second scan line GIL, stages GBS1, GBS2, and GBS3 for generating signals applied to the bypass control line GBL, and stages EMS1, EMS2, and EMS3 for generating signals applied to the optical emission signal line EML, and the stages for each signal are formed along a first direction (x-axis direction).

[0084] First, the data distribution unit including the demultiplexer Demux and the electrostatic discharge (ESD) prevention unit formed in the upper region 10-4 will be described.

[0085] The demultiplexer (Demux) and the electrostatic discharge (ESD) protection unit are located in the row between the first row of LED LDUs and the first row of pixel circuit units (PXCs) in the second direction (y-axis direction), and in the column between two adjacent LED LDUs in the first direction (x-axis direction). Furthermore, the demultiplexer (Demux) and the ESD protection unit are alternately arranged in the first direction (x-axis direction) such that if the demultiplexer (Demux) is located between the first column of LED LDUs and the second column of LED LDUs, then the ESD protection unit is located between the second column of LED LDUs and the third column of LED LDUs.

[0086] Multiple demultiplexers (Demux) are referred to as data distribution units. A single demultiplexer (Demux) comprises two sub-demultiplexers (DemmL and DemR), each connected to three data lines DLr, DLg, and DLb. One of the sub-demultiplexers (DemmL and DemR) can distribute the data voltage transmitted via a single wiring connected to the input side to the three data lines DLr, DLg, and DLb according to time, and transmit the distributed data voltage. As a result, a single demultiplexer (Demux) can transmit the data voltage to the pixel circuit units (PXCs) in two columns.

[0087] The ESD protection unit is connected to the data lines DLr, DLg, and DLb or other voltage lines to prevent components such as thin-film transistors in display panels from being damaged by static electricity generated during the manufacturing process. Subsequently, when the manufacturing process is complete, the ESD protection unit is electrically disconnected from the connection lines.

[0088] In the following text, a plurality of signal generation units according to some embodiments will be described.

[0089] Multiple signal generation units are arranged in the same row as unit light-emitting diodes (LEDs) LDUs in the second direction (y-axis direction) and between adjacent signal line extension regions (SLAs) in the first direction (x-axis direction). One or more stages may be formed in the signal generation units formed at positions corresponding to a unit light-emitting diode (LED) LDU, and each stage is connected to adjacent signal lines GIL, GWL, EML, and GBL.

[0090] For example, refer to Figure 2 Along the first direction (x-axis direction) extending from the data lines DLr, DLg, and DLb, since the data line extension region DLA, the unit light-emitting diode (LED) LDU, the pixel circuit unit PXC, the next row pixel circuit unit PXC, the next row unit light-emitting diode (LED) LDU, and the data line extension region DLA are positioned sequentially, a stage is formed one after another next to the unit light-emitting diode (LED) LDU and the next row unit light-emitting diode (LED) LDU. As a result, the stage adjacent to one side of the unit light-emitting diode (LED) LDU located above is connected to the signal line connected to the upwardly positioned pixel circuit unit PXC in the pixel circuit unit PXC, and the stage adjacent to one side of the unit light-emitting diode (LED) LDU located below is connected to the signal line connected to the next row pixel circuit unit PXC. Therefore, in the basic structure, only one stage can be located next to the unit light-emitting diode (LED) LDU.

[0091] However, referring again Figure 3In the upper left region 10-24, a first row of pixel circuit units (PXCs) is formed to apply signals to the first row of LED light-emitting diodes (LEDs) LDUs located in the upper region 10-4. However, the first row of LEDs LDUs and the first row of pixel circuit units (PXCs) are not positioned adjacent to each other like other pixels. For example, in order to reduce the non-display area by forming the first row of LEDs LDUs before the demultiplexer (Demux) and the ESD protection unit (ESD), the first row of pixel circuit units (PXCs) is located directly above the second row of LEDs LDUs. In this case, the diode connection portions LDEr, LDEg, and LDEb connecting the first row of pixel circuit units (PXCs) and the first row of LEDs LDUs are extended.

[0092] Furthermore, since the signal lines GIL, GWL, EML, and GBL connected to the first row pixel circuit unit PXC also pass directly above the second row unit light-emitting diode (LED) LDU in the second direction (y-axis direction), the level of the signal applied to the first row pixel circuit unit PXC is positioned adjacent to the second row unit light-emitting diode (LED) LDU. As a result, as Figure 3 As shown, the stages in the first row and the stages in the second row are formed next to a single LED LDU. This means that even in the lower region 10-5 of the display device 10, two stages can be located next to a single LED LDU, and this combination Figure 4 To describe in more detail.

[0093] On the other hand, some embodiments include multiple signal generation units comprising a first scan signal generation unit, a second scan signal generation unit, a bypass signal generation unit, and a light emission signal generation unit. The light emission signal stages EMS1, EMS2, and EMS3 for the light emission signal generation unit, the bypass signal stages GBS1, GBS2, and GBS3 for the bypass signal generation unit, the second scan signal stages GIS1, GIS2, and GIS3 for the second scan signal generation unit, and the first scan signal stages GWS1, GWS2, and GWS3 for the first scan signal generation unit are sequentially formed from the leftmost (outermost) towards the center. Identical stages are arranged along a first direction (x-axis direction).

[0094] Stages EMS1, EMS2, and EMS3, used for optical emission signals, are located between the first and second column LED LDUs. Stages GBS1, GBS2, and GBS3, used for bypass signals, are located between the second and third column LED LDUs. Stages GIS1, GIS2, and GIS3, used for the second scan signal, are located between the third and fourth column LED LDUs. Stages GWS1, GWS2, and GWS3, used for the first scan signal, are located between the fourth and fifth column LED LDUs.

[0095] After the fifth column of LED units, such as Figure 2 As shown, each stage is not formed in the central region 10-1 and between the unit light-emitting diodes (LEDs) LDU.

[0096] Furthermore, each level can be included even in the right region 10-3 of the display device 10, and each level can be formed with... Figure 3 The structure is symmetrical. For example, from the rightmost (outermost) towards the center, the stages EMS1, EMS2, and EMS3 for the light emission signal generation unit, the stages GBS1, GBS2, and GBS3 for the bypass signal generation unit, the stages GIS1, GIS2, and GIS3 for the second scan signal generation unit, and the stages GWS1, GWS2, and GWS3 for the first scan signal generation unit can be formed sequentially. Identical stages are arranged along a first direction (x-axis direction). For example, each of the signal lines GIL, GWL, EML, and GBL can have a structure in which the same signal is applied from two stages located in the left region 10-2 and the right region 10-3.

[0097] Therefore, in either the left region 10-2 or the right region 10-3, each of the stages GWS1, GWS2, and GWS3 for the first scan signal, GIS1, GIS2, and GIS3 for the second scan signal, GBS1, GBS2, and GBS3 for the bypass signal, and EMS1, EMS2, and EMS3 for the optical emission signal is located between two adjacent LED LDUs, and each stage for the same signal can be arranged along a first direction (x-axis direction). Furthermore, for each signal stage, in either the left region 10-2 or the right region 10-3, the stages EMS1, EMS2, and EMS3 for the optical emission signal are located on the outermost side, and the stages GBS1, GBS2, and GBS3 for the bypass signal, GIS1, GIS2, and GIS3 for the second scan signal, and GWS1, GWS2, and GWS3 for the first scan signal can be sequentially positioned inwards.

[0098] also, Figure 3 This shows where a dummy opening can be formed (see reference). Figure 5 / Figure 6 The opening forming region 60A is defined as 60). In some embodiments, the portion where the opening forming region 60A is located may be the left region 10-2, rather than the upper region 10-4. For example, even in the upper region 10-4, if space exists to form the dummy opening 60, the dummy opening 60 could be added, but this might be inappropriate. Figure 3 In one embodiment, an embodiment is provided in which the opening forming region 60A is located in the upper left region 10-24 having free space.

[0099] According to an embodiment, in the upper left region 10-24 of the display device 10, the opening forming region 60A can be located in the regions of the unpositioned unit light-emitting diode (LED) LDU, pixel circuit unit PXC, data line extension region DLA, signal line extension region SLA, demultiplexer Demux, electrostatic discharge (ESD) protection unit, and each level of EMS, GBS, GIS, and GWS. Furthermore, according to an embodiment, a dummy opening can be located in the data line extension region DLA or the signal line extension region SLA, and a dummy opening can be positioned if space also exists between each part.

[0100] In the above text, using Figure 3 The structure of the upper left region 10-24 was studied. (Refer to...) Figure 4 A more detailed description of... Figure 3 The structure of the upper left region 10-24 and the lower left region 10-25 (e.g., the lower side of the left region 10-2).

[0101] Figure 4This is a lower layout view of the driving area of ​​a light-emitting display device according to an embodiment.

[0102] Unlike the upper region 10-4, the lower region 10-5, according to some embodiments, does not include a data allocation unit, thus preventing the formation of multiple demultiplexers (Demux). However, the lower region 10-5 also includes an electrostatic discharge (ESD) protection unit. As a result, the demultiplexers are not included in the lower left region 10-25, and only the ESD protection unit is formed.

[0103] Due to the electrostatic discharge (ESD) protection unit, the last row of LED LDUs and the last row of pixel circuit units (PXCs) are separated from each other, just like the LED LDUs and PXCs in the first row. For example, the last row of LED LDUs is located below the ESD protection unit to reduce the non-display area, and the last row of PXCs is located directly below the LED LDUs in the second row starting from the last row. At this time, the diode connection portions LDEr, LDEg, and LDEb connecting the PXCs and LED LDUs in the last row are extended.

[0104] Furthermore, since the signal lines GIL, GWL, EML, and GBL connected to the pixel circuit unit PXC in the last row also pass directly beneath the unit light-emitting diode (LED) LDU in the second row starting from the last row in the second direction (y-axis direction), the signal stage applied to the pixel circuit unit PXC in the last row is positioned adjacent to the unit light-emitting diode (LED) LDU in the second row starting from the last row. As a result, as Figure 4 As shown, a last row of stages and a second row of stages starting from the last row are formed next to a single LED LDU.

[0105] Since the lower left region 10-25 also possesses the characteristics of the left region 10-2, the signal generation unit is located between the LED LDUs. Multiple signal generation units include a first scan signal generation unit, a second scan signal generation unit, a bypass signal generation unit, and a light emission signal generation unit. From the leftmost (outermost) side towards the center, the stages EMS1, EMS2, and EMS3 for the light emission signal generation unit, the stages GBS1, GBS2, and GBS3 for the bypass signal generation unit, the stages GIS1, GIS2, and GIS3 for the second scan signal generation unit, and the stages GWS1, GWS2, and GWS3 for the first scan signal generation unit are formed sequentially. Identical stages are arranged along a first direction (x-axis direction).

[0106] Figure 4 It also shows how a dummy opening can be formed (see reference). Figure 5 / Figure 6 The opening forming region 60A is defined as 60). In some embodiments, the portion where the opening forming region 60A is located may be the lower region 10-5 or the lower left region 10-25. For example, in the lower region 10-5, as... Figure 4 As shown, an opening forming region 60A that forms a dummy opening 60 can be located, which is why there is no demultiplexer Demux, so this space can be used.

[0107] Furthermore, in the lower left region 10-25 of the display device 10, the opening forming region 60A can be located in the region containing the unpositioned unit light-emitting diode (LED) LDU, pixel circuit unit PXC, data line extension region DLA, signal line extension region SLA, electrostatic discharge (ESD) protection unit, and each level of EMS, GBS, GIS, and GWS. Additionally, according to an embodiment, a dummy opening can be located in the data line extension region DLA or the signal line extension region SLA, and the dummy opening 60 can be positioned if there is space between each portion.

[0108] Next, we will refer to Figure 5 and Figure 6 The structure of the dummy opening 60 located around the pixel circuit unit PXC is described in more detail.

[0109] Figure 5 This is a layout diagram of the pixel circuit unit and its surroundings of a light-emitting display device according to an embodiment. Figure 6 According to the embodiments Figure 5 The VI-VI'-VI" section line and the cross-sectional view around the pixel circuit unit.

[0110] According to an embodiment, the pixel circuit unit PXC is in Figure 7 and Figure 8 as well as Figure 5 This is shown in more detail in the figures below, and therefore will be described in more detail in the description of the figures below. Therefore, based on... Figure 5 and Figure 6 The structure of the dummy opening 60 according to an embodiment is described.

[0111] exist Figure 5 In this process, the signal lines GIL, GWL, EML, and GBL are changed to numbers as reference numbers, and respectively, the first scan line GWL is numbered 151, the second scan line GIL is numbered 152, the bypass control line GBL is numbered 158, and the optical emission signal line EML is numbered 153.

[0112] Additionally, data lines DLr, DLg, and DLb are shown as number 171, and can be shown and described separately below as data lines 171R, 171G, and 171B.

[0113] Reference Figure 5 The dummy opening 60 is formed between the second scan line 152 and the first scan line 151, between the first scan line 151 and the light emission signal line 153, and between the light emission signal line 153 and the bypass signal line 158. As a result, the dummy opening 60 is formed between... Figures 2 to 4 The signal line extension area in the diagram is represented by the SLA.

[0114] In addition, refer to Figure 5 The dummy opening 60 is also formed above the second scan line 152 and below the bypass signal line 158. This part is... Figures 2 to 4 The opening in the region forms region 60A, so that the illusory opening 60 is also formed in the region. Figures 2 to 4 The opening is formed in region 60A.

[0115] exist Figure 5 In addition to the opening forming region 60A, an embodiment in which a dummy opening 60 is formed in the signal line extension region SLA is also shown. Furthermore, according to the embodiment, the dummy opening 60 can also be formed between data lines DLr, DLg, and DLb in the data line extension region DLA. On the other hand, referring to… Figure 6 This illustrates that the dummy opening 60 can also be located below the unit light-emitting diode (LED) LDU. For example, in Figure 6 The diagram shows a portion where the dummy opening 60 is also located below the cathode corresponding pads LDC1 and LDC2 to which the unit light-emitting diode (LED) LDU is attached. Furthermore, with... Figure 6 Unlike other light-emitting diodes (LEDs), the dummy opening 60 can be located below the corresponding anode pads LDA1 and LDA2 to which the LED LDU is attached.

[0116] In the following text, reference will be made to Figure 6 Describe the cross-sectional structure of the dummy opening 60.

[0117] Figure 6 A cross-sectional structure of the pixel circuit unit PXC and the dummy opening 60 around it in the display device 10 according to an embodiment is shown.

[0118] A buffer layer 112 may be located on a substrate 110, and a semiconductor layer 130 may be located on the buffer layer 112. Here, the substrate 110 may be a substrate formed of a flexible material such as plastic or polyimide (PI). When using a flexible substrate 110, impurities may flow from the substrate 110 into the semiconductor layer 130 during its formation; however, the buffer layer 112 can be formed to prevent such impurity flow. The buffer layer 112 may include materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x At least one inorganic insulating material selected from materials such as silicon oxide (SiO2) and silicon oxynitride (SiON). Additionally, according to embodiments, this can be achieved by using materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x At least one inorganic insulating material, selected from materials such as silicon oxynitride (SiON), is further used to form a barrier layer between the substrate 110 and the buffer layer 112. According to an embodiment, the substrate 110 may be formed from a glass substrate. In this case, the buffer layer 112 can be omitted, and the semiconductor layer 130 can be located directly on the substrate 110.

[0119] The first insulating layer 140 is located on the semiconductor layer 130, and the first insulating layer 140 may include, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x It is at least one of the following inorganic insulating materials: silicon oxynitride (SiON) and silicon oxynitride (SiON).

[0120] A first gate conductive layer is disposed on the first insulating layer 140, and the first gate conductive layer may include the gate electrode of a thin-film transistor and an electrode of a capacitor. Figure 6 In this diagram, one electrode of the capacitor is formed by the gate electrode 155 of the driving transistor, such that they are indicated by the same reference numerals. Additionally, various wirings for the signal generation unit and / or the demultiplexer Demux may be included in the first gate conductive layer, as discussed in the detailed description of each section. According to an embodiment, the first gate conductive layer is formed of a conductive material and may be formed of multiple conductive layers.

[0121] The first gate conductive layer is covered by a second insulating layer 141, and the second insulating layer 141 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x It is at least one of the following inorganic insulating materials: silicon oxynitride (SiON) and silicon oxynitride (SiON).

[0122] The second gate conductive layer is located on the second insulating layer 141, and the second gate conductive layer may include the storage electrode 172-2 of the capacitor. Furthermore, the second gate conductive layer may include an electrode of a capacitor included in the signal generation unit and / or demultiplexer Demux, or may include various components. This is discussed in the detailed description of each section. The second gate conductive layer may be formed of a conductive material, and according to embodiments, it may be formed of multiple conductive layers.

[0123] The second gate conductive layer is covered by a third insulating layer 142, and the third insulating layer 142 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x It is at least one of the following inorganic insulating materials: silicon oxynitride (SiON) and silicon oxynitride (SiON).

[0124] The first data conductive layer is located on the third insulating layer 142, and the first data conductive layer may include data lines 171, drive voltage lines 172-1, and data connection members 73 (hereinafter referred to as the third data connection member 73). Additionally, the first data conductive layer may include various wirings for a signal generation unit and / or a demultiplexer Demux, which will be described in the detailed description of each section. According to an embodiment, the first data conductive layer is formed of a conductive material and may be formed of multiple conductive layers.

[0125] The first data conductive layer is covered by a fourth insulating layer 143. The fourth insulating layer 143 may include an organic material.

[0126] The second data conductive layer is located on the fourth insulating layer 143, and the diode connection portion LDE and the power application wiring 172' can be included in the second data conductive layer. Here, the power application wiring 172' is electrically connected to the drive voltage line 172-1 through the opening 82 to transmit the drive voltage ELVDD. The power application wiring 172' is electrically isolated from the diode connection portion LDE and can be located entirely in the remaining portion except for the area where the diode connection portion LDE is located. In addition, according to an embodiment, the second data conductive layer can include various wirings of the signal generation unit and / or the demultiplexer Demux. According to an embodiment, the second data conductive layer is formed of a conductive material and can be formed of multiple conductive layers.

[0127] The second data conductive layer is covered by a fifth insulating layer 144, and the fifth insulating layer 144 may include an organic material.

[0128] A separator 145 is located on a fifth insulating layer 144 and includes openings in which anode pads LDA1 and LDA2 and cathode pads LDC1 and LDC2 are formed. Anode and cathode pads located on the bottom surface of a unit light-emitting diode (LED) LDU are attached to anode pads LDA1 and LDA2 and cathode pads LDC1 and LDC2. Anode pads LDA1 and LDA2 and cathode pads LDC1 and LDC2 may be located in different openings of separator 145. Anode pads LDA1 and LDA2 receive the output current of the pixel circuit unit PXC, and cathode pads LDC1 and LDC2 receive the drive low voltage (i.e., common voltage) ELVSS. Cathode pads LDC1 and LDC2 are electrically isolated from anode pads LDA1 and LDA2 and may be located entirely in the remaining portion except for the area where anode pads LDA1 and LDA2 are positioned. Separator 145 may include an organic material. The partition wall 145 can cover the cathode corresponding pads LDC1 and LDC2 except for the portions where the cathode corresponding pads LDC1 and LDC2 are open to contact the cathode pads of the unit light-emitting diode (LED) LDU.

[0129] The anode pads LDA1 and LDA2, and the cathode pads LDC1 and LDC2, can be formed as a double layer. The upper anode pad LDA2 and the upper cathode pad LDC2 can be formed of a transparent conductive material (such as ITO), and the lower anode pad LDA1 and the lower cathode pad LDC1 can be formed of an opaque conductive material or multiple conductive layers. According to an embodiment, the anode pads LDA1 and LDA2, and the cathode pads LDC1 and LDC2, can be formed as a single layer, and in this case, the second anode pad LDA2 and the second cathode pad LDC2 can be omitted.

[0130] exist Figure 6 The diagram shows a dummy opening 60, which, according to some embodiments, is formed in a first insulating layer 140, a second insulating layer 141, and a third insulating layer 142. Additionally, according to some embodiments, the dummy opening 60 can be stacked with cathode corresponding pads LDC1 and LDC2, such that the dummy opening 60 can also be located below the portion to which the unit light-emitting diode (LED) LDU is attached.

[0131] The dummy opening 60 can be formed up to the first insulating layer 140 and can be formed to a depth equal to that exposing the openings 67 and 69 of the semiconductor layer 130. The dummy opening 60 is used to allow hydrogen to escape from the semiconductor layer 130 during at least one manufacturing process. If hydrogen does not escape from the semiconductor layer 130 after various processes in which the semiconductor layer 130 is formed (e.g., crystallization process, annealing process, etc.), hydrogen accumulates at specific locations within the semiconductor layer 130, and its properties may change. For example, as... Figures 2 to 4 As shown, with sparsely positioned pixel circuit cells (PXCs), there are not enough openings in the portion adjacent to semiconductor layer 130, so hydrogen cannot escape, and some transistors will exhibit undesirable characteristics. However, when dummy openings 60 are formed as in various embodiments, dehydrogenation easily occurs in semiconductor layer 130, making the characteristics of semiconductor layer 130 and transistors constant. Dummy openings 60 can be covered with organic materials, and... Figure 6 In the middle, the dummy opening 60 is covered by a fourth insulating layer 143 formed of organic material.

[0132] In combination Figure 5 The described embodiment shows a structure in which the dummy openings 60 are arranged at regular intervals in quadrilateral shapes of constant size; however, according to some embodiments, the dummy openings 60 can be formed in various sizes and shapes. Furthermore, a single dummy opening can be formed in a wide area. Additionally, according to embodiments, such as Figures 26 to 28 As shown, a mask with a specific pattern can be used to form a dummy opening 60.

[0133] In the following text, reference will be made to Figure 7 A more detailed description of the structure of the pixel circuit unit PXC according to some embodiments is provided.

[0134] Figure 7 This is a layout diagram of the pixel circuit unit of a light-emitting display device according to an embodiment.

[0135] Figure 7 The structure of three pixel circuit units PXCs formed in the display device 10, arranged adjacent to each other, is shown. One of these pixel circuit units PXCs is described below.

[0136] The pixel circuit unit PXC of the light-emitting display device 10 according to an embodiment includes a first scan line 151, a second scan line 152, a light emission signal line 153, and a bypass signal line 158 extending along a second direction (y-axis direction) and respectively transmitting a first scan signal GW(n), a second scan signal GI(n), a light emission control signal EM(n), and a bypass signal GB(n). The light-emitting display device 10 includes data lines (171R, 171G, and 171B) and a drive voltage line 172-1 extending along a first direction (x-axis direction) and a second direction (y-axis direction) and respectively transmitting a data voltage Dm and a drive voltage ELVDD.

[0137] The light-emitting display device 10 includes a driving transistor T1 (also called a first transistor), a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0138] Each channel of driving transistors T1, T2, T3, T4, T5, T6, and T7 is disposed in an elongated semiconductor layer 130. The sides of the channels in the semiconductor layer 130 are formed by plasma processing to have the same properties as conductors and can be directly connected to adjacent transistors through the semiconductor layer 130. The semiconductor layer 130 can be formed in various bent shapes and comprises polycrystalline semiconductors, such as polycrystalline silicon or oxide semiconductors.

[0139] Each channel of multiple transistors T1, T2, T3, T4, T5, T6, and T7 is stacked with the gate electrode of each transistor T1, T2, T3, T4, T5, T6, and T7. The multiple transistors T1, T2, T3, T4, T5, T6, and T7 can be coupled with... Figure 6 The part represented by T1 has essentially the same stacking structure and is similar to... Figure 6 The portion represented by T1 has the same stacked structure. In the following text, the driving transistor T1 is described in detail, while the remaining transistors T2, T3, T4, T5, T6, and T7 are described simply.

[0140] The driving transistor T1, including a channel and a gate electrode 155, may further include a first region and a second region disposed on corresponding sides of the channel. The channel of the driving transistor T1 is located between the first region and the second region and is superimposed on the gate electrode 155 in a plane. Figure 7 As shown, the channel of the driving transistor T1 has a straight shape extending in the row direction; however, it can have various shapes (e.g., an "Ω" shape).

[0141] Storage electrode 172-2 is located on the gate electrode 155, which will be insulated. Storage electrode 172-2 is stacked on a plane with gate electrode 155 via a second insulating layer 141 to construct a storage capacitor Cst. Storage electrode 172-2 has an opening 56, allowing gate electrode 155 to be connected to a first data connection member 71. In opening 56, the upper surface of gate electrode 155 and the first data connection member 71 are electrically connected through opening 61. The first data connection member 71 is connected to a third transistor T3 and a fourth transistor T4, thereby driving the gate electrode 155 of transistor T1 to connect the third transistor T3 and the fourth transistor T4. Furthermore, storage electrode 172-2 is connected to drive voltage line 172-1 through opening 68, thereby receiving drive voltage ELVDD.

[0142] The gate electrode of the second transistor T2 may be part of the first scan line 151. The first region of the second transistor T2 is connected to the data line 171 through the opening 62, and the first region and the second region may be disposed on the semiconductor layer 130.

[0143] The third transistor T3 can be composed of two transistors that are adjacent to each other. For example, in Figure 7 In the diagram, relative to the bent portion of semiconductor layer 130, marking T3 is shown on the right and below. These two portions function as third transistors T3 and have a structure where a first region of one third transistor T3 is connected to a second region of the other third transistor T3. The gate electrodes of the two transistors T3 can be a portion of the first scan line 151 or a portion protruding upward from the first scan line 151. Such a structure can be referred to as a dual-gate structure and can be used to block the flow of leakage current. The third transistor T3 is connected to the sixth transistor T6 and the drive transistor T1. The third transistor T3 is connected to the first data connection member 71 through opening 63.

[0144] The fourth transistor T4 can also have a structure that blocks leakage current by having a dual-gate structure consisting of two fourth transistors T4. The two fourth transistors T4 are formed at the intersection of the second scan line 152 and the semiconductor layer 130. The gate electrode of the fourth transistor T4 can be part of the second scan line 152. The second data connection member 72 is connected to the first region of the fourth transistor T4 through an opening 65, and the first data connection member 71 is connected to the second region of the fourth transistor T4 through an opening 63.

[0145] The gate electrode of the fifth transistor T5 may be part of the light emission signal line 153. The drive voltage line 172-1 is connected to the first region of the fifth transistor T5 through the opening 67, and the second region of the fifth transistor T5 is connected to the drive transistor T1 through the semiconductor layer 130.

[0146] The gate electrode of the sixth transistor T6 may be part of the light emission signal line 153. The third data connection member 73 is connected to the second region of the sixth transistor T6 through the opening 69, and the first region of the sixth transistor T6 is connected to the driving transistor T1 through the semiconductor layer 130.

[0147] The gate electrode of the seventh transistor T7 can be part of the bypass signal line 158. The third data connection member 73 is connected to the first region of the seventh transistor T7 through opening 81, and the second region of the seventh transistor T7 is connected to the second data connection member 72 through opening 65. The second data connection member 72 is connected to the initialization voltage line 127 through opening 64, and the seventh transistor T7 and the fourth transistor T4 receive the initialization voltage V. INT (See Figure 8 ).

[0148] The parasitic capacitor control pattern 172-3 can be located between the dual gate electrodes of the compensation transistor T3. Parasitic capacitors exist within the pixel PX, and image quality characteristics may change if the voltage applied to the parasitic capacitor changes. The drive voltage line 172-1 is connected to the parasitic capacitor control pattern 172-3 through opening 66. Therefore, changes in image quality characteristics can be prevented by applying a constant DC drive voltage ELVDD to the parasitic capacitor. The parasitic capacitor control pattern 172-3 can be formed differently from the shape and position shown.

[0149] exist Figure 7 In the diagram, the portion marked with a shaded line is the first gate conductive layer, and the portion marked with dots is the first data conductive layer. The semiconductor layer 130 and the second gate conductive layer are not shown separately. Based on this, refer to... Figure 6 The cross-sectional structure of the light-emitting display device according to the embodiment is described below in stacking order.

[0150] In the light-emitting display device according to the embodiment, the buffer layer 112 may be located on the substrate 110, and the semiconductor layer 130, which includes a channel of a plurality of transistors T1, T2, T3, T4, T5, T6 and T7, a first region and a second region, is located on the buffer layer 112.

[0151] A first insulating layer 140 covering the semiconductor layer 130 is located thereon. A first gate conductive layer including the gate electrode 155 of a plurality of transistors T1, T2, T3, T4, T5, T6 and T7, a first scan line 151, a second scan line 152, a light emission signal line 153 and a bypass signal line 158 is located on the first insulating layer 140.

[0152] A second insulating layer 141 covering the first gate conductive layer is located on the first insulating layer 140. The first insulating layer 140 and the second insulating layer 141 may be made of materials such as silicon oxide (SiO2).x ), silicon nitride (SiN) x At least one inorganic insulating material selected from materials such as silicon oxynitride (SiON) is formed. A second gate conductive layer, including a first storage electrode 172-2, an initialization voltage line 127, and a parasitic capacitor control pattern 172-3, is located on the second insulating layer 141.

[0153] A third insulating layer 142 covering the second gate conductive layer is located on the second insulating layer 141. The third insulating layer 142 may be made of materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x It is formed from at least one inorganic insulating material among materials such as silicon oxynitride (SiON) and silicon oxynitride (SiON).

[0154] On the third insulating layer 142, a first data conductive layer is positioned, including a data line 171, a drive voltage line 172-1, a first data connection member 71, a second data connection member 72, and a third data connection member 73.

[0155] A fourth insulating layer 143, covering the first data conductive layer, is located on the first data conductive layer. Also referred to as a planarization film, the fourth insulating layer 143 may comprise an organic insulating material.

[0156] According to an embodiment, a second data conductive layer and a fifth insulating layer 144 may be positioned on the fourth insulating layer 143, and a separator wall 145, anode corresponding pads LDA1 and LDA2, and cathode corresponding pads LDC1 and LDC2 may be positioned on the fourth insulating layer 143. According to an embodiment, the second data conductive layer and the fifth insulating layer 144 may be omitted.

[0157] Data line 171 is connected to the first electrode of the second transistor T2 through an opening 62 formed in the first insulating layer 140, the second insulating layer 141 and the third insulating layer 142.

[0158] The driving voltage line 172-1 is connected to the first region of the fifth transistor T5 through an opening 67 formed in the first insulating layer 140, the second insulating layer 141 and the third insulating layer 142, connected to the storage electrode 172-2 through an opening 68 formed in the third insulating layer 142, and connected to the parasitic capacitor control pattern 172-3 through an opening 66 formed in the third insulating layer 142.

[0159] One end of the first data connection member 71 is connected to the gate electrode 155 through an opening 61 formed in the second insulating layer 141 and the third insulating layer 142, and the other end is connected to the third transistor T3 and the fourth transistor T4 through an opening 63 formed in the first insulating layer 140, the second insulating layer 141 and the third insulating layer 142.

[0160] One end of the second data connection member 72 is connected to the fourth transistor T4 through an opening 65 formed in the first insulating layer 140, the second insulating layer 141 and the third insulating layer 142, and the other end is connected to the initialization voltage line 127 through an opening 64 formed in the third insulating layer 142.

[0161] The third data connection member 73 is connected to the sixth transistor T6 through an opening 69 formed in the first insulating layer 140, the second insulating layer 141, and the third insulating layer 142. The third data connection member 73 is connected to the diode connection portion LDE through an opening 81, and the anode corresponding pads LDA1 and LDA2 are located at the ends of the diode connection portion LDE to transmit the output current to the unit light-emitting diode (LED) LDU.

[0162] In the following text, refer to Figure 8 and Figure 9 This describes an example circuit diagram and input signals for a pixel PX, which includes a light-emitting diode (LED). Note that... Figure 8 The embodiments shown also include a pixel output test unit PXCT capable of testing whether the output current is generated from the pixel circuit unit PXC.

[0163] Figure 8 This is a circuit diagram of the pixels of a light-emitting display device according to an embodiment. Figure 9 It is applied according to the embodiment to Figure 8 The waveform of the signal of the pixel.

[0164] Reference Figure 8 The pixel PX of the light-emitting display device 10 includes multiple transistors T1, T2, T3, T4, T5, T6, and T7 connected to several signal lines 127, 151, 152, 153, 158, 171, and 172-1, a storage capacitor Cst, and a light-emitting diode (LED). Furthermore, the pixel output test unit PXCT also includes an eighth transistor T8 and a test signal line 157 controlling the eighth transistor T8. However, according to an embodiment, the light-emitting display device 10 may not include the pixel output test unit PXCT.

[0165] First, the pixel circuit unit PXC, excluding the pixel output test unit PXCT and the light-emitting diode (LED), is described.

[0166] The plurality of transistors T1, T2, T3, T4, T5, T6 and T7 include a driving transistor T1 and a second transistor T2, and other transistors may include a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7 for operating a light-emitting diode (LED).

[0167] Multiple signal lines 127, 151, 152, 153, 158, 171 and 172-1 may include a first scan line 151, a second scan line 152, an optical emission signal line 153, a bypass signal line 158, a data line 171, a drive voltage line 172-1 and an initialization voltage line 127.

[0168] The first scan line 151 is connected to Figure 3 A stage GWS is used for the first scan signal to transmit the scan signal GW(n) to the second transistor T2 and the third transistor T3. A second scan line 152 is connected to a stage GIS for the second scan signal to transmit the second scan signal GI(n) to the fourth transistor T4. A light emission signal line 153 is connected to a stage EMS for the light emission signal to transmit the light emission control signal EM(n), which controls the timing of LED emission, to the fifth transistor T5 and the sixth transistor T6. A bypass signal line 158 is connected to the stage EMS for the light emission signal to transmit the bypass signal GB(n) to the seventh transistor T7.

[0169] Data line 171 is connected to the demultiplexer Demux, which serves as the wiring for transmitting data voltage Dm, and the illuminance of the light-emitting diode (LED) (also called the light-emitting element) varies according to the data voltage Dm. Drive voltage line 172-1 applies the drive voltage ELVDD, and initialization voltage line 127 transmits the initialization voltage V used to initialize the voltages of the gate electrode of the driving transistor T1, one electrode of the storage capacitor, and the anode of the light-emitting diode (LED). INT A low driving voltage ELVSS is applied to the cathode of the light-emitting diode (LED). The driving voltage ELVDD and the initialization voltage V are also mentioned. INT The driving voltage ELVSS can be a constant voltage.

[0170] The following text describes the connections between the multiple transistors included in the pixel circuit unit (PXC).

[0171] First, the driving transistor T1 is a transistor that adjusts the magnitude of its output current according to the applied data voltage Dm, and the output current of the driving transistor T1 is applied to the light-emitting diode (LED) so that the brightness of the LED is adjusted according to the data voltage Dm. For this purpose, the driving transistor T1 receives the driving voltage ELVDD at its input terminal via the fifth transistor T5, and also applies the data voltage Dm via the second transistor T2. The output terminal of the driving transistor T1 is configured to output current to the LED and is connected to the anode of the LED via the sixth transistor T6. Furthermore, the output terminal of the driving transistor T1 is connected to the third transistor T3. The gate electrode 155 of the driving transistor T1 is connected to one electrode of the storage capacitor Cst. Therefore, the voltage at the gate electrode 155 changes according to the voltage stored in the storage capacitor Cst, and the output current output by the driving transistor T1 changes accordingly.

[0172] The second transistor T2 is the transistor that receives the data voltage Dm in pixel PX. The gate electrode of the second transistor T2 is connected to the first scan line 151, the input terminal of the second transistor T2 is connected to the data line 171, and its output terminal is connected to the input terminal of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal GW(n) transmitted through the first scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the input terminal of the driving transistor T1.

[0173] The third transistor T3 is a transistor in which the data voltage Dm is output from the driving transistor T1 and transmitted back to the gate electrode 155 of the driving transistor T1 and one electrode of the storage capacitor Cst. The gate electrode of the third transistor T3 is connected to the first scan line 151, and the input terminal of the third transistor T3 is connected to the output terminal of the driving transistor T1. The output terminal of the third transistor T3 is connected to one electrode of the storage capacitor Cst and the gate electrode 155 of the driving transistor T1. The third transistor T3 is turned on according to the scan signal GW(n) received through the first scan line 151 to connect the gate electrode 155 of the driving transistor T1 and the output terminal of the driving transistor T1 to each other.

[0174] The fourth transistor T4 initializes the gate electrode 155 of the driving transistor T1 and one electrode of the storage capacitor Cst. The gate electrode of the fourth transistor T4 is connected to the second scan line 152, and the input terminal of the fourth transistor T4 is connected to the output terminal of the third transistor T3, one electrode of the storage capacitor Cst, and the gate electrode 155 of the driving transistor T1. The output terminal of the fourth transistor T4 is connected to the initialization voltage line 127. The fourth transistor T4 initializes the voltage V according to the second scan signal GI(n) transmitted through the second scan line 152. INT The voltage is transferred to the gate electrode 155 of the driving transistor T1 and one electrode of the storage capacitor Cst. Therefore, the gate voltage of the storage capacitor Cst and the gate electrode 155 of the driving transistor T1 is initialized. Initialization voltage V INT It has a low voltage value and can be a voltage that enables the driving transistor T1 to conduct.

[0175] The fifth transistor T5 is used to transmit the drive voltage ELVDD to the drive transistor T1. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 153, and the input terminal of the fifth transistor T5 is connected to the drive voltage line 172-1. The output terminal of the fifth transistor T5 is connected to the input terminal of the drive transistor T1.

[0176] The sixth transistor T6 is used to transfer the output current from the driving transistor T1 to the light-emitting diode (LED). The gate electrode of the sixth transistor T6 is connected to the light emission signal line 153, and the input terminal of the sixth transistor T6 is connected to the output terminal of the driving transistor T1. The output terminal of the sixth transistor T6 is electrically connected to the anode pad of the LED through the diode connection portion LDE. As a result, the output current from the driving transistor T1 is transferred to the anode of the LED.

[0177] If the driving voltage ELVDD is applied to the input terminal of the driving transistor T1 through the fifth transistor T5, then the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light emission control signal EM(n) transmitted through the light emission signal line 153, and the driving transistor T1 outputs an output current according to the voltage of the gate electrode 155 of the driving transistor T1 (e.g., the voltage at one terminal of the storage capacitor Cst). The output current is transmitted to the light-emitting diode (LED) through the sixth transistor T6. When the current flows through the LED, the LED emits light.

[0178] The seventh transistor T7 is used to initialize the anode of the light-emitting diode (LED). The gate electrode of the seventh transistor T7 is connected to bypass signal line 158, the input terminal of the seventh transistor T7 is connected to the anode of the LED, and the output terminal of the seventh transistor T7 is connected to initialization voltage line 127. When the seventh transistor T7 is turned on according to the bypass signal GB(n) transmitted through bypass signal line 158, the initialization voltage V... INT It is applied to the anode of the light-emitting diode (LED) and initialized.

[0179] One electrode of the storage capacitor Cst is connected to the gate electrode 155 of the driving transistor T1, the third transistor T3, and the fourth transistor T4, and its other electrode is connected to the driving voltage line 172-1. As a result, the storage capacitor Cst has the function of storing and maintaining the voltage of the gate electrode 155 of the driving transistor T1.

[0180] In some embodiments, the anode of each light-emitting diode (LED) included in the unit light-emitting diode (LED) LDU is electrically connected to the output terminal of the sixth transistor T6 and the input terminal of the seventh transistor T7 via anode corresponding pads LDA1 and LDA2 and diode connection portion LDE, and its cathode receives the common voltage ELVSS via cathode corresponding pads LDC1 and LDC2.

[0181] like Figure 8 As shown, the pixel circuit includes seven transistors T1 to T7 and a capacitor Cst; however, the embodiments are not limited to this, and the number of transistors, the number of capacitors, and their connections can be varied.

[0182] Reference Figure 8 and Figure 9 The operation of a pixel PX of the light-emitting display device according to an embodiment is described.

[0183] The period when the light emission control signal EM(n) has a low voltage is the light emission period, and the fifth transistor T5 and the sixth transistor T6 are turned on, so that the driving voltage ELVDD is applied to the driving transistor T1, and the output current of the driving transistor T1 is transmitted to the anode of the light-emitting diode (LED).

[0184] Subsequently, when the optical emission control signal EM(n) becomes high, the initialization period and the write period are executed.

[0185] The initialization period can be divided into a first initialization period for initializing the voltage of the gate electrode 155 of the driving transistor T1 and a second initialization period for initializing the anode voltage of the light-emitting diode (LED).

[0186] First, the first initialization period is controlled by the second scan signal GI(n). The fourth transistor T4 is turned on by the low voltage of the second scan signal GI(n), and the voltage of the gate electrode 155 of the driving transistor T1 is initialized to the initialization voltage V. INT .

[0187] Next, a write phase in which a data voltage Dm is applied to the pixel circuit unit PXC is performed. This write phase is controlled by the first scan signal GW(n), and the second transistor T2 is turned on by the low voltage of the first scan signal GW(n), and the data voltage Dm is transmitted to the input terminal of the driving transistor T1. At this time, in the driving transistor T1, due to the initialization voltage V applied to the gate electrode 155... INT The data voltage Dm is transmitted to the output terminal of the driving transistor T1.

[0188] The third transistor T3 is also turned on by the low voltage of the first scan signal GW(n), causing the voltage at the output terminal of the driving transistor T1 to be transmitted to the gate electrode 155 of the driving transistor T1 through the third transistor T3. As a result, when the voltage at the gate electrode 155 of the driving transistor T1 gradually increases, and then increases to a voltage lower than the threshold voltage of the driving transistor T1 (e.g., the data voltage Dm), the driving transistor T1 is turned off. At this time, the voltage lower than the threshold voltage of the driving transistor T1 than the data voltage Dm is stored in the storage capacitor Cst.

[0189] In combination Figure 9 In the described embodiment, the first initialization period and the write period are repeated three times, and among the data voltages Dm applied during the write period, the data voltage Dm applied during the third write period is the data voltage of the pixel circuit unit PXC, and the data voltage before it is the data voltage of the previous pixel circuit unit PXC. Applying the previous data voltage first is a driving method that reduces the length of the write period (1H period) by pre-charging.

[0190] When the third write phase ends, the second initialization phase continues. For example, during the second initialization phase, the bypass signal GB(n) is applied as a low voltage, resulting in the seventh transistor T7 turning on to change the anode voltage of the light-emitting diode (LED) to the initialization voltage V. INT .

[0191] Subsequently, the light emission period continues as the light emission control signal EM(n) goes low again. For example, when the fifth transistor T5 is turned on, the driving voltage ELVDD is applied to the input terminal of the driving transistor T1, and an output current is generated based on the difference between the voltage of the driving transistor T1 and the voltage of its gate electrode 155. Here, the voltage of the gate electrode 155 of the driving transistor T1 has a voltage lower than the threshold voltage of the driving transistor T1 than the data voltage Dm, and the threshold voltage is used to turn on the driving transistor T1, and the output current is generated based on the difference between the driving voltage ELVDD and the data voltage Dm. This driving method has the characteristic of compensating for the characteristics of each driving transistor T1, even though the threshold voltage of the driving transistor T1 is different for each pixel circuit unit PXC.

[0192] As described above, the output current generated from the driving transistor T1 passes through the sixth transistor T6, which is turned on by the low voltage of the light emission control signal EM(n), and is transmitted to the anode of the light-emitting diode (LED) via the diode connection portion LDE and the corresponding anode pads LDA1 and LDA2. The light emission level of the LED is adjusted according to the magnitude of the transmitted output current.

[0193] exist Figure 8 The system also includes a capacitor Cled for the light-emitting diode (LED) having electrodes respectively connected to the anode and cathode of the LED. The capacitor Cled for the LED can be a capacitor formed by stacking the anode corresponding pads LDA1 and LDA2 or the diode connection portion LDE with the cathode corresponding pads LDC1 and LDC2, and can perform the function of storing and holding the output current output from the pixel circuit unit PXC in the capacitor Cled for the LED. According to an embodiment, the capacitor Cled for the LED can be omitted.

[0194] Combination Figure 8 The described embodiments also include a pixel output test unit (PXCT).

[0195] The pixel output test unit PXCT is a component used to check whether the pixel circuit unit PXC properly generates output current before the attached unit light-emitting diode (LED) LDU, and according to embodiments, the pixel output test unit PXCT may not be included.

[0196] The pixel output test unit PXCT also includes an eighth transistor T8 and a test signal line 157 for controlling the eighth transistor T8.

[0197] The eighth transistor T8 includes a channel, a semiconductor layer with a first region and a second region located on both sides of the channel, and a gate electrode, and may have a dual-gate structure similar to the third transistor T3 and the fourth transistor T4. For example, in two eighth transistors T8, the channel is formed at the portion where the test signal line 157 and the semiconductor layer 130 meet, and the portion where the test signal line 157 and the semiconductor layer 130 meet is formed in two locations. In this case, the gate electrode of the eighth transistor T8 may be part of the test signal line 157. The input-side terminals of the eighth transistor T8 with the dual-gate structure are connected to the anode corresponding pads LDA1 and LDA2 or the diode connection portion LDE, and the output-side terminals are connected to the cathode corresponding pads LDC1 and LDC2. As a result, if a low voltage is applied to the test signal line 157, the output current of the pixel circuit unit PXC is input to the input-side terminals of the eighth transistor T8 and then output to the output-side terminals. For example, it is possible to check whether the pixel circuit unit PXC is generating an output current normally based on the output current flowing through the eighth transistor T8.

[0198] The light-emitting display device 10, including such a pixel output test unit PXCT, can have the same characteristics as... Figure 2 to Figure 4 Different structures, and through Figure 10A and Figure 10B The description includes a light-emitting display device 10 comprising a pixel output test unit PXCT.

[0199] Figure 10A and Figure 10B This is an upper layout view of the driving area of ​​a light-emitting display device according to an embodiment.

[0200] Figure 10A and Figure 10B A cut will be made at the cutting line, and when the cutting lines of the two drawings are connected, an upper layout diagram of the driving area of ​​the light-emitting display device is shown.

[0201] and Figure 3 In comparison, Figure 10A and Figure 10B In the middle, the pixel output test unit PXCT is located between two adjacent light-emitting diodes (LEDs) LDU in the second direction (y-axis direction), thus... Figure 3 Multiple signal generation units are stacked in the middle. As a result, in order to set up all four types of level EMS, GBS, GIS, and GWS, it is used with... Figure 3 Compared to twice the number of rows.

[0202] Furthermore, the pixel output test unit (PXCT) and multiple signal generation units are arranged alternately. For example, in the left region 10-2 or the right region 10-3, a stage of the signal of the pixel output test unit (PXCT) and multiple signal generation units is alternately arranged between two adjacent light-emitting diode (LED) units (LDUs) along the second direction (y-axis direction). More specifically, the pixel output test unit PXCT is located between the first column of LED LDUs and the second column of LED LDUs; stages EMS1, EMS2, and EMS3 for light emission signals are located between the second and third column of LED LDUs; the pixel output test unit PXCT is located between the third and fourth column of LED LDUs; stages GBS1, GBS2, and GBS3 for bypass signals are located between the fourth and fifth column of LED LDUs; the pixel output test unit PXCT is located between the fifth and sixth column of LED LDUs; and stage GIS1 for the second scan signal... GIS2 and GIS3 are located between the sixth and seventh column LED LDUs, the pixel output test unit PXCT is located between the seventh and eighth column LED LDUs, and the stages GWS1, GWS2 and GWS3 for the first scan signal are located between the eighth and ninth column LED LDUs.

[0203] The central region 10-1 is located after the ninth column unit light-emitting diode (LED) LDU, and from Figure 2 Initially, the pixel output test unit (PXCT) can be separately formed between the unit light-emitting diodes (LEDs) (LDUs). For example... Figure 10A As shown, the pixel output test unit PXCT can be sparsely formed.

[0204] exist Figure 10A and Figure 10BAlthough it is shown that there is space for pixel output test units (PXCTs) to be formed together in the areas forming the four types of level EMS, GBS, GIS, and GWS, according to an embodiment, in order to form a denser unit light-emitting diode (LED) LDU, the pixel output test units (PXCTs) cannot be positioned between adjacent unit light-emitting diode (LED) LDUs having one of the four types of level EMS, GBS, GIS, and GWS. However, according to an embodiment, if space exists, the pixel output test units (PXCTs) and one of the four types of level EM, GB, GIS, and GWS can be located between adjacent unit light-emitting diode (LED) LDUs and can be formed together.

[0205] In the following text, as an example, reference will be made to Figure 11 The description can locate the position of the opening forming region 60A with a dummy opening 60.

[0206] Figure 11 This is a view showing an area in a light-emitting display device according to an embodiment where an opening can be positioned.

[0207] In combination Figure 11 In the described embodiment, a central region 10-1 of the light-emitting display device 10 is shown, along with a pixel circuit unit forming region PXCA and a pixel output test unit PXCT. The pixel circuit unit forming region PXCA can represent a region where six pixel circuit units PXC are formed, and the pixel output test unit PXCT includes an eighth transistor T8 corresponding to three pixel circuit units PXC, thus one pixel output test unit PXCT can include three eighth transistors T8.

[0208] according to Figure 11 This illustrates that, in addition to the pixel circuit unit forming region PXCA in which pixel circuit units PXC are formed and the region in which pixel output test units PXCT are formed, an opening forming region 60A in which a dummy opening 60 can be formed can also be formed. Therefore, the dummy opening 60 can also be formed in the region where the unit light-emitting diode (LED) LDU is attached (see reference). Figure 12 The LDUA, DLA (data line extension area), and SLA (signal line extension area) are all located within this region. Additionally, a dummy opening 60 can even be formed in areas where nothing is formed. Here, "areas where nothing is formed" refers to regions where only an insulating layer is formed, and the dummy opening 60 can be formed within the insulating layer.

[0209] Although the dummy opening 60 can be formed in all opening forming regions 60A, the dummy opening 60 can only be formed in Figure 11 At least one of the opening forming regions 60A shown.

[0210] According to the combination Figure 11 In the left region 10-2 and right region 10-3 of the light-emitting display device 10 described in the embodiment, the dummy opening 60 may not be formed in the region where the signal generating unit is located. For example, in the region where each level of EMS, GBS, GIS and GWS is not located, the opening forming region 60A may not be located.

[0211] Furthermore, based on the combination Figure 11 In the upper region 10-4 and lower region 10-5 of the light-emitting display device 10 described in the embodiment, the dummy opening 60 may not be formed in the region including the data distribution unit of the demultiplexer Demux and the region where the electrostatic discharge (ESD) prevention unit is located, so that the opening forming region 60A may not be located.

[0212] For a dummy opening 60 located in the opening forming region 60A, such as Figure 5 As shown, a dummy opening 60 of a certain size can be formed according to the matrix, and the dummy opening 60 can be formed using a mask with a specific pattern, such as... Figures 27 to 28 As shown in the figure. In addition, the dummy opening 60 can be formed in various sizes and densities.

[0213] In the following text, refer to Figure 12 An embodiment for forming a dummy pattern is described.

[0214] Figure 12 This is a view illustrating a light-emitting display device including a dummy driver according to an embodiment.

[0215] In combination Figure 12 In the described embodiment, the central region 10-1 of the light-emitting display device 10 is shown, and Figure 12 This shows the state where a unit light-emitting diode (LED) LDU is not attached to the area where the unit light-emitting diode (LED) LDU is attached (LED attachment area LDUA).

[0216] like Figure 12 As shown, a pixel circuit unit forming region PXCA, a data line extension region DLA, a signal line extension region SLA, and a pixel output test unit PXCT are also formed, in which a pixel circuit unit PXC is formed. Specifically, a test signal line 157 connected to the gate electrode of the eighth transistor T8 included in the pixel output test unit PXCT is also formed.

[0217] In the central region 10-1 where these constituent elements are arranged, a dummy driver with the same pattern and dummy opening as the signal-generating stages in the left region 10-2 and right region 10-3 can be formed in the region where the signal-generating stages are located, including multiple signal generation units. For example, the same pattern can be formed using the same mask as one of the stages EMS, GBS, GIS, and GWS, and dummy openings can be included (see reference). Figure 27 and Figure 28 (60 in the text). Although the dummy driver has the same pattern as the actual EMS, GBS, GIS and GWS, it has a non-operating structure because no external signal or voltage is applied.

[0218] According to an embodiment, the dummy driver may include only some of the patterns of each level of EMS, GBS, GIS and GWS, and in this case, dummy openings may be included.

[0219] Within the central region 10-1, in the region adjacent to the left region 10-2, at the location where a dummy driver is formed from the leftmost column towards the center according to the arrangement of each level EMS, GBS, GIS, and GWS of the left region 10-2, the level EMS of the optical emission signal generation unit, the level GBS of the bypass signal generation unit, the level GIS of the second scan signal generation unit, and the level GWS of the first scan signal generation unit can be formed sequentially. Furthermore, the same levels can be arranged along a first direction (x-axis direction).

[0220] Within the central region 10-1, in the region adjacent to the right region 10-3, according to the arrangement of each level EMS, GBS, GIS, and GWS in the right region 10-3, from the rightmost column towards the center, the level EMS for the optical emission signal of the optical emission signal generation unit, the level GBS for the bypass signal of the bypass signal generation unit, the level GIS for the second scan signal of the second scan signal generation unit, and the level GWS for the first scan signal of the first scan signal generation unit can be formed sequentially. Furthermore, identical levels can be arranged along a first direction (x-axis direction).

[0221] In addition to the pixel circuit unit forming region PXCA and the pixel output test unit PXCT, the dummy opening 60 can be formed in areas other than the region where the dummy driver is located. For example, the dummy opening 60 can be further formed in the data line extension region DLA, the light-emitting diode (LED) attachment region LDUA, and areas where nothing is formed.

[0222] like Figure 5 As shown, a dummy opening 60 of constant size can be formed according to the matrix, and as... Figure 27 to Figure 28 As shown, a mask with a specific pattern can also be used to form the dummy opening 60. Furthermore, the dummy opening 60 can be formed in various sizes and densities.

[0223] In the following text, refer to Figures 13 to 22 The description provides more details about each stage of EMS, GBS, GIS, and GWS included in multiple signal generation units, the demultiplexer Demux included in the data distribution unit, and the signals applied to them.

[0224] First, refer to Figures 13 to 15 and Figure 22 Describes a level EMS that includes optical emission signals in multiple signal generation units.

[0225] Reference Figure 13 Describe the circuit structure of a stage EMS used for optical signal transmission.

[0226] Figure 13 This is a circuit diagram of a stage for emitting optical signals according to an embodiment.

[0227] According to the embodiment, the stage for each optical transmission signal includes a high-level output unit 2551, a low-level output unit 2552, a first node first controller 2553, a first node second controller 2554, a second node first controller 2555, a second node second controller 2556, a third node controller 2557, a first connection portion 2558, a second connection portion 2559, and a 2-1 node storage unit 2552-1.

[0228] The core structure of each stage for transmitting optical signals is described below.

[0229] The high-level output unit 2551 outputs the high voltage VGH of the optical emission signal, and the low-level output unit 2552 outputs the low voltage VGL of the optical emission signal. The high-level output unit 2551 and the low-level output unit 2552 are connected to the output terminal OUT. When the high-level output unit 2551 outputs the high voltage VGH, the low-level output unit 2552 does not output, and when the low-level output unit 2552 outputs the low voltage VGL, the high-level output unit 2551 does not output.

[0230] The high-level output unit 2551 is controlled based on the voltage of the first node EM_QB, and the voltage of the first node EM_QB is controlled by the first node first controller 2553 and the first node second controller 2554.

[0231] The low-level output unit 2552 is controlled based on the voltage of the second node SR_Q, and the voltage of the second node SR_Q is controlled by the second node first controller 2555. For example, the low-level output unit 2552 is connected to the second node SR_Q via the second connection portion 2559, and is thus controlled based on the voltage of the 2-1 node SR_Q_F. However, since the 212 transistor T212 included in the second connection portion 2559 receives a low voltage VGL as a control terminal and remains in an on state, the low-level output unit 2552 is actually controlled based on the voltage of the second node SR_Q.

[0232] The first node second controller 2554 is controlled by the voltage of the third node SR_QB, and the voltage of the third node SR_QB is controlled by the third node controller 2557. For example, the first node second controller 2554 is connected to the third node SR_QB via a first connection portion 2558 and is controlled according to the voltage of the 3-1 node SR_QB_F. However, since the transistor T211 included in the first connection portion 2558 receives a low voltage VGL as a control terminal and remains in an on state, the first node second controller 2554 is actually controlled according to the voltage of the third node SR_QB.

[0233] Figure 13 The stage for optical transmission signals receives two clock signals, EM_CLK1 and EM_CLK2, and is connected to the stage for optical transmission signals in the next row, such that the two clock signals are exchanged and input. Furthermore, the stage for optical transmission signals is shown receiving the FLM signal (hereinafter also referred to as the start signal) via an input terminal (hereinafter also referred to as the input-side terminal), but if a stage for the preceding optical transmission signal exists, the output of that stage can be input to the input stage.

[0234] Each part of each stage of the optical emission signal is described in more detail below.

[0235] The high-level output unit 2551 includes a 209-transistor T209. The gate electrode of transistor T209 is connected to the first node EM_QB, its input terminal is connected to the high voltage VGH terminal, and its output terminal is connected to the output terminal OUT. Consequently, when the voltage of the first node EM_QB is low, the high voltage VGH is output to the output terminal OUT, and when the voltage of the first node EM_QB is high, transistor T209 is turned off, and no output occurs.

[0236] The low-level output unit 2552 includes a 210 transistor T210. The gate electrode of transistor T210 is connected to node 2-1 SR_Q_F, its input terminal is connected to the low-voltage VGL terminal, and its output terminal is connected to the output terminal OUT. As a result, when the voltage of node 2-1 SR_Q_F is low, the low-voltage VGL is output to the output terminal OUT, and when the voltage of node 2-1 SR_Q_F is high, transistor T210 does not produce any output. Since the 212 transistor T212 included in the second connection portion 2559 receives the low-voltage VGL as a control terminal and remains in the on state, the voltage of node 2-1 SR_Q_F has essentially the same voltage as the voltage of the second node SR_Q. Therefore, the low-level output unit 2552 is controlled by the second node SR_Q.

[0237] The first node first controller 2553 and the first node second controller 2554, which control the voltage of the first node EM_QB, will now be described.

[0238] The first node first controller 2553 includes a transistor (transistor T208, 208) and a capacitor (capacitor Ca201, 201). The gate electrode of transistor T208 is connected to the second node SR_Q, its input terminal is connected to the high voltage VGH terminal, and its output terminal is connected to the first node EM_QB. When the second node SR_Q has a low voltage, transistor T208 transfers the high voltage VGH to the first node EM_QB. Therefore, the first node first controller 2553 is used to change the voltage of the first node EM_QB to the high voltage VGH. The two electrodes of capacitor Ca201 are connected to the input and output terminals of transistor T208, respectively, thus connecting capacitor Ca201 between the first node EM_QB and the high voltage VGH terminal. Therefore, capacitor Ca201 is used to store and hold the voltage of the first node EM_QB.

[0239] In this embodiment, the first node second controller 2554 includes two transistors (transistor T206 of size 206 and transistor T207 of size 207) and one capacitor (capacitor Ca202 of size 202). The gate electrode of transistor T206 of size 206 is connected to the first clock input terminal (in... Figure 13 The input terminal of transistor T207 is connected to node 3-1 SR_QB_F, its output terminal is connected to the first node EM_QB, and its input terminal is connected to the fourth node EM_C. The gate electrode of transistor T207 is connected to node 3-1 SR_QB_F, its output terminal is connected to the fourth node EM_C, and its input terminal is connected to the first clock input terminal. Figure 13(The input terminal applied by EM_CLK2). Since transistor T211, included in the first connection portion 2558, receives a low voltage VGL and remains on, the voltage of node 3-1 SR_QB_F has essentially the same voltage as the voltage of the third node SR_QB. Therefore, transistor T207 is controlled by the third node SR_QB. Thus, the first node second controller 2554 has the function of changing the voltage of the first node EM_QB to the low voltage of the clock signal EM_CLK2 when the voltage of the third node SR_QB and the voltage of the clock signal EM_CLK2 input to the first clock input terminal are both low. Capacitor Ca202 is connected between node 3-1 SR_QB_F and the fourth node EM_C, and the voltage variation at the two terminals can be reduced by using the voltage difference between the two nodes.

[0240] The second node first controller 2555, the second node second controller 2556, and the 2-1 node storage unit 2552-1 that control the voltage of the second node SR_Q will now be described.

[0241] The second node's first controller 2555 consists of a single transistor (transistor T201). The gate electrode of transistor T201 is connected to the second clock input terminal (in...). Figure 13 The input terminal with EM_CLK1 applied is connected to the start signal input terminal (the input terminal with the start signal EM_FLM applied or the input terminal to which the output of the previous optical transmission signal stage is input), and its output terminal is connected to the second node SR_Q. When applied to the second clock input terminal ( Figure 13 When the clock signal EM_CLK1 (applied to the input terminal) is low, transistor T201 changes the voltage of the second node SR_Q to the voltage of the start signal EM_FLM or the output signal of the previous optical transmission stage. For example, the second node first controller 2555 has the function of changing the voltage of the second node SR_Q to a carry signal (start signal EM_FLM or output signal of the previous optical transmission stage) according to the clock signal EM_CLK1.

[0242] The 212 transistor T212 included in the second connection portion 2559 receives the low voltage VGL as a control terminal and remains in the on state, and the voltage of node 2-1 SR_Q_F has the same voltage as the voltage of the second node SR_Q.

[0243] Since the voltage of node SR_Q_F in node 2-1 is the voltage of transistor T210 of the low-level output unit 2552, the voltage of node SR_Q_F in node 2-1 is stored and stabilized through node 2-1 storage unit 2552-1. For example, node 2-1 storage unit 2552-1 includes capacitor Ca203, and capacitor Ca203 is connected to the first clock input terminal ( Figure 13 The input terminal of EM_CLK2 is applied between node 2-1 and node SR_Q_F. Since transistor T201, included in the first controller 2555 of the second node, only operates when EM_CLK1 is low, node SR_Q and node 2-1 SR_Q_F can be floated under high voltage conditions, allowing capacitor Ca203 to maintain a low voltage at node 2-1 SR_Q_F by using low voltages of EM_CLK1 and EM_CLK2 with inverted signals.

[0244] The second node, the second controller 2556, includes two transistors (transistor T202, 202, and transistor T203, 203). Transistor T202's gate electrode is connected to the third node SR_QB, its input terminal is connected to the high-voltage VGH terminal, and its output terminal is connected to the fifth node EM_A. Transistor T203's gate electrode is connected to the first clock input terminal (in...). Figure 13 The input terminal of EM_CLK2 is applied, its input side terminal is connected to the fifth node EM_A, and its output side terminal is connected to the second node SR_Q. When both EM_CLK2 and the third node SR_QB have low voltage, the second controller 2556 of the second node is used to change the voltage of the second node SR_Q to high voltage.

[0245] The third-node controller 2557, which controls the voltage of the third node SR_QB, will now be described.

[0246] The third node controller 2557 includes two transistors (transistor T204, 204 transistors, and transistor T205, 205 transistors). The control terminal of transistor T204 is connected to the second node SR_Q, and its input terminal is connected to the second clock input terminal. Figure 13 The input terminal applied by EM_CLK1 is connected to the third node SR_QB, and its output terminal is connected to the third node SR_QB. Figure 13 The 204 transistor T204 comprises two transistors, each with its control terminal connected to the second node SR_Q for equivalent operation, and has a structure where the input terminal of one transistor and the output terminal of the other transistor are connected to each other. The control terminal of the 205 transistor T205 is connected to the second clock input terminal (in... Figure 13The input terminal to which EM_CLK1 is applied is connected to the low voltage VGL terminal, and its output terminal is connected to the third node SR_QB. Transistor T205 is used to make the voltage of the third node SR_QB low voltage VGL, and transistor T204 is used to change the voltage of the third node SR_QB to the voltage of the clock signal EM_CLK1 when the second node SR_Q has a low voltage.

[0247] Unlike the above, the input and output terminals can be named in reverse order of the magnitude of the voltage to be connected.

[0248] The operation of the stage for optical emission signals, configured as described above, is determined based on the signals applied to two clock input terminals, each with its own clock signal, and the signal applied to the start signal input terminal. The signals applied to the stage for optical emission signals include and are shown in... Figure 22 In the process, the operation of the stages for optical emission signals using EM_CLK1, EM_CLK2, EM_FLM and EM(1) is as follows: Figure 22 As shown in the image.

[0249] Figure 22 Two clock signals EM_CLK1 and EM_CLK2 and a start signal EM_FLM are shown, and EM(1) is also shown as an output signal based on them. For example, the stage output for the optical emission signal is a signal delayed by 1H from the input start signal EM_FLM. The optical emission control signal output from the stage for the optical emission signal is applied not only to the optical emission signal line 153, but also as the start signal EM_FLM to the stage for the optical emission signal in the next row.

[0250] based on Figure 22 The signal Figure 13 The operation of the stage used for optical signal transmission is described below.

[0251] In the following text, the stages used for optical transmission signals are broadly classified into cases where the start signal EM_FLM has a high voltage and cases where the start signal EM_FLM has a low voltage, and the operation according to the change of the voltage level of the clock signal in each category is described.

[0252] First, the operation is described as follows, with a high voltage applied to the start signal input terminal of the stage for optical emission signal, wherein the clock signal EM_CLK2 input to the first clock input terminal has a high voltage and the clock signal EM_CLK1 input to the second clock input terminal has a low voltage (hereinafter referred to as the first case).

[0253] Transistor T206 is turned off due to the high-voltage clock signal EM_CLK2, the first node EM_QB does not change to a low voltage, and transistor T203 also remains off, so the second node second controller 2556 does not operate, and the second node SR_Q does not change to a high voltage.

[0254] Due to the low voltage of the clock signal EM_CLK1, transistors 201 (T201) and 205 (T205) are turned on.

[0255] A high-voltage start signal EM_FLM, input to the start signal input terminal, is applied to the second node SR_Q and the 2-1 node SR_Q_F via transistor T201, thereby changing the voltages of the second node SR_Q and the 2-1 node SR_Q_F to high. Due to the high voltage of the 2-1 node SR_Q_F, transistor T210 is turned off. Furthermore, due to the high voltage of the second node SR_Q, transistors T208 and T204 are turned off.

[0256] Because transistor T205 is turned on, a low voltage VGL is applied to the third node SR_QB and the 3-1 node SR_QB_F. In this situation, when the second node SR_Q has a high voltage, transistor T204 is turned off, thus the voltages of the third node SR_QB and the 3-1 node SR_QB_F are controlled by transistor T205 and changed to the low voltage VGL.

[0257] Transistor T202 is turned on due to the low voltage of the third node SR_QB, causing a high voltage VGH to be applied to the fifth node EM_A; however, since transistor T203 is turned off by the high voltage clock signal EM_CLK2, the second node SR_Q does not change to a high voltage.

[0258] Transistor T207 (207) is turned on by the low voltage of node SR_QB_F (3-1). When transistor T207 is turned on, a high-voltage clock signal EM_CLK2 is applied to node EM_C (4th node). As a result, a high voltage (voltage of node EM_C) and a low voltage (voltage of node SR_QB_F (3-1)) are applied across capacitor Ca202. Furthermore, transistor T207 is turned on; however, since transistor T206 (206) is turned off by the high-voltage clock signal EM_CLK2, the voltage of node EM_QB (1st node) remains unchanged. Furthermore, since transistor T208 (208) is turned off, the voltage of node EM_QB (1st node) does not change even under the condition of a high voltage VGH, and maintains its existing voltage level.

[0259] For example, when the stage used for optical signal transmission is the first stage, the voltage of the first node EM_QB remains unchanged and maintains its existing voltage level. For example, when the stage used for optical signal transmission outputs a high voltage VGH through transistor T209, it can continuously output a high voltage VGH. At this time, since the second node SR_Q and the 2-1 node SR_Q_F have high voltages, a low voltage is not output through transistor T210.

[0260] The second case for the stage used for optical signal transmission will now be described. That is, the operation of the stage for optical signal transmission, in which the clock signal EM_CLK2 input to the first clock input terminal has a low voltage and the clock signal EM_CLK1 input to the second clock input terminal has a high voltage (hereinafter referred to as the second case), will be described as follows:

[0261] First, transistors 201 (T201) and 205 (T205) are turned off by a high-voltage clock signal EM_CLK1.

[0262] When transistor T201 is turned off, the voltages of the second node SR_Q and the 2-1 node SR_Q_F remain unchanged. Furthermore, the voltages of the third node SR_QB and the 3-1 node SR_QB_F do not change when transistor T205 is turned off.

[0263] Transistor T206 (206) is turned on due to the low-voltage clock signal EM_CLK2. At this time, transistor T207 (207) is turned on by the voltage of node SR_QB_F (e.g., the voltage stored in capacitor Ca202, 202). As a result, the low-voltage clock signal EM_CLK2 is applied to the first node EM_QB, and the voltage of the first node EM_QB is then changed to a low voltage. Therefore, when the stage used for the optical transmission signal is the second case, the voltage of the first node EM_QB changes to a low voltage, and then the high-voltage output VGH is initiated by transistor T209 (209).

[0264] In some embodiments, the second node SR_Q and the 2-1 node SR_Q_F are changed to high voltage by the second node second controller 2556. For example, transistor 203 T203 is turned on due to the low voltage clock signal EM_CLK2, and transistor 202 T202 is also turned on by the voltage of the third node SR_QB (e.g., the voltage of the 3-1 node SR_QB_F stored in capacitor 202 Ca202), and then the high voltage VGH is transmitted to the second node SR_Q. As a result, transistor 210 T210 is turned off and no low voltage is output.

[0265] The third case for the stage used for optical signal transmission will now be described. That is, the case where a low voltage is applied to the start signal input terminal of the stage used for optical signal transmission. The operation of the case in which the clock signal EM_CLK2 input to the first clock input terminal has a high voltage and the clock signal EM_CLK1 input to the second clock input terminal has a low voltage (hereinafter referred to as the third case) will now be described.

[0266] Because of the high-voltage clock signal EM_CLK2, transistor T206 is turned off, so the first node EM_QB does not change to a low voltage, and transistor T203 is also turned off, so the second node SR_Q also has a high voltage.

[0267] Transistor T201 (201) and transistor T205 (205) are turned on due to the low-voltage clock signal EM_CLK1.

[0268] A low-voltage start signal EM_FLM, input to the start signal input terminal via transistor T201, is applied to the second node SR_Q and node 2-1 SR_Q_F. Then, the second node SR_Q and node 2-1 SR_Q_F are changed to low voltage. Due to the low voltage at node 2-1 SR_Q_F, transistor T210 turns on and begins outputting a low voltage VGL.

[0269] Furthermore, transistors 208 (T208) and 204 (T204) are turned on due to the low voltage at the second node SR_Q. With transistor 208 on, the first node EM_QB changes to a high voltage VGH, and transistor 209 (T209) is turned off.

[0270] Because transistor T205 (205) is turned on, a low voltage VGL is applied to the third node SR_QB and the 3-1 node SR_QB_F. At this time, transistor T204 (204) is also turned on by the low voltage of the second node SR_Q, and the voltages of the third node SR_QB and the 3-1 node SR_QB_F are controlled by transistors T205 (205) and T204 (204) and changed to the low voltage VGL.

[0271] Transistor T202 is turned on due to the low voltage of the third node SR_QB, but transistor T203 is turned off due to the high voltage clock signal EM_CLK2, and the second node SR_Q remains at a high voltage.

[0272] Due to the low voltage at node 3-1 SR_QB_F, transistor T207 is turned on. However, because transistor T206 is turned off due to the high voltage clock signal EM_CLK2, the voltage at node EM_QB remains unchanged.

[0273] For example, when the stage used for optical signal transmission is the third case, the voltage of the first node EM_QB is changed to a high voltage VGH, causing transistor T209 to stop operating, and the second node SR_Q and the 2-1 node SR_Q_F are changed to low voltage, and the low voltage VGL is started to be output through transistor T210.

[0274] The fourth case for the stage used for optical signal transmission will now be described. That is, the case where a low voltage is applied to the start signal input terminal of the stage used for optical signal transmission, and the operation of the case in which the clock signal EM_CLK2 input to the first clock input terminal has a low voltage and the clock signal EM_CLK1 input to the second clock input terminal has a high voltage (hereinafter referred to as the fourth case) will now be described.

[0275] First, transistors 201 (T201) and 205 (T205) are turned off due to the high-voltage clock signal EM_CLK1.

[0276] Transistor T201 is turned off, and the voltages of the second node SR_Q and the 2-1 node SR_Q_F remain unchanged. Furthermore, the voltages of the third node SR_QB and the 3-1 node SR_QB_F do not change even when transistor T205 is turned off.

[0277] Transistor T206 (206) is turned on due to the low-voltage clock signal EM_CLK2. At this time, transistor T207 (207) can be turned on by the voltage at node 3-1 SR_QB_F (e.g., the voltage stored in capacitor Ca202, 202). As a result, a low-voltage clock signal EM_CLK2 can be applied, but due to the low voltage at the second node SR_Q, transistor T208 remains on, so the first node EM_QB is continuously supplied with a high voltage VGH without any change in voltage.

[0278] Therefore, when the stage used for optical transmission signal is the fourth case, the voltage of the first node EM_QB remains high, then transistor 209 T209 does not operate, and since the second node SR_Q and the 2-1 node SR_Q_F can maintain the existing low voltage, transistor 210 T210 continues its previous operation and outputs a low voltage.

[0279] Through the basic operation described above, the start signal EM_FLM input to the input terminal is delayed by 1H and can be output as a light emission control signal. The output light emission control signal is not only applied to the light emission signal line 153, but also applied as the start signal EM_FLM to the stage for light emission signals in the next row.

[0280] In the next row of stages for optical transmission signals, clock signal EM_CLK1 is applied to the first clock input terminal to which clock signal EM_CLK2 is applied, and clock signal EM_CLK2 is applied to the second clock input terminal to which clock signal EM_CLK1 is applied.

[0281] In the following text, reference will be made to Figure 14 and Figure 15 A more detailed structure of the stage for emitting optical signals according to an embodiment is described below.

[0282] Figure 14 This is a layout diagram of a stage for emitting optical signals according to an embodiment. Figure 15 This is a cross-sectional view of a stage for emitting optical signals according to an embodiment.

[0283] exist Figure 14 In the diagram, the mark represented by 'x' in the square indicates an opening located on the insulating layer, allowing the upper conductive layer and the lower conductive layer to be electrically connected to each other.

[0284] The transistors and capacitors included in the stage for emitting optical signals have the same cross-sectional structure.

[0285] and Figure 15 The 210 transistor shown is similar, and each transistor in the stage for emitting optical signals includes a semiconductor layer C210, a first insulating layer 140, and a gate electrode on a substrate 110. A channel is located at the portion where the semiconductor layer C210 and the gate electrode overlap each other, and source and drain regions, which are plasma-treated or doped to form conductors, are located on both sides of the channel in the semiconductor layer. This stacked structure is formed by the substrate 110, the semiconductor layer, the first insulating layer 140, the first gate conductive layer, the second insulating layer 141, the second gate conductive layer, the third insulating layer 142, the first data conductive layer, and the fourth insulating layer 143.

[0286] The first gate conductive layer includes the gate electrode of all transistors.

[0287] The gate electrode G201 of transistor T201 extends and is electrically connected to a second clock wiring 2103 to which the clock signal CLK1 is applied. Semiconductor layer C201 includes a channel, a source region, and a drain region. One side of semiconductor layer C201 is electrically connected to connection line 2205, to which the start signal EM_FLM or the output of the stage used for the previous optical emission signal is transmitted, and the other side is connected to connection portion 2301, which is electrically connected to the gate electrode G204 of transistor T204. Connection portion 2301 is located in the first data conductive layer. Transistor T201 is connected to transistors T208 and T212 via connection portion 2301, and semiconductor layer C201 extends directly and is also connected to transistor T203.

[0288] The gate electrode G202 of transistor T202 extends and is electrically connected to the connection portion 2302 for connecting transistors T204 and T211. One side of semiconductor layer C202 is electrically connected to a high-voltage wiring 2101 to which a high voltage VGH is applied, and the other side is directly connected to semiconductor layer C203 of transistor T203. The gate electrode G202 further extends and is electrically connected to the connection portion 2303, and is also electrically connected to transistors T204 and T205. Connection portions 2302 and 2303 are located in a first data conductive layer.

[0289] The gate electrode G203 of transistor T203 extends and is electrically connected to transistors T206 and T207, and capacitor Ca203 via connection portion 2304. One side of semiconductor layer C203 is connected to connection portion 2301, transistor T201 and semiconductor layer C203 extend directly to be connected, and the other side of semiconductor layer C203 extends and is directly connected to the semiconductor layer of transistor T202. Connection portion 2304 is located in the first data conductive layer.

[0290] The gate electrode G204 of transistor 204 consists of two parts: it is connected to one side of transistor 201 (T201) and electrically connected to connection portion 2301, and further extends to electrically connect to the gate electrode G208 of transistor 208 (T208) and one side of transistor 212 (T212). One side of semiconductor layer C204 is connected to connection portion 2303 to connect to one side of transistor 205 (T205), and is also additionally connected to the gate electrode G202 of transistor 202 (T202) and one side of transistor 211 (T211). The other side of semiconductor layer C204 is electrically connected via connection portion 2305 to a terminal of transistor 205 (T205) and a second clock wiring 2103 to which clock signal CLK1 is applied. Connection portion 2305 is located in the first data conductive layer.

[0291] The gate electrode G205 of transistor T205 extends to be electrically connected to a second clock wiring 2103 to which a clock signal CLK1 is applied, and further extends to the gate electrode G201 of transistor T201. One side of semiconductor layer C205 is electrically connected to a low-voltage wiring 2102 to which a low voltage VGL is applied, and the other side is electrically connected via connection portion 2303 to the gate electrodes G202 of transistors T204 and T202, and a terminal of transistor T211.

[0292] The gate electrode G206 of transistor T206 is electrically connected to connection portion 2304, and is electrically connected to the first clock wiring 2104 for applying the CLK2 clock signal via capacitor Ca203. It is also electrically connected to the gate electrode G203 of transistor T203 and a terminal of transistor T207 via connection portion 2304. One side of semiconductor layer C206 is connected to connection portion 2307 to connect to capacitor Ca201, one side of transistor T208, and the gate electrode G209 of transistor T209. The other side extends directly to connect to one side of transistor T207 and is electrically connected to capacitor Ca202 via connection portion 2308. Connection portions 2307 and 2308 are located in the first data conductive layer.

[0293] The gate electrode G207 of transistor T207 extends to form one electrode of capacitor Ca202 (202) and is connected to connection portion 2309 to connect to one end of transistor T211 (211). One side of semiconductor layer C207 is connected to connection portion 2304 to connect to the gate electrode G206 of transistor T206 and the gate electrode G203 of transistor T203, and is electrically connected to the first clock wiring 2104, through which the CLK2 clock signal is applied. The other side extends directly to connect to one side of transistor T206 and is connected to connection portion 2308 to electrically connect to the other electrode 202 of capacitor Ca202 (202).

[0294] The gate electrode G208 of transistor T208 extends to connect to one side of transistor T212, and is electrically connected to one side of transistor T201 and the gate electrode G204 of transistor T204 via connection portion 2301. One side of semiconductor layer C208 is connected to connection portion 2306 to connect to capacitor Ca201 and one side of transistor T206, and the other side is connected to connection portions 2310 and 2101-1 to electrically connect to high-voltage wiring 2101 to which a high voltage VGH is applied, and extends to a terminal of transistor T202. Connection portions 2306 and 2310 are located in the first data conductive layer, and connection portion 2101-1 is located in the second gate conductive layer.

[0295] The gate electrode G209 of transistor T209 is divided into multiple (in) Figure 14 The semiconductor layer C209 (consisting of four gate electrodes) extends to connect to capacitor Ca201 (201) and is connected to one side of transistor T206 (206) via connection portion 2307. One side of semiconductor layer C209 is electrically connected to high-voltage wiring 2101 via input-side electrode SD209 and connection portion 2101-2, and the other side is connected to output wiring 2201. Input-side electrode SD209 is located in the first data conductive layer, and connection portion 2101-2 is located in the second gate conductive layer.

[0296] The gate electrode G210 of transistor T210 is divided into multiple (in) Figure 14 The semiconductor layer C210 consists of four gate electrodes and is connected to capacitor Ca203 via connection portion 2311, and extends to the other side to connect to a terminal of transistor T212. One side of the semiconductor layer C210 is electrically connected to low-voltage wiring 2102 via input-side electrode SD210, and the other side is connected to output wiring 2201. Input-side electrode SD210 is located in the first data conductive layer.

[0297] The output wiring 2201 is electrically connected to the optical emission signal line 153 via the extension connection line 2202 and the connection portion 2202-1. The connection portion 2202-1 is located in the first gate conductive layer, and the connection line 2202 is located in the first data conductive layer.

[0298] The gate electrode G211 of transistor T211 extends to be electrically connected to low-voltage wiring 2102. One side of semiconductor layer C211 is connected to connection portion 2309 to connect to capacitor Ca202 of 202 and a terminal of transistor T207 of 207, and the other side is connected to the gate electrode G202 of transistor T202 of 202, a terminal of transistor T204 of 204 and a terminal of transistor T205 of 205 via connection portion 2302.

[0299] The gate electrode G212 of transistor T212 extends to be electrically connected to low-voltage wiring 2102. One side of semiconductor layer C212 is electrically connected to the gate electrode G210 of transistor T210, and the other side is electrically connected to one side of transistor T201, one side of transistor T203, the gate electrode G204 of transistor T204, and the gate electrode of transistor T208.

[0300] like Figure 15 Like the 203 capacitor Ca203 shown, capacitors Ca201, Ca202 and Ca203 have a cross-sectional structure including a first gate conductive layer and a second gate conductive layer as two electrodes and a second insulating layer 141 located therebetween as a dielectric material.

[0301] In capacitor Ca201 of type 201, one electrode 2212 is connected to high voltage wiring 2101, and another electrode 2211 extends to connect to the gate electrode G209 of transistor T209 of type 209, a terminal of transistor T206 of type 206, and a terminal of transistor T208 of type 208.

[0302] In capacitor Ca202 of 202, one electrode 2222 is connected to a terminal of transistor T206 of 206 and a terminal of transistor T207 of 207 via connection portion 2308, and another electrode 2221 extends to connect to the gate electrode G207 of transistor T207 of 207 and is connected to a terminal of transistor T211 of 211 via connection portion 2309.

[0303] In capacitor Ca203, one electrode 2232 is electrically connected via connection portion 2304 to the gate electrode G203 of transistor T203, the gate electrode G206 of transistor T206, a terminal 207 of transistor T207, and a first clock wiring 2104 to which the CLK2 clock signal is applied, and the other electrode 2231 is connected via connection portion 2311 to the gate electrode G210 of transistor T210.

[0304] In the following text, reference will be made to Figures 16 to 18 and Figure 22 The description includes a stage for scanning signals in multiple signal generation units. The stage for scanning signals can be shared with the stage for the first scanning signal GWS, the stage for the second scanning signal GIS, and the stage for the bypass signal GBS, and are the same stage, but the input clock signal and start signal are different to produce different outputs.

[0305] For example, in Figure 22 In the process, when the stage used for the scan signal is used as the stage used for the second scan signal GIS, CLK1 and CLK2 are applied as clock signals, and GI_FLM is applied as the start signal.

[0306] On the other hand, Figure 22 In the process, when the stage used for the scan signal is also used for the first scan signal GWS, CLK1 and CLK2 can be applied as clock signals, and a signal 1H later than GI_FLM is applied as the start signal. This is because the first scan signal GW(1) is a signal 1H later than the second scan signal GI(1).

[0307] In addition, Figure 22 In the process, when the stage used for scanning signals is used as the stage GBS used for bypass signals, CLK1 and CLK2 are applied as clock signals, and GB_FLM is applied as a start signal.

[0308] On the other hand, when the stage for scanning signals is used as the stage for the first scanning signal GWS, the stage for the second scanning signal GIS, and the stage for bypass signals GBS, the input terminals to which the clock signals are input can be interchanged. For example, in the stage for scanning signals in the current row, if clock signal CLK1 is applied to the first input terminal, then clock signal CLK2 is applied to the second input terminal; however, in the stage for scanning signals in the next row, clock signal CLK2 is applied to the first input terminal, and clock signal CLK1 is applied to the second input terminal.

[0309] In the following text, reference will be made to Figure 16 Describe the circuit structure of the stage used for scanning signals.

[0310] Figure 16 This is a circuit diagram of a stage for scanning signals according to an embodiment.

[0311] According to this embodiment, the stage for each scan signal includes a high-level output unit 3551, a low-level output unit 3552, a first node first controller 3555, a first node second controller 3556, a second node first controller 3553, a second node second controller 3554, and a first connection portion 3557.

[0312] The core structure of each scan signal stage is described below.

[0313] The high-level output unit 3551 is the component that outputs the high voltage VGH of the scan signal, and the low-level output unit 3552 is the component that outputs the low voltage VGL of the scan signal. The high-level output unit 3551 and the low-level output unit 3552 are connected to the output terminal OUT. When the high-level output unit 3551 outputs the high voltage VGH, the low-level output unit 3552 outputs, and when the low-level output unit 3552 outputs the low voltage VGL, the high-level output unit 3551 does not output.

[0314] The high-level output unit 3551 is controlled according to the voltage of the first node QB, and the voltage of the first node QB is controlled by the first controller 3555 and the second controller 3556 of the first node.

[0315] The low-level output unit 3552 is controlled by the voltage of the second node Q, and the voltage of the second node Q is controlled by the second node first controller 3553 and the second node second controller 3554. For example, the low-level output unit 3552 is connected to the second node Q via the first connection portion 3557, and therefore is controlled according to the voltage of the 2-1 node QF. However, since the 308 transistor T308 included in the first connection portion 3557 receives the low voltage VGL as a control terminal, it remains in the on state, so the low-level output unit 3552 is actually controlled according to the voltage of the second node Q.

[0316] Figure 16 The stage for scanning signals receives two clock signals, CLK1 and CLK2, and is connected to the stage for scanning signals in the next row, allowing the two clock signals to be swapped and input. Furthermore, Figure 16 The scanning signal stage is shown as receiving a start signal (FLM signal) through the input terminal, but when there is a previous stage for the scanning signal (the stage for the previous scanning signal), the output of the previous stage for the scanning signal can be input to the input terminal.

[0317] More detailed information about each part of the stage used to scan the signal is described below.

[0318] The high-level output unit 3551 includes a 306 transistor T306 and a 301 capacitor Ca301. The gate electrode of the 306 transistor T306 is connected to the first node QB, its input terminal is connected to the high voltage VGH terminal, and its output terminal is connected to the output terminal OUT. Consequently, when the voltage of the first node QB is low, the high voltage VGH is output to the output terminal OUT, and when the voltage of the first node QB is high, the 306 transistor T306 is turned off and no output occurs. The high voltage VGH is applied to one terminal of the 301 capacitor Ca301, and the other terminal is connected to the first node QB to maintain the voltage of the first node QB.

[0319] The low-level output unit 3552 includes a 307 transistor T307 and a 302 capacitor Ca302. The gate electrode of the 307 transistor T307 is connected to node 2-1 QF, its input terminal is connected to the first input terminal to which the first clock signal CLK1 is applied, and its output terminal is connected to the output terminal OUT. As a result, when the voltage of node 2-1 QF is low, the voltage of the first clock signal CLK1 is output to the output terminal OUT, and when the voltage of node 2-1 QF is high, the 307 transistor T307 does not produce any output. Here, to make node 2-1 QF low, a low voltage must be applied to the second node Q as a start signal FLM, and the low voltage applied to node 2-1 QF is stored in the 302 capacitor Ca302. At this time, the voltage of the first clock signal CLK1 is output to the output terminal OUT. The transistor T308, included in the first connection portion 3557, receives a low voltage VGL from the control terminal and remains on, so the voltage at node 2-1 QF has essentially the same voltage as the voltage at the second node Q. Therefore, the low-level output unit 3552 is controlled by the second node SR_Q. One terminal of capacitor Ca302 (302) is connected to the output terminal OUT, and the other terminal is connected to node 2-1 QF, thereby storing and holding the voltage at node 2-1 QF.

[0320] The first node first controller 3555 and the first node second controller 3556, which are used to control the voltage of the first node QB, will now be described.

[0321] The first node first controller 3555 includes a 304 transistor T304. The gate electrode of the 304 transistor T304 is connected to the second node Q, its input terminal is connected to the first input terminal to which the second clock signal CLK2 is applied, and its output terminal is connected to the first node QB. As a result, the voltage of the first node QB is controlled according to the voltage of the second node Q, and in some embodiments, the voltage of the first node QB is changed to the high voltage of the clock signal.

[0322] The first node second controller 3556 includes a 305 transistor T305. The gate electrode of the 305 transistor T305 is connected to a first input terminal to which a second clock signal CLK2 is applied, its input side terminal receives a low voltage VGL, and its output side terminal is connected to the first node QB. As a result, according to the second clock signal CLK2 input to the first input terminal, the voltage of the first node QB changes to a low voltage VGL.

[0323] The second node first controller 3553 and the second node second controller 3554, which are used to control the voltage of the second node Q, will now be described.

[0324] The second node first controller 3553 includes a 301 transistor T301. The gate electrode of transistor T301 is connected to a first input terminal to which a second clock signal CLK2 is applied. Its input side terminals are connected to a start signal input terminal (the input terminal to which the start signal (FLM signal) or the output of the stage used for the previous scan signal is input), and its output side terminals are connected to the second node Q. Transistor T301 can consist of two transistors, with their gate electrodes connected to the first input terminal in the same manner. One transistor's input side terminal is connected to the start signal input terminal, and the other transistor's output side terminal is connected to the second node Q. The output side terminals of one transistor and the input side terminals of the other transistor can be connected to each other. As a result, according to the second clock signal CLK2 input to the first input terminal, the voltage of the second node Q is changed to the voltage input to the start signal input terminal.

[0325] The second node, second controller 3554, includes transistors 302 (T302) and 303 (T303). The gate electrode of transistor 302 is connected to the first node (QB), its input terminal receives a high voltage VGH, and its output terminal is connected to the input terminal of transistor 303 (T303). The gate electrode of transistor 303 (T303) is connected to a second input terminal to which a first clock signal CLK1 is applied, its input terminal is connected to the output terminal of transistor 302 (T302), and its output terminal is connected to the second node Q. Consequently, when the first node QB has a low voltage and the first clock signal CLK1 has a low voltage, the second node Q becomes high voltage VGH. Therefore, when the first node QB has a low voltage VGL and the first clock signal CLK1 has a low voltage, the voltage of the second node Q is high voltage VGH.

[0326] Unlike the above, the input and output terminals can be named in reverse order of the magnitude of the voltage to be applied.

[0327] The operation of the scanning signal stage with such a configuration is determined based on the signals applied to two clock input terminals and a start signal input terminal, which respectively apply two clock signals.

[0328] When the stage used for the scan signal is used as the stage for the first scan signal GWS, the stage for the second scan signal GIS, and the stage for the bypass signal GBS, CLK1 and CLK2 are used as follows: Figure 22 The clock signal shown is used, and different start signals are applied as start signals. For example, Figure 22 shows GI_FLM as the start signal applied when the stage used for it is used as the stage for the second scan signal GIS, and GB_FLM as the start signal applied when the stage used for it is used as the stage for the bypass signal GBS. Meanwhile, when the stage used for it is used as the stage for the first scan signal GWS, a signal 1 hour later than GI_FLM is applied as the start signal.

[0329] Since the operation is the same, therefore, by using Figure 22 CLK1, CLK2, and GI_FLM are used to focus on and describe the case of the level used for the second scan signal GIS among the three levels.

[0330] The output of the stage's output terminal OUT for scanning signals is determined by the operation of transistors 306 (T306) and 307 (T307).

[0331] When transistor T305 is turned on, since the first node QB has a low voltage VGL, transistor T306, which outputs a high voltage VGH, outputs VGH to the output terminal OUT. Transistor T305 is turned on only when the second clock signal CLK2 applied to the first input terminal has a low voltage. Therefore, if the second clock signal CLK2 applied to the first input terminal has a low voltage, the stage used for the scan signal outputs a high voltage VGH.

[0332] When the second clock signal CLK2 is low, transistor T301 is also turned on, and the start signal FLM or the output of the previous stage used for the scan signal is transmitted to the second node Q and the 2-1 node QF and stored in capacitor Ca302. At this time, if the start signal FLM or the output of the previous stage used for the scan signal has a high voltage, transistor T307 is not turned on and does not operate. However, when the start signal FLM or the output of the previous stage used for the scan signal has a low voltage, transistor T307 is turned on to output the first clock signal CLK1. If the second clock signal CLK2 has a low voltage, the first clock signal CLK1 has a high voltage, therefore the output terminal OUT of the stage used for the scan signal outputs a high voltage. However, when the second clock signal CLK2 has a high voltage, transistor T307 is turned on by the low voltage stored in capacitor Ca302, and at this time outputs the first clock signal CLK1 (i.e., low voltage).

[0333] Therefore, in the stage used for the scan signal, when the second clock signal CLK2 has a low voltage, the start signal FLM or the output of the previous stage used for the scan signal is stored in capacitor 302 Ca302. Then, when the second clock signal CLK2 has a high voltage, the low-voltage first clock signal CLK1 is output through transistor 307 T307. Thus, there is a clock signal difference between the input and output, and the output is delayed by a clock signal width of 1H.

[0334] Reference Figure 22 The GI_FLM start signal has a different waveform than the output second scan signal GI(1). However, since the GI_FLM start signal actually used in the operation of the stage used for the scan signal is only the voltage when the second clock signal CLK2 has a low voltage, applying GI_FLM as the start signal or applying the second scan signal GI(n) of the previous stage will produce the same output.

[0335] Furthermore, in some embodiments, three low voltages exist in a frame for the first scan signal GW(n) and the second scan signal GI(n), but only one low voltage exists in a frame for the bypass signal GB(n). However, according to an embodiment, only one low voltage may exist in a frame for all the first scan signals GW(n), the second scan signal GI(n), and the bypass signal GB(n).

[0336] In the following text, refer to Figure 17 and Figure 18 Describe the structure of the stage used for scanning signals.

[0337] Figure 17 This is a layout diagram of the stages for scanning signals according to an embodiment. Figure 18 This is a cross-sectional view of a level for scanning signals according to an embodiment.

[0338] exist Figure 17 In the diagram, the mark represented by 'x' in the square indicates an opening located in the insulating layer that electrically connects the upper and lower conductive layers to each other.

[0339] like Figure 18 Like the 306 transistor T306 shown, each transistor in the stage for scanning signals includes a semiconductor layer, a first insulating layer 140, and a gate electrode on a substrate 110, with a channel located at the portion where the semiconductor layer and the gate electrode are stacked, and source and drain regions, which are plasma-treated or doped and made into conductors, located on both sides of the channel in the semiconductor layer.

[0340] The gate electrode G301 of transistor 301 T301 consists of two parts: one side extends to the gate electrode G305 of transistor 305 T305, and the other side extends to be electrically connected to the first clock wiring 2104 to which the CLK2 clock signal is applied. Additionally, the gate electrode G301 is connected to one side of transistor 304 T304 via connection portion 3302. One side of semiconductor layer C301 is electrically connected to connection line 3205, to which the start signal (FLM signal) or the output of the previous stage used for the scan signal is transmitted, and the other side is connected to the gate electrode G304 of transistor 304 T304, one side of transistor 308 T308, and one side of connection portion 3301 electrically connected to transistor 303 T303. Connection portions 3301 and 3302 are located in the first data conductive layer.

[0341] The gate electrode G302 of transistor 302 extends to one electrode 3211 of transistor 306 (T306) and capacitor Ca301 (Ca301). It is also connected to connection portion 3303 to electrically connect to one side of transistor 304 (T304) and one side of transistor 305 (T305). One side of semiconductor layer C302 is electrically connected to a high-voltage wiring 3101 to which a high voltage VGH is applied, and the other side is directly connected to one side of transistor 303 (T303), which has a semiconductor layer. For example, semiconductor layer C302 extends and is integral with the semiconductor layer C303 of transistor 303 (T303). Connection portion 3303 is located in the first data conductive layer.

[0342] The gate electrode G303 of transistor 303 extends to one side to be electrically connected to the second clock wiring 3103 on which the clock signal CLK1 is applied, and extends to the other side to be connected to one side of transistor 307 T307. One side of semiconductor layer C303 is connected to one side of transistor 301 T301 via connection portion 3301, and semiconductor layer C303 extends to be directly connected to one side of transistor 302 T302, which has a semiconductor layer.

[0343] The gate electrode G304 of transistor 304 extends to one side to connect to transistors 301 and 303 via connection portion 3301, and extends to the other side to connect to one side of transistor 308 via connection portion 3304. One side of semiconductor layer C304 is connected to the gate electrode G301 of transistor 301 via connection portion 3302, and the other side is electrically connected to the gate electrode G302 of transistor 302, the gate electrode G306 of transistor 306, and one side of transistor 305 via connection portion 3303. Connection portion 3304 is located in the first data conductive layer.

[0344] The gate electrode G305 of transistor 305 extends to connect to the gate electrode G301 of transistor 301, and is electrically connected to the first clock wiring 2104 to which the CLK2 clock signal is applied. One side of semiconductor layer C305 is electrically connected to a low-voltage wiring 3102 to which a low voltage VGL is applied, and the other side is electrically connected via connection portion 3303 to the gate electrode G302 of transistor 302, the gate electrode G306 of transistor 306, and one side of transistor 304.

[0345] The gate electrode G306 of the 306 transistor T306 is divided into multiple (in) Figure 17The semiconductor layer C306 consists of two gate electrodes and extends to connect to one electrode 3211 of capacitor Ca301 (301) and the gate electrode G302 of transistor T302 (302). One side of the semiconductor layer C306 is connected to one electrode 3212 of capacitor Ca301 via a connection electrode SD306, and is electrically connected to high-voltage wiring 3101 via capacitor Ca301. The other side of the semiconductor layer C306 is connected to output wiring 3201. The connection electrode SD306 is located in the first data conductive layer.

[0346] The gate electrode G307 of transistor T307 is divided into multiple (in) Figure 17 The semiconductor layer C307 consists of four gate electrodes, and a portion of it forms an electrode 3221 of the 302 capacitor Ca302, extending to a terminal of the 308 transistor T308 via a connection portion 3305. One side of the semiconductor layer C307 is electrically connected to the gate electrode G303 of the 303 transistor T303 via a connection electrode SD307, and is also connected to the second clock wiring 2103, to which the clock signal CLK1 is applied. The other side of the semiconductor layer C307 is connected to the output wiring 3201. The connection electrode SD307 is located in the first data conductive layer.

[0347] Output wiring 3201 is electrically connected to the signal line via connection portion 3101-1 and connection line 3202. Output wiring 3201 and connection line 3202 are located in the first data conductive layer, and connection portion 3101-1 is located in the first gate conductive layer. When the stage used for the scan signal is the stage used for the first scan signal GWS, the signal line is the first scan line 151; when it is the stage used for the second scan signal GIS, the signal line is the second scan line 152; and when it is the stage used for the bypass signal GBS, the signal line is the bypass signal line 158.

[0348] The gate electrode G308 of transistor T308 extends and is electrically connected to a low-voltage wiring 3102 to which a low voltage VGL is applied. One side of semiconductor layer C308 is electrically connected to the gate electrode G307 of transistor T307 via connection portion 3305, and the other side is electrically connected to the gate electrode G304 of transistor T304 via connection portion 3304.

[0349] Capacitors Ca301 and Ca302 have a cross-sectional structure comprising a first gate conductive layer and a second gate conductive layer as two electrodes and a second insulating layer 141 located between them as a dielectric material.

[0350] For capacitor Ca301 of 301, one electrode 3212 extends to connect to high voltage wiring 3101, and another electrode 3211 is located at a portion of the gate electrode G306 of transistor T306 of 306.

[0351] For capacitor 302 Ca302, one electrode 3222 is electrically connected to the output wiring 3201, and the other electrode 3221 is located at a portion of the gate electrode G307 of transistor 307 T307.

[0352] In the following text, reference will now be made to Figures 19 to 22 The description includes the demultiplexer Demux in the data allocation unit.

[0353] First, refer to Figure 19 Describe the circuit structure of the demultiplexer Demux.

[0354] Figure 19 This is a circuit diagram of the data allocation unit according to an embodiment.

[0355] The demultiplexer Demux has one input terminal and three output terminals, and the signals input to the input terminal are output to the output terminals selected by the selection signals CLA, CLB and CLC.

[0356] The demultiplexer Demux includes three transistors T401, T402, and T403. The input-side terminals are connected to the main data line 170-0 to input the main data voltage DATA, and each data line 171R, 171G, and 171B is connected to the output-side terminals.

[0357] In transistor T401 (401), the gate electrode is connected to the first select line 4201, the input-side terminal is connected to the main data line 170-0, and the output-side terminal is connected to the red data line 171R. Transistor T401 selects a portion of the main data voltage DATA by applying a CLA select signal to the first select line 4201, and applies this portion as the data voltage Dmr to the red data line 171R.

[0358] Transistor T402 includes a gate electrode connected to the second select line 4202, an input-side terminal connected to the main data line 170-0, and an output-side terminal connected to the green data line 171G. Transistor T402 selects a portion of the main data voltage DATA by applying a CLB select signal to the second select line 4202, and applies it as the data voltage Dmg to the green data line 171G.

[0359] Transistor T403 has a gate electrode connected to the third select line 4203, an input-side terminal connected to the main data line 170-0, and an output-side terminal connected to the blue data line 171B. Transistor T403 selects a portion of the main data voltage DATA by applying a CLC select signal to the third select line 4203, and applies it as the data voltage Dmb to the blue data line 171B.

[0360] As a result, if the input main data voltage DATA, the demultiplexer Demux applies data voltages Dmr, Dmg, and Dmb, divided by selection signals CLA, CLB, and CLC, to each data line 171R, 171G, and 171B. According to this embodiment, the selection signals CLA, CLB, and CLC are... Figure 22 As shown, the low voltages do not overlap. Consequently, the data voltages Dmr, Dmg, and Dmb applied to each data line 171R, 171G, and 171B via Demux do not overlap in time. Furthermore, according to... Figure 22 All three selection signals CLA, CLB, and CLC are applied during the 1H time period.

[0361] In the following text, refer to Figure 20 and Figure 21 Describe the structure of the demultiplexer Demux.

[0362] Figure 20 This is a layout diagram of the data allocation unit according to an embodiment. Figure 21 This is a cross-sectional view of the data allocation unit according to an embodiment.

[0363] exist Figure 20 In the diagram, the mark represented by 'x' in the square indicates an opening located in the insulating layer that allows the upper conductive layer and the lower conductive layer to be electrically connected to each other.

[0364] like Figure 21 Like the 401 transistor T401 shown, each transistor included in the demultiplexer Demux includes a semiconductor layer C401, a first insulating layer 140, and a gate electrode G401 located on a substrate 110. A channel is located at the portion where the semiconductor layer C401 and the gate electrode G401 are stacked, and source and drain regions, which are plasma-treated or doped and made into conductors, are located on both sides of the channel in the semiconductor layer C401.

[0365] The gate electrode G401 of transistor T401 extends in a straight line along the extension direction of data lines 171R, 171G, and 171B to be electrically connected to the first select line 4201. Semiconductor layer C401 extends along the gate electrode G401 and is wider than the gate electrode G401. The input-side electrode S401 is electrically connected to the main data line 170-0, and the output-side electrode D401 is electrically connected to the red data line 171R via a connection portion 4301.

[0366] The gate electrode G402 of transistor T402 extends in a straight line along the extension direction of data lines 171R, 171G, and 171B to be electrically connected to the second select line 4202. Semiconductor layer C402 extends along the gate electrode G402 and is wider than the gate electrode G402. The input-side electrode S402 is electrically connected to the main data line 170-0, and the output-side electrode D402 is electrically connected to the green data line 171G via a connection portion 4302.

[0367] The gate electrode G403 of transistor T403 extends in a straight line along the extension direction of data lines 171R, 171G, and 171B to be electrically connected to the third select line 4203. Semiconductor layer C403 extends along the gate electrode G403 and is wider than the gate electrode G403. The input-side electrode S403 is electrically connected to the main data line 170-0, and the output-side electrode D403 is electrically connected to the blue data line 171B via a connection portion 4303.

[0368] Select lines 4201, 4202, and 4203 are formed in the first data conductive layer, and main data line 170-0 and connection portions 4301, 4302, and 4303 are formed in the first gate conductive layer.

[0369] On the other hand, in the upper region 10-4 of the light-emitting display device 10, a high-voltage wiring 4101 with a high voltage VGH and a low-voltage wiring 4102 with a low voltage VGL are also formed on the same layer (first data conductive layer) as the selection lines 4201, 4202, and 4203. The high-voltage wiring 4101 and the low-voltage wiring 4102 extend in a direction parallel to the selection lines 4201, 4202, and 4203. The high-voltage wiring 4101 and the low-voltage wiring 4102 can be connected to a stage for light emission signals or a stage for scanning signals to apply the high voltage VGH and the low voltage VGL. Furthermore, according to an embodiment, the high-voltage wiring 4101 and the low-voltage wiring 4102 can be wiring that applies a driving voltage ELVDD or a driving low voltage ELVSS to a pixel circuit unit PXC or a unit light-emitting diode (LED) LDU.

[0370] Figure 22 The signals applied to the data distribution unit and each signal generation unit, as well as the output signals, are shown.

[0371] Figure 22 It is a waveform diagram of the signals applied to the stage for optical emission signals, the stage for scanning signals, and the data distribution unit, and their output signals, according to an embodiment.

[0372] The following reference Figure 22 Describe the overall operation of the light-emitting display device 10.

[0373] In the stage for optical emission signal EMS, while outputting an optical emission control signal EM(n) with a high voltage, the first scan signal GW(n) and the second scan signal GI(n) with three times the low voltage are output in the stage for scanning signals used as the stage for the first scan signal GWS and the stage for the second scan signal GIS. In the stage for scanning signals used as the stage for bypass signal GBS, a bypass signal GB(n) with one times the low voltage is output.

[0374] A low-voltage first scan signal GW(n) is applied after 1H of which a low-voltage second scan signal GI(n) is applied, and a low-voltage bypass signal GB(n) is applied after 1H of which a first scan signal GW(n) with three times the low voltage is applied.

[0375] For the three selection signals CLA, CLB, and CLC applied to the demultiplexer Demux, a low voltage selection signal is applied every 1H, and all three selection signals CLA, CLB, and CLC are applied sequentially within the 1H time period. The low voltage periods of the three selection signals CLA, CLB, and CLC do not overlap with each other.

[0376] As a result, if data voltages Dmr, Dmg, and Dmb are applied to each of the three data lines 171R, 171G, and 171B within 1H via three selection signals CLA, CLB, and CLC, and are received in the pixel circuit unit PXC when a low-voltage first scan signal GW(n) is applied, for example, the second transistor T2 of the pixel circuit unit PXC is turned on by the first scan signal GW(n), and the corresponding data voltages Dmr, Dmg, and Dmb are input to the pixel circuit unit PXC. When a first scan signal GW(n) of three times the low voltage is applied, the data voltages Dmr, Dmg, and Dmb applied to data lines 171R, 171G, and 171B are the corresponding data voltages Dmr, Dmg, and Dmb of the pixel circuit unit PXC, and if the light emission control signal EM(n) changes to a low voltage, an output current is generated based on the data voltages Dmr, Dmg, and Dmb to be output to the unit light-emitting diode (LED) LDU.

[0377] In the following text, refer to Figure 23 and Figure 24 The display quality was compared and studied based on the presence or absence of the dummy opening 60.

[0378] Figure 23 This is a view showing the difference in display illuminance between the light-emitting display devices according to a comparative example. Figure 24 This is a view showing that the display illuminance of the light-emitting display device according to an embodiment is uniform.

[0379] first, Figure 23 The comparative example is in Figure 10A and Figure 10B The structure does not include a light-emitting display device with a fictitious opening 60, and Figure 24 The embodiments are as follows Figure 10A and Figure 10B One of the embodiments, such as Figure 5 The embodiment shown depicts a dummy opening 60.

[0380] Figure 23 Part X1 shows an image taken on the right side of the light-emitting display device according to the comparative example, and an enlarged image of the portion having the upper right corner. (See image X1.) Figure 23 As confirmed in the data analysis, it can be seen that although data voltages are applied to display the same color or illuminance, there are sections with different colors or illuminances along the right side in the comparison example. Figure 23 In the middle, compared with the central region 10-1, the part with different color or illuminance is the right region 10-3, in which multiple signal generation units are located, and when multiple signal generation units are further formed, it is easier to identify display defects caused by hydrogen accumulation in the semiconductor layer in the pixel circuit unit PXC.

[0381] exist Figure 24 Part X2 shows an image taken from the right side of the light-emitting display device 10 according to an embodiment, and an enlarged image having the upper right corner portion. Figure 24 In, with Figure 23 In contrast, it can be confirmed that areas with different colors and illuminance did not appear. That is, in this embodiment, since the dummy opening 60 is formed and hydrogen does not accumulate in the semiconductor layer, the pixel circuit unit PXC is unaffected even if multiple signal generating units are positioned adjacent to the pixel circuit unit PXC in the right region 10-3 of the light-emitting display device 10, allowing a constant output current to be generated. As a result, the display does not deteriorate.

[0382] In the light-emitting display device 10 described above, such as Figures 2 to 4As confirmed, the unit light-emitting diode (LED) LDU is located on the outermost side of the light-emitting display device 10. For example, the unit light-emitting diode (LED) LDU is located outside of multiple signal generation units, electrostatic discharge (ESD) protection units, and demultiplexers, thus the non-display area is very narrow. Therefore, even if a large-size display device is formed by attaching multiple light-emitting display devices 10 in some embodiments, images can be continuously displayed in the non-display area of ​​the portion of the light-emitting display device 10 to which the light-emitting display device 10 is attached.

[0383] In the following text, refer to Figure 25 Describes a large-size display device formed by attaching multiple light-emitting display devices 10.

[0384] Figure 25 This is a schematic diagram of a large-size display device according to an embodiment.

[0385] like Figure 25 As shown, a large-size display device 1 is formed by attaching multiple light-emitting display devices 10. Figure 25 In one embodiment, six light-emitting display devices 10 are attached. However, according to another embodiment, two or more light-emitting display devices 10 may be attached to form a large-size display device 1.

[0386] According to Figures 1 to 22 In the embodiment of the light-emitting display device 10, such as Figure 3 and Figure 4 As shown, the LED LDUs in the first row and the LED LDUs in the last row are located outside the driver unit (ESD protection unit and / or demultiplexer), so there is no non-display area.

[0387] In addition, refer to Figure 2 In the left region 10-2, in the outermost left column, there is a unit light-emitting diode (LED) LDU, and multiple signal generating units EMS, GBS, GIS, and GWS are located between the unit light-emitting diode (LED) LDUs. As a result, there is almost no non-display area in the left region 10-2, and almost no non-display area in the right region 10-3, which is symmetrical to this.

[0388] Therefore, even if multiple light-emitting display devices 10 according to some embodiments are attached to any one of the top / bottom / left / right sides, there is no (or substantially no) non-display area between two light-emitting display devices 10, so images can be displayed continuously.

[0389] Furthermore, if the spacing between the ends of the unit light-emitting diodes (LEDs) LDUs arranged in the light-emitting display device 10 and the substrate 110 is set to be equal to half the spacing between the arranged unit light-emitting diodes (LEDs), the spacing between the unit light-emitting diodes (LEDs) LDUs can remain constant even when multiple unit light-emitting diodes (LEDs) LDUs are attached. In this case, the spacing between the ends of the unit light-emitting diodes (LEDs) LDUs and the substrate 110 can be narrower than half the spacing between the unit light-emitting diodes (LEDs), thereby allowing the unit light-emitting diodes (LEDs) LDUs to be evenly spaced by taking into account the thickness of the attachment material used to attach the unit light-emitting diodes (LEDs). As a result, it is difficult for the user to identify multiple light-emitting display devices 10 attached.

[0390] In the following text, refer to Figures 26 to 28 The shape and location of the dummy opening 60 to be formed are described according to some embodiments.

[0391] Figures 26 to 28 This is a view illustrating various arrangements of dummy openings according to some embodiments.

[0392] Figure 26 The dummy opening 60 shown is created by forming the opening as is located in... Figure 7 The dummy opening 60 pattern is formed by masking the opening on the pixel circuit unit PXC.

[0393] Figure 27 The dummy opening 60 shown is created by forming the opening as is located in... Figure 14 The dummy opening 60 pattern is formed by a mask of the opening on the stage used for emitting optical signals.

[0394] Figure 28 The dummy opening 60 shown is created by forming the opening as is located in... Figure 17 The dummy opening 60 pattern is formed by a mask of the opening on the level used for scanning signals.

[0395] In addition to the pixel circuit unit forming region PXCA in which pixel circuit units PXC are formed and the region in which pixel output test units PXCT are formed, it is also possible to form a region located in Figure 26 The dummy opening 60 pattern in Figure 28. Therefore, the dummy opening 60 can be formed in the area of ​​the attached unit light-emitting diode (LED) LDU (see reference). Figure 12The dummy opening 60 pattern can be formed in at least one of the aforementioned regions, specifically in the LDUA (Data Line Extension Area), DLA (Data Line Extension Area), and SLA (Signal Line Extension Area). Furthermore, the dummy opening 60 pattern can even be formed in areas where nothing is formed. Here, an area where nothing is formed refers to an area where only an insulating layer is formed, and the dummy opening 60 can be formed within the insulating layer.

[0396] Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A light-emitting display device, the light-emitting display device comprising: The pixel circuit unit is configured to generate output current; The data distribution unit is configured to apply a data voltage to the pixel circuit unit via a data line; Multiple signal generation units are configured to apply scanning signals and light emission control signals to the pixel circuit unit through multiple signal lines; A unit light-emitting diode is configured to receive the output current of the pixel circuit unit and is attached to the pixel circuit unit; as well as A fictitious opening is formed in the area where the pixel circuit unit, the data allocation unit, and the plurality of signal generation units are not located; as well as A signal line extension region, in which multiple signal lines extend in a second direction. The pixel circuit unit and the signal line extension region are formed to repeat along the second direction. The multiple signal lines include a first scan line, a second scan line, a bypass control line, and an optical emission signal line. The plurality of signal generation units include: a first stage configured to transmit a first scan signal to the first scan line; a second stage configured to transmit a second scan signal to the second scan line; a third stage configured to transmit a bypass signal to the bypass control line; and a fourth stage configured to transmit an optical emission signal to the optical emission signal line. Each of the first to fourth stages is located between two adjacent unit light-emitting diodes, and Wherein, the same level for each of the first scanning signal, the second scanning signal, the bypass signal and the light emission signal is arranged along a first direction and located in the left or right region of the light-emitting display device, and the second direction intersects the first direction.

2. The light-emitting display device according to claim 1, wherein: The unit light-emitting diode includes a red light-emitting diode, a green light-emitting diode, and a blue light-emitting diode; and The pixel circuit unit includes: a red pixel circuit unit, a green pixel circuit unit, and a blue pixel circuit unit; a red diode connection portion electrically connecting the red light-emitting diode and the red pixel circuit unit; a green diode connection portion electrically connecting the green light-emitting diode and the green pixel circuit unit; and a blue diode connection portion electrically connecting the blue light-emitting diode and the blue pixel circuit unit. The red diode connection portion, the green diode connection portion, and the blue diode connection portion each include a red anode corresponding pad, a green anode corresponding pad, and a blue anode corresponding pad, respectively.

3. The light-emitting display device according to claim 1, wherein: The pixel circuit unit and the unit light-emitting diode have a unit pixel arrangement structure; and The unit pixel arrangement structure includes: the pixel circuit units, arranged in two rows; The unit light-emitting diodes are positioned on both sides of the pixel circuit units in the two rows and electrically connected to the pixel circuit units in the row.

4. The light-emitting display device according to claim 3, further comprising: A data cable extension area, in which the data cable extends in the first direction. The unit light-emitting diode, the pixel circuit unit, the pixel circuit unit of the next row, the unit light-emitting diode of the next row, and the data line extension area are sequentially positioned along the first direction.

5. The light-emitting display device according to claim 4, wherein: Of the first to fourth levels located in the left or right region, the fourth level is located in the outermost region; and The third level, the second level, and the first level are positioned sequentially toward the inner region relative to the outermost region.

6. The light-emitting display device according to claim 4, further comprising: The pixel output test unit is located between two adjacent light-emitting diodes in the second direction. The pixel output test unit includes an eighth transistor. The pixel output test unit is positioned in an inclined direction within the pixel circuit unit forming region. The pixel circuit unit is located within the pixel circuit unit forming region. In the left or right region, the pixel output test unit and at least one of the first to fourth levels are alternately located between two adjacent light-emitting diodes in the second direction.

7. The light-emitting display device according to claim 6, wherein: In the central region between the left region and the right region, a dummy driver having the same pattern and dummy opening as at least one of the first to fourth levels is located in the region where at least one of the first to fourth levels is positioned.

8. The light-emitting display device according to claim 6, wherein: The region with the dummy opening is located in the region where the unit light-emitting diode is attached, the data line extension region, the signal line extension region, and the region where nothing is formed except for at least one insulating layer.

9. The light-emitting display device according to claim 8, wherein: The dummy opening is one of a plurality of dummy openings, each of which has a constant size; and The plurality of dummy openings are formed in regions where the pixel circuit unit, the data distribution unit, and the plurality of signal generation units are not located according to the matrix, or the dummy openings are formed using a mask for forming the pixel circuit unit or the plurality of signal generation units.

10. The light-emitting display device according to claim 9, wherein: The data allocation unit includes multiple demultiplexers; The light-emitting display device also includes an electrostatic discharge prevention unit located adjacent to the plurality of demultiplexers; and In the plan view, the plurality of dummy openings are spaced apart from the plurality of demultiplexers and the electrostatic discharge prevention unit.

11. A light-emitting display device, the light-emitting display device comprising a plurality of light-emitting display devices attached to each other, in, At least one of the plurality of light-emitting display devices includes: The pixel circuit unit is configured to generate output current; The data distribution unit is configured to apply a data voltage to the pixel circuit unit via a data line; Multiple signal generation units are configured to apply scanning signals and light emission control signals to the pixel circuit unit through multiple signal lines; A unit light-emitting diode is configured to receive the output current of the pixel circuit unit and is attached to the pixel circuit unit; A dummy opening is formed in the region where the pixel circuit unit, the data allocation unit, and the plurality of signal generation units are not located; and A signal line extension region, in which multiple signal lines extend in a second direction. The pixel circuit unit and the signal line extension region are formed to repeat along the second direction. The multiple signal lines include a first scan line, a second scan line, a bypass control line, and an optical emission signal line. The plurality of signal generation units include: a first stage configured to transmit a first scan signal to the first scan line; a second stage configured to transmit a second scan signal to the second scan line; a third stage configured to transmit a bypass signal to the bypass control line; and a fourth stage configured to transmit an optical emission signal to the optical emission signal line. Each of the first to fourth stages is located between two adjacent unit light-emitting diodes, and The same level for each of the first scanning signal, the second scanning signal, the bypass signal, and the light emission signal is arranged along a first direction and located in the left or right region of the light-emitting display device, and the second direction intersects the first direction.

12. The light-emitting display device according to claim 11, wherein: The unit light-emitting diode is one of a plurality of unit light-emitting diodes; and In the plan view, the unit LEDs in the first row and the unit LEDs in the last row are spaced apart from the data distribution unit.

13. The light-emitting display device according to claim 11, wherein: In the left and right regions of the light-emitting display device, the unit light-emitting diodes are located in the outermost region and the plurality of signal generating units are located in the innermost region. The plurality of signal generation units include multiple stages; and In the central region between the left region and the right region, a dummy driver having the same pattern and dummy opening as at least one of the plurality of levels is located in the region where at least one of the plurality of levels is positioned.

14. The light-emitting display device according to claim 11, further comprising: A data cable extension area, in which the data cable extends in the first direction. The opening-forming region that forms the dummy opening is located in the region where the unit light-emitting diode is attached, the data line extension region, the signal line extension region, and the region where nothing is formed except for the insulating layer. The dummy opening is one of a plurality of dummy openings, each of which has a constant size; and The plurality of dummy openings are formed in the opening forming region according to a matrix, or the plurality of dummy openings are formed using a mask for forming the pixel circuit unit or the plurality of signal generating units.

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