Semiconductor device and method of manufacturing the same

Abstract

Methods of fabricating semiconductor devices are disclosed. The methods include forming a recess along a top surface of a semiconductor substrate. The methods include forming a nitride-based spacer layer extending along a first sidewall of the recess. The methods include forming a field oxide layer in the recess, the field oxide layer extending along a bottom surface of the recess, and the nitride-based spacer layer preventing lateral tips of the field oxide layer from extending to any portion of the semiconductor substrate other than the recess. Embodiments of the present application also relate to semiconductor devices.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this improvement in integration density comes from the repeated reduction in the size of the smallest component, which allows more components to be integrated into a given area. Summary of the Invention

[0003] Some embodiments of this application provide a method of manufacturing a semiconductor device, comprising: forming a groove along a top surface of a semiconductor substrate; forming a nitride-based spacer layer extending along a first sidewall of the groove; and forming a field oxide layer in the groove, the field oxide layer extending along a bottom surface of the groove, wherein the nitride-based spacer layer prevents the lateral tips of the field oxide layer from extending to any part of the semiconductor substrate other than the groove.

[0004] Other embodiments of this application provide a method of manufacturing a semiconductor device, comprising: forming an isolation structure extending from a top surface of a semiconductor substrate into the semiconductor substrate; recessing the semiconductor substrate to define a first sidewall, a bottom surface, and a second sidewall, wherein the second sidewall is opposite to the first sidewall, thereby exposing a portion of the isolation structure; forming an oxide pad layer extending along the first sidewall and located above the bottom surface; forming a dielectric spacer layer, also extending along the first sidewall, above the oxide pad layer; and at least thermally oxidizing a portion of the semiconductor substrate disposed below the bottom surface, thereby converting the portion of the semiconductor substrate overlapping the bottom surface with the oxide pad layer into a field oxide layer, wherein the dielectric spacer layer is configured to prevent oxygen atoms from diffusing to the exterior of the first sidewall during the thermal oxidation step.

[0005] Some embodiments of this application provide a semiconductor device, including: a gate dielectric layer filling a recess in a semiconductor substrate, wherein the gate dielectric layer extends laterally with a tip terminating at a sidewall of the recess; an isolation structure at least adjacent to a portion of the gate dielectric layer laterally opposite the tip; a source region laterally configured adjacent to the tip; a drain region laterally configured opposite the gate dielectric layer relative to the isolation structure; and a gate structure disposed at least above the gate dielectric layer. Attached Figure Description

[0006] When with attachment Figure 1When reading this invention, the various aspects will be best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is an example flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 Each of the examples illustrates a method according to some embodiments. Figure 1 Cross-sectional or top-view views of example semiconductor devices prepared during various manufacturing stages using the method. Detailed Implementation

[0009] The following disclosure provides numerous embodiments or instances of different components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various embodiments. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0010] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and “bottom” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0011] The demand for more compact, portable, and low-cost consumer electronics has prompted electronics manufacturers to develop and manufacture integrated circuits (ICs) that operate at low supply voltages to achieve low power consumption. However, components of these devices may require voltages higher than the low supply voltage. For example, liquid crystal display (LCD) drivers can use high-voltage (HV) metal-oxide-semiconductor (MOS) transistors to drive LCD pixels.

[0012] Typically, HV MOS transistors have an isolation structure. This isolation structure can be, for example, a localized oxidation of silicon (LOCOS) structure beneath the gate structure (or electrode) of the HV MOS transistor. The LOCOS structure has a thickness in the thousands of angstroms range. Therefore, such an HV MOS transistor can have a relatively high operating (e.g., breakdown) voltage applied to the gate electrode. The LOCOS structure is formed over the upper portion of a thermally oxidized silicon substrate, for example, by converting the upper portion of the silicon substrate into a silicon oxide layer. Due to the nature of thermal oxidation, the LOCOS structure can extend vertically and laterally by a certain thickness and distance. Therefore, the LOCOS structure is typically formed with a beak-like profile at its side ends. Such a beak-like profile can extend undesirably by a certain distance, which does not necessarily provide a substantial advantage for improving transistor performance. On the contrary, due to this undesirable lateral extension, reducing the transistor size (e.g., channel length) is challenging, which adversely increases the complexity and workload of integrating HV MOS transistors with advanced transistors. Therefore, existing HV MOS transistors are not entirely satisfactory in many respects.

[0013] This invention provides various embodiments of a method for manufacturing a high-voltage transistor having a localized oxidation (LOCOS) structure of at least silicon. As disclosed herein, the method utilizes a nitride-based spacer layer to block the lateral extension of the LOCOS structure, thereby minimizing the beak-like profile of the LOCOS structure (e.g., substantially limiting the distance of lateral expansion). For example, the disclosed method includes forming a groove along the top surface of a silicon substrate and blocking the sidewalls of the groove with a nitride-based spacer layer while forming the LOCOS structure. In this way, the LOCOS structure can be confined within the groove, i.e., it does not extend laterally into other portions of the silicon substrate where a LOCOS structure should not be formed. In some embodiments, the high-voltage transistor may have a LOCOS structure formed by the disclosed method, which is operatively used as part of the gate dielectric layer. Furthermore, such a high-voltage transistor may have its source and drain regions arranged asymmetrically relative to the LOCOS structure. In some other embodiments, the high-voltage transistor may have a LOCOS structure that pushes its drain region away from its gate structure, thereby defining an extended drift region. With any of the above configurations, the LOCOS structure formed by the method of the present invention can reduce the size (e.g., channel length) of the corresponding high-voltage transistor, which can advantageously make the high-voltage transistor more scalable with increasingly smaller devices that operate at relatively low voltages.

[0014] Figure 1 A flowchart of an example method 100 for forming at least a portion of a semiconductor device 200 according to some embodiments is shown. It should be noted that method 100 is merely an example and is not intended to limit the invention. Therefore, it should be understood that... Figure 1 The order of operations in method 100 can be changed. Figure 1 Additional operations are provided before, during, and after method 100, and some other operations are only briefly described herein. In some embodiments, the operation of method 100 may be related to, for example, Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 The cross-sectional or top view of the example semiconductor device 200 shown at each manufacturing stage is associated with it.

[0015] also, Figures 2-16The semiconductor device 200 shown may include one or more transistors formed in a first region of a substrate that operate at relatively high gate and drain voltages (e.g., above about 20V). Hereinafter, these transistors will be referred to as high-voltage transistors. It should be understood that... Figure 1 At least some operations of method 100 can be shared (e.g., performed simultaneously) to form one or more transistors operating at relatively low gate and / or drain voltages in a second region of the same substrate. Hereinafter, these transistors are referred to as low-voltage or medium-voltage transistors. Each transistor has a conductivity type, such as, for example, an n-type transistor or a p-type transistor. As used herein, the term "n-type" may refer to a conductivity type of a transistor having electrons as its conductive charge carriers; and as used herein, the term "p-type" may refer to a conductivity type of a transistor having holes as its conductive charge carriers.

[0016] In summary, method 100 begins with operation 102, which provides a substrate. Method 100 continues to operation 104, where a plurality of isolation structures are formed. Method 100 continues to operation 106, where a well region is formed. Method 100 continues to operation 108, where a trench is formed. Method 100 continues to operation 110, where a pad oxide layer is formed. Method 100 continues to operation 112, where a nitride-based spacer layer is formed. Method 100 continues to operation 114, where a portion of the pad oxide layer is removed. Method 100 continues to operation 116, where a field oxide layer is formed. Method 100 continues to operation 118, where a sacrificial oxide layer is formed. Method 100 continues to operation 120, where a dummy gate structure is formed. Method 100 continues to operation 122, where a source region and a drain region are formed. Method 100 continues to operation 124, where a metal gate structure is formed. Method 100 continues to operation 126, where a plurality of contact structures are formed.

[0017] Corresponding to Figure 1 Operation 102, Figure 2 This is a cross-sectional view taken along the X direction of a semiconductor device 200 including a substrate 202 according to some embodiments. As described above, the substrate 202 may have a first region and a second region, wherein one or more high-voltage transistors and low / medium-voltage transistors are formed, respectively. Figure 2 The cross-sectional view (and the accompanying figures) is for this first region.

[0018] Substrate 202 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., having p-type or n-type dopants) or undoped. Substrate 202 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate that is typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of substrate 202 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0019] Corresponding to Figure 1 Operation 104, Figure 3 This is a cross-sectional view taken along the X-direction of a semiconductor device 200 including multiple isolation structures 302, 304, and 306 according to some embodiments. Isolation structures 302 and 306, formed of insulating material, can electrically isolate adjacent device components from each other, for example, isolating a high-voltage transistor to be formed from other transistors formed on a substrate. Isolation structure 304, formed of the same insulating material, can help release the electric field below the gate electrode of the high-voltage transistor to be formed and next to the drain region of the high-voltage transistor to be formed.

[0020] As an example, the formation of isolation structures 302-306 may include dry etching into multiple trenches in the substrate 202 and filling these trenches with an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, isolation structures 302-306 may sometimes be referred to as shallow trench isolation (STI) structures. The insulating material (to fill the trenches) may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., depositing a CVD-based material in a remote plasma system and post-curing it to transform it into another material, such as an oxide), or combinations thereof. Each filled trench may have a multilayer structure, such as a thermal oxide pad layer filled with silicon nitride or silicon oxide.

[0021] Typically, isolation structures 302-306 can be formed using the following process sequence: growing pad oxide, forming a low-pressure chemical vapor deposition (LPCVD) nitride layer, patterning STI openings using photoresist and a mask, etching trenches in the substrate, optionally growing thermal oxide trench liners to improve trench interfaces, filling the trenches with CVD oxide, using a chemical mechanical polishing (CMP) process for etch-back and planarization, and using a nitride stripping process to remove silicon nitride. In some embodiments, the depth of isolation structures 302-306 ranges from approximately 0.2 micrometers (μm) to approximately 0.5 μm, measured vertically from the top surface of substrate 202A, depending on the device technology. In some other embodiments, isolation structure 304 near the drain region can have a fully isolated structure similar to isolation structures 302 and 306, or may include a structure with multiple partially trenched openings.

[0022] Corresponding to Figure 1 Operation 106, Figure 4 This is a cross-sectional view taken along the X direction of a semiconductor device 200 including a well region 402 according to some embodiments.

[0023] Well region 402 can be doped with a certain concentration of a type of dopant. For example, in order to form a high-voltage transistor as an n-type transistor for semiconductor device 200, well region 402 can be silicon doped with a p-type dopant such as boron (B), aluminum (Al), indium (In), gallium (Ga), or any other suitable p-type dopant. In another example, in order to form a high-voltage transistor as a p-type transistor for semiconductor device 200, well region 402 can be silicon doped with an n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb), or any other suitable n-type dopant. In some additional or optional embodiments, a sub-well region (not shown) doped with a dopant of the opposite type to that of well region 402 can be formed within well region 402. Such a sub-well region (configured to further release the electric field caused by the gate structure of the high-voltage transistor to be formed) can be laterally disposed around isolation structure 304.

[0024] Corresponding to Figure 1 Operation 108, Figure 5 This is a cross-sectional view taken along the X direction of a semiconductor device 200 including a recess 502 according to some embodiments.

[0025] As shown in the figure, a groove 502 is formed in the trap region 402 and close to the isolation structure 304, thereby exposing a portion of the sidewall of the isolation structure 304. After the groove 502 is formed, a bottom surface 503 and sidewalls 505A and 505B are defined, wherein sidewall 505B exposes a portion of the sidewall of the isolation structure 304.

[0026] As an example, a process sequence such as the following can be used to form the recess 502: growing a pad oxide 510 over a substrate 202, forming a low-pressure chemical vapor deposition (LPCVD) nitride-based (e.g., silicon nitride) layer 520 over the pad oxide 510, patterning layers 510 and 520 using photoresist and a mask to form an opening defining the location of the recess 502, and etching the substrate 202 (or well region 402) through the opening. In some embodiments, the recess 502 has a depth “D” measured vertically from the top surface 202A of the substrate to the bottom surface 503 of the recess. The depth D can be controlled based on the growth rate of the field oxide layer formed later. For example, the field oxide layer can be grown to about 800–1200 angstroms within a certain time window at a certain growth rate. At this time, the depth D can be controlled to be approximately half the thickness of the field oxide layer, that is, approximately... Therefore, the top surface of the field oxide layer can be coplanar with the top surface 202A of the substrate, which will be discussed below.

[0027] Corresponding to Figure 1 Operation 110, Figure 6 This is a cross-sectional view taken along the X direction of a semiconductor device 200 including a pad oxide layer 602 according to some embodiments.

[0028] A pad oxide layer 602 can be formed in the recess 502. For example, the pad oxide layer 602 is formed to line the sidewalls 505A and bottom surface 503 of the recess 502. Specifically, the pad oxide layer 602 can be formed by a thermal oxidation process that consumes a portion of the silicon in the well region 402. Thus, the pad oxide layer 602 can have a portion of the silicon from the original sidewall 505A ( Figure 6 The horizontally extending vertical portion 602V (the dashed line) and the portion extending from the original bottom surface 503 ( Figure 6 The horizontal portion 602L extends vertically (as shown by the dashed line). When forming the liner oxide layer 602, one sidewall (505A) and the bottom surface (503) of the groove 502 can be redefined as 505A' and 503', respectively, as... Figure 6 As shown.

[0029] Corresponding to Figure 1 Operation 112, Figure 7 This is a cross-sectional view taken along the X direction of a semiconductor device 200 including a nitride-based spacer layer 702 according to some embodiments.

[0030] The nitride-based spacer layer 702 is formed to extend at least along the sidewall 505A' of the recess 502. According to various embodiments, the nitride-based spacer layer 702 is configured to prevent a subsequently formed field oxide layer from laterally extending into portions of the well region 402 where a field oxide layer should not be formed. In other words, the field oxide layer can be confined in the recess 502 in a certain way without excessively extending beyond the nitride-based spacer layer 702. In some embodiments, the nitride-based spacer layer 702 is formed by depositing a nitride-based (e.g., silicon nitride, silicon carbonitride, silicon carbonitride oxynitride, or combinations thereof) blanket layer by low-pressure chemical vapor deposition (LPCVD), followed by an etching process to pattern the blanket layer. In some embodiments, the blanket layer formed as a conformal layer may have approximately The thickness. The etching process can be anisotropic. In this way, most of the lateral extension of the blanket layer above the bottom surface 503' and layer 520 is removed, wherein the remaining (or patterned) portion of the blanket layer is formed as a nitride-based spacer layer 702.

[0031] Corresponding to Figure 1 Operation 114, Figure 8 It is a cross-sectional view taken along the X direction of the semiconductor device 200 according to some embodiments, in which a portion of the pad oxide layer 602 has been removed.

[0032] As shown in the figure, for example, a wet etching process removes the lateral portions of the pad oxide layer 602 that are not covered by the nitride-based spacer layer 702. This exposes the surface of the silicon-containing well region 402, which again defines the bottom surface of the recess 502 as 503". This exposed surface of the well region 402 is configured to form the field oxide layer confined therein, which will be discussed below.

[0033] Corresponding to Figure 1 Operation 116, Figure 9 This is a cross-sectional view taken along the X direction of a semiconductor device 200 including a field oxide layer 902 according to some embodiments.

[0034] The field oxide layer 902, primarily comprising silicon oxide, is formed by thermally oxidizing the exposed surface of the silicon-containing well region 402. The field oxide layer 902 is sometimes referred to as a localized oxidation (LOCOS) structure of silicon. For example, the field oxide layer 902 can be formed by heating the workpiece at a temperature of approximately 980°C in the presence of oxygen. It should be understood that other processing conditions can be used to form thermally oxidized LOCOS structures. Since the nitride-based spacer layer 702 terminates the diffusion path of oxygen into the portion of the well region 402 other than the groove 502, the field oxide layer 902 can be formed to extend vertically from the bottom surface 503”, as indicated by symbols 903 and 905, respectively.

[0035] In some embodiments, the ratio of upward expansion (903) to downward expansion (905) can be about 1. Furthermore, the thermal oxidation process can be controlled to terminate until the top surface 902A of the field oxide layer is formed substantially coplanar with the top surface of the substrate 202A. As shown, most of the top surface 902A is formed as a substantially flat surface coplanar with the top surface 202A. In this case, the groove 502 has approximately Following the aforementioned example of depth D, the field oxide layer 902 can have approximately The thickness. However, it should be understood that the field oxide layer 902 may optionally include other thicknesses and materials while remaining within the scope of the invention. In some embodiments, after forming the field oxide layer 902, layers 510 and 520, the remaining portion of the oxide liner layer 602, and the nitride-based spacer layer 702 may be removed.

[0036] More specifically, when the nitride-based spacer layer 702 is formed as a barrier layer, the field oxide layer 902 may have a tip terminating at the lateral portion 602L or the nitride-based spacer layer 702. Although in some cases the tip may be formed with a beak-like profile, it should be understood that such a tip of the disclosed field oxide layer 902 will not extend excessively beyond the nitride-based spacer layer 702, thereby allowing the source region of the high-voltage transistor to be formed to be formed closer to the tip. This, in turn, can significantly reduce the channel length of the high-voltage transistor to be formed. On the other side of the field oxide layer 902, the field oxide layer 902 and the isolation structure 304 may be merged. In examples where both the field oxide layer 902 and the isolation structure 304 are formed of silicon oxide, the field oxide layer 902 and the isolation structure 304 may be formed as a single structure. However, in some embodiments, the isolation structure 304 extends into the well region 402 at a depth greater than that of the field oxide layer 902. A deeper isolation structure 304 can help extend or otherwise define the drift region for high-voltage transistors, which will be discussed below.

[0037] Corresponding to Figure 1 Operation 118, Figure 10 This is a cross-sectional view taken along the X direction of a semiconductor device 200 including a sacrificial oxide layer 1002 according to some embodiments.

[0038] As mentioned above, Figure 1 Some operations of method 100 can be performed simultaneously on a second region of substrate 202 to form multiple low / medium voltage transistors. In some embodiments, when forming field oxide layer 902 (which is configured to serve as the gate dielectric layer of the high voltage transistor to be formed), sacrificial oxide layer 1002 can generally be formed in a first region of substrate 202 (e.g., Figure 10Above the first region (shown) and the second region (not shown). A sacrificial oxide layer 1002 may be formed in the second region before forming one or more doped well regions, which are typically characterized by a higher doping concentration than the well region 402 in the first region. Thus, a transistor formed in the first region can have a higher operating (e.g., breakdown) voltage than a transistor formed in the second region. In some embodiments, the sacrificial oxide layer 1002 may be removed after the doping process in the second region. After removing the sacrificial oxide layer 1002, processes may be performed simultaneously in the first and second regions. Figure 1 The following operations of method 100 are used to form a plurality of high-voltage transistors and a plurality of low / medium-voltage transistors, respectively.

[0039] Corresponding to Figure 1 Operation 120, Figure 11 This is a cross-sectional view taken along the X direction of a semiconductor device 200 including a dummy gate structure 1102 according to some embodiments.

[0040] In some embodiments, the dummy gate structure 1102 may be formed above the field oxide layer 902, such as Figure 11 As shown. Specifically, the dummy gate structure 1102 can be formed above the substantially flat portion of the top surface 902A of the field oxide layer and a portion of the top surface of the isolation structure 304. After forming the dummy gate structure 1102, a gate spacer 1104 can be formed on the opposite side of the dummy gate structure 1102. The gate spacer 1104 can be a low-k spacer and can be formed from a suitable dielectric material, such as silicon oxide, silicon carbonitride, etc. Any suitable deposition method, such as thermal oxidation, chemical vapor deposition (CVD), etc., can be used to form the gate spacer 1104.

[0041] The dummy gate structure 1102 comprises multiple layers stacked on top of each other. For example, in some embodiments, the dummy gate structure 1102 includes a dummy gate dielectric and a dummy gate. To form the dummy gate structure 1102, a dielectric layer is formed over a substrate 202. The dielectric layer can be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, multilayers thereof, etc., and can be deposited or thermally grown. Next, a gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer can be deposited over the dielectric layer and then planarized, for example, by CMP. The mask layer can be deposited over the gate layer. The gate layer can be formed of, for example, polysilicon, but other materials can also be used. The mask layer can be formed of, for example, silicon nitride. After forming the layers (e.g., the dielectric layer, the gate layer, and the mask layer), the mask layer can be patterned using suitable photolithography and etching techniques. The pattern of the mask can then be transferred to the gate layer and the dielectric layer using suitable etching techniques to form the dummy gate structure 1102.

[0042] Corresponding to Figure 1 Operation 122, Figure 12 This is a cross-sectional view taken along the X direction of a semiconductor device 200 including a source region 1202 and a drain region 1204 according to some embodiments.

[0043] As shown in the figure, source region 1202 and drain region 1204 are formed along the top surface 202A of the substrate by implanting dopant into well region 402. The type of dopant used to form source region 1202 and drain region 1204 can be opposite to the type of dopant used in well region 402. Source region 1202 can be formed laterally close to the tip of field oxide layer 902, wherein an L-shaped groove in well region 402 is located between source region 1202 and field oxide layer 902. Although in Figure 12 In the illustrated embodiment, the bottom boundary of the source region 1202 is formed above the corner of the L-shaped profile; however, it should be understood that this bottom boundary may extend below the corner of the L-shaped profile while remaining within the scope of the invention. The drain region 1204 may be formed laterally between the isolation structures 304 and 306.

[0044] When the high-voltage transistor to be formed is configured as n-type, the source region 1202 and drain region 1204 may be doped with n-type dopants, such as phosphorus (P), arsenic (As), antimony (Sb), or any other suitable n-type dopant. When such a high-voltage transistor is configured as p-type, the source region 1202 and drain region 1204 may be doped with p-type dopants, such as boron (B), aluminum (Al), indium (In), gallium (Ga), or any other suitable p-type dopant. According to some embodiments, the doping concentration of the source region 1202 and drain region 1204 may be higher than the doping concentration of the well region 402.

[0045] Corresponding to Figure 1 Operation 124 Figure 13 This is a cross-sectional view taken along the X direction of a semiconductor device 200 including a metal gate structure 1302 according to some embodiments.

[0046] After forming the source region 1202 and the drain region 1204, a first interlayer dielectric (ILD) 1304 is formed over the substrate 202. The first ILD 1304 is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and can be deposited by any suitable method, such as CVD, PECVD, or FCVD.

[0047] Next, a gate replacement process is performed to replace the polysilicon gate structure 1102 with a metal gate structure 1302. Figure 12In some embodiments, the metal gate structure 1302 may include multiple layers stacked on top of each other. For example, the metal gate structure 1302 may include a high-k dielectric layer and a metal gate layer.

[0048] High-k dielectric layers may include materials selected from: Al₂O₃, HfAlO, HfAlON, AlZrO, HfO₂, HfSiO x HfAlO x HfZrSiO x High-k dielectric layers can be HfSiON, LaAlO3, ZrO2, or combinations thereof. A high-k dielectric layer may comprise a stack of multiple high-k dielectric layers. Any suitable method can be used to deposit the high-k dielectric layer, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc.

[0049] Metal gate layers may include p-type work-function layers, n-type work-function layers, multiple layers thereof, or combinations thereof. In the discussion herein, work-function layers may also be referred to as work-function metals. Examples of p-type work-function metals that may be included in gate structures for p-type devices include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, other suitable p-type work-function materials, or combinations thereof. Examples of n-type work-function metals that may be included in gate structures for n-type devices include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work-function materials, or combinations thereof. Work-function layers may be deposited using CVD, physical vapor deposition (PVD), ALD, and / or other suitable processes. After depositing one or more work-function layers, a planarization process such as CMP may be performed to remove excess metal.

[0050] After forming the metal gate structure 1302, a high-voltage transistor 1350 can be formed. The high-voltage transistor 1350 can be any suitable transistor, such as, but not limited to, a field-effect transistor (FET). According to various embodiments, the high-voltage transistor 1350 can be composed of at least an isolation structure 304, a well region 402, a field oxide layer 902, a source region 1202, a drain region 1204, and a metal gate structure 1302. Specifically, the field oxide layer 902 can serve as part of the gate dielectric layer of the high-voltage transistor 1350. Utilizing its relatively thick thickness (e.g., approximately...), The field oxide layer 902 can withstand relatively high voltages, typically greater than 20V, applied to the metal gate structure 1302. Utilizing this strong electric field induced by the gate structure, the isolation structure 304, extending further into the well region 402 than the field oxide layer 902, can generate a drift region to release the strong electric field.

[0051] As shown in the figure, arrow 1353 indicates the current flow when the high-voltage transistor 1350 is in the on state. This current flow originates from the source region 1202, travels along the bottom boundary (or surface) of the field oxide layer 902 and along the lower portion of the isolation structure 304, and reaches the drain region 1204. In some cases, the lower portion of the isolation structure 304 can be used as a drift region (e.g., configured to release a high gate electric field). Transistors having an isolation structure formed on one side of the field oxide layer can sometimes be referred to as asymmetric transistors. It should be understood that methods disclosed herein (e.g., Figure 1 Method 100) is not limited to fabricating a field oxide layer for asymmetric transistors. For example, the disclosed method can also be applied to the formation of symmetric transistors (e.g., forming another isolation structure on the source side of the field oxide layer, or not forming an isolation structure on either side of the field oxide layer).

[0052] Furthermore, by using the currently disclosed method to form the field oxide layer 902, the lateral extension of the tip of the field oxide layer 902 toward the source region 1202 can be significantly reduced. For example, according to various embodiments of the invention, the spacing “S1” extending in the X direction between the tip and the edge of the source region 1202 can be reduced to as low as about 0.2 μm (compared to the case where the spacing of the field oxide layer is typically in the range of about 0.35 to 0.45 μm using existing methods).

[0053] Figure 14 A top view of an embodiment of a semiconductor device 200 (e.g., a high-voltage transistor 1350) according to various embodiments is shown. It should be understood that... Figure 14 The top view is simplified for illustrative purposes and therefore some components (e.g., gate spacer 1104) may not be shown. As shown, the source region 1202 and drain region 1204 of the high-voltage transistor 1350 are arranged asymmetrically with respect to the metal gate structure 1302. For example, an isolation structure 304 is located between the drain region 1204 and the metal gate structure 1302, with a portion of the isolation structure 304 overlapping the metal gate structure. Furthermore, on the other side of the metal gate structure 1302 (e.g., the side closer to the source region 1202), there is no such isolation structure located between the metal gate structure 1302 and the source region 1202.

[0054] Figure 15A top view of another embodiment of a portion of a semiconductor device 200 (e.g., a high-voltage transistor 1350) according to various embodiments is shown. As shown, the isolation structure 304 is formed as a partially slotted structure. This partially slotted isolation structure 304 may include a plurality of protrusions 310 having edges adjacent to the edges of the drain region 1204. Thus, a portion of the well region 402 is disposed between adjacent protrusions 310 (or within the slots between the protrusions). It should be understood that the number of protrusions may vary depending on the technology node process and the specific application. Moreover, on the substrate 202 ( Figure 3 During the formation of the isolation structure 304 in the transistor, a partially slotted isolation structure 304 can be formed by modifying the pattern layout of the trenches. A high-voltage transistor 1350 with a partially slotted isolation structure 304 can have various advantages, which will be discussed below.

[0055] like Figure 15 As shown, the partially slotted isolation structure 304 includes a protrusion width “S2” measured in a direction (e.g., the Y direction) along the edge of the drain region 1204, a protrusion length “d2” measured in a direction (e.g., the X direction) from the drain region 1204 to the source region 1202, and a spacing “d1” between adjacent protrusions 310. In various embodiments, the protrusion width (S2) can range from about 0.8 μm to about 1.2 μm to provide a 3D electric field without compromising (e.g., significantly reducing) the breakdown voltage, and when S2 is small, the on-resistance can be improved by the larger active region of the exposed well region 402. Furthermore, it has been observed that the protrusion length (d2) significantly affects the breakdown voltage as d2 increases, and therefore the protrusion length (d2) can range from about 1 μm to about 2 μm. In some embodiments, the protrusion length (d2) can be normalized to the total length 320 of the partially slotted isolation structure 304, such that the protrusion length (d2) is approximately 25% to 50% of the total length 320. Furthermore, it has been observed that the spacing (d1) between adjacent protrusions 310 can be in the range of approximately 1.5 μm to approximately 2 μm (wherein, fixed d2 = 2 μm and d2 = 1 μm) without compromising the breakdown voltage and can reduce the on-resistance by 20% (compared to...). Figure 14 (Compared to the "fully" isolated structure 304). It should be noted that the specific examples disclosed above are for specific technology node processes, and other sizes can be used in other technology processes without departing from the scope of the invention.

[0056] Corresponding to Figure 1 Operation 126, Figure 16 This is a cross-sectional view taken along the X direction of a semiconductor device 200 including multiple contact structures 1602, 1606 and 1608 according to some embodiments.

[0057] As shown in the figure, contact structures 1602 to 1608 are formed to electrically couple to the source region 1602, the metal gate structure 1302, and the drain region 1204, respectively. Before forming the contact structures 1602 to 1608, a second ILD 1620 may be deposited over the first ILD 1304, followed by an etching process to form a plurality of vertical trenches (or recesses) extending through ILDs 1304 and 1620 to expose the source region 1202, the metal gate structure 1302, and the drain region 1204, respectively. These trenches can then be filled with a metal filler material to form the contact structures 1602 to 1608. The metal filler material includes at least one metallic material selected from the group consisting of tungsten, copper, cobalt, ruthenium, titanium, tantalum, or combinations thereof. The metal filler material can be deposited by a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or combinations thereof. In addition, multiple interconnect structures 1608, 1610, and 1612 can be formed to be electrically coupled to contact structures 1602 to 1608, respectively. Following a similar process, a third ILD 1622 is formed over the second ILD 1620, followed by an etching process to form trenches and fill these trenches with a metal filler material.

[0058] Interconnect structures 1608, 1610, and 1612 are sometimes referred to as M1 interconnect structures. According to some embodiments, since the spacing S1 between the source region 1202 and the field oxide layer 902 can be reduced, the spacing S3 extending in the X direction between interconnect structures 1608 and 1610, respectively coupled to the source region 1202 and the field oxide layer 902, can be correspondingly reduced. Furthermore, the total area of ​​the high-voltage transistor 1350 and its interconnect structures can be reduced, allowing more of these high-voltage transistors to be integrated within a limited area. Therefore, the power performance area (PPA) of the integrated circuit having these high-voltage transistors can be significantly improved.

[0059] In one aspect of the invention, a method of manufacturing a semiconductor device is disclosed. The method includes forming a recess along a top surface of a semiconductor substrate. The method includes forming a nitride-based spacer layer extending along a first sidewall of the recess. The method includes forming a field oxide layer in the recess, the field oxide layer extending along a bottom surface of the recess, while the nitride-based spacer layer prevents lateral tips of the field oxide layer from extending into any portion of the semiconductor substrate other than the recess.

[0060] In some embodiments, prior to forming the nitride-based spacer layer, a pad oxide layer extending along the first sidewall of the trench is further formed. In some embodiments, the top surface of the field oxide layer is coplanar with the top surface of the semiconductor substrate. In some embodiments, prior to forming the trench, a shallow trench isolation (STI) structure extending at least into the semiconductor substrate is further formed. In some embodiments, a second sidewall of the trench laterally opposite to the first sidewall is defined by the shallow trench isolation structure. In some embodiments, the method further includes: forming a source region along the top surface of the semiconductor substrate, wherein the source region is laterally configured to approach a lateral tip of the field oxide layer; further forming a drain region along the top surface of the semiconductor substrate, wherein the drain region is laterally configured to approach a shallow trench isolation structure adjacent to the field oxide layer; and forming a gate structure over the field oxide layer and the shallow trench isolation structure. In some embodiments, the gate structure is laterally confined within a common region of the field oxide layer and the shallow trench isolation structure. In some embodiments, the minimum distance between the tip of the source region and the tip of the field oxide layer is less than about 0.3 micrometers (μm). In some embodiments, a transistor comprising at least the source region, the drain region, the field oxide layer, the shallow trench isolation structure, and the gate structure is operably used as a high-voltage transistor, wherein a voltage applied to each of the drain region and the gate structure is greater than about 20 volts (V). In some embodiments, the nitride-based spacer layer is removed after the field oxide layer is formed.

[0061] In another aspect of the invention, a method of manufacturing a semiconductor device is disclosed. The method includes forming an isolation structure extending from a top surface of a semiconductor substrate into the semiconductor substrate. The method includes recessing the semiconductor substrate to define a first sidewall, a bottom surface, and a second sidewall, wherein the second sidewall, opposite to the first sidewall, exposes a portion of the isolation structure. The method includes forming an oxide pad layer extending along the first sidewall and located above the bottom surface. The method includes forming a dielectric spacer layer, also extending along the first sidewall, over the oxide pad layer. The method includes thermally oxidizing at least a portion of the semiconductor substrate disposed below the bottom surface, thereby converting the portion of the semiconductor substrate overlapping the bottom surface with the oxide pad layer into a field oxide layer, wherein the dielectric spacer layer is configured to prevent oxygen atoms from diffusing to the exterior of the first sidewall during the thermal oxidation step.

[0062] In some embodiments, the step of recessing the semiconductor substrate further includes controlling the height of the first sidewall to correspond to the growth rate of the field oxide layer. In some embodiments, the top surface of the field oxide layer is coplanar with the top surface of the semiconductor substrate. In some embodiments, the method further includes: forming a source region along the top surface of the semiconductor substrate, wherein the source region is laterally configured adjacent to the first sidewall; further forming a drain region along the top surface of the semiconductor substrate, wherein the drain region is laterally configured opposite the field oxide layer relative to the isolation structure; and forming a gate structure at least above the field oxide layer. In some embodiments, the gate structure includes a high-k dielectric layer and a metal gate. In some embodiments, the gate structure does not laterally extend beyond the tip of the field oxide layer adjacent to the first sidewall. In some embodiments, a transistor consisting at least of the source region, the drain region, the field oxide layer, the isolation structure, and the gate structure is operatively used as a high-voltage transistor, wherein a voltage applied to each of the drain region and the gate structure is greater than about 20 volts (V).

[0063] In another aspect of the invention, a semiconductor device is disclosed. The semiconductor device includes a gate dielectric layer filling a trench in a semiconductor substrate, wherein the gate dielectric layer extends laterally with a tip terminating at a sidewall of the trench. The semiconductor device includes an isolation structure adjacent at least to a portion of the gate dielectric layer laterally opposite the tip. The semiconductor device includes a source region laterally configured adjacent to the tip. The semiconductor device includes a drain region laterally configured opposite the gate dielectric layer relative to the isolation structure. The semiconductor device includes a gate structure disposed at least above the gate dielectric layer.

[0064] In some embodiments, the minimum distance between the tip of the source region and the tip of the field oxide layer is less than about 0.3 micrometers (μm). In some embodiments, the transistor is configured to operate at a high voltage, wherein the voltage applied to each of the drain region and the gate structure is greater than about 20 volts (V).

[0065] As used herein, the terms “about” and “approximately” generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0066] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: A groove is formed along the top surface of the semiconductor substrate; A nitride-based spacer layer is formed extending along a first sidewall of the groove, wherein a second sidewall of the groove, laterally opposite to the first sidewall, is defined by a shallow trench isolation structure extending into the semiconductor substrate. as well as A field oxide layer is formed in the groove, the field oxide layer extending along the bottom surface of the groove, while the nitride-based spacer layer prevents the lateral tips of the field oxide layer from extending laterally beyond the first sidewall to any part of the semiconductor substrate.

2. The method according to claim 1, wherein, Prior to forming the nitride-based spacer layer, a pad oxide layer extending along the first sidewall of the groove is also formed.

3. The method according to claim 1, wherein, The top surface of the field oxide layer is coplanar with the top surface of the semiconductor substrate.

4. The method according to claim 1, wherein, Prior to forming the groove, the shallow trench isolation structure is also formed, extending at least into the semiconductor substrate.

5. The method according to claim 1, wherein, The shallow trench isolation structure includes silicon oxide, silicon nitride, or silicon oxynitride.

6. The method according to claim 4, further comprising: A source region is formed along the top surface of the semiconductor substrate, wherein the source region is laterally positioned close to the lateral tip of the field oxide layer; A drain region is also formed along the top surface of the semiconductor substrate, wherein the drain region is laterally configured as a shallow trench isolation structure adjacent to the field oxide layer; and A gate structure is formed above the field oxide layer and the shallow trench isolation structure.

7. The method according to claim 6, wherein, The gate structure is laterally confined within the common region of the field oxide layer and the shallow trench isolation structure.

8. The method according to claim 6, wherein, The minimum distance between the tip of the source region and the tip of the field oxide layer is less than about 0.3 micrometers (μm).

9. The method according to claim 6, wherein, A transistor comprising at least the source region, the drain region, the field oxide layer, the shallow trench isolation structure, and the gate structure is operable as a high-voltage transistor, wherein the voltage applied to each of the drain region and the gate structure is greater than about 20 volts (V).

10. The method according to claim 1, wherein, After forming the field oxide layer, the process also includes removing the nitride-based spacer layer.

11. A method for manufacturing a semiconductor device, comprising: An isolation structure is formed extending from the top surface of the semiconductor substrate into the semiconductor substrate; The semiconductor substrate is recessed to define a first sidewall, a bottom surface, and a second sidewall, wherein the second sidewall is opposite to the first sidewall, thereby exposing a portion of the isolation structure, wherein the second sidewall is defined by the isolation structure; An oxide liner layer is formed that extends along the first sidewall and is located above the bottom surface; A dielectric spacer layer extending along the first sidewall is formed above the oxide liner layer; and At least a portion of the semiconductor substrate disposed below the bottom surface is thermally oxidized, thereby transforming the portion of the semiconductor substrate overlapping the bottom surface with the oxide pad layer into a field oxide layer, wherein the dielectric spacer layer is configured to prevent oxygen atoms from diffusing to the exterior of the first sidewall during the thermal oxidation step.

12. The method according to claim 11, wherein, The step of recessing the semiconductor substrate further includes controlling the height of the first sidewall to correspond to the growth rate of the field oxide layer.

13. The method according to claim 11, wherein, The top surface of the field oxide layer is coplanar with the top surface of the semiconductor substrate.

14. The method of claim 11, further comprising: A source region is formed along the top surface of the semiconductor substrate, wherein the source region is laterally positioned adjacent to the first sidewall; A drain region is also formed along the top surface of the semiconductor substrate, wherein the drain region is laterally positioned opposite the field oxide layer relative to the isolation structure; and A gate structure is formed over at least the field oxide layer.

15. The method according to claim 14, wherein, The gate structure includes a high-k dielectric layer and a metal gate.

16. The method of claim 14, wherein, The gate structure does not extend laterally beyond the tip of the field oxide layer adjacent to the first sidewall.

17. The method of claim 14, wherein, A transistor consisting of at least the source region, the drain region, the field oxide layer, the isolation structure, and the gate structure is operable as a high-voltage transistor, wherein the voltage applied to each of the drain region and the gate structure is greater than about 20 volts (V).

18. A semiconductor device, comprising: A gate dielectric layer that fills a groove in a semiconductor substrate, wherein the gate dielectric layer extends laterally with a tip terminating at a sidewall of the groove; An isolation structure, at least adjacent to the portion of the gate dielectric layer laterally opposite the tip; A nitride-based spacer layer extends along the first sidewall of the groove, and a second sidewall of the groove, laterally opposite to the first sidewall, is defined by an isolation structure extending into the semiconductor substrate. A field oxide layer extends along the bottom surface of the groove, while the nitride-based spacer layer prevents the lateral tip of the field oxide layer from extending laterally beyond the first sidewall to the semiconductor substrate. The source region is laterally positioned adjacent to the tip; The drain region is laterally configured to be opposite the gate dielectric layer relative to the isolation structure; and A gate structure is disposed at least above the gate dielectric layer.

19. The semiconductor device according to claim 18, wherein, The minimum distance between the tip of the source region and the lateral tip of the field oxide layer is less than about 0.3 micrometers (μm).

20. The semiconductor device according to claim 18, wherein, The transistor including the drain region and the gate structure is configured to operate at a high voltage, wherein the voltage applied to each of the drain region and the gate structure is greater than about 20 volts (V).

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