Electrode structures for memory devices and associated devices and systems

Abstract

The present disclosure relates to electrode structures for memory devices and associated devices and systems. Disclosed herein are memory devices and associated systems and methods having electrode structures with increased resistivity with thermal cycling. In some embodiments, a memory device includes a memory element and an electrode structure electrically coupled to the memory element. The electrode structure can include a material including a combination of tungsten, silicon, and germanium.

Description

Technical Field

[0001] This technology generally relates to memory devices, and more specifically, to memory devices having electrode structures with increased resistivity through thermal cycling. Background Technology

[0002] Memory devices are widely used to store information associated with various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of memory cells. Various types of memory devices exist, such as non-volatile memory devices (e.g., NAND flash memory devices) and volatile memory devices (e.g., dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), and the like).

[0003] Improving memory devices can broadly include increasing memory cell density, increasing read / write speeds or otherwise reducing operational latency, improving reliability, increasing data retention, reducing power consumption, or lowering manufacturing costs. Manufacturers can reduce manufacturing costs, for example, by reducing the amount of power or materials used. Similarly, manufacturers can improve reliability by using specific materials or configurations to form memory devices that do not degrade rapidly over time. Summary of the Invention

[0004] On one hand, this disclosure provides a memory device comprising: a memory element; and an electrode structure electrically coupled to the memory element, wherein the electrode structure comprises a material comprising a composition of tungsten, silicon, and germanium.

[0005] On the other hand, this disclosure further provides a memory device comprising: a memory element; and an electrode structure electrically coupled to the memory element, wherein the electrode structure is configured to have a first resistivity prior to exposure to a plurality of thermal cycles, wherein the electrode structure is configured to have a second resistivity after exposure to the plurality of thermal cycles, wherein the first resistivity is less than about 0.01 ohm-cm, and wherein the second resistivity is greater than the first resistivity.

[0006] In another aspect, this disclosure further provides a memory device comprising: a memory element; a first electrode structure electrically coupled to the memory element, wherein the first electrode structure comprises a first material comprising a composition of tungsten, silicon, and germanium; and a second electrode structure electrically coupled to the memory element, wherein the second electrode structure comprises a second material comprising a composition of tungsten, silicon, and germanium. Attached Figure Description

[0007] Referring to the accompanying drawings will provide a better understanding of many aspects of this technology. The components in the drawings are not necessarily drawn to scale. The focus should be on clearly illustrating the principles of this technology.

[0008] Figure 1 This is an enlarged cross-sectional side view of a portion of a memory device according to an embodiment of the present technology.

[0009] Figure 2 This describes the effect of temperature cycling according to embodiments of the present technology. Figure 1 The effect of resistivity on the electrode structure of the memory device.

[0010] Figure 3 This is an illustrative description of embodiments according to the present technology. Figure 1 A graph showing the resistivity of the electrode structure and the peak current obtained through the electrode structure throughout the entire lifespan of the memory device.

[0011] Figures 4 to 7 Additional embodiments of the present technology include a memory cell, a first electrode structure, and a second electrode structure. Figure 1 An enlarged view of the array of memory devices, illustrating different arrangements of the first electrode structure and / or the second electrode structure.

[0012] Figure 8 This is a schematic diagram of a system including a memory device according to an embodiment of the present technology. Detailed Implementation

[0013] Embodiments of this technology pertain to memory devices, associated systems, and methods having electrode structures with increased resistivity through thermal cycling. In some embodiments, the memory device includes a memory element and an electrode structure electrically coupled to the memory element. The electrode structure may include a first material and a second material between the first material and the memory element. The first material may be different from the second material, and in some embodiments, the first material may include a combination of tungsten, silicon, and germanium (WGeSi).

[0014] In some aspects of this technology, the initial resistivity of the electrode structure can be lower than the operating resistivity of the electrode structure after the memory device has been exposed to multiple heating cycles. For example, the electrode structure may initially have a relatively low resistivity after formation and may increase its resistance during operation as the memory device undergoes thermal cycling during conditioning, programming, writing, reading, etc. The resistivity of the electrode structure is a material property that varies due to the heat generated by the voltage across the electrode structure and the current through the electrode structure throughout the lifetime of the memory device. In some embodiments, the resistivity may be directly proportional to the voltage across the electrode structure and the current through the electrode structure throughout the lifetime of the memory device. Therefore, the current through the electrode structure (e.g., spike current) may decrease proportionally to the increase in resistivity throughout the lifetime of the memory device. Thus, the electrode structure may: (i) have a relatively low resistivity and a high corresponding spike current at the beginning of the lifetime of the memory device (e.g., during conditioning); and (ii) have a relatively high resistivity and a low corresponding spike current after the lifetime of the memory device and at the end of the lifetime of the memory device (e.g., during operation). The relatively high resistivity and low corresponding peak current can vary in magnitude throughout the lifetime of the memory device due to, for example, accumulated material effects or the selected (WGeSi) composition based on the electrode structure.

[0015] In some aspects of this technology, the relatively low resistivity of the electrode structure at the beginning of the memory device's lifespan can improve the regulation efficiency of the memory device. For example, the reduced resistivity can decrease the electrical force required to generate the same regulation current spikes through the electrode structure in the memory device. Simultaneously, the relatively high resistivity of the electrode structure during operation of the memory device can improve the durability of the memory device. For example, the increased resistance can reduce the magnitude of current spikes through the electrode structure and / or memory elements (e.g., cells) during operation, thereby reducing memory device degradation. Therefore, forming an electrode structure comprising a WGeSi composition can reduce manufacturing costs and / or improve the lifespan of the memory device by improving regulation efficiency and / or reducing memory device degradation during operation.

[0016] Numerous specific details are disclosed herein to provide a comprehensive and enabling description of embodiments of the present technology. However, those skilled in the art will understand that the technology may have additional embodiments, and may be described without further reference. Figures 1 to 8 The described techniques are practiced in the context of certain details in the embodiments described. For example, some details of memory devices well known in the art have been omitted to avoid obscuring the technology. Generally, it should be understood that various other devices and systems besides the specific embodiments disclosed herein are within the scope of this technology.

[0017] As used herein, the terms “vertical,” “horizontal,” “up,” “down,” “above,” and “below” can refer to the relative orientation or position of a feature in a semiconductor device given the orientation shown in the figures. For example, “up” or “top” can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, above / below, above / below, up / down, and left / right can be interchanged depending on the orientation.

[0018] Figure 1 This is an enlarged cross-sectional side view of a portion of a memory device 100 according to an embodiment of the present technology. In the illustrated embodiment, the memory device 100 includes a plurality of memory elements 102, each electrically coupled to a corresponding first electrode structure 110 (e.g., an upper electrode structure, a top electrode structure) and a corresponding second electrode structure 120 (e.g., a lower electrode structure, a bottom electrode structure). The first electrode structure 110 may include a first material 112 (e.g., a first electrode material, a resistivity control material) and a second material 114 (e.g., a second electrode material). Similarly, the second electrode structure 120 may include a third material 122 (e.g., a third electrode material, a resistivity control material) and a fourth material 124 (e.g., a fourth electrode material). In some embodiments, the memory elements 102 and the corresponding first and second electrode structures 110, 120 may be arranged in columns 107 separated by electrically insulating pillars 104.

[0019] In some embodiments, the memory device 100 further includes: (i) a first metallization layer 106 extending at least partially over the upper portion of the first electrode structure 110 and the insulating pillar 104; and (ii) a second metallization layer 108 extending at least partially over the lower portion of the second electrode structure 120 and the insulating pillar 104. The first and second metallization layers 106 and 108 may include, for example, a metal of tungsten, a metal alloy, a material containing a conductive metal, and / or the like. In some embodiments, the first and second metallization layers 106 and 108 may include metal wires extending orthogonally through the insulating material. The insulating pillar 104 may include an oxide material, a dielectric material, a nitride material, and / or the like.

[0020] In some embodiments, memory element 102 may comprise, for example, one or more chalcogenides and / or phase change materials. In some embodiments, memory element 102 may each comprise a dedicated memory cell and a selector electrically coupled together. In other embodiments, memory element 102 may comprise a self-selecting memory cell. For example, memory element 102 may each comprise a chalcogenide element configured as both a memory storage element and a select element. In operation, each of memory elements 102 may store data bits and may be written to (e.g., accessed) by changing the voltage supplied to the corresponding element in the first electrode structure 110 via the first metallization layer 106 (e.g., word line, bit line, and / or another suitable structure); and / or (ii) the voltage supplied to the corresponding element in the second electrode structure 120 via the second metallization layer 108 (e.g., word line, bit line, and / or another suitable structure). In some embodiments, memory element 102 is non-volatile.

[0021] The first metallization layer 106 and / or the second metallization layer 108 may be electrically coupled to conductive vias, conductive contacts, and / or other suitable structures of the memory device 100 (not shown) for operatively coupling the memory device 100 to external devices (e.g., processor devices) and / or other components (e.g., other memory devices) within an integrated memory package. Those skilled in the art will understand that the memory device 100 may be further “encapsulated” for protection and includes appropriate electrical interconnections.

[0022] In the illustrated embodiment, the first material 112 of the first electrode structure 110 is positioned above (e.g., above) the second material 114 and between the second material 114 and the first metallization layer 106. Similarly, the third material 122 of the second electrode structure 120 is positioned above (e.g., below) the fourth material 124 and between the fourth material 124 and the second metallization layer 108. In some embodiments, the second and fourth materials 114, 124 may include conductive metals. In some embodiments, the second and fourth materials 114, 124 may be carbon-based materials including amorphous carbon, carbide materials, and / or other carbon-based materials. In some embodiments, the second and fourth materials 114, 124 may be different materials, such as different carbide materials.

[0023] The first and third materials 112 and 122 may comprise the same or different materials. For example, in some embodiments, the first and third materials 112 and 122 may each comprise a composition (e.g., an alloy) of tungsten, germanium, and silicon (WGeSi). The first and third materials 112 and 122 may be deposited via sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, electroplating, electroless plating, and / or another suitable deposition technique (e.g., deposited onto the second material 114 and the second metallization layer 108, respectively). In some embodiments, the first and third materials 112 and 122 may be deposited as films (e.g., thin films) having a thickness between about 10 and 30 angstroms, between about 50 and 90 angstroms, less than 100 angstroms, between about 10 and 100 angstroms, between about 80 and 150 angstroms, between about 50 and 200 angstroms, or greater than about 200 angstroms. The first and third materials 112 and 122 may be configured to control, define, and / or influence the resistivity (e.g., resistivity profile) of the first and second electrode structures 110 and 120, respectively. More specifically, the first and third materials 112 and 122 may be configured such that the first and second electrode structures 110 and 120 have initially low resistivity that increases as the memory device 100 cycles (e.g., electrical cycle on / off) during its lifetime and thus experiences thermal cycling at higher and lower temperatures.

[0024] For example, Figure 2 This describes the effect of temperature cycling according to embodiments of the present technology on the resistivity (e.g., bulk resistivity) of one of the first electrode structures 110 containing WGeSi and / or one of the second electrode structures 120 containing WGeSi (collectively or individually referred to as "electrode structures containing WGeSi"). As shown, the electrode structures containing WGeSi can be subjected to temperature cycling at an initial temperature T before temperature cycling. initial The initial resistivity R is located at or near the point. initial Initial temperature T initial The manufacturing temperature can be room temperature, above room temperature, below room temperature, or below room temperature. Electrode structures incorporating WGeSi can have an initial resistivity R during device fabrication after the electrode structure is formed (e.g., deposited). initial In some embodiments, the initial temperature T initial It can be between approximately 20°C and 30°C (e.g., approximately 25°C). In some embodiments, the value R initial It can be less than about 0.1 ohm-cm, less than about 0.01 ohm-cm, less than about 0.008 ohm-cm, less than about 0.0005 ohm-cm, less than 0.0003 ohm-cm, or smaller.

[0025] As by Figure 2Line 230 shows that when the electrode structure containing WGeSi is initially heated during one or more first heating cycles (e.g., a single first heating cycle or the average of multiple first heating cycles), the resistivity of the electrode structure containing WGeSi can be maintained at the operating temperature T of the memory device 100. operating The initial decrease occurs before the temperature is increased to or near the operating temperature T. In some embodiments, the operating temperature T... operating It can be between approximately 400°C and 500°C (e.g., approximately 450°C) or higher. As shown by line 231, when the electrode structure containing WGeSi is initially cooled during (several) first heating cycles, the resistivity of the electrode structure containing WGeSi can return to its initial temperature T as the electrode structure returns to its initial temperature T. initial The increase makes the resistivity greater than the initial resistivity R. initial .

[0026] As illustrated by line 232, when the electrode structure containing WGeSi is reheated during one or more second heating cycles (e.g., a single second heating cycle or the average of multiple second heating cycles), the resistivity of the electrode structure containing WGeSi can again be maintained at the operating temperature T. operating Before increasing to a temperature greater than or equal to the operating temperature T during (several) first heating cycles, the initial temperature T is reduced to a value greater than or equal to the operating temperature T. operating The resistivity of the WGeSi-containing electrode structure can return to its initial temperature T as the electrode structure cools again during (several) second heating cycles. As shown in line 233, when the electrode structure containing WGeSi is cooled again during these second heating cycles, the resistivity of the WGeSi-containing electrode structure can return to its initial temperature T. initial The increase makes the resistivity greater than the initial resistivity R. initial And it is greater than or equal to the resistivity after (several) first heating cycles. As shown by line 234, when the electrode structure containing WGeSi is reheated during one or more third heating cycles (e.g., a single third heating cycle or the average of multiple third heating cycles), the resistivity of the electrode structure containing WGeSi can be at the operating temperature T. operating Reduce to a temperature greater than or equal to the operating temperature T during (several) second heating cycles before reaching equilibrium at or near the operating temperature. operating The resistivity of the WGeSi-containing electrode structure can return to its initial temperature T when the electrode structure is cooled again during (several) third heating cycles. As shown in line 235, the resistivity of the WGeSi-containing electrode structure can return to its initial temperature T as the electrode structure returns to its initial temperature T. initial The increase makes the resistivity higher than the initial resistivity R. initial And it is greater than or equal to the resistivity after (several) second heating cycles.

[0027] Therefore, in some aspects of this technology, the initial resistivity R of the electrode structure containing WGeSi is... initial(For example, at the initial temperature T) initial (below or near) the operating resistivity R of the electrode structure after the memory device 100 has been cycled through multiple heating cycles. operating (For example, at operating temperature T) operating (below or near). That is, the resistivity of the electrode structure containing WGeSi can have a relatively low resistivity after formation and can increase its resistance during operation as the memory device 100 thermally cycles. In some embodiments, the resistivity of the electrode structure containing WGeSi can move towards the operating resistivity R after the memory device 100 has been cycled through multiple heating cycles. operating convergence.

[0028] Refer again Figure 1 Throughout the entire lifecycle of the memory device 100, the resistivity of the first and second electrode structures 110 and 120 is directly proportional to the heat induced / generated by the voltage across the first and second electrode structures 110 and 120 and the current through the first and second electrode structures 110 and 120. Figure 3 This is a schematic diagram illustrating the resistivity of the first and second electrode structures 110, 120 (containing WGeSi) according to an embodiment of the present technology, and the resulting peak current through the first and second electrode structures 110, 120 over the entire lifetime of the memory device 100. Figure 3 As shown, the memory device 100 can undergo conditioning, programming, and operation during its lifespan, each of which may include multiple thermal cycles. For example, conditioning (e.g., adaptation) of the first and second electrode structures 110, 120 may include repeatedly powering the first and second electrode structures 110, 120 until the memory element 102 reaches a stable state. Similarly, programming may include repeatedly powering the first and second electrode structures 110, 120 to write data to the memory element 102. Operation of the memory device 100 may include repeatedly powering the first and second electrode structures 110, 120 to read data from the memory element 102.

[0029] For reference Figure 2 In detail, the resistivity of the first and second electrode structures 110, 120 can increase throughout the entire lifespan of the memory device 100 as the first and second electrode structures 110, 120 are powered and thermally cycled during adjustment, programming, and operation. Therefore, the current (e.g., spike current) through the first and second electrode structures 110, 120 (e.g., for the same applied voltage) can decrease proportionally to the increase in resistivity throughout the entire lifespan of the memory device 100. Thus, as... Figure 3As shown, the first and second electrode structures 110 and 120 may: (i) have relatively low resistivity and high corresponding peak current at the beginning of the lifetime of the memory device 100 (e.g., during adjustment); and (ii) have relatively high resistivity and low corresponding peak current at the end of the lifetime of the memory device 100 (e.g., during operation).

[0030] In some aspects of this technology, the relatively low resistivity of the first and second electrode structures 110, 120 at the beginning of the lifecycle of the memory device 100 can improve the regulation efficiency of the memory device 100. For example, the reduced resistivity initially reduces the electrical force required to be applied to the memory device 100 to generate the same regulation current spikes through the first and second electrode structures 110, 120. Simultaneously, the relatively high resistivity of the first and second electrode structures 110, 120 during operation of the memory device 100 can improve the durability of the memory device 100. For example, the increased resistance can reduce the magnitude of current spikes through the first and second electrode structures 110, 120 during operation (e.g., read and / or write operations), thereby reducing degradation of the memory device 100. In contrast, carbon electrodes typically have low initial resistivity, but the resistivity irreversibly decreases when heated during device cycling, thereby resulting in relatively large current spikes during device operation that can reduce the device's lifespan. Similarly, silicon tungsten nitride (WSiN) and carbon nitride (CN) based electrodes typically have a substantially constant resistivity when heated during device cycling, but the resistivity can be too high to effectively regulate the device. Alternatively, WSiN and CN based electrodes may have a resistivity that decreases upon heating, resulting in higher peak currents and increased cell damage. Therefore, forming first and second electrode structures comprising a first material 112 and a third material 122 including WGeSi can reduce manufacturing costs and / or improve the lifespan of the memory device 100 by improving regulation efficiency and / or reducing degradation of the memory device 100 during operation.

[0031] Let's refer to each other. Figure 1 and 2 In some embodiments, the composition of the first material 112 and / or the third material 122 may be selected to provide specific resistivity profiles for the first electrode structure 110 and / or the second electrode structure 120, respectively. In some embodiments, the resistivity profiles of the first and second electrode structures 110, 120 may be specifically selected based on the characteristics of the memory element 102 (e.g., size, composition). More specifically, the first and third materials 112, 122 may contain tungsten and silicon and germanium (W x Si y Ge zThe ratios (e.g., mass ratio, volume ratio, molecular ratio) of the first and second electrode structures 110 and 120 can be changed to alter the initial resistivity R. initial Operating resistivity R operating and / or another characteristic. For example, in some embodiments, the first and third materials 112, 122 may include W 1.0 Si 2.4 Ge 3.6 W 1.0 Si 3.5 Ge 1.2 W 1.0 Si 4.9 Ge 2.0 Or similar materials. In some embodiments, the first and third materials 112, 122 may include W 0.2–1.0 Si 1.0 Ge 0.2–1.0 Therefore, the first and third materials 112 and 122 may include a composition of tungsten, silicon, and germanium, wherein: (i) the ratio of silicon to tungsten is greater than 1.0, (ii) the ratio of germanium to tungsten is greater than 1.0, (iii) the ratio of germanium to tungsten is greater than the ratio of silicon to tungsten, (iv) the ratio of germanium to tungsten is less than the ratio of silicon to tungsten, and so on. In some embodiments, the first and third materials 112 and 122 may include tungsten silicon germanium nitride (WSiGeN).

[0032] In some embodiments, increasing the amount of silicon in the composition can increase the operating resistivity R. operating In some embodiments, increasing the amount of germanium in the composition may increase: (i) the operating resistivity R operating (ii) Operating temperature T operating The thermal resistance below, and / or (iii) the operating resistivity R operating With initial resistivity R initial The difference between them. In some embodiments, increasing the amount of tungsten in the composition can reduce the operating resistivity R. operating and / or reduce the operating resistivity R operating With initial resistivity R initial The differences between them.

[0033] In some embodiments, the position and / or thickness of the first and third materials 112, 122 within the first and second electrode structures 110, 120 may be altered to, for example, provide a specific resistivity to the first and second electrode structures 110, 120. For example, as described in detail above, in Figure 1 In the embodiments described herein, the first material 112 has a smaller thickness than the second material and is positioned above the second material 114, and the third material 122 has a smaller thickness than the fourth material 124 and is positioned above the fourth material 124. Figures 4 to 7This describes different arrangements of the first and second materials 112, 114 in the first electrode structure 110 and / or different arrangements of the third and fourth materials 122, 124 in the second electrode structure 120 according to additional embodiments of the present technology. Figure 1 A magnified view of one of the columns 107.

[0034] First refer to Figure 4 In some embodiments, the third material 122 may be positioned between the first layer 425a and the second layer 425b of the fourth material 124. In some embodiments, the volume of the third material 122 and the volume of the fourth material 124 may be equal to or substantially equal to Figure 1 The volume of the third and fourth materials 122 and 124 in the embodiment. The first electrode structure 110 can be as follows: Figure 1 The typical arrangement in the embodiments.

[0035] refer to Figure 5 In some embodiments, the thickness of the third material 122 may be greater than the thickness of the fourth material 124. In some embodiments, the volume of the third material 122 may be greater than... Figure 1 The volume of the third material 122 in the embodiment, and the volume of the fourth material 124 may be smaller than that of the third material 122. Figure 1 The volume of the fourth material 124 in the embodiments. That is, for example, the third material 122 may at least partially replace a portion of the fourth material 124. In some embodiments, the fourth material 124 may serve as a barrier to prevent interaction between the third material 122 and the memory element 102, and may have a thickness selected (e.g., only large enough to achieve this function). The first electrode structure 110 may be as follows Figure 1 The typical arrangement in the embodiments.

[0036] refer to Figure 6 In some embodiments, the first material 112 may be positioned between the first layer 615a and the second layer 615b of the second material 114. In some embodiments, the volume of the first material 112 and the volume of the second material 114 may be equal to or substantially equal to Figure 1 The volume of the first and second materials 112, 114 in the embodiment. The second pole structure 120 can be as follows: Figure 5 The typical arrangement in the embodiments.

[0037] refer to Figure 7 In some embodiments, the first material 112 may be arranged in the first layer 717a and the second layer 717b relative to the first layer 615a and the second layer 615b of the second material 114. That is, the first layer 717a and the second layer 717b of the first material may be alternated between the first layer 615a and the second layer 615b of the second material 114 (e.g., alternating with the first layer 615a and the second layer 615b). The second pole structure 120 may be as follows: Figure 5 The typical arrangement in the embodiments.

[0038] Despite Figures 4 to 7 Various arrangements of the first and second electrode structures 110 and 120 are shown, but those skilled in the art will understand that these arrangements can be combined and / or modified. For example, the thickness of various materials can be varied and / or the materials can be arranged in more or fewer layers. Furthermore, different columns 107 in the memory device 100 may have different arrangements of the first electrode structure 110 and / or the second electrode structure 120. That is, columns 107 in the memory device 100 may be the same or different.

[0039] The memory devices described herein can be fabricated at the wafer level or at the die level and can be formed using conventional semiconductor manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0040] The above reference Figures 1 to 7 The memory device 100 described in detail and / or the package incorporated in the memory device 100 can be incorporated into any of a multitude of larger and / or more complex systems, a representative example of which is Figure 8 The system 840 is schematically shown in the diagram. System 840 may include a processor 842, a memory 844 (e.g., SRAM, DRAM, NAND, flash, and / or other memory devices), an input / output device 846, and / or other subsystems or components 848. (See above reference) Figures 1 to 7 The described memory device and / or package may be included in Figure 8 The resulting system 840 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Therefore, representative examples of system 840 include (but are not limited to) computers and / or other data processors, such as desktop computers, laptop computers, internet devices, handheld devices (e.g., PDAs, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of system 840 include lights, cameras, vehicles, etc. Regarding these and other examples, system 840 can be housed in a single unit or distributed across multiple interconnected units, for example, via a communication network. The components of system 840 can therefore include any of local and / or remote memory storage devices and a wide variety of suitable computer-readable media.

[0041] As should be understood from the foregoing, specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from this disclosure. Therefore, the invention is limited only by the appended claims. Furthermore, certain aspects of the new technology described in the context of specific embodiments may be incorporated into or eliminated from other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need to exhibit such advantages to fall within the scope of the present technology. Therefore, this disclosure and related technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A memory device comprising: Memory elements; and An electrode structure electrically coupled to the memory element, wherein the electrode structure comprises a material made of WGeSi or WSiGeN, wherein the electrode structure is configured to have a first resistivity before exposure to multiple thermal cycles, wherein the electrode structure is configured to have a second resistivity after exposure to the multiple thermal cycles, and wherein the second resistivity is greater than the first resistivity.

2. The memory device of claim 1, wherein the material is a first material, and wherein the electrode structure further comprises a second material different from the first material.

3. The memory device of claim 2, wherein the second material is between the memory element and the first material.

4. The memory device of claim 2, wherein the second material is a carbon-based material.

5. The memory device of claim 2, wherein the first material has a greater thickness than the second material.

6. The memory device of claim 2, wherein the second material has a greater thickness than the first material.

7. The memory device of claim 2, wherein the thickness of the first material is less than 100 angstroms.

8. The memory device of claim 2, wherein the thickness of the first material is between 50 and 90 angstroms.

9. The memory device of claim 2, wherein the thickness of the first material is between 10 and 30 angstroms.

10. The memory device of claim 1, wherein the ratio of Si to W is greater than or equal to 1.

0.

11. The memory device of claim 1, wherein the ratio of Ge to W is greater than or equal to 1.

0.

12. The memory device of claim 1, wherein the ratio of Si to W is greater than the ratio of Ge to W.

13. The memory device of claim 1, wherein the ratio of Si to W is less than the ratio of Ge to W.

14. A memory device comprising: Memory elements; and An electrode structure electrically coupled to the memory element, wherein the electrode structure comprises a material made of WGeSi or WSiGeN, wherein the electrode structure is configured to have a first resistivity before exposure to multiple thermal cycles, wherein the electrode structure is configured to have a second resistivity after exposure to the multiple thermal cycles, wherein the first resistivity is less than 0.01 ohm-cm, and wherein the second resistivity is greater than the first resistivity.

15. The memory device of claim 14, wherein the electrode structure further comprises a carbide material, and wherein the material made of WGeSi or WSiGeN is formed as a thin film on the carbide material.

16. The memory device of claim 14, wherein the memory element comprises a phase change material.

17. A memory device comprising: Memory elements; A first electrode structure electrically coupled to the memory element, wherein the first electrode structure comprises a first material made of WGeSi or WSiGeN, wherein the first electrode structure is configured to have a first resistivity before exposure to multiple thermal cycles, wherein the first electrode structure is configured to have a second resistivity after exposure to the multiple thermal cycles, and wherein the second resistivity is greater than the first resistivity. and A second electrode structure electrically coupled to the memory element, wherein the second electrode structure comprises a second material made of WGeSi or WSiGeN, wherein the second electrode structure is configured to have a third resistivity before exposure to multiple thermal cycles, wherein the second electrode structure is configured to have a fourth resistivity after exposure to the multiple thermal cycles, and wherein the fourth resistivity is greater than the third resistivity.

18. The memory device of claim 17, wherein the first electrode structure further comprises a third material different from the first material, and wherein the second electrode structure further comprises a fourth material different from the second material.

19. The memory device of claim 18, wherein the third material is between the first material and the memory element, and wherein the fourth material is between the second material and the memory element.

20. The memory device of claim 18, wherein the third and fourth materials are different.

21. The memory device of claim 18, wherein the third and fourth materials are carbide materials.

22. The memory device of claim 17, wherein the first and second materials are the same.

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