An internal clock driving circuit architecture for information hiding

Abstract

The application belongs to the technical field of information hiding, and discloses an internal clock driving circuit architecture for realizing information hiding, which comprises an FPGA and a control module, an information representation circuit, an information cover circuit and an RO clock circuit based on the FPGA. The circuit architecture generates an internal high-frequency clock based on a ring oscillator, divides the circuit into different clock domains, arranges corresponding circuits according to the area division of the area to be information represented, and uses the high-frequency flip characteristics of the ring oscillator RO to make the clock generated by the RO the input clock of the information representation part circuit when the information is represented, so that the working frequency of the part circuit is extremely high, enough heat is generated, a hot spot is formed, the expression of the hidden information is completed, and compared with the circuit architecture of self-excitation heat, more ring oscillators are used and are easy to be exposed, and the architecture disclosed by the application is safer.

Description

Technical Field

[0001] This invention belongs to the field of information hiding technology, specifically relating to an internal clock driving circuit architecture for implementing information hiding. Background Technology

[0002] The principle of information hiding technology is to conceal hidden information within a carrier. Traditional information hiding techniques include hiding data using low-order data in images, hiding information using punctuation marks, and so on. Traditional information hiding techniques are mostly single-time hiding techniques, making them relatively easy to crack.

[0003] The circuit architecture for achieving information hiding and self-heating uses a ring oscillator as the core of self-heating, and uses the hot spot formed in the area where the ring oscillator is located to represent information. However, in order to generate enough heat, a considerable number of ring oscillators need to be arranged, which may attract the attention of attackers. Summary of the Invention

[0004] The purpose of this invention is to provide an internal clock drive circuit architecture for achieving information hiding, so as to solve the problems in the prior art mentioned in the background section.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] An internal clock drive circuit architecture for achieving information hiding includes;

[0007] FPGA and a control module, information display circuit, information masking circuit and RO clock circuit based on the FPGA;

[0008] The information display circuit, information cover circuit, and RO clock circuit are all connected to the control module, and the RO clock circuit and the information display circuit are connected.

[0009] Furthermore, the information representation circuit is distributed in a specific area according to the FPGA heat distribution information representation method. In the initial normal state, the entire circuit is controlled by the clock from the FPGA crystal oscillator. The power consumption of the entire circuit is evenly distributed, thus hiding the hot spot information representation area.

[0010] Furthermore, the FPGA model is XC7A100T.

[0011] Furthermore, the RO clock circuit includes:

[0012] The processor module, the communication interface connected to the processor module, and the RO module are provided. The processor module is connected to the host computer through the communication interface, and the RO module is connected to the information representation circuit.

[0013] Furthermore, a thermal imager is connected to the FPGA, which detects the temperature of the FPGA chip before and after the host computer sends commands, and obtains the corresponding thermal distribution map.

[0014] Furthermore, the RO module includes:

[0015] The register and the signal input terminal connected to the register, the source of the signal input terminal including the source clock signal of the FPGA device crystal oscillator and the internal clock signal generated by RO.

[0016] Furthermore, the internal clock signal is generated by using the LUT resources of the FPGA to implement an inverter, and then processing its output signal and enable signal through an AND gate as the input of the inverter, thus forming a loop to generate a high-frequency clock.

[0017] Technical effects and advantages of the present invention: The internal clock driving circuit architecture for information hiding proposed in this invention has the following advantages compared with the prior art:

[0018] 1. This circuit architecture is based on generating an internal high-frequency clock using a ring oscillator. The circuit is divided into different clock domains. According to the domain division, the corresponding circuits are arranged in the area where the information is to be represented. When representing hidden information, the high-frequency switching characteristic of the ring oscillator RO is used to make the clock generated by RO the input clock of the information representation circuit. This makes the operating frequency of this part of the circuit extremely high, generating enough heat to form a hot spot, thus completing the expression of hidden information. Compared with the self-heating circuit architecture, which uses more ring oscillators and is easy to expose, the architecture proposed in this invention is more secure.

[0019] 2. This invention utilizes the high-frequency switching characteristic of the ring oscillator RO to use the clock generated by RO as the input clock of the information representation circuit, making the circuit operate at an extremely high frequency and generating sufficient heat to form a hot spot, thereby completing the expression of hidden information. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the internal clock drive circuit architecture for implementing information hiding in this invention.

[0021] Figure 2 This is a schematic diagram of the internal clock drive circuit architecture for implementing information hiding in this invention.

[0022] Figure 3 This is a schematic diagram of the RO circuit structure of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The specific embodiments described herein are merely used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] The embodiments of the present invention provide, for example Figure 1-3 The diagram illustrates an internal clock-driven circuit architecture for information hiding, comprising: an FPGA and a control module, an information representation circuit, an information masking circuit, and an RO clock circuit based on the FPGA; the information representation circuit, the information masking circuit, and the RO clock circuit are all connected to the control module, and the RO clock circuit and the information representation circuit are connected.

[0025] This circuit architecture uses a ring oscillator to generate an internal high-frequency clock, dividing the circuit into different clock domains to achieve information hiding. This embodiment uses an FPGA-based information hiding method, representing information through the FPGA's heat distribution and arranging corresponding circuits in the areas to be represented according to the regional division. When representing concealed information, the high-frequency switching characteristic of the ring oscillator (RO) is utilized, using the clock generated by RO as the input clock for the information representation circuit. This results in an extremely high operating frequency for this part of the circuit, generating sufficient heat to form a hotspot. This embodiment applies an FPGA-based internal clock driving circuit architecture to achieve information hiding, effectively concealing and expressing hidden information.

[0026] The FPGA model is XC7A100T. The information representation circuit is distributed in a specific area according to the FPGA thermal distribution information representation method. In the initial normal state, the entire circuit is controlled by the clock from the FPGA crystal oscillator. The power consumption of the entire circuit is evenly distributed, hiding the hot spot information representation area.

[0027] The circuit is divided into a hotspot information display section and a shielding circuit section. The display section and the shielding circuit are independent of each other and both use operational circuits. The frequency at which the circuit operates continuously is affected by the clock frequency.

[0028] Based on an FPGA-based thermal distribution information representation method, hotspot information representation circuitry is placed in a specific area. Under initial normal conditions, the entire circuit is controlled by the clock from the FPGA crystal oscillator, resulting in an even distribution of power consumption. This effectively hides the hotspot information representation area, making it undetectable.

[0029] To obtain hidden information, the masking circuit module is put into sleep mode. Simultaneously, the ring oscillator circuit is enabled, causing it to oscillate at high frequency to generate a RO clock. The input clock of the information display circuit is then switched to the RO clock. The area where the information display circuit is located experiences a significantly higher temperature than other areas during information display, indicating the information being represented. This is due to the circuit's efficient heat generation under the control of the RO high-frequency clock. In this way, the temperature of the local area where the information display circuit is located can be effectively distinguished from the information masking circuit area. By encoding the information representation in this local area (based on spatial division encoding), effective information transmission can be achieved based on the circuit's thermal distribution.

[0030] Regarding the information hiding process, the circuit architecture proposed in this invention operates under normal clock conditions in the initial state, where both the information masking circuit and the information representation circuit function normally. This makes it difficult for attackers to crack the circuit and obtain the hidden information. However, the recipient of the information can control the circuit according to a pre-agreed operating method, causing the information masking circuit to go into sleep mode while the information representation circuit operates under the RO clock, thereby obtaining the information corresponding to the heat distribution. The party that knows which control information to send to achieve the hidden information representation is the legitimate party; the attacker is the party that does not know what information to send or how to obtain it.

[0031] In addition, a thermal imager is connected to the FPGA. The circuit information is converted into a bit stream file using a synthesis tool and configured into the FPGA. The thermal imager detects the temperature of the FPGA chip before and after the host computer sends a command, and obtains the corresponding thermal distribution map. This circuit architecture can effectively realize information hiding and acquisition based on the thermal distribution of the FPGA.

[0032] exist Figure 1 Based on the general architecture, the specific architecture of the internal clock driving circuit for information hiding proposed in this invention is as follows: Figure 2 As shown, the proposed circuit architecture uses a processor soft core as the control unit and receives commands from the host computer through a communication interface to achieve real-time control of the information masking circuit, information display circuit, and RO module.

[0033] The RO clock circuit includes: a processor module, a communication interface connected to the processor module, and an RO module. The processor module is connected to a host computer through the communication interface, and the RO module is connected to the information representation circuit.

[0034] The RO module includes a register and a signal input terminal connected to the register. The source of the signal input terminal includes the source clock signal of the FPGA device crystal oscillator and the internal clock signal generated by the RO.

[0035] The register's input clock has two sources: one is the source clock from the FPGA device's crystal oscillator, and the other is an internal clock generated by the RO (Reverse Oscillator). The RO's internal clock is generated by implementing an inverter using the FPGA's LUT (Least Underlying Unit) resources. The output signal and enable signal are then ANDed together with the inverter's input, forming a loop to generate a high-frequency clock. When laying out the information representation circuit, an FPGA-based single-hotspot distribution method is used. This method represents information based on the location of hotspots, placing them in designated positions to achieve information representation.

[0036] When the processor receives a command from the host computer, it will control the information masking circuit to go into sleep mode, enable the RO circuit to work, and connect it to the information representation circuit. This area will then work efficiently to form a "hot spot". The hidden information is obtained according to the information representation method of the custom single hot spot distribution.

[0037] In this embodiment, the high-frequency switching characteristic of the ring oscillator RO is utilized to use the clock generated by RO as the input clock of the information representation circuit, making the circuit operate at an extremely high frequency and generating sufficient heat to form a hot spot, thereby completing the expression of hidden information. Compared with the self-heating circuit architecture that uses more ring oscillators and is easily exposed, the internal clock driving circuit architecture proposed in this invention is more secure.

[0038] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An internal clock driving circuit architecture implementing information hiding, characterized by, include; FPGA and a control module, information display circuit, information masking circuit and RO clock circuit based on the FPGA; The information display circuit, information cover circuit, and RO clock circuit are all connected to the control module, and the RO clock circuit and the information display circuit are connected. The information representation circuit is distributed in a specific area according to the information representation method of FPGA heat distribution. In the initial normal state, the entire circuit is controlled by the clock from the FPGA crystal oscillator. The power consumption of the entire circuit is evenly distributed, hiding the hot spot information representation area. When representing concealed information, the high-frequency switching characteristic of the ring oscillator RO is utilized to use the clock generated by RO as the input clock of the information representation circuit, making the circuit operate at an extremely high frequency and generating sufficient heat to form a hot spot. When the hidden information is obtained, the masking circuit module will go into sleep mode. At the same time, the ring oscillator circuit will be enabled, causing the ring oscillator to oscillate at high frequency to generate the RO clock, and the input clock of the information display circuit will be switched to the RO clock. In the initial state of the circuit architecture, both the information masking circuit and the information display circuit operate under the normal clock.

2. The internal clock driving circuit architecture for information hiding according to claim 1, characterized in that: The FPGA model is XC7A100T.

3. The internal clock driving circuit architecture for information hiding according to claim 2, characterized in that: The RO clock circuit includes: The processor module, the communication interface connected to the processor module, and the RO module are provided. The processor module is connected to the host computer through the communication interface, and the RO module is connected to the information representation circuit.

4. The internal clock driving circuit architecture for information hiding according to claim 3, characterized in that: A thermal imager is connected to the FPGA. The thermal imager detects the temperature of the FPGA chip before and after the host computer sends a command, and obtains the corresponding thermal distribution map.

5. The internal clock driving circuit architecture for information hiding according to claim 4, characterized in that: The RO module includes: The register and the signal input terminal connected to the register, the source of the signal input terminal including the source clock signal of the FPGA device crystal oscillator and the internal clock signal generated by RO.

6. The internal clock driving circuit architecture for information hiding according to claim 5, characterized in that: The internal clock signal is generated by using the LUT resources of the FPGA to implement an inverter, and then processing its output signal and enable signal through an AND gate as the input of the inverter, thus forming a loop to generate a high-frequency clock.

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