Analog-to-digital converter and image sensor with individually applied bias according to operating mode

Abstract

An image sensor supporting a full resolution mode and a crop mode, the image sensor comprising: a pixel array comprising a plurality of pixels configured to generate a pixel signal by sensing an object; an analog-to-digital converter configured to convert the pixel signal to a digital signal, and comprising a plurality of metal lines; a bias generator configured to apply a bias voltage to the plurality of metal lines; and a bias controller comprising a first transistor configured to activate all of the plurality of metal lines based on a first control signal, and a second transistor configured to activate a first metal line of the plurality of metal lines for the crop mode based on a second control signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0053755, filed on April 26, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a complementary metal-oxide-semiconductor (CMOS) image sensor, and more specifically, to an analog-to-digital converter that applies a bias voltage individually according to an operating mode, and an image sensor including the analog-to-digital converter. Background Technology

[0004] An image sensor is a sensor that detects and transmits information used to generate an image. Complementary metal-oxide-semiconductor (CMOS) image sensors are one of the two main types of electronic image sensors. In CMOS image sensors, correlated double sampling (CDS) is used to remove pixel reset noise. To improve the performance of an image sensor, an analog-to-digital converter (ADC) can be used in conjunction with the CDS method.

[0005] An ADC may include a power-saving switch to reduce power when the ADC is not used for sensing. However, the power-saving switch may introduce its own on-resistance and cause variations in the amplifier's input range. Summary of the Invention

[0006] An exemplary embodiment of the present invention provides an image sensor that applies a bias voltage individually according to the operating mode without including a separate power-saving switch.

[0007] According to an exemplary embodiment of the present invention, an image sensor supporting a full-resolution mode and a cropping mode is provided. The image sensor includes: a pixel array comprising a plurality of pixels configured to generate pixel signals by sensing an object; an analog-to-digital converter configured to convert the pixel signals into digital signals and including a plurality of metal lines; a bias generator configured to apply a bias voltage to the plurality of metal lines; and a bias controller including a first transistor configured to activate all metal lines of the plurality of metal lines based on a first control signal, and a second transistor configured to activate the first metal line of the plurality of metal lines for the cropping mode based on a second control signal.

[0008] According to an exemplary embodiment of the present invention, an analog-to-digital converter (ADC) configured to convert a pixel signal sensed at a pixel into a digital signal is provided. The ADC includes: a comparator comprising a first metal line and a second metal line activated according to a bias voltage, the comparator being configured to generate a comparison signal by comparing the pixel signal with the ramp signal based on the bias voltage; a counter configured to generate a digital signal by counting the comparison signal based on a clock signal; and a first transistor and a second transistor configured to determine the path of the bias voltage applied to the first metal line and the second metal line.

[0009] According to an exemplary embodiment of the present invention, an image sensor supporting a full-resolution mode and a cropping mode is provided. The image sensor includes: a pixel array comprising a plurality of pixels configured to generate pixel signals by sensing an object; an analog-to-digital converter array comprising a plurality of analog-to-digital converters, each configured to convert the pixel signals into digital signals, the analog-to-digital converter array including a plurality of metal lines commonly connected to the plurality of analog-to-digital converters; a bias generator configured to apply a bias voltage to the plurality of metal lines; and a bias controller comprising a first transistor configured to activate all of the plurality of metal lines based on a first control signal, a second transistor configured to activate a first metal line among the plurality of metal lines for the cropping mode based on a second control signal, and an output buffer configured to output a digital signal. Attached Figure Description

[0010] Embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating an image sensor according to an exemplary embodiment of a concept based on the present invention;

[0012] Figure 2 This is a circuit diagram illustrating a pixel according to an example embodiment of the concept of the present invention;

[0013] Figure 3 This is a schematic diagram illustrating an analog-to-digital converter array according to an exemplary embodiment of the present invention;

[0014] Figure 4A This is a circuit diagram of an amplifier used as a comparative example. Figure 4B This is a circuit diagram illustrating an amplifier according to an exemplary embodiment of the concept of the present invention;

[0015] Figure 5A , Figure 5B and Figure 5C This is a schematic diagram illustrating multiple metal lines, a bias generator, and multiple transistors according to an exemplary embodiment of the present invention.

[0016] Figure 6A , Figure 6B and Figure 6C This is a schematic diagram illustrating multiple metal lines, a bias generator, and multiple transistors according to an exemplary embodiment of the present invention. Figure 6D This is a table illustrating the signal levels of an analog-to-digital converter operating in an exemplary embodiment according to the present invention;

[0017] Figure 7A This is a diagram illustrating a pixel array in cropping mode according to an exemplary embodiment of the present invention. Figure 7B These are illustrations used to explain image processing in exemplary embodiments of the present invention.

[0018] Figure 8 This is a block diagram of an electronic device including a multi-camera module, based on an exemplary embodiment of the present invention; and

[0019] Figure 9 These are exemplary embodiments of the concept of the present invention. Figure 8 Detailed block diagram of the camera module. Detailed Implementation

[0020] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 This is a block diagram illustrating an image sensor 100 according to an example embodiment of the concept of the present invention.

[0022] Reference Figure 1 The image sensor 100 can be installed on an electronic device capable of sensing images or light. For example, the image sensor 100 can be installed in electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) objects, tablet PCs, personal digital assistants (PDAs), portable multimedia players (PMPs), navigation devices, etc. Alternatively, the image sensor 100 can be installed in electronic devices provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring devices, etc.

[0023] Image sensor 100 can convert light signals from an object incident through an optical lens into electrical signals, and then convert the electrical signals into image data IDT. For example, image sensor 100 may include a pixel array 110 and various circuits for sensing, the pixel array 110 including a plurality of pixels arranged in two dimensions. Image sensor 100 may be implemented as a semiconductor chip including pixel array 110 and sensing circuitry.

[0024] Image sensor 100 may include pixel array 110, row driver 120, analog-to-digital converter (ADC) array 130 including analog-to-digital converter (ADC) 131, bias generator 140, bias controller 150, ramp generator 160, clock generator 170, column decoder 180, output buffer 190, and control logic 195.

[0025] Pixel array 110 can convert received optical signals into electrical signals. Pixel array 110 may include multiple pixels 111, each connected to multiple row lines and multiple column lines (COL) and arranged in a matrix. Each of the multiple pixels 111 may include a photoelectric conversion element. For example, pixel 111 may be implemented as a photoelectric conversion element such as a charge-coupled device (CCD) or complementary metal-oxide-semiconductor (CMOS), and may be implemented using various types of photoelectric conversion elements. For example, photoelectric conversion elements may include photodiodes, phototransistors, photogates, or pinned photodiodes. Each of the multiple pixels 111 may include at least one photoelectric conversion element, and multiple photoelectric conversion elements may be stacked on top of each other.

[0026] Multiple pixels 111 can use photoelectric conversion elements to sense light and convert the sensed light into a pixel signal PS as an electrical signal. The pixel signal PS may include a reset signal generated based on a reset operation of each of the multiple pixels 111, and may include an image signal based on a light sensing operation of each of the multiple pixels 111. In other words, the pixel signal PS may include both a reset signal and an image signal.

[0027] Each of the plurality of pixels 111 can detect light within a specific spectral range. For example, the plurality of pixels 111 may include a red pixel for converting light in the red spectral range into an electrical signal, a green pixel for converting light in the green spectral range into an electrical signal, and a blue pixel for converting light in the blue spectral range into an electrical signal. A color filter for transmitting light within the specific spectral range may be provided on each of the plurality of pixels 111. As another example, the plurality of pixels 111 may include cyan pixels, yellow pixels, magenta pixels, or white pixels.

[0028] Microlenses and color filters can be stacked on each of a plurality of pixels 111, and the plurality of color filters of the plurality of pixels 111 can constitute a color filter array. The color filters can transmit light of a specific color, i.e., the wavelength of a specific color region, in the light incident through the microlenses. The color detectable by pixel 111 can be determined based on the color filters disposed in pixel 111. However, the inventive concept is not limited thereto, and in embodiments, a photoelectric conversion element provided in pixel 111 can convert light corresponding to the wavelength of the color region into an electrical signal based on the level of the applied electrical signal (e.g., voltage level). Therefore, the color detectable by pixel 111 can be determined based on the level of the electrical signal applied to the photoelectric conversion element.

[0029] In an example embodiment, each of the plurality of pixels 111 may use at least two photoelectric conversion elements to sense an object. For example, each of the plurality of pixels 111 may include at least one first photoelectric conversion element arranged to the left (or upward) relative to the optical axis of the microlens and at least one second photoelectric conversion element arranged to the right (or downward) relative to the optical axis of the microlens. Each of the plurality of pixels 111 may output a first image signal generated from the first photoelectric conversion element or a second image signal generated from the second photoelectric conversion element. One of two pixels 111 arranged in different adjacent rows and the same column may output the first image signal generated from the first photoelectric conversion element, and the other pixel 111 may output the second image signal generated from the second photoelectric conversion element. In this case, the two pixels 111 may detect the same color. Based on the first and second image signals output from the two pixels 111, autofocus data, such as a phase detection signal pair, for phase difference calculation for autofocus function can be generated. In addition, pixel 111 may output a sum image signal generated from at least one first photoelectric conversion element and at least one second photoelectric conversion element as a pixel signal PS. Image signals can be used to generate images in frames.

[0030] Row driver 120 can drive pixel array 110 row by row. Row driver 120 can decode the row control signal CTR_R generated by control logic 195 and select at least one row line from the row lines constituting pixel array 110 in response to the decoded row control signal. For example, row control signal CTR_R may include an address signal or a command indicating address information. In an exemplary embodiment of the inventive concept, row driver 120 can generate a row selection signal. Pixel array 110 can output pixel signals PS of the row selected by the row selection signal via column lines, which is provided from row driver 120. In other words, a plurality of pixels 111 of pixel array 110 can sequentially output pixel signals row by row.

[0031] Analog-to-digital converter array 130 can convert a pixel signal PS (which is an analog signal input from pixel array 110) into a digital value. Analog-to-digital converter array 130 may include a plurality of ADCs 131 arranged in the column direction to process the pixel signal PS provided through column lines COL.

[0032] In an exemplary embodiment of the present invention, the analog-to-digital converter array 130 may be referred to as a correlated double sampling circuit. The pixel signal PS output from a plurality of pixels 111 may have biases due to the characteristics of each pixel (e.g., column fixed pattern noise (CFPN)) and / or due to differences in the characteristics of the logic used to output the pixel signal from the pixels 111. To compensate for these biases between the pixel signals PS, correlated double sampling involves: obtaining a reset component (or reset signal) and an image component (or image signal) for each pixel signal PS; and extracting the difference between the reset component and the image component as the valid signal component.

[0033] The analog-to-digital converter array 130 can receive the bias control signal BCS generated by the bias controller 150, the ramp signal RS generated by the ramp generator 160, and the counter clock signal CLK generated by the clock generator 170. The ADC 131 can convert the pixel signal PS, which is an analog signal, into a digital value based on the bias control signal BCS, the ramp signal RS, and the counter clock signal CLK.

[0034] According to an exemplary embodiment of the present invention, ADC 131 can activate at least some of the column lines COL based on a bias control signal BCS, and generate a comparison signal by comparing a pixel signal PS output from a pixel 111 connected to an activated column line COL with a ramp signal RS and amplifying the comparison result. According to an exemplary embodiment of the present invention, ADC 131 can convert the comparison signal into a digital signal based on a counter clock signal CLK. ADC 131 will... Figure 3 A more detailed description is provided below.

[0035] The bias generator 140 can operate based on a bias control signal CTR_B provided from control logic 195. The bias generator 140 generates the bias voltage required to amplify the pixel signal PS and provides the generated bias voltage to the analog-to-digital converter array 130. The bias controller 150 can determine the path of the bias voltage provided to the analog-to-digital converter array 130. Depending on the operating mode, multiple ADCs 131 may share this bias voltage, and the bias controller 150 can activate at least some of the multiple column lines COL by determining the path, thereby providing the bias voltage to the multiple ADCs 131 arranged in parallel.

[0036] The ramp generator 160 can operate based on a ramp control signal CTR_RP provided from control logic 195. The ramp control signal CTR_RP can include a ramp enable signal. When the ramp enable signal is activated, the ramp generator 160 can generate a ramp signal RS with a slope. The ramp signal RS is a signal that gradually rises or falls with a constant amplitude. The ramp signal RS can include a reset ramp period for resetting and a signal ramp period for sensing the signal. For example, when the ramp signal RS is used for correlated double sampling (CDS), the ramp signal RS can sequentially have a reset ramp period and a signal ramp period.

[0037] According to an exemplary embodiment of the invention, the ramp generator 160 can generate a ramp signal RS having a specific slope, ramp time, ramp start voltage level, and / or ramp end voltage level in response to a ramp control signal CTR_RP. For example, the ramp generator 160 can generate a ramp signal that decreases at a constant slope, or it can generate a reverse ramp signal that increases at a constant slope.

[0038] Clock generator 170 can operate based on a clock control signal CTR_CK provided from control logic 195. Clock generator 170 can generate a counting clock signal CLK to be provided to analog-to-digital converter array 130. The timing and frequency of the generation of the counting clock signal CLK can be controlled by control logic 195. In an exemplary embodiment of the inventive concept, clock generator 170 can be implemented as a Gray code generator. Clock generator 170 can generate multiple code values ​​with a resolution that depends on the number of bits set to the counting clock signal CLK. For example, when 10 bits are set, clock generator 170 can generate a counting clock signal CLK including 1024 code values, and when 11 bits are set, clock generator 170 can generate a counting clock signal CLK including 2048 code values.

[0039] The output buffer 190 can temporarily store the digital signal output from the analog-to-digital converter array 130, then sense the digital signal, amplify the sensed digital signal, and output the amplified digital signal. The output buffer 190 may also include a column memory and a sense amplifier. The column memory can temporarily store the digital signal output from each of the multiple ADCs 131 and output that digital signal to the sense amplifier, which can sense and amplify the digital signal output from the column memory. The sense amplifier can output the amplified digital signal as image data ITA.

[0040] As described above, the column memory is included in the output buffer 190, but the inventive concept is not limited thereto. For example, the column memory may be included in the analog-to-digital converter array 130 in the form of a latch. In addition, the column memory may be implemented as static random access memory (SRAM), a latch, a flip-flop, or a combination thereof, but is not limited thereto.

[0041] Column decoder 180 operates based on a column control signal CTR_C provided from control logic 195. Column decoder 180 controls the output timing of pixel values ​​stored in output buffer 190 according to the column control signal CTR_C. Column decoder 180 can select a specific column line from multiple column lines COL by decoding the column control signal CTR_C. Column decoder 180 can control output buffer 190 to provide image data IDTA corresponding to the selected column line COL, temporarily stored in the memory of output buffer 190, to the outside.

[0042] Control logic 195 can control image sensor 100 by generating various control signals. According to an exemplary embodiment of the present invention, control logic 195 can generate a row control signal CTR_R for controlling row driver 120, a bias control signal CTR_B for controlling bias generator 140, a ramp control signal CTR_RP for controlling ramp generator 160, a clock control signal CTR_CK for controlling clock generator 170, and a column control signal CTR_C for controlling column decoder 180. For example, control logic 195 can adjust the application time, application rate, slope, start voltage level, and / or end voltage level of bias signal BS, ramp signal RS, and counter clock signal CLK by determining the timing, level, amplitude, duty cycle, and application time of row control signal CTR_R, bias control signal CTR_B, ramp control signal CTR_RP, clock control signal CTR_CK, and / or column control signal CTR_C.

[0043] Control logic 195 can interpret externally provided commands and adjust various control signals (e.g., row control signal CTR_R, bias control signal CTR_B, ramp control signal CTR_RP, clock control signal CTR_CK, and / or column control signal CTR_C) to correspond to the command. According to an exemplary embodiment of the present invention, when the central processing unit (e.g., an application processor) of the electronic device including image sensor 100 determines the operating mode of image sensor 100, control logic 195 can control the functional units of image sensor 100 to correspond to the determined operating mode. For example, image sensor 100 may support a full-resolution mode and a cropped mode. In other words, image sensor 100 may support a first mode and a second mode. When the application processor commands the operating mode to change to cropped mode, control logic 195 can adjust the row control signal CTR_R, bias control signal CTR_B, ramp control signal CTR_RP, clock control signal CTR_CK, and / or column control signal CTR_C to correspond to the cropped mode.

[0044] Control logic 195 can be implemented as a central processing unit (CPU), an arithmetic logic unit (ALU) performing arithmetic and logical operations, a shifter, a digital signal processor (DSP), a microprocessor, an application-specific integrated circuit (ASIC), control logic, etc., but is not limited thereto. In some embodiments of the present invention, control logic 195 may include a state machine consisting of multiple logic gates, and may include a processor and a memory storing instructions to be executed by the processor.

[0045] Figure 2 This is a circuit diagram illustrating a sample embodiment of pixel 111 according to the concept of the present invention. Figure 1 and Figure 2 Refer to this together.

[0046] Reference Figure 2 Pixel 111 may include a photodiode PD, a transmission transistor TX, a floating diffusion node FD, a reset transistor RX, a drive transistor DX, and a selection transistor SX. However, the inventive concept is not limited thereto, and the photodiode PD may be replaced by another photoelectric conversion element.

[0047] Each of the following signals—the reset control signal RS provided to the gate electrode of the reset transistor RX, the transmission control signal TS provided to the gate electrode of the transmission transistor TX, and the selection control signal SEL provided to the gate electrode of the selection transistor SX—can be controlled by the row driver 120 according to control logic 195. Figure 1 The line control signal CTR_R generated (as shown in the diagram) is used to provide this.

[0048] A photodiode (PD) can generate photocharge that varies depending on the intensity of incident light. For example, when the photodiode (PD) is a PN junction diode, it can generate a charge proportional to the amount of incident light (e.g., electrons as negative charges and holes as positive charges). The photodiode (PD) is an example of a photoelectric conversion element and can be at least one of a phototransistor, a photogate, a pinned photodiode (PPD), and combinations thereof.

[0049] A floating diffusion node (FD), which can be referred to as a floating diffusion region, can be formed between the transfer transistor (TX), the reset transistor (RX), and the drive transistor (DX). The transfer transistor (TX) can be configured according to the following parameters: Figure 1 The transmission control signal TS output by the row driver 120 transfers photocharge to the floating diffusion node FD. According to an exemplary embodiment of the invention, the floating diffusion node FD can operate as a capacitor. When the transmission transistor TX is turned on in response to the transmission control signal TS applied to the gate terminal of the transmission transistor TX, the charge (e.g., photocharge) generated by the photodiode PD can be transferred to the floating diffusion node FD and stored therein.

[0050] The driving transistor DX amplifies the photocharge based on the potential corresponding to the amount of photocharge accumulated in the floating diffusion node FD, and transfers the amplified photocharge to the selection transistor SX. The drain of the selection transistor SX is connected to the source of the driving transistor DX, and the pixel signal PS can be transmitted to the column line COL connected to pixel 111 based on the selection signal SEL output from the row driver 120. The reset transistor RX can reset the floating diffusion node FD to the power supply voltage VDD level based on the reset control signal RS provided from the row driver 120.

[0051] The reset transistor RX periodically resets the charge accumulated in the floating diffusion node FD. The source electrode of the reset transistor RX can be connected to the floating diffusion node FD, and the drain electrode of the reset transistor RX can be connected to the power supply voltage VDD. When the reset transistor RX turns on in response to a reset control signal RS applied to its gate electrode, the power supply voltage VDD connected to the drain electrode of the reset transistor RX is transferred to the floating diffusion node FD. When the reset transistor RX is on, the charge accumulated in the floating diffusion node FD can be discharged to reset the floating diffusion node FD.

[0052] The driving transistor DX can operate as a source follower. The driving transistor DX receives a signal with the charge amount of the floating diffusion node FD (in other words, the potential of the floating diffusion node FD) through its gate electrode and buffers the received signal to output it to the select transistor SX. The select transistor SX can be turned on in response to a select signal SEL applied to its gate electrode, and when the select transistor SX is turned on, the buffered signal output from the driving transistor DX is output as the pixel signal PS through the column line COL.

[0053] exist Figure 2 Although pixel 111 is shown as having a 4-transistor (4T) structure including a photodiode PD and four transistors TX, RX, DX and SX, each of the plurality of pixels 111 included in the image sensor in the exemplary embodiment of the present invention is not limited to Figure 2 The structure of pixel 111 is a pixel with a three-transistor (3T) structure, which may include a photodiode (PD) and include three transistors selected from a transmission transistor TX, a reset transistor RX, a drive transistor DX, and a selection transistor SX.

[0054] Figure 3 This is a schematic diagram illustrating an example embodiment of an analog-to-digital converter array 130 according to a concept of the present invention. Figure 1 and Figure 3 Refer to this together.

[0055] Reference Figure 3 The analog-to-digital converter array 130 may include multiple ADCs 131, and includes a bias signal ( Figure 1 The bias voltage V in BS) BIAS Included in slope signals ( Figure 1 The ramp voltage V in RS) RAMP The counter clock signal CLK can be provided to each of the ADC 131.

[0056] According to an exemplary embodiment of the present invention, ADC 131 may include comparator 210 and counter 230. Comparator 210 may be electrically connected to bias generator 140 and bias controller 150.

[0057] In this embodiment, for ease of explanation, the comparator 210 is shown to compare the pixel signal PS with the ramp signal ( Figure 1 The inventive concept is not limited thereto. For example, it can be understood that ADC 131 may include a comparator that generates the comparison signal and an amplifier that amplifies the comparison signal, which is the result of comparator 210 receiving pixel signal PS.

[0058] According to an exemplary embodiment of the present invention, comparator 210 may include multiple metal lines. The multiple metal lines may be for image sensor 100 ( Figure 1 The various operating modes supported (as shown in the diagram) are configured respectively. For example, comparator 210 may include a first metal line for imaging the object in full-resolution mode and may include a second metal line for imaging the object in cropping mode. In an exemplary embodiment of the inventive concept, cropping mode is an operating mode for imaging only a portion of the imageable region of the object, rather than the entire imageable object. The activation of at least one of the metal lines (e.g., a bias voltage V) can be used as a basis for imaging. BIAS The application of the comparator 210 determines the operation of the comparator 210 in a specific operating mode of the image sensor 100.

[0059] In an exemplary embodiment of the present invention, multiple metal lines may be positioned above or below the analog-to-digital converter array 130. In an exemplary embodiment of the present invention, multiple metal lines may be positioned below the comparator 210, with a bias voltage V. BIAS Multiple comparators 210 included in the analog-to-digital converter array 130 can be supplied via multiple metal lines. In this embodiment, it is understood that the lines connected to the bias voltage V... BIAS The comparator 210 of the metal wire has been activated. In other words, when a bias voltage V is applied to the metal wire... BIAS At that time, comparator 210 connected to the metal wire is activated. According to an exemplary embodiment of the invention, the bias voltage V can be... BIAS By applying voltage to at least one of multiple metal lines and activating comparator 210 connected to the metal line to which the voltage is applied, the pixel signal PS can be compared, amplified, or inverted. The bias controller 150 can determine the bias voltage V. BIAS The path is used to control whether comparator 210 is activated. (Refer to...) Figures 5A to 5C and Figures 6A to 6C Describe the activation of comparator 210.

[0060] Comparator 210 can compare the pixel signal PS with the ramp voltage V RAMP The comparison is performed, and the result is amplified or inverted. When based on the bias voltage V... BIAS From the connection to column line COL ( Figure 1 Pixel 111 of any of the lines shown) Figure 1 When the output pixel signal PS (as shown in the diagram) is displayed, comparator 210 can amplify the pixel signal PS to a voltage level suitable for analog-to-digital conversion. When the ramp voltage V... RAMPWhen the level of the signal is equal to the level of the amplified signal, comparator 210 can output a comparison signal COMP that transitions from, for example, a first logic level high to, for example, a second logic level low. The timing of the transition of the comparison signal COMP can be determined based on the level of the pixel signal PS.

[0061] Comparator 210 may include a differential amplifier, which can be implemented as an operational transconductance amplifier (OTA), operational amplifier, etc. A ramp voltage V can be received at the input terminals of comparator 210. RAMP and pixel signal PS as input signal ( Figure 4A and Figure 4B (INP). For example, the pixel signal PS can be input to the negative input terminal of comparator 210, and the ramp voltage V RAMP It can be input to the positive input terminal of comparator 210. Comparator 210 can compare the pixel signal PS with the ramp voltage V. RAMP The comparison is performed, and the result of the comparison operation is output as a comparison signal COMP via the output terminal.

[0062] ADC 131 may also include limiting circuitry. This limiting circuitry can be connected to the output terminal of comparator 210 and limits the voltage at the output terminal; in other words, it limits the level of the comparison signal COMP. The limiting circuitry can prevent the level of the comparison signal COMP from dropping below a specific level by providing current to the output terminal. Therefore, in comparator 210, the drain / source voltage of the transistor to which the pixel signal PS is input can be prevented from dropping below a specific level, and column fixed-mode noise (CFPN) due to trap charge can be prevented.

[0063] Each of the multiple counters 230 can be connected to the output terminal of comparator 210 to count each comparison signal COMP. For example, control logic 195 ( Figure 1 (As shown in the figure) can generate a counter clock signal and a counter reset signal for controlling the reset operation of the plurality of counters 230, as well as a counter control signal including an inverted signal for inverting the internal bits of each of the plurality of counters 230.

[0064] Each of the multiple counters 230 can count the number of level transitions of the comparison signal output from the comparator 210 corresponding to the same column, based on the counting clock signal CLK, and output the count value as a digital signal DS. The counters 230 can transmit the digital signal DS to... Figure 1 The output buffer is 190.

[0065] In an exemplary embodiment of the present invention, counter 230 may include latch circuitry and arithmetic circuitry. When the level of the comparison signal received from comparator 210 changes, the latch circuitry may latch the code value received as a counting clock signal CLK. The latch circuitry may latch each of the code value corresponding to a reset signal (e.g., a reset value) and the code value corresponding to an image signal (e.g., an image signal value). The arithmetic circuitry may calculate the reset value and the image signal value to generate an image signal value from which the reset level of pixel 111 is removed. Counter 230 may output the image signal value from which the reset level has been removed as the pixel value. However, the present invention is not limited thereto; counter 230 may be implemented as an up counter, an up / down counter, or a bit-inverting counter that sequentially increments the count value based on the counting clock signal CLK and the arithmetic circuitry. In this case, the bit-inverting counter may perform operations similar to an up / down counter. For example, when a specific signal is input, the bit-inverting counter may perform the function of counting only up and obtaining the complement of 1 by inverting all bits within the counter. The bit-inverting counter performs a reset count, and then converts the reset count to two's complement of 1 by inverting the reset count, in other words, converting it to a negative value.

[0066] However, the image sensor 100 according to an exemplary embodiment of the present invention is not limited thereto. The image sensor 100 may further include a counting code generator that executes counting codes under the control of control logic 195. The counting code generator may be implemented as a Gray code generator and may generate multiple code values ​​as counting codes having a resolution depending on a set number of bits. For example, multiple counters 230 may include latch circuitry and arithmetic circuitry, and the latch circuitry may receive counting codes from the counting code generator and an output signal from a comparator, and may latch the code values ​​of the counting codes when the level of the comparator signal changes. The arithmetic circuitry may generate an image signal value from which the reset level of pixel 111 has been removed by calculating a reset value and an image signal value.

[0067] Figure 4A This is a circuit diagram of comparator 210a as an example of a comparison. Figure 4B This is a circuit diagram illustrating a comparator 210b according to an exemplary embodiment of the present invention.

[0068] Reference Figure 4A The comparator 210a may include a plurality of transistors MP11, MP12, MN11, MN12, MN21a, MN22a and MN23a, and some of the plurality of transistors MN21a, MN22a and MN23a may be equivalently represented as a current source CSa.

[0069] exist Figure 4AIn this circuit, comparator 210a may include a first P-type transistor MP11, a second P-type transistor MP12, a first N-type transistor MN11, and a second N-type transistor MN12. Furthermore, comparator 210a may include a third N-type transistor MN21a, a fourth N-type transistor MN22a, and a fifth N-type transistor MN23a between the first node NN and ground. For example, the third N-type transistor MN21a, the fourth N-type transistor MN22a, and the fifth N-type transistor MN23a may be implemented as a current source CSa. The current source CSa may be implemented as an NMOS transistor, in other words, an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), and the first terminal of the current source CSa may be connected to ground, and the second terminal of the current source CSa may be connected to the first node NN, thereby generating a bias current.

[0070] The first N-type transistor MN11 and the second N-type transistor MN12 can each receive differential inputs (e.g., a first input signal INP and a second input signal INN), and generate differential currents based on the level difference between the first input signal INP and the second input signal INN. For example, they can receive ramp voltage V. RAMP The first input signal INP can be received, and the pixel signal PS can be received as the second input signal INN.

[0071] When the first input signal INP equals the second input signal INN, the same amount of current can flow in the first N-type transistor MN11 and the second N-type transistor MN12. Furthermore, when the first input signal INP differs from the second input signal INN, different amounts of current can flow in the first N-type transistor MN11 and the second N-type transistor MN12. The sum of the currents flowing through the first N-type transistor MN11 and the second N-type transistor MN12 can equal the bias current.

[0072] A power supply voltage VDD can be applied to the first terminal of the first P-type transistor MP11, and the second terminal of the first P-type transistor MP11 can be connected to a second output terminal for outputting a second output signal OUTN. The power supply voltage VDD is applied to the first terminal of the second P-type transistor MP12, and a first output terminal for outputting a first output signal OUTP can be formed at the second terminal of the second P-type transistor MP12. The first output signal OUTP and the second output signal OUTN can be determined based on current mirroring of the first P-type transistor MP11 and the second P-type transistor MP12. The first output signal OUTP and the second output signal OUTN can be determined based on the amount of current flowing through the first N-type transistor MN11 and the second N-type transistor MN12. When the level of the first input signal INP is higher than the level of the second input signal INN, a larger amount of current flows through the first N-type transistor MN11 compared to the second N-type transistor MN12. Therefore, the level of the first output signal OUTP can increase, and the level of the second output signal OUTN can decrease.

[0073] First bias voltage V BIAS1 Can be used as Figure 1 The bias signal BS is applied to the gate electrode of the third N-type transistor MN21a, and the second bias voltage V BIAS2 The bias signal BS can be applied to the gate electrode of the fourth N-type transistor MN22a, and the power-saving signal PDB can be applied to the gate electrode of the fifth N-type transistor MN23a. When the first bias voltage V is applied... BIAS1 and / or second bias voltage V BIAS2 At this time, comparator 210a can amplify the pixel signal PS. First bias voltage V BIAS1 With the second bias voltage V BIAS2 Instead of providing power to only one comparator 210a, it can simultaneously supply power to the analog-to-digital converter array 130. Figure 1 The ADC 131 includes multiple comparators (as shown in the diagram). The power-saving signal PDB is used in the ADC 131 (…). Figure 1 Some of the signals shown are not used to cut off power to minimize power supply when sensing. In this case, the fifth N-type transistor MN23a, which is provided with the power-saving signal PDB, is used as a physical power-saving switch.

[0074] Because physical switches are added to the analog-to-digital converter array 130, their own on-resistance is introduced, and the amplifier's input range and bias current can be altered. For example, Figure 4A The comparator 210a in the example employs a structure of three transistors connected in series. As a result, the power-saving switch may limit the input range of the minimum operating voltage and degrade the on-resistance distribution.

[0075] Reference Figure 4BThe comparator 210b of the exemplary embodiment of the present invention may include a third N-type transistor MN21b and a fourth N-type transistor MN22b serving as switches for receiving bias voltages, but may not include a fifth N-type transistor MN23a using a physical power-saving switch. Figure 4A (As shown in the figure). The third N-type transistor MN21b and the fourth N-type transistor MN22b can be equivalently represented as current sources CSb.

[0076] Comparator 210b, according to an exemplary embodiment of the invention, can cut off power to some parts of the ADC 131 when not used for sensing, by applying a bias voltage individually according to the operating mode, in the absence of a physical power-saving switch (e.g., the fifth N-type transistor MN23a). Reference will be made below. Figure 5A Describe in detail the method of applying bias voltage individually according to the operating mode.

[0077] Figures 5A to 5C This is a schematic diagram illustrating a plurality of metal lines 211, 212 and 213, a bias generator 140, and bias controllers 151, 152 and 153 according to an exemplary embodiment of the present invention.

[0078] Reference Figure 5A as well as Figure 1 and Figure 3 The first metal line ML1 and the second metal line ML2 included in the ADC 131 may be referred to as multiple metal lines 211. According to an exemplary embodiment of the present invention, multiple metal lines 211 may be provided in the comparator 210 (…). Figure 3 (as shown) below or above, and receives bias voltage V BIAS For example, the bias voltage V BIAS It may include a first bias voltage V with different levels BIAS1 Second bias voltage V BIAS2 .

[0079] According to an exemplary embodiment of the present invention, an image sensor 100 ( Figure 1 The image sensor 100 provides multiple metal lines 211 to support the operating modes shown in the diagram. The operating modes of the image sensor 100 may include full-resolution mode, cropping mode, binning mode, power-saving mode (e.g., power saving), etc., and may vary depending on the imaging scenario. For example, in cropping mode, the first metal line ML1 can bias the voltage V... BIAS Provided to some of the comparators among the multiple comparators 210 included in the analog-to-digital converter array 130. Additionally, the second metal line ML2 may not pass the bias voltage V. BIAS The bias voltage V is provided to the remaining comparators among the plurality of comparators 210 included in the analog-to-digital converter array 130. No bias voltage V is provided to any of the plurality of comparators 210.BIAS The remaining comparators may include the pixel array 100 that is not sensed in the cropping mode. Figure 1 The column line COL (as shown in the figure) Figure 1 In the corresponding ADC 131 (shown in the diagram), because of the bias voltage V... BIAS Since no comparator 210 is applied to the area not being sensed, the power consumption of the image sensor 100 can be minimized.

[0080] According to an exemplary embodiment of the present invention, the bias controller 151 may further include a first transistor TR1a, a second transistor TR2a, and a first switch SW1a. The first transistor TR1a and the second transistor TR2a can determine the bias voltage V supplied to the plurality of metal lines 211. BIAS The path. According to an exemplary embodiment of the invention, the activation of the first metal line ML1 and / or the second metal line ML2 can be determined by the on / off state of the first transistor TR1a and / or the second transistor TR2a. For example, when the first transistor TR1a is on, ground voltage can be applied to the first metal line ML1. In this case, no bias voltage is applied to the first metal line ML1, thus the first metal line ML1 can be deactivated. For example, when the second transistor TR2a is on, ground voltage can be applied to the second metal line ML2. In this case, no bias voltage is applied to the second metal line ML2, thus the second metal line ML2 can be deactivated.

[0081] According to an exemplary embodiment of the present invention, a first control signal CS1 may be provided to the gate electrode of a first transistor TR1a, and a second control signal CS2 may be provided to the gate electrode of a second transistor TR2a. Whether the first transistor TR1a and the second transistor TR2a are activated can be determined based on the logic level (e.g., logic high or logic low) of the first control signal CS1 and the second control signal CS2. Activation of the first transistor TR1a and the second transistor TR2a may mean turning the first transistor TR1a and the second transistor TR2a on / off.

[0082] According to an exemplary embodiment of the present invention, the first transistor TR1a can determine whether to apply the bias voltage V. BIAS The bias voltage V is applied to all the multiple metal lines 211. The second transistor TR2a determines whether to apply the bias voltage V. BIAS The second metal wire ML2 is applied to the multiple metal wires 211.

[0083] According to an exemplary embodiment of the present invention, a first switch SW1a may be included between a first transistor TR1a and a second transistor TR2a. The first switch SW1a may be controlled by a first switch signal SS1a. The first switch SW1a may prevent the application of ground voltage to the second metal line ML2 when the first transistor TR1a is turned on, or prevent the application of ground voltage to the first metal line ML1 when the second transistor TR2a is turned on.

[0084] In an exemplary embodiment of the present invention, for image sensor 100 ( Figure 1 The various operations shown in the diagram illustrate the first bias voltage V. BIAS1 Second bias voltage V BIAS2 Both are used as bias signals BS ( Figure 1 As shown in the diagram, a bias voltage V is applied to comparator 210a, but the inventive concept is not limited thereto. Comparator 210a can receive a bias voltage V through a transistor (e.g., a third N-type transistor MN21a). BIAS1 Alternatively, it can receive three or more bias voltages through three or more transistors.

[0085] The analog-to-digital converter array 130 and / or the image sensor 100 including the analog-to-digital converter array 130, according to an exemplary embodiment of the present invention, can reduce the number of physical switches by applying bias voltages individually according to the operating mode. Therefore, the analog-to-digital converter array 130 and the image sensor 100 can reduce noise caused by physical switches (e.g., CFPN or thermal noise), minimize the increase in resistance, and stabilize the input range of the comparator 210.

[0086] Furthermore, since the analog-to-digital converter array 130 and / or the image sensor 100 including the analog-to-digital converter array 130 of the exemplary embodiments of the present invention can reduce noise by reducing the number of physical switches, low-power circuit design can be easily implemented even if the input voltage is gradually reduced to achieve low power.

[0087] Furthermore, the analog-to-digital converter array 130 and / or the image sensor 100 including the analog-to-digital converter array 130 in the exemplary embodiments of the present invention can increase space efficiency in circuit layout design by reducing the number of physical switches.

[0088] Reference Figure 5B as well as Figure 1 and Figure 3The bias controller 152 also includes a first transistor TR1b, a second transistor TR2b and a second switch SW2b, and a third transistor TR3b and a third switch SW3b. Furthermore, since the image sensor 100 supports various modes (e.g., merged mode), in addition to the first metal line ML1 and the second metal line ML2, the multiple metal lines 212 may also include a third metal line ML3. Figure 5A and Figure 5B For the sake of simplicity, multiple metal lines 211 and 212 are shown, including two or three metal lines ML1, ML2, and ML3; however, the inventive concept is not limited thereto. By combining various numbers of metal lines, metal lines that are not sensed or processed for each operating mode can be deactivated.

[0089] Because in Figure 5B The multiple metal wires 212 include three metal wires ML1 to ML3, therefore compared to Figure 5A Additional transistors can be added. According to an exemplary embodiment of the invention, the first transistor TR1b can be connected to the common node of the first metal line ML1 and the bias generator 140, and can be controlled by the first control signal CS1. The second transistor TR2b can be connected to the second metal line ML2, and can be controlled by the second control signal CS2. The third transistor TR3b can be connected to the third metal line ML3, and can be controlled by the third control signal CS3.

[0090] The second switch SW2b can be connected between the common node of the first metal line ML1 and the bias generator 140 and the common node of the second transistor TR2b and the second metal line ML2, and can be controlled by the second switch signal SS2b. The third switch SW3b can be connected between the common node of the first metal line ML1 and the bias generator 140 and the common node of the third transistor TR3b and the third metal line ML3, and can be controlled by the third switch signal SS3b.

[0091] According to an exemplary embodiment of the present invention, the first transistor TR1b can determine whether to apply the bias voltage V. BIAS The bias voltage V is applied to all the multiple metal lines 212. The second transistor TR2b determines whether to apply the bias voltage V. BIAS The bias voltage V is applied to the second metal line ML2 in the plurality of metal lines 212. The third transistor TR3b determines whether to apply the bias voltage V. BIAS The third metal wire ML3 is applied to the multiple metal wires 212.

[0092] The second switch SW2b can prevent the application of ground voltage to the second metal line ML2 when the first transistor TR1b is turned on, or prevent the application of ground voltage to the first metal line ML1 or the third metal line ML3 when the second transistor TR2b is turned on. The third switch SW3b can prevent the application of ground voltage to the third metal line ML3 when the first transistor TR1b is turned on, or prevent the application of ground voltage to the first metal line ML1 or the second metal line ML2 when the third transistor TR3b is turned on.

[0093] Reference Figure 5C as well as Figure 1 and Figure 3 The bias controller 153 may further include a first transistor TR1c, a second transistor TR2c, a third transistor TR3c, a fourth switch SW1c, and a fifth switch SW3c. Multiple metal lines 213 may include a first metal line ML1 and a second metal line ML2.

[0094] According to an exemplary embodiment of the present invention, a first transistor TR1c can be connected to a common node of the first metal line ML1 and the bias generator 140, and can be controlled by a first control signal CS1. A second transistor TR2c can be connected to the second metal line ML2, and can be controlled by a second control signal CS2. A third transistor TR3c can be connected to the first metal line ML1, and can be controlled by a third control signal CS3.

[0095] The fourth switch SW1c can be connected between the common node of the first metal line ML1 and the bias generator 140 and the common node of the second transistor TR2c and the second metal line ML2, and can be controlled by the fourth switch signal SS1c. The fifth switch SW3c can be connected between the common node of the first metal line ML1 and the bias generator 140 and the common node of the third transistor TR3c and the first metal line ML1, and can be controlled by the fifth switch signal SS3c.

[0096] According to an exemplary embodiment of the present invention, the first transistor TR1c can determine whether to apply the bias voltage V. BIAS The bias voltage V is applied to all the multiple metal lines 213. The second transistor TR2c can determine whether to apply the bias voltage V. BIAS The bias voltage V is applied to the second metal line ML2 among the multiple metal lines 213. The third transistor TR3c can determine whether to apply the bias voltage V. BIAS The first metal wire ML1 is applied to one of the multiple metal wires 213.

[0097] The fourth switch SW1c can prevent the application of ground voltage to the second metal line ML2 when the first transistor TR1c is turned on, or prevent the application of ground voltage to the first metal line ML1 when the second transistor TR2c is turned on. The fifth switch SW3c can prevent the application of ground voltage to the first metal line ML1 when the first transistor TR1c is turned on, or prevent the application of ground voltage to the second metal line ML2 when the third transistor TR3c is turned on.

[0098] According to an exemplary embodiment of the invention, each of at least two metal lines (e.g., a first metal line ML1 and a second metal line ML2) of a plurality of metal lines 213 can be connected to a transistor (e.g., a second transistor TR2c or a third transistor TR3c) and a switch (e.g., a fourth switch SW1c or a fifth switch SW3c). Therefore, the image sensor 100 operating in cropping mode ( Figure 1 As shown, the comparator 210 required for the trimming mode can be selectively activated. Figure 3 (as shown in the image).

[0099] Figures 6A to 6C This is a schematic diagram illustrating multiple metal lines 211, a bias generator 140, and multiple transistors TR1 and TR2 according to an exemplary embodiment of the present invention. Figure 1 and Figure 5A and Figures 6A to 6C Refer to this together.

[0100] In this embodiment, for ease of description, it is assumed that both the first transistor TR1 and the second transistor TR2 are N-type MOSFETs. Therefore, the first control signal CS1 and the second control signal CS2 of the first transistor TR1 and the second transistor TR2 are described based on N-type MOSFETs. However, the inventive concept is not limited to this, and therefore, the inventive concept does not exclude the case where the first transistor TR1 and the second transistor TR2 are P-type MOSFETs. In this case, the logic levels of the first control signal CS1 and the second control signal CS2 of the first transistor TR1 and the second transistor TR2 may have opposite phases.

[0101] Reference Figure 6A The first control signal CS1 can be applied as logic low (L). In this case, the channel of the first transistor TR1 is not formed, and the first transistor TR1 is deactivated. As a result, the ground voltage connected to one end of the first transistor TR1 is not provided to the other end of the first transistor TR1.

[0102] The second control signal CS2 can be applied as logic low (L). In this case, the channel of the first transistor TR1 is not formed, and the second transistor TR2 is deactivated. Therefore, the ground voltage connected to one end of the second transistor TR2 is not provided to the other end of the second transistor TR2.

[0103] The first switch signal SS1 can be applied as logic high H, and the first switch SW1 can be shorted.

[0104] As a result, the bias voltage V generated by the bias generator 140 BIAS It can be supplied to both the first metal line ML1 and the second metal line ML2. The first metal line ML1 can supply the bias voltage V. BIAS Provided to some of the comparators 210, and the second metal line ML2 can bias the voltage V BIAS This is provided to the remaining comparators in the plurality of comparators 210. In other words, the first metal line ML1 can provide a bias voltage V to the first portion of the plurality of comparators 210. BIAS Furthermore, the second metal line ML2 can provide a bias voltage V to the second portion of the plurality of comparators 210. BIAS As a result, a bias voltage can be provided to all comparators 210 (e.g., to activate them). Bias voltage V BIAS The case applied to all comparators 210 can correspond to the full-resolution mode.

[0105] Reference Figure 6B The first control signal CS1 can be applied as logic low L. In this case, the channel of the first transistor TR1 is not formed, and the first transistor TR1 is deactivated. Therefore, the ground voltage connected to one end of the first transistor TR1 is not provided to the other end of the first transistor TR1.

[0106] The second control signal CS2 can be applied as logic high (H). In this case, a channel can be formed in the second transistor TR2, and the second transistor TR2 is turned on. Therefore, the ground voltage connected to one end of the second transistor TR2 is provided to the other end of the second transistor TR2. In this case, the ground voltage can be applied to the second metal line ML2 to deactivate the second metal line ML2.

[0107] The first switch signal SS1 can be applied as logic low L, and the first switch SW1 can be open to prevent the supply of ground voltage to the first metal line ML1.

[0108] As a result, the bias voltage V generated by the bias generator 140 BIAS It can be provided to the first metal line ML1. The first metal line ML1 can provide the bias voltage V. BIAS Provided to some of the comparators in the plurality of comparators 210, and the second metal line ML2 may not bias the voltage V BIAS This is provided to the remaining comparators in the plurality of comparators 210. Therefore, only some of the comparators in the plurality of comparators 210 can perform the analog-to-digital conversion operation. Bias voltage V BIASThe case where only some of the comparators in the multiple comparators 210 are applied can correspond to the trimming mode.

[0109] Reference Figure 6C The first control signal CS1 can be applied as logic high H to form the channel of the first transistor TR1, and the first transistor TR1 is activated. Therefore, the ground voltage connected to one end of the first transistor TR1 is provided to the other end of the first transistor TR1.

[0110] The second control signal CS2 can be applied as logic high (H). In this case, the channel of the second transistor TR2 is formed, and the second transistor TR2 is activated. Therefore, the ground voltage connected to one end of the second transistor TR2 is provided to the other end of the second transistor TR2. Thus, the ground voltage can be applied to the second metal line ML2 to deactivate the second metal line ML2.

[0111] In this scenario, the first switch signal SS1 can be applied as either logic high (H) or logic low (L) (D: no effect). This is because if the first switch SW1 is open, ground voltage can be supplied to the first metal line ML1 through the first transistor TR1, and ground voltage can be supplied to the second metal line ML2 through the second transistor TR2. Conversely, if the first switch SW1 is shorted, ground voltage can be supplied to both the first metal line ML1 and the second metal line ML2 through the first transistor TR1. Therefore, when the second control signal CS2 is logic high (H), the logic level of the first switch signal SS1 has no effect (D).

[0112] Using similar logic, when the first control signal CS1 is applied as logic high (H), the logic level of the second control signal CS2 is unaffected when the first switch signal SS1 is applied as logic high (D). For example, when the second control signal CS2 is logic low (L), because the first transistor TR1 is activated, ground voltage can be provided to the second metal line ML2 through the shorted first switch SW1. Furthermore, when the second control signal CS2 is logic high (H), because the first transistor TR1 is activated, ground voltage can be provided to the second metal line ML2 through the shorted first switch SW1, or because the second transistor TR2 is activated, ground voltage can be directly provided to the second metal line ML2.

[0113] By applying ground voltage to all multiple metal lines 211 without bias voltage V BIAS The situation where all multiple comparators 210 are deactivated can correspond to the power saving mode.

[0114] Figure 6D This is a table showing signal levels depending on the operating mode of the ADC 131, according to an example embodiment of the present invention.

[0115] Reference Figure 6D as well as Figures 6A to 6C To support the ADC131's full-resolution mode, both the first control signal CS1 and the second control signal CS2 need to be applied as logic low (L), and the first switching signal SS1 needs to be applied as logic high (H). As a result, the bias voltage V... BIAS It can be applied to the first metal line ML1 and the second metal line ML2.

[0116] To support the CROP mode of the ADC 131, both the first control signal CS1 and the first switch signal SS1 need to be applied as logic low (L), and the second control signal CS2 needs to be applied as logic high (H). As a result, the bias voltage V... BIAS It can be applied to the first metal line ML1, and the ground voltage V SS It can be applied to the second metal line ML2.

[0117] To support the power-saving mode PWROFF of the ADC 131, at least two of the first control signal CS1, the second control signal CS2, and the first switch signal SS1 need to be logic high (H). For example, when the first control signal CS1 and the second control signal CS2 are applied as logic high (H), the logic level of the voltage applied to the first switch signal SS1 is unaffected (D). Similarly, when the first control signal CS1 and the first switch signal SS1 are applied as logic high (H), the logic level of the voltage applied to the second control signal CS2 is unaffected (D). As a result, the ground voltage V... SS It can be applied to both the first metal line ML1 and the second metal line ML2. As described above, when the first transistor TR1 and the second transistor TR2 are P-type MOSFETs, the logic levels of the control signals CS1 and CS2 of transistors TR1 and TR2 can be opposite in phase.

[0118] Figure 7A This is a diagram illustrating a pixel array according to a cropping pattern, representing an example embodiment of the concept according to the present invention.

[0119] Reference Figure 7A The pixel array 110 can sequentially read multiple rows from ROW1 to ROW(N+1) that correspond to the cropping region CROPAREA.

[0120] Image sensor 100 according to an example embodiment of the present invention Figure 1 The operating mode (as shown in the diagram) can be determined by an external controller (e.g., an application processor). For example, the cropping region CROPAREA can be set as the target region via an external application processor.

[0121] The CROP AREA may include rows M to N (crop row regions). In an exemplary embodiment of the present invention, pixel array 110 may skip the remaining rows except for the CROP AREA and sequentially read row M (M) to row N (N). The pixel signal PS read for each row can be output in the column direction of pixel array 110.

[0122] Depending on the control of the application processor used for the crop area, positional information of pixel 111 with respect to the crop area, in other words, positional information of the column line (COL), can also be provided. For example, under the control of the application processor, column decoder 170 ( Figure 1 As shown, it is possible to select only the columns corresponding to the CROP AREA (e.g., the CROP column area), and the modulus conversion operation can be performed only on the columns corresponding to the CROP AREA. In this case, the comparator 210 ( Figure 3 Of the metal lines shown, only those corresponding to the CROP AREA can be activated, while those not included in the CROP AREA can be deactivated.

[0123] Figure 7B This is a diagram used to explain image processing in an exemplary embodiment of the concept according to the present invention.

[0124] The readout pixel is represented by four sub-pixels, where red, green, and blue are arranged clockwise in RGBG order from the top left. Figure 7B In all the drawings, the four sub-pixels arranged clockwise in RGBG order from the top left represent the color represented by the combination of RGB light when output to the display unit, and the actual implementation of the pixel array 110 of the image sensor 100 does not mean that the pixel array 110 consists of four sub-pixels.

[0125] The first image IMG1 corresponds to the result of the image sensor 100 capturing the object in full-resolution mode, and the second image IMG2 corresponds to the result of the image sensor 100 capturing the object in cropping mode. According to an exemplary embodiment of the present invention, among the plurality of comparators 210 included in the analog-to-digital converter array 130, a bias voltage may not be provided to the comparators 210 not included in the cropping region. Therefore, the power consumed by the comparators 210 that do not perform analog-to-digital conversion operations can be reduced.

[0126] Figure 8 This is a block diagram of an electronic device including a multi-camera module according to an exemplary embodiment of the present invention. Figure 9These are exemplary embodiments of the concept of the present invention. Figure 8 Detailed block diagram of the camera module.

[0127] Reference Figure 8 The electronic device 1000 may include a camera module group 1100, an application processor 1200, a power management integrated circuit (PMIC) 1300, and an external memory 1400.

[0128] Camera module group 1100 may include multiple camera modules 1100a, 1100b, and 1100c. Although Figure 8 An embodiment in which three camera modules 1100a, 1100b, and 1100c are arranged is shown, but the inventive concept is not limited thereto. In some embodiments of the inventive concept, the camera module group 1100 may be modified to include only two camera modules. Additionally, in some embodiments of the inventive concept, the camera module group 1100 may be modified to include n camera modules (n is a natural number greater than or equal to 4).

[0129] The following will refer to Figure 9 The construction of camera module 1100b is described in more detail, but the following description can be applied equally to other camera modules 1100a and 1100c.

[0130] Reference Figure 9 The camera module 1100b may include a prism 1105, an optical path folding element (hereinafter referred to as "OPFE") 1110, an actuator 1130, an image sensing device 1140, and a storage unit 1150.

[0131] The prism 1105 may include a reflective surface 1107 of light-reflecting material to modify the path of light L incident from the outside.

[0132] In some embodiments of the present invention, the prism 1105 can change the path of light L incident in the first direction X to a second direction Y perpendicular to the first direction X. Furthermore, by rotating the reflective surface 1107 of the light-reflecting material about the central axis 1106 in direction A, or by rotating the central axis 1106 in direction B, the prism 1105 can change the path of light L incident in the first direction X to a second direction Y perpendicular to the first direction X. In this case, the OPFE 110 can also move in a third direction Z perpendicular to the first direction X and the second direction Y.

[0133] In some embodiments of the present invention, as shown, the maximum rotation angle of the prism 1105 in the A direction may be 15 degrees or less in the positive (+) A direction and greater than 15 degrees in the negative (-) A direction, but the present invention is not limited thereto.

[0134] In some embodiments of the present invention, the prism 1105 can rotate approximately 20 degrees in the positive (+)B direction or the negative (-)B direction, or rotate between 10 and 20 degrees, or rotate between 15 and 20 degrees. Here, the rotation angle can be the same angle in the positive (+)B direction or the negative (-)B direction, or it can be a nearly similar angle within a range differing by approximately 1 degree.

[0135] In some embodiments of the present invention, the prism 1105 can move the reflective surface 1107 of the light-reflecting material in a third direction (e.g., the Z direction) parallel to the extension direction of the central axis 1106.

[0136] OPFE 1110 may include, for example, an optical lens consisting of m (where m is a natural number) lenses. The m lenses can be moved in the second direction Y to change the optical zoom ratio of camera module 1100b. For example, assuming the basic optical zoom ratio of camera module 1100b is Z, when the m optical lenses included in OPFE 1110 are moved, the optical zoom ratio of camera module 1100b can be changed to 3Z or 5Z, or 5Z or greater.

[0137] Actuator 1130 can move OPFE 1110 or optical lens (hereinafter referred to as optical lens) to a specific position. For example, actuator 1130 can adjust the position of optical lens so that image sensor 1142 is located at the focal length of optical lens for precise sensing.

[0138] Image sensing device 1140 may include image sensor 1142, control logic 1144, and memory 1146. Image sensor 1142 uses light L provided by an optical lens to sense an image of a target. Control logic 1144 can control the overall operation of camera module 1100b. For example, control logic 1144 can control the operation of camera module 1100b according to control signals provided through control signal line CSLb.

[0139] Memory 1146 may store information necessary for the operation of camera module 1100b, such as calibration data 1147. Calibration data 1147 may include information required by camera module 1100b to generate image data using light L provided externally. Calibration data 1147 may include, for example, information about rotation angle, information about focal length, and information about the optical axis, as described above. When camera module 1100b is implemented as a multi-state camera in which the focal length changes according to the position of the optical lens, calibration data 1147 may include focal length values ​​for each position (or state) of the optical lens and information related to autofocus.

[0140] Storage unit 1150 can store image data sensed by image sensor 1142. Storage unit 1150 can be disposed outside image sensing device 1140 and can be implemented on sensor chip constituting image sensing device 1140 in a stacked manner. In some embodiments of the present invention, storage unit 1150 can be implemented as electrically erasable programmable read-only memory (EEPROM), but the present invention is not limited thereto.

[0141] Refer to together Figure 8 and Figure 9 In some embodiments of the present invention, each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Therefore, each of the plurality of camera modules 1100a, 1100b, and 1100c may include the same or different calibration data 1147 depending on the operation of the included actuator 1130.

[0142] In some embodiments of the present invention, one of the multiple camera modules 1100a, 1100b and 1100c (e.g. 1100b) may be a folding lens type camera module including the aforementioned prism 1105 and OPFE 1110, while the remaining camera modules (e.g. 1100a and 1100c) may be vertical camera modules excluding the prism 1105 and OPFE 1110. However, the present invention is not limited thereto.

[0143] In some embodiments of the present invention, one of the multiple camera modules 1100a, 1100b, and 1100c (e.g., 1100c) may be, for example, a vertical depth camera for extracting depth information using infrared (IR) rays. In this case, the application processor 1200 can generate a three-dimensional (3D) depth image by merging image data provided from the depth camera and image data provided from another camera module (e.g., 1100a or 1100b).

[0144] In some embodiments of the present invention, at least two camera modules (e.g., 1100a, 1100b) of the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view from each other. In this case, for example, the optical lenses of at least two camera modules (e.g., 1100a, 1100b) of the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other, but the present invention is not limited thereto.

[0145] Furthermore, in some embodiments of the present invention, the viewing angle of each of the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other. In this case, the optical lenses included in each of the plurality of camera modules 1100a, 1100b, and 1100c may also be different, but are not limited thereto.

[0146] In some embodiments of the present invention, each of the plurality of camera modules 1100a, 1100b, and 1100c can be configured to be physically separate from each other. In other words, an independent image sensor 1142 can be provided within each of the plurality of camera modules 1100a, 1100b, and 1100c, instead of the plurality of camera modules 1100a, 1100b, and 1100c sharing the sensing area of ​​a single image sensor 1142.

[0147] Return to reference Figure 8 The application processor 1200 may include an image processor 1210, a memory controller 1220, and internal memory 1230. The application processor 1200 may be implemented separately from the multiple camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the multiple camera modules 1100a, 1100b, and 1100c may each be implemented as a separate semiconductor chip.

[0148] Image processor 1210 may include multiple sub-image processors 1212a, 1212b and 1212c, image generator 1214 and camera module controller 1216.

[0149] Multiple sub-image processors 1212a, 1212b and 1212c can correspond to the number of multiple camera modules 1100a, 1100b and 1100c.

[0150] Image data generated from each of camera modules 1100a, 1100b, and 1100c can be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c via image signal lines ISLa, ISLb, and ISLc, which are separate from each other. For example, image data generated from camera module 1100a can be provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b can be provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c can be provided to sub-image processor 1212c via image signal line ISLc. This image data transmission can be performed using, for example, a Camera Serial Interface (CSI) based on the Mobile Industry Processor Interface (MIPI), but the inventive concept is not limited thereto.

[0151] In some embodiments of the present invention, a sub-image processor can be arranged to correspond to multiple camera modules. For example, sub-image processors 1212a and 1212c may not be implemented separately as shown, but can be implemented by integration into a single sub-image processor, and image data provided from camera modules 1100a and 1100c can be selected by a selection device (e.g., a multiplexer) and then provided to the integrated sub-image processor.

[0152] Image data provided to each of the sub-image processors 1212a, 1212b, and 1212c can be provided to the image generator 1214. The image generator 1214 can generate an output image based on image generation (or production) information or pattern signals, using the image data provided from each of the sub-image processors 1212a, 1212b, and 1212c.

[0153] For example, image generator 1214 can generate an output image by merging at least some of the image data generated from camera modules 1100a, 1100b, and 1100c with different viewpoints, based on image generation information or a mode signal. Alternatively, image generator 1214 can generate an output image by selecting any one of the image data generated from camera modules 1100a, 1100b, and 1100c with different viewpoints, based on image generation information or a mode signal.

[0154] In some embodiments of the present invention, the image generation information may include a scaling signal or a scaling factor. Additionally, in some embodiments of the present invention, the mode signal may be, for example, a signal based on a user-selected mode.

[0155] When the image generation information is a zoom signal (e.g., zoom factor), and each camera module 1100a, 1100b, and 1100c has a different field of view (e.g., angle of view), the image generator 1214 can perform different operations depending on the type of zoom signal. For example, when the zoom signal is a first signal, the image generator 1214 can merge image data output from camera module 1100a and image data output from camera module 1100c, and then generate an output image by using the merged image signal and image data output from camera module 1100b, which is not used for merging. In the case where the zoom signal is a second signal different from the first signal, the image generator 1214 can generate an output image by selecting any one of the image data output from each of camera modules 1100a, 1100b, and 1100c without performing such image data merging. However, the inventive concept is not limited thereto, and the method for processing image data can be modified and implemented as needed.

[0156] In some embodiments of the present invention, the image generator 1214 may receive multiple image data with different exposure times from at least one of a plurality of sub-image processors 1212a, 1212b, and 1212c, and perform high dynamic range (HDR) processing on the plurality of image data. Through such processing, the image generator 1214 can generate merged image data with increased dynamic range.

[0157] The camera module controller 1216 can provide control signals to each of the camera modules 1100a, 1100b, and 1100c. The control signals generated from the camera module controller 1216 can be provided to the respective camera modules 1100a, 1100b, and 1100c via separate control signal lines CSLa, CSLb, and CSLc.

[0158] Any one of the multiple camera modules 1100a, 1100b, and 1100c can be designated as the master camera (e.g., 1100b) based on image generation information including zoom signals or mode signals, and the remaining camera modules (e.g., 1100a and 1100c) can be designated as slave cameras. Such information can be included in control signals and provided to the respective camera modules 1100a, 1100b, and 1100c via separate control signal lines CSLa, CSLb, and CSLc.

[0159] The camera module, operating as both a master and slave device, can change its operation based on the zoom factor or operating mode signal. For example, when the field of view of camera module 1100a is wider than that of camera module 1100b and the zoom factor indicates a low zoom ratio, camera module 1100b can operate as the master device, and camera module 1100a can operate as the slave device. Conversely, when the zoom factor indicates a high zoom ratio, camera module 1100a can operate as the master device, and camera module 1100b can operate as the slave device.

[0160] In some embodiments of the present invention, the control signals provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, when camera module 1100b is the main camera and camera modules 1100a and 1100c are the slave cameras, the camera module controller 1216 may transmit the synchronization enable signal to camera module 1100b. Camera module 1100b, receiving the synchronization enable signal, may generate a synchronization signal based on the received synchronization enable signal and provide the generated synchronization signal to camera modules 1100a and 1100c via the synchronization signal line SSL. The synchronization signal can be used to synchronize camera module 1100b and camera modules 1100a and 1100c to transmit image data to application processor 1200.

[0161] In some embodiments of the present invention, the control signals provided from the camera module controller 1216 to the plurality of camera modules 1100a, 1100b, and 1100c may include mode information dependent on the mode signal. Based on the mode information, the plurality of camera modules 1100a, 1100b, and 1100c may operate in a first operating mode and a second operating mode in relation to the sensing rate.

[0162] In the first operating mode, multiple camera modules 1100a, 1100b, and 1100c can generate image signals at a first rate (e.g., at a first frame rate), encode the image signals at a second rate higher than the first rate (e.g., at a second frame rate higher than the first frame rate), and send the encoded image signals to the application processor 1200. In this case, the second rate can be 30 times or less than 30 times the first rate.

[0163] Application processor 1200 can store the received image signal (in other words, the encoded image signal) in memory 1230 or external memory 1400 located outside application processor 1200, then read the encoded image signal from memory 1230 or external memory 1400 and decode it, and display image data generated based on the decoded image signal. For example, a corresponding sub-image processor among the plurality of sub-image processors 1212a, 1212b and 1212c of image processor 1210 can perform decoding and can also perform image processing on the decoded image signal.

[0164] In the second operating mode, multiple camera modules 1100a, 1100b, and 1100c can generate image signals at a third rate lower than the first rate, for example, at a third frame rate lower than the first frame rate, and send the image signals to the application processor 1200. The image signals provided to the application processor 1200 can be unencoded signals. The application processor 1200 can perform image processing on the received image signals or store the image signals in memory 1230 or external memory 1400.

[0165] PMIC 1300 can supply power (e.g., power supply voltage) to each of a plurality of camera modules 1100a, 1100b, and 1100c. For example, under the control of application processor 1200, PMIC 1300 can supply a first power to camera module 1100a via power signal line PSLa, a second power to camera module 1100b via power signal line PSLb, and a third power to camera module 1100c via power signal line PSLc.

[0166] The 164PMIC 1300 can generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c in response to a power control signal PCON from the application processor 1200, and also adjust the power level. The power control signal PCON can include a power regulation signal for each operating mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operating mode can include a low-power mode, and in this case, the power control signal PCON can include information about the camera module operating in the low-power mode and the set power level. The power levels supplied to each of the plurality of camera modules 1100a, 1100b, and 1100c can be the same or different from each other. Furthermore, the power levels can be changed dynamically.

[0167] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made to the inventive concept without departing from the spirit and scope of the inventive concept set forth in the appended claims.

Claims

1. An image sensor supporting full-resolution mode and cropping mode, the image sensor comprising: A pixel array comprising a plurality of pixels configured to generate pixel signals by sensing an object; An analog-to-digital converter configured to convert the pixel signal into a digital signal, and comprising multiple metal lines; A bias generator configured to apply a bias voltage to the plurality of metal lines; as well as Bias controller, comprising: A first transistor has one end connected between the plurality of metal lines and the bias generator, and is configured to activate all of the plurality of metal lines based on a first control signal. as well as The second transistor has one end connected between the first metal line and the first transistor, and is configured to deactivate the first metal line among the plurality of metal lines based on a second control signal in the cutting mode.

2. The image sensor according to claim 1, further comprising: A first switch is located between the first transistor and the second transistor.

3. The image sensor according to claim 2, wherein, The full-resolution mode corresponds to the inactive state of the first transistor and the second transistor, as well as the short-circuited state of the first switch.

4. The image sensor according to claim 2, wherein, The cutting mode corresponds to the inactive state of the first transistor, the active state of the second transistor, and the open state of the first switch.

5. The image sensor according to claim 2, wherein, The image sensor also supports a power-saving mode. The power-saving mode corresponds to the active state of the first transistor and the active state of the second transistor or the short-circuited state of the first switch.

6. The image sensor according to claim 1, wherein, The first transistor and the second transistor include N-type metal-oxide-semiconductor field-effect transistors.

7. The image sensor according to claim 1, wherein, In the full-resolution mode, both the first control signal and the second control signal are at a first logic level.

8. The image sensor according to claim 1, wherein, In the trimming mode, the first control signal is at a first logic level, and the second control signal is at a second logic level that is the opposite of the first logic level.

9. The image sensor according to claim 1, wherein, In the full-resolution mode, the bias voltage is applied to all of the plurality of metal lines.

10. The image sensor according to claim 1, wherein, In the cutting mode, a bias voltage is provided to the remaining metal wires of the plurality of metal wires, excluding the first metal wire, and A ground voltage is provided to the first metal wire.

11. The image sensor according to claim 1, wherein, The image sensor also supports a power-saving mode. In the power-saving mode, a ground voltage is applied to all of the multiple metal wires.

12. An analog-to-digital converter configured to convert pixel signals sensed at pixels into digital signals, the analog-to-digital converter comprising: A comparator including a first metal line and a second metal line activated according to a bias voltage, the comparator being configured to generate a comparison signal by comparing the pixel signal with a ramp signal based on the bias voltage; A counter configured to generate a digital signal by counting the comparison signal based on a clock signal; as well as A first transistor and a second transistor are configured to determine the path of the bias voltage applied to the first metal line and the second metal line. Wherein, one end of the first transistor is connected between the first metal line and the second metal line and the bias generator for generating the bias voltage, and one end of the second transistor is connected between the second metal line and the first transistor.

13. The analog-to-digital converter according to claim 12, wherein, The first transistor is configured to determine whether the bias voltage is applied to the first metal line and the second metal line.

14. The analog-to-digital converter according to claim 12, wherein, The analog-to-digital converter is configured to support a cutting mode for activating at least one of the first and second metal wires, and The first transistor is configured to determine whether to apply the bias voltage to the first metal line used for the cutting mode.

15. The analog-to-digital converter according to claim 14, wherein, In the trimming mode, a first control signal for controlling the first transistor is at a first logic level, and a second control signal for controlling the second transistor is at a second logic level that is opposite to the first logic level.

16. The analog-to-digital converter according to claim 12, further comprising: A first switch is located between the first transistor and the second transistor.

17. The analog-to-digital converter according to claim 16, wherein, The analog-to-digital converter supports cutting modes for activating at least one of the first and second metal wires, and The cutting mode corresponds to the inactive state of the first transistor, the active state of the second transistor, and the open state of the first switch.

18. The analog-to-digital converter according to claim 16, wherein, The analog-to-digital converter supports a power-saving mode for deactivating the first and second metal lines, and The power-saving mode corresponds to any two of the following states: the active state of the first transistor, the active state of the second transistor, and the short-circuited state of the first switch.

19. The analog-to-digital converter according to claim 12, wherein, The analog-to-digital converter supports cutting modes for activating at least one of the first and second metal wires, and In the cutting mode, the bias voltage is provided to the first metal wire, and A ground voltage is provided to the second metal wire.

20. An image sensor supporting full-resolution mode and cropping mode, the image sensor comprising: A pixel array comprising a plurality of pixels configured to generate pixel signals by sensing an object; An analog-to-digital converter array includes multiple analog-to-digital converters, each configured to convert the pixel signal into a digital signal, the analog-to-digital converter array including multiple metal lines commonly connected to the multiple analog-to-digital converters; A bias generator configured to apply a bias voltage to the plurality of metal lines; as well as A bias controller is configured to determine the path to apply the bias voltage to the plurality of metal lines. The bias controller includes a first transistor and a second transistor. One end of the first transistor is connected between the plurality of metal lines and the bias generator, and is configured to activate all of the plurality of metal lines based on a first control signal. One end of the second transistor is connected between the first metal line and the first transistor, and is configured to deactivate the first metal line among the plurality of metal lines based on a second control signal in the trimming mode. as well as An output buffer is configured to output the digital signal.

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