Display panel, preparation method thereof and display device

Abstract

The present disclosure belongs to the technical field of display, and relates to a display panel, a preparation method thereof and a display device. The display panel comprises a first substrate and a second substrate arranged oppositely, a transistor formed on the first substrate, and an organic insulating layer formed on the first substrate and covering the transistor, wherein the organic insulating layer comprises a first organic insulating part and a second organic insulating part, the first organic insulating part covers a wiring area, the second organic insulating part covers a sub-pixel area, the thickness of the first organic insulating part is greater than the thickness of the second organic insulating part, a spacer is formed on the side of the second substrate facing the first substrate, and the orthographic projection of the spacer on the first substrate is located in the orthographic projection of the first organic insulating part on the first substrate. The scheme increases the relative distance from the lower surface of the spacer to the pixel area of the array substrate, and avoids the spacer from being pressed and tilted to the pixel area to damage the film layer of the pixel area.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] Liquid crystal display (LCD) panels are an important type of flat panel display device, widely used in mobile phones, automotive displays, monitors, televisions, and public displays. The market demand for large-size LCD panels is also increasing. Currently, LCD panels have problems such as low transmittance and easy light leakage after impact. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display panel and its manufacturing method, as well as a display device, thereby overcoming, to at least to some extent, one or more problems caused by the limitations and defects of related technologies.

[0004] This disclosure provides a display panel, including an array substrate and a mating substrate disposed opposite to each other, wherein the array substrate includes:

[0005] The first substrate (10) includes a sub-pixel region and a wiring region disposed around the sub-pixel region;

[0006] A transistor (11) is disposed on the first substrate (10) and located in the wiring area;

[0007] An organic insulating layer (12) is formed on the first substrate (10) and includes a first organic insulating portion (120) and a second organic insulating portion (121). The first organic insulating portion (120) covers the wiring area and the transistor (11), and the second organic insulating portion (121) covers the sub-pixel area. The thickness of the first organic insulating portion (120) is greater than the thickness of the second organic insulating portion (121).

[0008] The mating substrate includes:

[0009] A second substrate (20) is disposed opposite to the first substrate (10);

[0010] A spacer (13) is formed on the side of the second substrate (20) facing the first substrate (10), and the orthographic projection of the spacer (13) on the first substrate (10) lies within the orthographic projection of the first organic insulating portion (120) on the first substrate (10).

[0011] In one exemplary embodiment of this disclosure, the display panel includes a plurality of spacers (13), wherein the spacers (13) are main spacers (1301) or auxiliary spacers (1302), and in the thickness direction of the display panel, the height of the main spacer (1301) is greater than the height of the auxiliary spacer (1302).

[0012] The height difference ΔH between the surfaces of the first organic insulating portion (120) and the second organic insulating portion (121) away from the first substrate is greater than the height difference ΔH between the main spacer (1301) and the auxiliary spacer (1302). ps .

[0013] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0014] Scan lines (17) are disposed on the first substrate (10) and arranged in the wiring area along the row direction;

[0015] Data lines (16) are disposed on the first substrate (10) and arranged in the wiring area along the column direction;

[0016] A common line (18) is disposed on the first substrate (10) and arranged in the wiring area along the row direction;

[0017] The pixel electrode (14) and the common electrode (15) are both disposed on the first substrate (10), and the common electrode (15) is electrically connected to the common line (18);

[0018] The transistor (11) includes a gate, a first electrode, and a second electrode. The gate is electrically connected to the scan line (17), the first electrode is electrically connected to the data line (16), and the second electrode is electrically connected to the pixel electrode (14).

[0019] The scan line (17), data line (16), common line (18), and transistor (11) are all located on the side of the organic insulating layer (12) facing the first substrate (10), and the pixel electrode (14) and common electrode (15) are all located on the side of the organic insulating layer (12) away from the first substrate (10).

[0020] In one exemplary embodiment of this disclosure, the first organic insulating portion (120) covers the transistor (11), and the orthographic projection of the spacer (13) on the first substrate (10) covers the orthographic projection of the transistor (11) on the first substrate (10).

[0021] In one exemplary embodiment of this disclosure, the first organic insulating portion (120) covers the common line (18), and the orthographic projection of the spacer (13) on the first substrate (10) covers a portion of the orthographic projection of the common line (18) on the first substrate (10).

[0022] In one exemplary embodiment of this disclosure, the first organic insulating portion (120) covers the data line (16) and the scan line (17), and the orthographic projection of the spacer (13) on the first substrate (10) covers a portion of the orthographic projection of the data line (16) and / or a portion of the scan line (17) on the first substrate (10).

[0023] In one exemplary embodiment of this disclosure, the ratio of the thickness of the first organic insulating portion (120) to the thickness of the second organic insulating portion (121) is 2 to 4.

[0024] In one exemplary embodiment of this disclosure, the thickness of the first organic insulating portion (120) is 2 μm to 4 μm; the thickness of the second organic insulating portion (121) is less than 2 μm.

[0025] In one exemplary embodiment of this disclosure, the thickness of the second organic insulating portion (121) is 0.

[0026] In one exemplary embodiment of this disclosure, the first substrate (10) includes a plurality of sub-pixel regions arranged in an array along the row direction and the column direction, and the spacer (13) is disposed between two adjacent sub-pixel regions in the column direction;

[0027] In each of the three adjacent columns of the sub-pixel areas, at least one column is provided with the spacer (13), and in the column where the spacer (13) is provided, there is a spacer (13) between any two adjacent sub-pixel areas.

[0028] In one exemplary embodiment of this disclosure, the plurality of spacers (13) includes a plurality of main spacers (1301) and a plurality of auxiliary spacers (1302), wherein the number of auxiliary spacers (1302) is greater than the number of main spacers (1301);

[0029] In each of the three adjacent columns of the sub-pixel regions, at least one column contains all the spacers (13) that are the auxiliary spacers (1302).

[0030] In one exemplary embodiment of this disclosure, the projection of the spacer (13) onto the first substrate (10) is rectangular, circular, or elliptical.

[0031] In one exemplary embodiment of this disclosure, the distance between the projection of the spacer (13) on the first substrate (10) and the edge of the adjacent sub-pixel region is 15-50 μm.

[0032] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0033] A color resist layer (101) is disposed on the first substrate (10) and located on the side of the organic insulating layer (12) close to the first substrate (10). The color resist layer covers the sub-pixel area and at least part of the wiring area.

[0034] In one exemplary embodiment of this disclosure, the color resist layer (101) has an opening (1010) in the wiring area, the organic insulating layer (12) is recessed at the opening of the color resist layer, and the projection of the spacer (13) on the first substrate (10) is located within the projection of the opening (1010) on the first substrate (10).

[0035] In one exemplary embodiment of this disclosure, both the common electrode (15) and the pixel electrode (14) are located on the side of the organic insulating layer (12) away from the first substrate (10);

[0036] The pixel electrode (14) has a plurality of first electrode strips spaced apart in the row direction;

[0037] The common electrode (15) is disposed on the same layer as the pixel electrode (14). The common electrode (15) has a plurality of second electrode strips arranged at intervals in the row direction. The second electrode strips and the first electrode strips are arranged alternately in the row direction, and there is a gap between the second electrode strips and the first electrode strips. The common electrode (15) is connected to the common line (18) through a via.

[0038] In one exemplary embodiment of this disclosure, the array substrate further includes:

[0039] A liquid crystal layer is disposed between the array substrate and the mating substrate;

[0040] A first alignment layer (102) is disposed on the first substrate (10) and covers the side of the common electrode (15) and pixel electrode (14) away from the first substrate (10);

[0041] A second alignment layer (22) is disposed on the second substrate (20) and located between the spacer (13) and the second substrate (20).

[0042] A second aspect of this disclosure provides a method for manufacturing a display panel, comprising:

[0043] A first substrate is provided, the first substrate being divided into a sub-pixel region and a wiring region disposed around the sub-pixel region;

[0044] A transistor is formed in the wiring region of the first substrate;

[0045] An organic insulating layer is formed on the first substrate. The organic insulating layer includes a first organic insulating portion and a second organic insulating portion, such that the first organic insulating portion covers the wiring area and the transistor, and the second organic insulating portion covers the sub-pixel area; wherein the thickness of the first organic insulating portion is greater than the thickness of the second organic insulating portion.

[0046] Provide a second substrate;

[0047] A spacer is formed on the side of the second substrate facing the first substrate, such that the orthographic projection of the spacer on the first substrate lies within the orthographic projection of the first organic insulating portion on the first substrate.

[0048] In one exemplary embodiment of this disclosure, forming an organic insulating layer includes:

[0049] An organic insulating material is coated on a first substrate on which the transistor is formed;

[0050] The organic insulating material is exposed and developed using a halftone mask or a grayscale mask, so that the thickness of the organic insulating material in the sub-pixel area is less than the thickness of the organic insulating material in the wiring area.

[0051] A third aspect of this disclosure provides a display device including the display panel described above.

[0052] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0053] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0054] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0055] Figure 1 A cross-sectional view showing structural variations of a display panel in related technologies is shown;

[0056] Figure 2 A top view of the first type of display panel of this disclosure is shown;

[0057] Figure 3 The first type of display panel is shown. Figure 2 Cross-sectional views at points A-A' and B-B';

[0058] Figure 4 A top view of the second type of display panel of this disclosure is shown;

[0059] Figure 5 The second type of display panel is shown. Figure 4 Cross-sectional views at points A-A' and B-B';

[0060] Figure 6 A top view of the third type of display panel of this disclosure is shown;

[0061] Figure 7 The third type of display panel is shown. Figure 6 Cross-sectional views at points A-A' and B-B';

[0062] Figure 8 A top view of the fourth type of display panel of this disclosure is shown;

[0063] Figure 9 The fourth type of display panel is shown. Figure 8 Cross-sectional views at points A-A' and B-B';

[0064] Figure 10 A top view of the fifth type of display panel of this disclosure is shown;

[0065] Figure 11 A schematic diagram of the arrangement of the spacers disclosed herein is shown;

[0066] Figure 12 A schematic diagram of the structure of the main septum and the auxiliary septum of this disclosure is shown.

[0067] Explanation of reference numerals in the attached figures:

[0068] 10. First substrate; 11. Transistor; 110. First electrode; 111. Second electrode; 112. Active layer; 114. Passivation layer; 12. Organic insulating layer; 120. First organic insulating portion; 121. Second organic insulating portion; 13. Spacer; 1301. Main spacer; 1302. Secondary spacer; 14. Pixel electrode; 15. Common electrode; 16. Data line; 17. Scan line; 18. Common line; 19. Gate insulating layer; 101. Color resist layer; 1010. Opening; 102. First alignment layer;

[0069] 20. Second substrate; 21. Masking layer; 22. Second alignment layer; 23. Protective layer; Detailed Implementation

[0070] The technical solutions of this disclosure will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of this disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of this disclosure and should not be construed as a limitation thereof.

[0071] Furthermore, in the following detailed description, numerous specific details are set forth for ease of explanation to provide a thorough understanding of the embodiments disclosed herein. However, it will be apparent that one or more embodiments may be practiced without these specific details.

[0072] In related technologies, the main development trend of TFT-LCD liquid crystal panels is high resolution and high transmittance. (Reference) Figure 1 Liquid crystal display panels are mainly composed of a thin-film transistor array substrate, a mating substrate, a liquid crystal layer disposed between the two substrates, and columnar spacers (PS). The columnar spacers 13 are made of a resin with a certain degree of elasticity, serving as support and buffer, and maintaining the optimal liquid crystal layer thickness by controlling the gap between the two substrates. However, during the cell assembly process and subsequent use, existing liquid crystal display panels inevitably experience external pressure. When the external force is excessive, the spacers 13 slide, scratching the alignment film of the display area on the array substrate, resulting in a loss of alignment liquid crystal capability. For high-resolution products, the width of the black matrix is ​​very small and cannot cover the scratches on the alignment film. In dark scenes, light leakage occurs at the scratches, forming "spot-like" defects.

[0073] "Spot-like" defects not only severely affect display quality but also reduce the yield rate of LCD panels and increase production costs. Common solutions include increasing the number of spacers, changing their position and shape, and increasing the width of the black matrix. However, these methods are not very effective for high-resolution products, defects still occur frequently, and they also reduce the transmittance of the LCD panel.

[0074] This is a schematic diagram of a stress model for a liquid crystal panel. When the liquid crystal panel is subjected to excessive oblique pressure or impact, the spacer PS slides to the pixel area of ​​the array substrate. The maximum length of the spacer that slides out in the thickness direction of the display panel is H. shift The varying thickness of the organic protective film at different locations creates a height difference, increasing the relative height ΔH between the lower surface of the septum and the upper surface of the display area film, making ΔH greater than H. shift This causes the spacer PS to slip and fail to contact the TFT side substrate.

[0075] To address the aforementioned problems, this disclosure provides a display panel that can be applied to a display device, specifically a liquid crystal display device. (Reference) Figure 2 and Figure 3 The display panel of this embodiment may include a first substrate 10, sub-pixel units, an organic insulating layer 12, a second substrate, and spacers 13. Each sub-pixel unit may include at least one transistor 11, which may be formed on the first substrate 10. The organic insulating layer 12 may be formed on the first substrate 10 and cover the transistor 11. The organic insulating layer 12 includes a first organic insulating portion 120 and a second organic insulating portion 121. The first organic insulating portion 120 covers the wiring area and the transistor 11, and the second organic insulating portion 121 covers the sub-pixel area. The thickness of the first organic insulating portion 120 is greater than the thickness of the second organic insulating portion 121. The second substrate 20 is correspondingly disposed to the first substrate 10. The spacers 13 may be formed on the side of the second substrate 20 facing the first substrate 10, and the orthographic projection of the spacers 13 on the first substrate 10 lies within the orthographic projection of the first organic insulating portion 120 on the first substrate. In the embodiments of this disclosure, by using an organic insulating material, namely an organic insulating layer 12, to cover the transistor 11, compared to using an inorganic material such as silicon nitride to cover the transistor 11, the flatness of the array substrate 1 side can be improved, so that the spacer 13 can occupy the array substrate 1.

[0076] Meanwhile, the thickness of the organic insulating layer 12 in the wiring area is greater than that in the pixel area. When the spacer 13 abuts against the wiring area of ​​the array substrate, it can increase the relative height ΔH between the lower surface of the spacer and the upper surface of the sub-pixel area film layer of the array substrate, making ΔH greater than H. shift This causes the spacer PS to slip and fail to contact the TFT side substrate, thereby reducing the risk of the spacer shifting to the sub-pixel area and scratching the sub-pixel film layer when subjected to pressure. This can effectively solve the spot defects in the liquid crystal panel and improve the redundancy of the product manufacturing and use.

[0077] Furthermore, due to the increased relative height, the lateral dimension (PS Shift) occupied by the spacers after offset is reduced, eliminating the need for the mating substrate to block the PS Shift area. This allows for further reduction in the width of the black matrix, thereby improving the panel's aperture ratio and transmittance. Moreover, the thinner organic insulating layer in the sub-pixel area of ​​the array substrate mitigates backlight intensity loss to some extent, improves contrast, and reduces lens mura sensitivity in the exposure machine, thus enhancing display quality.

[0078] In the embodiments of this disclosure, the sub-pixel unit may include a common electrode 15 and a pixel electrode 14 in addition to the aforementioned transistor 11; and the array substrate 1 may include a scan line 17, a data line 16 and a common line 18 in addition to the aforementioned first substrate 10, sub-pixel unit and organic insulating layer 12.

[0079] The array substrate 1 of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0080] In embodiments of this disclosure, such as Figure 2 As shown, the first substrate 10 may have a plurality of sub-pixel regions A2, a plurality of rows of first wiring regions A1, and a plurality of columns of second wiring regions A3 arranged in an array along the row direction X and the column direction Y. The first wiring regions A1 and the sub-pixel regions A2 are arranged alternately in the column direction Y, and the second wiring regions A3 and the sub-pixel regions A2 are arranged alternately in the row direction X. It should be understood that there is an overlap between the first wiring regions A1 and the second wiring regions A3.

[0081] For example, the first substrate 10 may be a single-layer structure, and the material of the first substrate 10 may be glass; but it is not limited to this, the first substrate 10 may also be a multi-layer structure; and the material of the first substrate 10 is not limited to glass, but may also be other materials, such as polyimide (PI) and other materials, depending on the specific circumstances.

[0082] In embodiments of this disclosure, such as Figure 2 As shown, the scan line 17 can extend in the row direction X. This scan line 17 can be located in the first wiring area A1 and is used to provide scan signals for the sub-pixel units. For example, multiple rows of scan lines 17 can be set, wherein one row of scan lines 17 can be set on each first wiring area A1, but it is not limited to this, and two or more rows of scan lines 17 can also be set.

[0083] In embodiments of this disclosure, such as Figure 2 As shown, the common line 18 can extend in the row direction X. This common line 18 can be located in the first wiring area A1 and is used to provide a common signal for the sub-pixel unit. For example, the common line 18 can be set in multiple rows, wherein one row of common line 18 can be set in each first wiring area A1, but it is not limited to this, and two or more rows of common lines 18 can also be set.

[0084] Common line 18 and scan line 17 can be arranged on the same layer to simplify the process and reduce costs. It should be noted that, as... Figure 2 As shown, in each first wiring area A1, the orthographic projection of the common line 18 on the first substrate 10 and the orthographic projection of the scan line 17 on the first substrate 10 do not overlap and are spaced apart from each other. That is, the orthographic projection of the common line 18 on the first substrate 10 and the orthographic projection of the gate of the transistor 11 on the first substrate 10 do not overlap.

[0085] Furthermore, it should be understood that in this disclosure, "same-layer setup" refers to a layer structure formed using the same film deposition process to create a film layer for forming a specific pattern, and then using the same mask to form a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0086] For example, the common line 18 and scan line 17 of this embodiment may be made of metal or alloy materials, such as molybdenum, aluminum and titanium, to ensure good conductivity. However, they are not limited to this and may also be made of other materials with good conductivity.

[0087] In embodiments of this disclosure, such as Figure 2 As shown, the data line 16 can extend in the column direction Y. This data line 16 can be located in the second wiring area A3 to provide data signals to the sub-pixel unit. For example, the data line 16 can be arranged in multiple columns, wherein one row of data line 16 can be arranged on each second wiring area A3, but it is not limited to this, and two or more rows of data lines 16 can also be arranged.

[0088] For example, the data line 16 may be located on the side of the scan line 17 and the common line 18 away from the first substrate 10, and a gate insulating layer 19 is disposed between the data line 16 and the scan line 17 and the common line 18, such as... Figure 2 As shown, to avoid contact between data line 16 and scan line 17 and common line 18, data line 16 may be made of metal or alloy material, such as a single-layer or multi-layer metal structure formed by molybdenum, aluminum and titanium, etc., wherein the multi-layer structure is a multi-metal stack, such as a titanium, aluminum and titanium three-layer metal stack (Ti / Al / Ti), etc.

[0089] It should be understood that the gate insulating layer 19 mentioned in the embodiments of this disclosure can be disposed on the array substrate 1 in its entirety. This gate insulating layer 19 can be made of inorganic materials, such as silicon oxide, silicon nitride, and other inorganic materials.

[0090] In the embodiments of this disclosure, multiple sub-pixel units can be arranged in an array along the row direction X and the column direction Y. Only two sub-pixel units arranged along the X direction are shown in the figure. Each sub-pixel unit corresponds one-to-one with a sub-pixel region A2, that is, each sub-pixel unit is correspondingly disposed on a sub-pixel region A2. Specifically, at least a portion of the common electrode 15 and the pixel electrode 14 of each sub-pixel unit are located on a sub-pixel region A2, and at least a portion of the transistor 11 of each sub-pixel unit can be located in the first wiring region A1.

[0091] like Figure 2 and Figure 3 As shown, transistor 11 may include an active layer 112, a gate, and a second electrode 111 and a first electrode 110 disposed on the same layer. A gate insulating layer 19 may be disposed between the gate and the active layer 112 to insulate the gate from the active layer 112. The thickness of the gate insulating layer 19 may be about 0.4 μm, but is not limited thereto. For example, in this embodiment, the gate may be disposed on the same layer as the aforementioned scan line 17 and interconnected with it. In other words, the gate may be a part of the structure of the aforementioned scan line 17. The second electrode 111 and the first electrode 110 may be connected to the source doped region and the drain doped region of the active layer 112, respectively.

[0092] The second electrode 111 and the first electrode 110 can be arranged on the same layer as the aforementioned data line 16 to simplify the process and reduce costs.

[0093] For example, the transistor 11 in the embodiments of this disclosure may be a bottom-gate type, that is: the gate may be formed on the first substrate 10 first; then, a gate insulating layer 19 may be formed on the first substrate 10, which covers the gate; then, an active layer 112 may be formed on the side of the gate insulating layer 19 away from the first substrate 10, that is: the active layer 112 is located on the side of the gate away from the first substrate 10, and the active layer 112 overlaps with the orthographic projection of the gate on the first substrate 10. For example, the orthographic projection of the active layer 112 on the first substrate 10 may be located within the orthographic projection of the gate on the first substrate 10; the second electrode 111 and the first electrode 110 may be formed after the active layer 112 is formed, a part of the first electrode 110 may overlap the drain doped region of the active layer 112, and another part of the first electrode 110 may be located on the sub-pixel region A2 to be connected to the pixel electrode 14; a part of the second electrode 111 may overlap the source doped region of the active layer 112, and another part of the second electrode 111 may be connected to the data line 16. A passivation layer 114 covers the first electrode 110 and the second electrode 111.

[0094] It should be noted that the transistor 11 in this embodiment is not limited to the bottom-gate type mentioned above, but can also be a top-gate type, that is, the gate is formed after the active layer 112 is formed and before the second electrode 111 and the first electrode 110 are formed. It should be understood that a gate insulating layer 19 is formed between the gate and the active layer 112 and between the gate and the first (second) electrode. When the transistor 11 is a top-gate type, the second electrode 111 and the first electrode 110 can be connected to the opposite ends of the active layer 112 through a transition via, that is, a transition via that penetrates the two layers of gate insulating layers 19.

[0095] In one implementation, such as Figure 3As shown, after forming transistor 11, a color resist layer 101 with red, green, and blue color resist blocks can be formed on transistor 11. The color resist layer 101 covers the sub-pixel area and the wiring area. This technology is called COA technology, which is an integration technology that directly fabricates the color filter layer on the array substrate. By placing the color filter layer and the TFT array on the same side, it can effectively solve the misalignment caused by the alignment in the cell assembly process of the liquid crystal display device. The black matrix design of the COA structure further reduces the width, improves the aperture ratio of the liquid crystal display panel, and significantly improves the transmittance. Of course, the color resist layer 101 can also be formed on the mating substrate.

[0096] After the color resist layer 101 is formed, the aforementioned organic insulating layer 12 can be formed. This organic insulating layer 12 is disposed on the first substrate 10 and covers the aforementioned color resist layer 101, active layer 112, second electrode 111, first electrode 110, data line 16, scan line 17 and common line 18, etc.

[0097] When fabricating the organic insulating layer 12, at least two organic insulating portions of different thicknesses need to be fabricated, such as a first organic insulating portion 120 and a second organic insulating portion 121. The orthographic projection of the first organic insulating portion 120 on the first substrate 10 covers the orthographic projection of the transistor 11 on the first substrate 10; the orthographic projection of the second organic insulating portion 121 on the first substrate 10 covers the orthographic projections of the pixel electrode 14 and the common electrode 15 on the first substrate 10; wherein, the thickness H1 of the first organic insulating portion 120 is greater than the thickness H2 of the second organic insulating portion 121.

[0098] For example, the ratio of the thickness H1 of the first organic insulating portion 120 to the thickness H2 of the second organic insulating portion 121 can be 2 to 4, such as 2, 2.5, 3, 3.5, 4, etc. The thickness H1 of the first organic insulating portion 120 can be 1 μm to 3 μm, such as 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc.; the thickness H2 of the second organic insulating portion 121 can be 0.8 μm to 1.5 μm, such as 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, etc.

[0099] For another example, the thickness of the second organic insulating portion 121 can also be 0, that is, the second organic insulating portion 121 is not provided in the sub-pixel area. This can maximize the relative distance between the lower surface of the spacer 13 and the sub-pixel area, and prevent the spacer 13 from laterally scratching the film layer of the sub-pixel area. Moreover, reducing the film layer in the sub-pixel area is beneficial to reducing light intensity loss and improving the transmittance of the panel.

[0100] It should be noted that, in order to achieve different thicknesses in the organic insulating layer 12, either HTM (Half-Tone Mask) or GTM (Grey Tone Mask) processes can be used to fabricate the organic insulating layer 12. The thicknesses of the first organic insulating portion 120 and the second organic insulating portion 121 can be achieved by controlling process parameters. In the embodiments of this disclosure, combined with Figure 2 and Figure 3 The pixel electrode 14 and common electrode 15 of each sub-pixel unit are both located on the first substrate 10, and at least a portion of the pixel electrode 14 and common electrode 15 in each sub-pixel unit are located within a sub-pixel region A2. The orthographic projection of the pixel electrode 14 onto the first substrate 10 partially overlaps with the orthographic projection of the common electrode 15 onto the first substrate 10, and the pixel electrode 14 is connected to the first electrode 110 of the transistor 11. Specifically, one of the pixel electrode 14 and the common electrode 15 is located on the side of the organic insulating layer 12 closer to the first substrate 10, and the other is located on the side of the organic insulating layer 12 away from the first substrate 10.

[0101] For example, in this embodiment of the present disclosure, both the common electrode 15 and the pixel electrode 14 can be located on the side of the organic insulating layer 12 away from the first substrate 10. That is, the organic insulating layer 12 is first formed on the first substrate 10, and then the pixel electrode 14 and the common electrode 22 are formed. The pixel electrode 14 can be connected to the first electrode 110 of the transistor 11 through a via structure (not shown in the figure) on the organic insulating layer 12, and the common electrode 22 can be connected to the common line through a via structure (not shown in the figure) on the organic insulating layer 12.

[0102] In this embodiment, both the common electrode 15 and the pixel electrode 14 are transparent electrodes, which can be made of ITO (indium tin oxide) material, but are not limited to this, and can also be made of transparent materials such as indium zinc oxide (IZO) and zinc oxide (ZnO).

[0103] like Figure 2 As shown, the pixel electrode 14 may have a plurality of first electrode strips arranged at intervals in the row direction X, and these first electrode strips may be disposed on the sub-pixel area A2; it should be understood that the ends of each first electrode strip located on the same side may be connected to each other, so that the pixel electrode as a whole has a shape similar to a "comb".

[0104] The first electrode strip can be bent as a whole, with a bending angle α1 of 150° to 170°. Specifically, the first electrode strip can include two parts, with the included angle α1 between the two parts being 150° to 160°, such as 150°, 156°, 162°, 166°, 170°, etc. In other words, the included angles α2 and α3 between the extension direction of the two parts and the column direction Y are 5° to 15°, such as 5°, 7°, 9°, 12°, 15°, etc.

[0105] like Figure 2 and Figure 3 As shown, the common electrode 22 can be disposed in the same layer as the pixel electrode 14; for example, the aforementioned common electrode 22 and pixel electrode 14 can be transparent electrodes, and the common electrode 22 and pixel electrode 14 can be made of ITO (indium tin oxide) material, but are not limited to this, and can also be made of materials such as IZO (indium zinc oxide). It should be understood that there is a gap between the common electrode 22 and the pixel electrode 14 (i.e., they do not contact each other).

[0106] like Figure 2 As shown, the common electrode 22 can also be configured in a comb-like shape, that is, it includes multiple second electrode strips arranged at intervals in the row direction X. These second electrode strips can be located in the sub-pixel area A2; and the ends of each second electrode strip 220 on the same side are connected to each other. Thus, the sub-pixel electrode and the common electrode 22 can be in an interlocking state. That is, the array substrate of this embodiment can be in IPS (In-Plane Switching) mode. This design can reduce the parasitic capacitance generated between the sub-pixel electrode and the common electrode, thereby improving the pixel charging rate and aperture ratio. However, it is not limited to this. The common electrode 22 and the pixel electrode 14 can also be located in different layers of the array substrate and arranged opposite to each other. One of the common electrode 22 and the pixel electrode 14 is a slit electrode with a gap, and the other is a plate electrode without a gap. That is, the array substrate of this embodiment can also be in FFS (Fringe Field Switching) mode, depending on the specific situation.

[0107] It should be noted that the common electrodes 22 of each sub-pixel can be connected to each other to form a whole.

[0108] In embodiments of this disclosure, the second electrode strip may be bent, with a bending angle β1 of 150° to 170°. Specifically, the second electrode strip may include two structural parts, with an included angle β1 of 150° to 160° between the two structural parts; for example: 150°, 156°, 162°, 166°, 170°, etc. In other words, the included angles β2 and β3 between the extension directions of the two structural parts and the column direction Y are 5° to 15°, for example: 5°, 7°, 9°, 12°, 15°, etc.

[0109] The second electrode strip can be basically parallel to the first electrode strip, that is, the bending angle β1 of the second electrode strip can be the same as the bending angle α1 of the first electrode strip.

[0110] It should be noted that the first and second electrode strips in each sub-pixel are not limited to alternating arrangement in the row direction X as mentioned above, but can also be alternating arrangement in the column direction Y, depending on the actual needs.

[0111] In the embodiments of this disclosure, each first wiring area A1 may be provided with a row of scan lines 17 and a row of common lines 18, and each second wiring area A3 may be provided with a column of data lines 16. Each row of scan lines 17 is connected to the transistors 11 of the adjacent sub-pixel units in the same row; each row of common lines 18 is connected to the common electrode 15 of the adjacent sub-pixel units in the same row; each column of data lines 16 is connected to the second electrode 111 of the transistors 11 of the even-numbered sub-pixel units in an adjacent column of sub-pixel units, and to the second electrode of the transistors 11 of the odd-numbered sub-pixel units in another adjacent column of sub-pixel units; however, it is not limited to this, each column of data lines 16 is only connected to the second electrode 111 of the transistors 11 of each sub-pixel unit in the adjacent column of sub-pixel units.

[0112] It should be noted that the array substrate 1 of this embodiment may also include a jumper wire (not shown in the figure) disposed on the same layer as the data line 16. This jumper wire can connect the common electrode 15 of two adjacent sub-pixel units in the column direction Y through a via structure.

[0113] Since the pixel electrode 14 and the common electrode 15 need to be connected to other film layers below through vias, vias need to be etched on the organic insulating layer 12. During the via etching process, the organic insulating layer 12 will be damaged to some extent. Since the sub-pixel area is protected by the second organic insulating part 121, the RGB color resist under the second organic insulating part 121 will not be damaged.

[0114] like Figure 3As shown, the array substrate 1 of this embodiment may further include a first alignment layer 102, which may be located on the top layer of the array substrate 1, that is, the first alignment layer 102 is disposed on the entire layer and covers the pixel electrode 14 and the common electrode 15.

[0115] In embodiments of this disclosure, the mating substrate may include a second substrate 20 and a shielding layer 21 located on the side of the second substrate 20 closer to the array substrate 1. The second substrate 20 may have the same structure as the first substrate 10, as specifically described above, but is not limited thereto; the structure of the second substrate 20 may also differ from that of the first substrate 10, depending on the specific circumstances. The orthogonal projection of the shielding layer 21 onto the first substrate 10 completely covers the transistor 11, scan line 17, data line 16, common line 18, and spacer 13, and may also cover the edges of the common electrode 15 and pixel electrode 14. Areas where the shielding layer 21 is not disposed may be covered by a transparent protective layer 23.

[0116] The mating substrate 2 may also be provided with a second alignment layer 22, which is located on the side of the transparent protective layer 23 away from the second substrate 20 and is disposed throughout the entire layer. The spacer 13 is formed after the second alignment layer 22 and is located on the side of the second alignment layer 22 away from the second substrate 20.

[0117] In embodiments of this disclosure, the spacer 13 may contact the first alignment layer 102 of the array substrate. As the height difference between the upper surfaces of the first organic insulating portion 120 and the second organic insulating portion 121 increases, the relative distance between the lower surface of the spacer 13 and the first alignment layer 102 of the sub-pixel region also increases, which can prevent the spacer 13 from laterally scratching the first alignment layer 102 of the sub-pixel region.

[0118] In the embodiments of this disclosure, multiple spacers 13 can be provided on the array substrate 1, and are divided into main spacers 1301 and auxiliary spacers 1302. That is, the spacers 13 of this disclosure can be either main spacers 1301 or auxiliary spacers 1302. When the panel is not subjected to external pressure, the two ends of the main spacer 1301 can contact the array substrate 1 and the mating substrate respectively, mainly playing a supporting role. When the display panel is not subjected to external pressure, if the auxiliary spacer 1302 is formed on the array substrate 1, the side of the auxiliary spacer 1302 away from the first substrate 10 has a certain distance from the mating substrate. That is, there is a step height difference between the main spacer 1301 and the auxiliary spacer 1302. By adjusting the step difference between the main spacer 1301 and the auxiliary spacer 1302, the thickness of the display panel can be finely adjusted.

[0119] For example, in the thickness direction of the panel, the height of the main spacer 1301 is greater than the height of the auxiliary spacer 1302, and the height difference between the two is ΔH. ps ,like Figure 1 As shown. When the display panel is subjected to external pressure, the main spacer 1301 first bears all the pressure and is compressed. When the main spacer 1301 is compressed to the height difference ΔH between the main spacer 1301 and the auxiliary spacer 1302, the compression continues. ps When the pressure drops to 0, the main septum 1301 and the auxiliary septum 1302 jointly bear the external pressure.

[0120] refer to Figure 1 The main spacer 1301 is prone to lateral slippage under pressure, and the length of its slippage in the thickness direction of the display panel is Hshift, which is less than ΔH. ps When the main spacer 1301 does not slip, the relative height ΔH between its lower surface and the upper surface of the display area film layer is the height difference ΔH between the surfaces of the first organic insulating portion 120 and the second organic insulating portion 121 that are away from the first substrate. When the height difference ΔH between the surfaces of the first organic insulating portion 120 and the second organic insulating portion 121 that are away from the first substrate is greater than the height difference ΔH between the main spacer 1301 and the auxiliary spacer 1302... ps When ΔH is greater than Hshift, even if the main spacer 1301 slips, its lower surface will not contact the sub-pixel area of ​​the first substrate, thus not causing damage to the display area.

[0121] The orthographic projection of the spacer 13 on the first substrate 10 in the embodiments of this disclosure is located within the orthographic projection of the first organic insulating portion 120 on the first substrate 10, and its specific position can be varied.

[0122] In one embodiment of this disclosure, reference is made to Figure 2 and Figure 3 The first organic insulating portion 120 covers the transistor 11, and the orthogonal projection of the spacer 13 on the first substrate 10 covers the orthogonal projection of the transistor 11 on the first substrate 10. Since the transistor film is relatively thick, its upper surface is the thickest point of the array substrate, thus maximizing the height difference between the upper surfaces of the first organic insulating portion 120 and the second organic insulating portion 121.

[0123] In another embodiment of this disclosure, reference is made to Figure 4 and Figure 5 The first organic insulating portion 120 covers the common line 18, and the orthographic projection of the spacer 13 on the first substrate 10 covers a portion of the orthographic projection of the common line 18 on the first substrate 10. As shown, a portion of the common line 18 is not covered by the upper film layer, and the spacer 13 can also be disposed at this location.

[0124] In another embodiment of this disclosure, reference is made to... Figure 6 and Figure 7The first organic insulating portion 120 covers the data line 16 and the scan line 17. The orthographic projection of the spacer 13 on the first substrate 10 covers part of the data line 16 and / or part of the scan line 17 on the first substrate. That is, the orthographic projection of the spacer 13 can cover part of the data line 16, part of the scan line 17, and the overlapping area between the data line 16 and the scan line 17 at the same time.

[0125] In one embodiment of this disclosure, reference is made to Figure 8 and Figure 9 , Figure 9 for Figure 8 The cross-sectional diagrams along the A-A' and B-B' directions are shown. It should be noted that... Figure 8 Only the color resist layer, spacers, and some signal lines are shown. Figure 9 The complete film structure is shown in the image. The color resist layer 101 has an opening 1010 in the wiring region, and the projection of the spacer 13 onto the first substrate 10 lies within the projection of the opening 1010 onto the first substrate 10. Because the color resist layer 101 has an opening 1010, the upper organic insulating layer 12 and the first alignment layer 102 will both be recessed at positions corresponding to the opening 1010, forming a notch. When the spacer 13 is subjected to downward pressure and moves towards the array substrate, it will extend into and press against this notch. Since the surrounding film layers are higher, they can "cover" the end of the spacer 13, thereby further preventing the spacer 13 from laterally sliding into the sub-pixel region. The opening 1010 may or may not penetrate the color resist layer 101.

[0126] It should be noted that the above-mentioned limitation on the projection relationship between the spacer 13 and the first organic insulating portion 120 is at least a limitation on the projection relationship between the main spacer 1301 and the first organic insulating portion 120. Of course, the projection relationship between the auxiliary spacer 1302 and the first organic insulating portion 120 can also satisfy the above limitation.

[0127] Figure 10 A schematic diagram of a display panel comprising multiple spacers is shown. As shown, spacers 13 are arranged sequentially in a column direction, with one spacer 13 positioned between two adjacent sub-pixel areas in the column direction. It should be noted that in this figure, the spacers 13 are precisely located between two adjacent sub-pixel areas. Figure 6 In the structure shown, the spacer 13 is located on one side between the upper and lower sub-pixel areas, close to the upper and lower sub-pixel areas of an adjacent column. In this case, it can also be regarded as corresponding to the sub-pixel areas of that column. The spacer 13 can be a main spacer 1301 or an auxiliary spacer 1302. Figure 11The diagram illustrates two distribution patterns of spacers. In the diagram, M represents the primary spacer and S represents the secondary spacer. Although M and S are located within sub-pixel areas, they actually indicate that the primary or secondary spacer is located between adjacent sub-pixel areas. The primary and secondary spacers can have different arrangements.

[0128] In one embodiment of this disclosure, at least one column of every three adjacent sub-pixel regions is provided with spacers 13, and a spacer is provided between any two adjacent sub-pixel regions in a column provided with spacers 13. That is, all spacers are arranged along the column direction between each sub-pixel region, thereby allowing for the provision of more spacers to provide more stable and uniform pressure.

[0129] Furthermore, in another embodiment of this disclosure, the number of auxiliary spacers 1302 is greater than that of the main spacers 1301; in each of three adjacent columns of sub-pixel areas, at least one column has all the spacers 13 as auxiliary spacers 1302. For example, in the arrangement shown in the figure, in each of three adjacent columns of sub-pixel areas, two columns are provided with spacers 13, such as the red sub-pixel column and the green sub-pixel column. A spacer 13 is provided between every two adjacent red sub-pixel areas in the column direction, and these spacers 13 are all auxiliary spacers 1302; a spacer 13 is also provided between every two adjacent green sub-pixel areas in the column direction, with some spacers 13 being main spacers 1301 and the remaining spacers 13 being auxiliary spacers 1302. No spacers 13 are provided in the blue pixel column. In this disclosure, the auxiliary spacers 1302 are arranged at a higher density, providing more support. The main spacers 1301 are spaced apart among the auxiliary spacers 1302 to achieve uniform distribution and provide uniform support.

[0130] It is understood that in other embodiments, spacer 13 may also be disposed in sub-pixel columns of other colors, such as red and blue, or green and blue. Of course, spacer 13 may also be disposed in only one color sub-pixel column, or in sub-pixel columns of all colors.

[0131] In this disclosure, the projection of the spacer 13 onto the first substrate 10 can be rectangular, circular, or elliptical, etc. In the embodiment shown in the figure, whether it is the main spacer 1301 or the auxiliary spacer 1302, its projection onto the first substrate 10 is rectangular. Rectangular spacers have better compressive strength and are easy to position during the manufacturing process.

[0132] The size of the spacer can be set according to the size of the wiring area. When it is circular, its diameter can be 10-30 μm. When it is rectangular, its side length can be 10-40 μm. When it is elliptical, its minor diameter can be 10-20 μm and its major diameter can be 15-30 μm.

[0133] The distance between the projection of the main spacer 1301 onto the first substrate 10 and the edge of the adjacent sub-pixel region affects the risk of damage to the sub-pixel region when the spacer slips laterally. If the distance is too small, the main spacer 1301 is prone to slipping into the sub-pixel region and causing damage when lateral slip occurs. If the distance is too large, the cross-sectional area of ​​the spacer is too small under the premise of fixed pixel size, making it difficult to provide sufficient support. Since the structure of the organic insulating layer 12 provided in this disclosure can reduce the risk of the main spacer 1301 damaging the sub-pixel region to a certain extent, the distance d between the main spacer 1301 and the adjacent sub-pixel region can be set between 15-50 μm, which can further prevent the spacer from damaging the sub-pixel region and also ensure that the spacer has a sufficient cross-sectional area. Typically, the spacer is positioned midway between two sub-pixel areas, so its distance from the edges of the two sub-pixel areas is equal. For example, the figure shows the distance between the spacer and the edge of the upper sub-pixel area, where the distance d between the rectangular main spacer and the edge of the upper sub-pixel area is 42 μm, and the distance d between the rectangular auxiliary spacer and the edge of the upper sub-pixel area is 30.5 μm. In addition, the distance between the spacer 13 and the two adjacent sub-pixel areas can also be 15 μm, 20 μm, 25 μm, 35 μm, 45 μm, 50 μm, etc.

[0134] This disclosure also provides a method for preparing a display panel to form... Figure 3 Taking the structure shown as an example, the steps include:

[0135] Step S100: A first substrate 10 is provided, the first substrate being divided into a sub-pixel region and a wiring region surrounding the sub-pixel region; a transistor 11 is formed in the wiring region of the first substrate.

[0136] In step S200, an organic insulating layer 12 is formed on the first substrate 10. The organic insulating layer 12 includes a first organic insulating portion 120 and a second organic insulating portion 121, such that the first organic insulating portion 120 covers the wiring area and the transistor 11, and the second organic insulating portion 121 covers the sub-pixel area; wherein the thickness of the first organic insulating portion 120 is greater than the thickness of the second organic insulating portion 121.

[0137] In step S300, a second substrate 20 is provided, and a spacer 13 is formed on the side of the second substrate facing the first substrate, such that the orthographic projection of the spacer 13 on the first substrate is located within the orthographic projection of the first organic insulating portion 120 on the first substrate.

[0138] The formation of the organic insulating layer 12 may include the following sub-steps:

[0139] Step S210: Coating an organic insulating material onto the first substrate on which the transistor 11 is formed;

[0140] In step S220, the organic insulating material is exposed and developed using a halftone mask or a grayscale mask, so that the thickness of the organic insulating material in the sub-pixel area is less than the thickness of the organic insulating material in the wiring area, thereby obtaining a thicker first organic insulating part 120 and a thinner second organic insulating part 121.

[0141] The remaining structures in the figure, such as transistor 11, color resist layer 101, first alignment layer 102, second alignment layer 22, etc., can be referred to the above description and will not be repeated here.

[0142] This disclosure also provides a display device, which includes the display panel mentioned in any of the foregoing embodiments, and will not be repeated here. The display device may further include a liquid crystal layer (not shown in the figure) located between the array substrate 1 and the mating substrate 2; that is, this display device may be a liquid crystal display device. The liquid crystal molecules in the liquid crystal layer may be negative liquid crystals to improve transmittance, but are not limited thereto, and may also be positive liquid crystals.

[0143] According to the embodiments of this disclosure, the specific type of display device is not particularly limited, and any type of display device commonly used in the art is acceptable, such as liquid crystal displays, mobile devices such as mobile phones and laptops, wearable devices such as watches, VR devices, etc. Those skilled in the art can make appropriate selections according to the specific purpose of the display device, which will not be elaborated here.

[0144] It should be noted that, in addition to the display panel, the display device also includes other necessary components and parts. Taking a monitor as an example, it may also include a backlight module, a housing, a main circuit board, a power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.

[0145] It should be noted that the terms "on," "formed on," and "set on" used in this article can indicate that one layer is directly formed or set on another layer, or that one layer is indirectly formed or set on another layer, meaning that there are other layers between the two layers.

[0146] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0147] It should be noted that while terms such as "first," "second," etc., may be used herein to describe various components, parts, elements, regions, layers, and / or portions, these components, parts, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one component, part, element, region, layer, and / or portion from another.

[0148] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

[0149] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A display panel, characterized in that, The array includes an array substrate and a mating substrate disposed opposite to each other, wherein the array substrate includes: The first substrate (10) includes a sub-pixel region and a wiring region disposed around the sub-pixel region; A transistor (11) is disposed on the first substrate (10) and located in the wiring area; An organic insulating layer (12) is formed on the first substrate (10) and includes a first organic insulating portion (120) and a second organic insulating portion (121). The first organic insulating portion (120) covers the wiring area and the transistor (11), and the second organic insulating portion (121) covers the sub-pixel area. The thickness of the first organic insulating portion (120) is greater than the thickness of the second organic insulating portion (121). The pixel electrode (14) and the common electrode (15) are both disposed on the first substrate (10) and are both located on the side of the organic insulating layer (12) away from the first substrate (10); The mating substrate includes: A second substrate (20) is disposed opposite to the first substrate (10); A spacer (13) is formed on the side of the second substrate (20) facing the first substrate (10), and the orthographic projection of the spacer (13) on the first substrate (10) lies within the orthographic projection of the first organic insulating portion (120) on the first substrate (10).

2. The display panel according to claim 1, characterized in that, The display panel includes a plurality of spacers (13), wherein the spacers (13) are main spacers (1301) or auxiliary spacers (1302), and in the thickness direction of the display panel, the height of the main spacer (1301) is greater than the height of the auxiliary spacer (1302). The height difference ΔH between the surfaces of the first organic insulating portion (120) and the second organic insulating portion (121) away from the first substrate is greater than the height difference ΔH between the main spacer (1301) and the auxiliary spacer (1302). ps .

3. The display panel according to claim 2, characterized in that, The array substrate further includes: Scan lines (17) are disposed on the first substrate (10) and arranged along the row direction in the wiring area; Data lines (16) are disposed on the first substrate (10) and arranged in the wiring area along the column direction; A common line (18) is disposed on the first substrate (10) and arranged in the wiring area along the row direction; the common electrode (15) is electrically connected to the common line (18). The transistor (11) includes a gate, a first electrode, and a second electrode. The gate is electrically connected to the scan line (17), the first electrode is electrically connected to the data line (16), and the second electrode is electrically connected to the pixel electrode (14). The scan line (17), data line (16), common line (18), and transistor (11) are all located on the side of the organic insulating layer (12) facing the first substrate (10).

4. The display panel according to claim 3, characterized in that, The first organic insulating portion (120) covers the transistor (11), and the orthographic projection of the spacer (13) on the first substrate (10) covers the orthographic projection of the transistor (11) on the first substrate (10).

5. The display panel according to claim 3, characterized in that, The first organic insulating portion (120) covers the common line (18), and the orthographic projection of the spacer (13) on the first substrate (10) covers a portion of the orthographic projection of the common line (18) on the first substrate (10).

6. The display panel according to claim 3, characterized in that, The first organic insulating portion (120) covers the data line (16) and the scan line (17), and the orthographic projection of the spacer (13) on the first substrate (10) covers part of the orthographic projection of the data line (16) and / or part of the scan line (17) on the first substrate (10).

7. The display panel according to claim 2, characterized in that, The ratio of the thickness of the first organic insulating portion (120) to the thickness of the second organic insulating portion (121) is 2 to 4.

8. The display panel according to claim 7, characterized in that, The thickness of the first organic insulating part (120) is 2 μm to 4 μm; the thickness of the second organic insulating part (121) is less than 2 μm.

9. The display panel according to claim 2, characterized in that, The thickness of the second organic insulating part (121) is 0.

10. The display panel according to claim 2, characterized in that, The first substrate (10) includes a plurality of sub-pixel regions arranged in an array along the row direction and the column direction, and the spacer (13) is disposed between two adjacent sub-pixel regions in the column direction; In each of the three adjacent columns of the sub-pixel areas, at least one column is provided with the spacer (13), and in the column where the spacer (13) is provided, there is a spacer (13) between any two adjacent sub-pixel areas.

11. The display panel according to claim 10, characterized in that, The plurality of septa (13) includes a plurality of main septa (1301) and a plurality of auxiliary septa (1302), wherein the number of auxiliary septa (1302) is greater than the number of main septa (1301). In each of the three adjacent columns of the sub-pixel regions, at least one column of all the spacers (13) are the auxiliary spacers (1302).

12. The display panel according to claim 1, characterized in that, The projection of the spacer (13) onto the first substrate (10) is rectangular, circular, or elliptical.

13. The display panel according to claim 12, characterized in that, The distance between the projection of the spacer (13) on the first substrate (10) and the edge of the adjacent sub-pixel area is 15-50 μm.

14. The display panel according to claim 1, characterized in that, The array substrate further includes: A color resist layer (101) is disposed on the first substrate (10) and located on the side of the organic insulating layer (12) close to the first substrate (10). The color resist layer covers the sub-pixel area and at least part of the wiring area.

15. The display panel according to claim 14, characterized in that, The color resist layer (101) has an opening (1010) in the wiring area, the organic insulating layer (12) is recessed at the opening of the color resist layer, and the projection of the spacer (13) on the first substrate (10) is located within the projection of the opening (1010) on the first substrate (10).

16. The display panel according to claim 3, characterized in that, The common electrode (15) and the pixel electrode (14) are both located on the side of the organic insulating layer (12) away from the first substrate (10); The pixel electrode (14) has a plurality of first electrode strips spaced apart in the row direction; The common electrode (15) is disposed on the same layer as the pixel electrode (14). The common electrode (15) has a plurality of second electrode strips arranged at intervals in the row direction. The second electrode strips and the first electrode strips are arranged alternately in the row direction, and there is a gap between the second electrode strips and the first electrode strips. The common electrode (15) is connected to the common line (18) through a via.

17. The display panel according to claim 16, characterized in that, The array substrate further includes: A liquid crystal layer is disposed between the array substrate and the mating substrate; A first alignment layer (102) is disposed on the first substrate (10) and covers the side of the common electrode (15) and pixel electrode (14) away from the first substrate (10); The second alignment layer (22) is disposed on the second substrate (20) and located between the spacer (13) and the second substrate (20).

18. A method for manufacturing a display panel, characterized in that, include: A first substrate is provided, the first substrate being divided into a sub-pixel region and a wiring region disposed around the sub-pixel region; A transistor is formed in the wiring region of the first substrate; An organic insulating layer is formed on the first substrate. The organic insulating layer includes a first organic insulating portion and a second organic insulating portion, such that the first organic insulating portion covers the wiring area and the transistor, and the second organic insulating portion covers the sub-pixel area; wherein the thickness of the first organic insulating portion is greater than the thickness of the second organic insulating portion. Provide a second substrate; A spacer is formed on the side of the second substrate facing the first substrate, such that the orthographic projection of the spacer on the first substrate lies within the orthographic projection of the first organic insulating portion on the first substrate.

19. The method for manufacturing a display panel according to claim 18, characterized in that, The formation of an organic insulating layer includes: An organic insulating material is coated on a first substrate on which the transistor is formed; The organic insulating material is exposed and developed using a halftone mask or a grayscale mask, so that the thickness of the organic insulating material in the sub-pixel area is less than the thickness of the organic insulating material in the wiring area.

20. A display device, characterized in that, The display panel includes any one of claims 1-17.

Images